1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Object/MachOFormat.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetAsmBackend.h"
26 #include "llvm/Target/TargetRegistry.h"
30 class ARMAsmBackend : public TargetAsmBackend {
31 bool isThumbMode; // Currently emitting Thumb code.
33 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
35 bool MayNeedRelaxation(const MCInst &Inst) const;
37 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
39 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
41 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
53 unsigned getPointerSize() const { return 4; }
54 bool isThumb() const { return isThumbMode; }
55 void setIsThumb(bool it) { isThumbMode = it; }
57 } // end anonymous namespace
59 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
60 // FIXME: Thumb targets, different move constant targets..
64 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
65 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
69 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
71 assert (((Count & 1) == 0) && "Unaligned Nop data fragment!");
72 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
73 // use 0x46c0 (which is a 'mov r8, r8' insn).
75 for (uint64_t i = 0; i != Count; ++i)
81 for (uint64_t i = 0; i != Count; ++i)
82 OW->Write32(0xe1a00000);
86 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
89 llvm_unreachable("Unknown fixup kind!");
92 case ARM::fixup_arm_movt_hi16:
93 case ARM::fixup_arm_movw_lo16: {
94 unsigned Hi4 = (Value & 0xF000) >> 12;
95 unsigned Lo12 = Value & 0x0FFF;
98 Value = (Hi4 << 16) | (Lo12);
101 case ARM::fixup_arm_ldst_pcrel_12:
102 // ARM PC-relative values are offset by 8.
105 case ARM::fixup_t2_ldst_pcrel_12: {
106 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
109 if ((int64_t)Value < 0) {
113 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
114 Value |= isAdd << 23;
116 // Same addressing mode as fixup_arm_pcrel_10,
117 // but with 16-bit halfwords swapped.
118 if (Kind == ARM::fixup_t2_ldst_pcrel_12) {
119 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
120 swapped |= (Value & 0x0000FFFF) << 16;
126 case ARM::fixup_arm_adr_pcrel_12: {
127 // ARM PC-relative values are offset by 8.
129 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
130 if ((int64_t)Value < 0) {
134 assert(ARM_AM::getSOImmVal(Value) != -1 &&
135 "Out of range pc-relative fixup value!");
136 // Encode the immediate and shift the opcode into place.
137 return ARM_AM::getSOImmVal(Value) | (opc << 21);
139 case ARM::fixup_arm_branch:
140 // These values don't encode the low two bits since they're always zero.
141 // Offset by 8 just as above.
142 return 0xffffff & ((Value - 8) >> 2);
143 case ARM::fixup_t2_branch: {
145 Value >>= 1; // Low bit is not encoded.
148 out |= (Value & 0x80000) << 7; // S bit
149 out |= (Value & 0x40000) >> 7; // J2 bit
150 out |= (Value & 0x20000) >> 4; // J1 bit
151 out |= (Value & 0x1F800) << 5; // imm6 field
152 out |= (Value & 0x007FF); // imm11 field
154 uint64_t swapped = (out & 0xFFFF0000) >> 16;
155 swapped |= (out & 0x0000FFFF) << 16;
158 case ARM::fixup_arm_thumb_bl: {
159 // The value doesn't encode the low bit (always zero) and is offset by
160 // four. The value is encoded into disjoint bit positions in the destination
161 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
163 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
165 // Note that the halfwords are stored high first, low second; so we need
166 // to transpose the fixup value here to map properly.
167 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
169 Value = 0x3fffff & ((Value - 4) >> 1);
170 Binary = (Value & 0x7ff) << 16; // Low imm11 value.
171 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value.
172 Binary |= isNeg << 10; // Sign bit.
175 case ARM::fixup_arm_thumb_blx: {
176 // The value doesn't encode the low two bits (always zero) and is offset by
177 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit
178 // positions in the destination opcode. x = unchanged, I = immediate value
179 // bit, S = sign extension bit, 0 = zero.
181 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0
183 // Note that the halfwords are stored high first, low second; so we need
184 // to transpose the fixup value here to map properly.
185 unsigned isNeg = (int64_t(Value) < 0) ? 1 : 0;
187 Value = 0xfffff & ((Value - 2) >> 2);
188 Binary = (Value & 0x3ff) << 17; // Low imm10L value.
189 Binary |= (Value & 0xffc00) >> 10; // High imm10H value.
190 Binary |= isNeg << 10; // Sign bit.
193 case ARM::fixup_arm_thumb_cp:
194 // Offset by 4, and don't encode the low two bits. Two bytes of that
195 // 'off by 4' is implicitly handled by the half-word ordering of the
196 // Thumb encoding, so we only need to adjust by 2 here.
197 return ((Value - 2) >> 2) & 0xff;
198 case ARM::fixup_arm_thumb_cb: {
199 // Offset by 4 and don't encode the lower bit, which is always 0.
200 uint32_t Binary = (Value - 4) >> 1;
201 return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3);
203 case ARM::fixup_arm_thumb_bcc:
204 // Offset by 4 and don't encode the lower bit, which is always 0.
205 return ((Value - 4) >> 1) & 0xff;
206 case ARM::fixup_arm_pcrel_10:
207 Value = Value - 6; // ARM fixups offset by an additional word and don't
208 // need to adjust for the half-word ordering.
210 case ARM::fixup_t2_pcrel_10: {
211 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
214 if ((int64_t)Value < 0) {
218 // These values don't encode the low two bits since they're always zero.
220 assert ((Value < 256) && "Out of range pc-relative fixup value!");
221 Value |= isAdd << 23;
223 // Same addressing mode as fixup_arm_pcrel_10,
224 // but with 16-bit halfwords swapped.
225 if (Kind == ARM::fixup_t2_pcrel_10) {
226 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
227 swapped |= (Value & 0x0000FFFF) << 16;
238 // FIXME: This should be in a separate file.
239 // ELF is an ELF of course...
240 class ELFARMAsmBackend : public ARMAsmBackend {
241 MCELFObjectFormat Format;
244 Triple::OSType OSType;
245 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
246 : ARMAsmBackend(T), OSType(_OSType) {
247 HasScatteredSymbols = true;
250 virtual const MCObjectFormat &getObjectFormat() const {
254 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
255 uint64_t Value) const;
257 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
258 return createELFObjectWriter(OS, /*Is64Bit=*/false,
260 /*IsLittleEndian=*/true,
261 /*HasRelocationAddend=*/false);
265 // FIXME: Raise this to share code between Darwin and ELF.
266 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
267 unsigned DataSize, uint64_t Value) const {
268 unsigned NumBytes = 4; // FIXME: 2 for Thumb
269 Value = adjustFixupValue(Fixup.getKind(), Value);
270 if (!Value) return; // Doesn't change encoding.
272 unsigned Offset = Fixup.getOffset();
273 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
275 // For each byte of the fragment that the fixup touches, mask in the bits from
276 // the fixup value. The Value has been "split up" into the appropriate
278 for (unsigned i = 0; i != NumBytes; ++i)
279 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
282 // FIXME: This should be in a separate file.
283 class DarwinARMAsmBackend : public ARMAsmBackend {
284 MCMachOObjectFormat Format;
286 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
287 HasScatteredSymbols = true;
290 virtual const MCObjectFormat &getObjectFormat() const {
294 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
295 uint64_t Value) const;
297 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
298 // FIXME: Subtarget info should be derived. Force v7 for now.
299 return createMachObjectWriter(OS, /*Is64Bit=*/false,
300 object::mach::CTM_ARM,
301 object::mach::CSARM_V7,
302 /*IsLittleEndian=*/true);
305 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
310 /// getFixupKindNumBytes - The number of bytes the fixup may change.
311 static unsigned getFixupKindNumBytes(unsigned Kind) {
314 llvm_unreachable("Unknown fixup kind!");
316 case ARM::fixup_arm_thumb_bcc:
317 case ARM::fixup_arm_thumb_cp:
320 case ARM::fixup_arm_thumb_cb:
323 case ARM::fixup_arm_ldst_pcrel_12:
324 case ARM::fixup_arm_pcrel_10:
325 case ARM::fixup_arm_adr_pcrel_12:
326 case ARM::fixup_arm_branch:
330 case ARM::fixup_t2_ldst_pcrel_12:
331 case ARM::fixup_t2_branch:
332 case ARM::fixup_t2_pcrel_10:
333 case ARM::fixup_arm_thumb_bl:
334 case ARM::fixup_arm_thumb_blx:
339 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
340 unsigned DataSize, uint64_t Value) const {
341 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
342 Value = adjustFixupValue(Fixup.getKind(), Value);
343 if (!Value) return; // Doesn't change encoding.
345 unsigned Offset = Fixup.getOffset();
346 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
348 // For each byte of the fragment that the fixup touches, mask in the
349 // bits from the fixup value.
350 for (unsigned i = 0; i != NumBytes; ++i)
351 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
354 } // end anonymous namespace
356 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
357 const std::string &TT) {
358 switch (Triple(TT).getOS()) {
360 return new DarwinARMAsmBackend(T);
361 case Triple::MinGW32:
364 assert(0 && "Windows not supported on ARM");
366 return new ELFARMAsmBackend(T, Triple(TT).getOS());