1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Object/MachOFormat.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetAsmBackend.h"
26 #include "llvm/Target/TargetRegistry.h"
30 class ARMAsmBackend : public TargetAsmBackend {
31 bool isThumbMode; // Currently emitting Thumb code.
33 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
35 bool MayNeedRelaxation(const MCInst &Inst) const;
37 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
39 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
41 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
53 unsigned getPointerSize() const { return 4; }
54 bool isThumb() const { return isThumbMode; }
55 void setIsThumb(bool it) { isThumbMode = it; }
57 } // end anonymous namespace
59 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
60 // FIXME: Thumb targets, different move constant targets..
64 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
65 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
69 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
71 assert (((Count & 1) == 0) && "Unaligned Nop data fragment!");
72 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
73 // use 0x46c0 (which is a 'mov r8, r8' insn).
75 for (uint64_t i = 0; i != Count; ++i)
81 for (uint64_t i = 0; i != Count; ++i)
82 OW->Write32(0xe1a00000);
86 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
89 llvm_unreachable("Unknown fixup kind!");
92 case ARM::fixup_arm_movt_hi16:
93 case ARM::fixup_arm_movw_lo16: {
94 unsigned Hi4 = (Value & 0xF000) >> 12;
95 unsigned Lo12 = Value & 0x0FFF;
98 Value = (Hi4 << 16) | (Lo12);
101 case ARM::fixup_arm_ldst_pcrel_12: {
103 // ARM PC-relative values are offset by 8.
105 if ((int64_t)Value < 0) {
109 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
110 Value |= isAdd << 23;
113 case ARM::fixup_arm_adr_pcrel_12: {
114 // ARM PC-relative values are offset by 8.
116 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
117 if ((int64_t)Value < 0) {
121 assert(ARM_AM::getSOImmVal(Value) != -1 &&
122 "Out of range pc-relative fixup value!");
123 // Encode the immediate and shift the opcode into place.
124 return ARM_AM::getSOImmVal(Value) | (opc << 21);
126 case ARM::fixup_arm_branch:
127 // These values don't encode the low two bits since they're always zero.
128 // Offset by 8 just as above.
129 return 0xffffff & ((Value - 8) >> 2);
130 case ARM::fixup_arm_thumb_bl: {
131 // The value doesn't encode the low bit (always zero) and is offset by
132 // four. The value is encoded into disjoint bit positions in the destination
133 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
134 // xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
135 // Note that the halfwords are stored high first, low second; so we need
136 // to transpose the fixup value here to map properly.
137 // FIXME: Something isn't quite right with this. Some, but not all, BLX
138 // instructions are getting the encoded value off by one.
139 uint32_t Binary = 0x3fffff & ((Value - 4) >> 1);
140 Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
143 case ARM::fixup_arm_thumb_cp:
144 // Offset by 4, and don't encode the low two bits. Two bytes of that
145 // 'off by 4' is implicitly handled by the half-word ordering of the
146 // Thumb encoding, so we only need to adjust by 2 here.
147 return ((Value - 2) >> 2) & 0xff;
148 case ARM::fixup_arm_pcrel_10:
149 Value = Value - 6; // ARM fixups offset by an additional word and don't
150 // need to adjust for the half-word ordering.
152 case ARM::fixup_t2_pcrel_10: {
153 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
156 if ((int64_t)Value < 0) {
160 // These values don't encode the low two bits since they're always zero.
162 assert ((Value < 256) && "Out of range pc-relative fixup value!");
163 Value |= isAdd << 23;
165 // Same addressing mode as fixup_arm_pcrel_10,
166 // but with 16-bit halfwords swapped.
167 if (Kind == ARM::fixup_t2_pcrel_10) {
168 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
169 swapped |= (Value & 0x0000FFFF) << 16;
180 // FIXME: This should be in a separate file.
181 // ELF is an ELF of course...
182 class ELFARMAsmBackend : public ARMAsmBackend {
183 MCELFObjectFormat Format;
186 Triple::OSType OSType;
187 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
188 : ARMAsmBackend(T), OSType(_OSType) {
189 HasScatteredSymbols = true;
192 virtual const MCObjectFormat &getObjectFormat() const {
196 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
197 uint64_t Value) const;
199 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
200 return createELFObjectWriter(OS, /*Is64Bit=*/false,
202 /*IsLittleEndian=*/true,
203 /*HasRelocationAddend=*/false);
207 // FIXME: Raise this to share code between Darwin and ELF.
208 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
209 unsigned DataSize, uint64_t Value) const {
210 unsigned NumBytes = 4; // FIXME: 2 for Thumb
211 Value = adjustFixupValue(Fixup.getKind(), Value);
212 if (!Value) return; // Doesn't change encoding.
214 unsigned Offset = Fixup.getOffset();
215 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
217 // For each byte of the fragment that the fixup touches, mask in the bits from
218 // the fixup value. The Value has been "split up" into the appropriate
220 for (unsigned i = 0; i != NumBytes; ++i)
221 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
224 // FIXME: This should be in a separate file.
225 class DarwinARMAsmBackend : public ARMAsmBackend {
226 MCMachOObjectFormat Format;
228 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
229 HasScatteredSymbols = true;
232 virtual const MCObjectFormat &getObjectFormat() const {
236 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
237 uint64_t Value) const;
239 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
240 // FIXME: Subtarget info should be derived. Force v7 for now.
241 return createMachObjectWriter(OS, /*Is64Bit=*/false,
242 object::mach::CTM_ARM,
243 object::mach::CSARM_V7,
244 /*IsLittleEndian=*/true);
247 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
252 /// getFixupKindNumBytes - The number of bytes the fixup may change.
253 static unsigned getFixupKindNumBytes(unsigned Kind) {
256 llvm_unreachable("Unknown fixup kind!");
258 case ARM::fixup_arm_thumb_cp:
261 case ARM::fixup_arm_ldst_pcrel_12:
262 case ARM::fixup_arm_pcrel_10:
263 case ARM::fixup_arm_adr_pcrel_12:
264 case ARM::fixup_arm_branch:
268 case ARM::fixup_t2_pcrel_10:
269 case ARM::fixup_arm_thumb_bl:
274 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
275 unsigned DataSize, uint64_t Value) const {
276 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
277 Value = adjustFixupValue(Fixup.getKind(), Value);
278 if (!Value) return; // Doesn't change encoding.
280 unsigned Offset = Fixup.getOffset();
281 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
283 // For each byte of the fragment that the fixup touches, mask in the
284 // bits from the fixup value.
285 for (unsigned i = 0; i != NumBytes; ++i)
286 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
289 } // end anonymous namespace
291 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
292 const std::string &TT) {
293 switch (Triple(TT).getOS()) {
295 return new DarwinARMAsmBackend(T);
296 case Triple::MinGW32:
299 assert(0 && "Windows not supported on ARM");
301 return new ELFARMAsmBackend(T, Triple(TT).getOS());