1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/Target/TargetAsmBackend.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCObjectFormat.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionELF.h"
19 #include "llvm/MC/MCSectionMachO.h"
20 #include "llvm/Support/ELF.h"
21 #include "llvm/Support/MachO.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Target/TargetAsmBackend.h"
29 class ARMAsmBackend : public TargetAsmBackend {
31 ARMAsmBackend(const Target &T)
32 : TargetAsmBackend(T) {
35 bool MayNeedRelaxation(const MCInst &Inst) const;
37 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
39 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
41 unsigned getPointerSize() const {
46 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
47 // FIXME: Thumb targets, different move constant targets..
51 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
52 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
56 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
57 // if ((Count % 4) != 0) {
58 // // Fixme: % 2 for Thumb?
61 // FIXME: Zero fill for now. That's not right, but at least will get the
62 // section size right.
63 for (uint64_t i = 0; i != Count; ++i)
67 } // end anonymous namespace
70 // FIXME: This should be in a separate file.
71 // ELF is an ELF of course...
72 class ELFARMAsmBackend : public ARMAsmBackend {
73 MCELFObjectFormat Format;
76 Triple::OSType OSType;
77 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
78 : ARMAsmBackend(T), OSType(_OSType) {
79 HasScatteredSymbols = true;
82 virtual const MCObjectFormat &getObjectFormat() const {
86 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
87 uint64_t Value) const;
89 bool isVirtualSection(const MCSection &Section) const {
90 const MCSectionELF &SE = static_cast<const MCSectionELF&>(Section);
91 return SE.getType() == MCSectionELF::SHT_NOBITS;
94 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
95 return createELFObjectWriter(OS, /*Is64Bit=*/false,
97 /*IsLittleEndian=*/true,
98 /*HasRelocationAddend=*/false);
102 // Fixme: can we raise this to share code between Darwin and ELF?
103 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
104 uint64_t Value) const {
105 assert(0 && "ELFARMAsmBackend::ApplyFixup() unimplemented");
108 // FIXME: This should be in a separate file.
109 class DarwinARMAsmBackend : public ARMAsmBackend {
110 MCMachOObjectFormat Format;
113 DarwinARMAsmBackend(const Target &T)
115 HasScatteredSymbols = true;
118 virtual const MCObjectFormat &getObjectFormat() const {
122 void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
123 uint64_t Value) const;
125 bool isVirtualSection(const MCSection &Section) const {
126 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
127 return (SMO.getType() == MCSectionMachO::S_ZEROFILL ||
128 SMO.getType() == MCSectionMachO::S_GB_ZEROFILL ||
129 SMO.getType() == MCSectionMachO::S_THREAD_LOCAL_ZEROFILL);
132 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
133 // FIXME: Subtarget info should be derived. Force v7 for now.
134 return createMachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPUTypeARM,
135 MachO::CPUSubType_ARM_V7,
136 /*IsLittleEndian=*/true);
139 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
144 static unsigned getFixupKindNumBytes(unsigned Kind) {
146 default: llvm_unreachable("Unknown fixup kind!");
147 case FK_Data_4: return 4;
148 case ARM::fixup_arm_pcrel_12: return 2;
149 case ARM::fixup_arm_vfp_pcrel_12: return 1;
150 case ARM::fixup_arm_branch: return 3;
154 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
157 llvm_unreachable("Unknown fixup kind!");
160 case ARM::fixup_arm_pcrel_12:
161 // ARM PC-relative values are offset by 8.
163 case ARM::fixup_arm_branch:
164 case ARM::fixup_arm_vfp_pcrel_12:
165 // These values don't encode the low two bits since they're always zero.
166 // Offset by 8 just as above.
167 return (Value - 8) >> 2;
171 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
172 uint64_t Value) const {
173 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
174 Value = adjustFixupValue(Fixup.getKind(), Value);
176 assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
177 "Invalid fixup offset!");
178 // For each byte of the fragment that the fixup touches, mask in the
179 // bits from the fixup value.
180 for (unsigned i = 0; i != NumBytes; ++i)
181 DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
183 } // end anonymous namespace
185 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
186 const std::string &TT) {
187 switch (Triple(TT).getOS()) {
189 return new DarwinARMAsmBackend(T);
190 case Triple::MinGW32:
193 assert(0 && "Windows not supported on ARM");
195 return new ELFARMAsmBackend(T, Triple(TT).getOS());