1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMFixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCObjectFormat.h"
18 #include "llvm/MC/MCObjectWriter.h"
19 #include "llvm/MC/MCSectionELF.h"
20 #include "llvm/MC/MCSectionMachO.h"
21 #include "llvm/Object/MachOFormat.h"
22 #include "llvm/Support/ELF.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetAsmBackend.h"
26 #include "llvm/Target/TargetRegistry.h"
30 class ARMAsmBackend : public TargetAsmBackend {
31 bool isThumbMode; // Currently emitting Thumb code.
33 ARMAsmBackend(const Target &T) : TargetAsmBackend(), isThumbMode(false) {}
35 bool MayNeedRelaxation(const MCInst &Inst) const;
37 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
39 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
41 void HandleAssemblerFlag(MCAssemblerFlag Flag) {
53 unsigned getPointerSize() const { return 4; }
54 bool isThumb() const { return isThumbMode; }
55 void setIsThumb(bool it) { isThumbMode = it; }
57 } // end anonymous namespace
59 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
60 // FIXME: Thumb targets, different move constant targets..
64 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
65 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
69 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
71 assert (((Count & 1) == 0) && "Unaligned Nop data fragment!");
72 // FIXME: 0xbf00 is the ARMv7 value. For v6 and before, we'll need to
73 // use 0x46c0 (which is a 'mov r8, r8' insn).
75 for (uint64_t i = 0; i != Count; ++i)
81 for (uint64_t i = 0; i != Count; ++i)
82 OW->Write32(0xe1a00000);
86 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
89 llvm_unreachable("Unknown fixup kind!");
92 case ARM::fixup_arm_movt_hi16:
93 case ARM::fixup_arm_movw_lo16: {
94 unsigned Hi4 = (Value & 0xF000) >> 12;
95 unsigned Lo12 = Value & 0x0FFF;
98 Value = (Hi4 << 16) | (Lo12);
101 case ARM::fixup_arm_ldst_pcrel_12: {
103 // ARM PC-relative values are offset by 8.
105 if ((int64_t)Value < 0) {
109 assert ((Value < 4096) && "Out of range pc-relative fixup value!");
110 Value |= isAdd << 23;
113 case ARM::fixup_arm_adr_pcrel_12: {
114 // ARM PC-relative values are offset by 8.
116 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
117 if ((int64_t)Value < 0) {
121 assert(ARM_AM::getSOImmVal(Value) != -1 &&
122 "Out of range pc-relative fixup value!");
123 // Encode the immediate and shift the opcode into place.
124 return ARM_AM::getSOImmVal(Value) | (opc << 21);
126 case ARM::fixup_arm_branch:
127 // These values don't encode the low two bits since they're always zero.
128 // Offset by 8 just as above.
129 return 0xffffff & ((Value - 8) >> 2);
130 case ARM::fixup_t2_branch: {
132 Value >>= 1; // Low bit is not encoded.
135 Value |= (Value & 0x80000) << 7; // S bit
136 Value |= (Value & 0x40000) >> 7; // J2 bit
137 Value |= (Value & 0x20000) >> 4; // J1 bit
138 Value |= (Value & 0x1F800) << 5; // imm6 field
139 Value |= (Value & 0x007FF); // imm11 field
141 uint64_t swapped = (out & 0xFFFF0000) >> 16;
142 swapped |= (out & 0x0000FFFF) << 16;
145 case ARM::fixup_arm_thumb_bl: {
146 // The value doesn't encode the low bit (always zero) and is offset by
147 // four. The value is encoded into disjoint bit positions in the destination
148 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit
149 // xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
150 // Note that the halfwords are stored high first, low second; so we need
151 // to transpose the fixup value here to map properly.
152 // FIXME: Something isn't quite right with this. Some, but not all, BLX
153 // instructions are getting the encoded value off by one.
154 uint32_t Binary = 0x3fffff & ((Value - 4) >> 1);
155 Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
158 case ARM::fixup_arm_thumb_cp:
159 // Offset by 4, and don't encode the low two bits. Two bytes of that
160 // 'off by 4' is implicitly handled by the half-word ordering of the
161 // Thumb encoding, so we only need to adjust by 2 here.
162 return ((Value - 2) >> 2) & 0xff;
163 case ARM::fixup_arm_thumb_br: {
164 // Offset by 4 and don't encode the lower bit, which is always 0.
165 uint32_t Binary = (Value - 4) >> 1;
166 return ((Binary & 0x20) << 9) | ((Binary & 0x1f) << 3);
168 case ARM::fixup_arm_pcrel_10:
169 Value = Value - 6; // ARM fixups offset by an additional word and don't
170 // need to adjust for the half-word ordering.
172 case ARM::fixup_t2_pcrel_10: {
173 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
176 if ((int64_t)Value < 0) {
180 // These values don't encode the low two bits since they're always zero.
182 assert ((Value < 256) && "Out of range pc-relative fixup value!");
183 Value |= isAdd << 23;
185 // Same addressing mode as fixup_arm_pcrel_10,
186 // but with 16-bit halfwords swapped.
187 if (Kind == ARM::fixup_t2_pcrel_10) {
188 uint64_t swapped = (Value & 0xFFFF0000) >> 16;
189 swapped |= (Value & 0x0000FFFF) << 16;
200 // FIXME: This should be in a separate file.
201 // ELF is an ELF of course...
202 class ELFARMAsmBackend : public ARMAsmBackend {
203 MCELFObjectFormat Format;
206 Triple::OSType OSType;
207 ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
208 : ARMAsmBackend(T), OSType(_OSType) {
209 HasScatteredSymbols = true;
212 virtual const MCObjectFormat &getObjectFormat() const {
216 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
217 uint64_t Value) const;
219 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
220 return createELFObjectWriter(OS, /*Is64Bit=*/false,
222 /*IsLittleEndian=*/true,
223 /*HasRelocationAddend=*/false);
227 // FIXME: Raise this to share code between Darwin and ELF.
228 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
229 unsigned DataSize, uint64_t Value) const {
230 unsigned NumBytes = 4; // FIXME: 2 for Thumb
231 Value = adjustFixupValue(Fixup.getKind(), Value);
232 if (!Value) return; // Doesn't change encoding.
234 unsigned Offset = Fixup.getOffset();
235 assert(Offset % NumBytes == 0 && "Offset mod NumBytes is nonzero!");
237 // For each byte of the fragment that the fixup touches, mask in the bits from
238 // the fixup value. The Value has been "split up" into the appropriate
240 for (unsigned i = 0; i != NumBytes; ++i)
241 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
244 // FIXME: This should be in a separate file.
245 class DarwinARMAsmBackend : public ARMAsmBackend {
246 MCMachOObjectFormat Format;
248 DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
249 HasScatteredSymbols = true;
252 virtual const MCObjectFormat &getObjectFormat() const {
256 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
257 uint64_t Value) const;
259 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
260 // FIXME: Subtarget info should be derived. Force v7 for now.
261 return createMachObjectWriter(OS, /*Is64Bit=*/false,
262 object::mach::CTM_ARM,
263 object::mach::CSARM_V7,
264 /*IsLittleEndian=*/true);
267 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
272 /// getFixupKindNumBytes - The number of bytes the fixup may change.
273 static unsigned getFixupKindNumBytes(unsigned Kind) {
276 llvm_unreachable("Unknown fixup kind!");
278 case ARM::fixup_arm_thumb_cp:
281 case ARM::fixup_arm_thumb_br:
284 case ARM::fixup_arm_ldst_pcrel_12:
285 case ARM::fixup_arm_pcrel_10:
286 case ARM::fixup_arm_adr_pcrel_12:
287 case ARM::fixup_arm_branch:
291 case ARM::fixup_t2_branch:
292 case ARM::fixup_t2_pcrel_10:
293 case ARM::fixup_arm_thumb_bl:
298 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data,
299 unsigned DataSize, uint64_t Value) const {
300 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
301 Value = adjustFixupValue(Fixup.getKind(), Value);
302 if (!Value) return; // Doesn't change encoding.
304 unsigned Offset = Fixup.getOffset();
305 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
307 // For each byte of the fragment that the fixup touches, mask in the
308 // bits from the fixup value.
309 for (unsigned i = 0; i != NumBytes; ++i)
310 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
313 } // end anonymous namespace
315 TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
316 const std::string &TT) {
317 switch (Triple(TT).getOS()) {
319 return new DarwinARMAsmBackend(T);
320 case Triple::MinGW32:
323 assert(0 && "Windows not supported on ARM");
325 return new ELFARMAsmBackend(T, Triple(TT).getOS());