1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/DebugInfo.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ELF.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/TargetRegistry.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/Mangler.h"
54 #include "llvm/Target/TargetMachine.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
73 class AsmAttributeEmitter : public AttributeEmitter {
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
113 StringRef StringValue;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
129 Size += sizeof(int8_t); // Is this really necessary?
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
172 ContentsSize += getULEBSize(Attribute);
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag);
199 default: llvm_unreachable("Invalid attribute type");
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(item.StringValue.upper());
205 Streamer.EmitIntValue(0, 1); // '\0'
214 } // end of anonymous namespace
216 /// EmitDwarfRegOp - Emit dwarf register operation.
217 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
218 bool Indirect) const {
219 const TargetRegisterInfo *RI = TM.getRegisterInfo();
220 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
221 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
224 assert(MLoc.isReg() && !Indirect &&
225 "This doesn't support offset/indirection - implement it if needed");
226 unsigned Reg = MLoc.getReg();
227 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
228 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
229 // S registers are described as bit-pieces of a register
230 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
231 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
233 unsigned SReg = Reg - ARM::S0;
234 bool odd = SReg & 0x1;
235 unsigned Rx = 256 + (SReg >> 1);
237 OutStreamer.AddComment("DW_OP_regx for S register");
238 EmitInt8(dwarf::DW_OP_regx);
240 OutStreamer.AddComment(Twine(SReg));
244 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
245 EmitInt8(dwarf::DW_OP_bit_piece);
249 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
255 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
256 // Q registers Q0-Q15 are described by composing two D registers together.
257 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
260 unsigned QReg = Reg - ARM::Q0;
261 unsigned D1 = 256 + 2 * QReg;
262 unsigned D2 = D1 + 1;
264 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
265 EmitInt8(dwarf::DW_OP_regx);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
271 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
272 EmitInt8(dwarf::DW_OP_regx);
274 OutStreamer.AddComment("DW_OP_piece 8");
275 EmitInt8(dwarf::DW_OP_piece);
280 void ARMAsmPrinter::EmitFunctionBodyEnd() {
281 // Make sure to terminate any constant pools that were at the end
285 InConstantPool = false;
286 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
289 void ARMAsmPrinter::EmitFunctionEntryLabel() {
290 if (AFI->isThumbFunction()) {
291 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
292 OutStreamer.EmitThumbFunc(CurrentFnSym);
295 OutStreamer.EmitLabel(CurrentFnSym);
298 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
299 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
300 assert(Size && "C++ constructor pointer had zero size!");
302 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
303 assert(GV && "C++ constructor pointer was not a GlobalValue!");
305 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
306 (Subtarget->isTargetDarwin()
307 ? MCSymbolRefExpr::VK_None
308 : MCSymbolRefExpr::VK_ARM_TARGET1),
311 OutStreamer.EmitValue(E, Size);
314 /// runOnMachineFunction - This uses the EmitInstruction()
315 /// method to print assembly for each instruction.
317 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
318 AFI = MF.getInfo<ARMFunctionInfo>();
319 MCP = MF.getConstantPool();
321 return AsmPrinter::runOnMachineFunction(MF);
324 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
325 raw_ostream &O, const char *Modifier) {
326 const MachineOperand &MO = MI->getOperand(OpNum);
327 unsigned TF = MO.getTargetFlags();
329 switch (MO.getType()) {
330 default: llvm_unreachable("<unknown operand type>");
331 case MachineOperand::MO_Register: {
332 unsigned Reg = MO.getReg();
333 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
334 assert(!MO.getSubReg() && "Subregs should be eliminated!");
335 if(ARM::GPRPairRegClass.contains(Reg)) {
336 const MachineFunction &MF = *MI->getParent()->getParent();
337 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
338 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
340 O << ARMInstPrinter::getRegisterName(Reg);
343 case MachineOperand::MO_Immediate: {
344 int64_t Imm = MO.getImm();
346 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
347 (TF == ARMII::MO_LO16))
349 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
350 (TF == ARMII::MO_HI16))
355 case MachineOperand::MO_MachineBasicBlock:
356 O << *MO.getMBB()->getSymbol();
358 case MachineOperand::MO_GlobalAddress: {
359 const GlobalValue *GV = MO.getGlobal();
360 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
361 (TF & ARMII::MO_LO16))
363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
364 (TF & ARMII::MO_HI16))
366 O << *Mang->getSymbol(GV);
368 printOffset(MO.getOffset(), O);
369 if (TF == ARMII::MO_PLT)
373 case MachineOperand::MO_ExternalSymbol: {
374 O << *GetExternalSymbolSymbol(MO.getSymbolName());
375 if (TF == ARMII::MO_PLT)
379 case MachineOperand::MO_ConstantPoolIndex:
380 O << *GetCPISymbol(MO.getIndex());
382 case MachineOperand::MO_JumpTableIndex:
383 O << *GetJTISymbol(MO.getIndex());
388 //===--------------------------------------------------------------------===//
390 MCSymbol *ARMAsmPrinter::
391 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
392 SmallString<60> Name;
393 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
394 << getFunctionNumber() << '_' << uid << '_' << uid2;
395 return OutContext.GetOrCreateSymbol(Name.str());
399 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
400 SmallString<60> Name;
401 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
402 << getFunctionNumber();
403 return OutContext.GetOrCreateSymbol(Name.str());
406 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
407 unsigned AsmVariant, const char *ExtraCode,
409 // Does this asm operand have a single letter operand modifier?
410 if (ExtraCode && ExtraCode[0]) {
411 if (ExtraCode[1] != 0) return true; // Unknown modifier.
413 switch (ExtraCode[0]) {
415 // See if this is a generic print operand
416 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
417 case 'a': // Print as a memory address.
418 if (MI->getOperand(OpNum).isReg()) {
420 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
425 case 'c': // Don't print "#" before an immediate operand.
426 if (!MI->getOperand(OpNum).isImm())
428 O << MI->getOperand(OpNum).getImm();
430 case 'P': // Print a VFP double precision register.
431 case 'q': // Print a NEON quad precision register.
432 printOperand(MI, OpNum, O);
434 case 'y': // Print a VFP single precision register as indexed double.
435 if (MI->getOperand(OpNum).isReg()) {
436 unsigned Reg = MI->getOperand(OpNum).getReg();
437 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
438 // Find the 'd' register that has this 's' register as a sub-register,
439 // and determine the lane number.
440 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
441 if (!ARM::DPRRegClass.contains(*SR))
443 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
444 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
449 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
450 if (!MI->getOperand(OpNum).isImm())
452 O << ~(MI->getOperand(OpNum).getImm());
454 case 'L': // The low 16 bits of an immediate constant.
455 if (!MI->getOperand(OpNum).isImm())
457 O << (MI->getOperand(OpNum).getImm() & 0xffff);
459 case 'M': { // A register range suitable for LDM/STM.
460 if (!MI->getOperand(OpNum).isReg())
462 const MachineOperand &MO = MI->getOperand(OpNum);
463 unsigned RegBegin = MO.getReg();
464 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
465 // already got the operands in registers that are operands to the
466 // inline asm statement.
468 if (ARM::GPRPairRegClass.contains(RegBegin)) {
469 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
470 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
471 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
472 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
474 O << ARMInstPrinter::getRegisterName(RegBegin);
476 // FIXME: The register allocator not only may not have given us the
477 // registers in sequence, but may not be in ascending registers. This
478 // will require changes in the register allocator that'll need to be
479 // propagated down here if the operands change.
480 unsigned RegOps = OpNum + 1;
481 while (MI->getOperand(RegOps).isReg()) {
483 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
491 case 'R': // The most significant register of a pair.
492 case 'Q': { // The least significant register of a pair.
495 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
496 if (!FlagsOP.isImm())
498 unsigned Flags = FlagsOP.getImm();
499 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
501 InlineAsm::hasRegClassConstraint(Flags, RC);
502 if (RC == ARM::GPRPairRegClassID) {
505 const MachineOperand &MO = MI->getOperand(OpNum);
508 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
509 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
510 ARM::gsub_0 : ARM::gsub_1);
511 O << ARMInstPrinter::getRegisterName(Reg);
516 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
517 if (RegOp >= MI->getNumOperands())
519 const MachineOperand &MO = MI->getOperand(RegOp);
522 unsigned Reg = MO.getReg();
523 O << ARMInstPrinter::getRegisterName(Reg);
527 case 'e': // The low doubleword register of a NEON quad register.
528 case 'f': { // The high doubleword register of a NEON quad register.
529 if (!MI->getOperand(OpNum).isReg())
531 unsigned Reg = MI->getOperand(OpNum).getReg();
532 if (!ARM::QPRRegClass.contains(Reg))
534 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
535 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
536 ARM::dsub_0 : ARM::dsub_1);
537 O << ARMInstPrinter::getRegisterName(SubReg);
541 // This modifier is not yet supported.
542 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
544 case 'H': { // The highest-numbered register of a pair.
545 const MachineOperand &MO = MI->getOperand(OpNum);
548 const MachineFunction &MF = *MI->getParent()->getParent();
549 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
550 unsigned Reg = MO.getReg();
551 if(!ARM::GPRPairRegClass.contains(Reg))
553 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
554 O << ARMInstPrinter::getRegisterName(Reg);
560 printOperand(MI, OpNum, O);
564 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
565 unsigned OpNum, unsigned AsmVariant,
566 const char *ExtraCode,
568 // Does this asm operand have a single letter operand modifier?
569 if (ExtraCode && ExtraCode[0]) {
570 if (ExtraCode[1] != 0) return true; // Unknown modifier.
572 switch (ExtraCode[0]) {
573 case 'A': // A memory operand for a VLD1/VST1 instruction.
574 default: return true; // Unknown modifier.
575 case 'm': // The base register of a memory operand.
576 if (!MI->getOperand(OpNum).isReg())
578 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
583 const MachineOperand &MO = MI->getOperand(OpNum);
584 assert(MO.isReg() && "unexpected inline asm memory operand");
585 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
589 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
590 if (Subtarget->isTargetDarwin()) {
591 Reloc::Model RelocM = TM.getRelocationModel();
592 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
593 // Declare all the text sections up front (before the DWARF sections
594 // emitted by AsmPrinter::doInitialization) so the assembler will keep
595 // them together at the beginning of the object file. This helps
596 // avoid out-of-range branches that are due a fundamental limitation of
597 // the way symbol offsets are encoded with the current Darwin ARM
599 const TargetLoweringObjectFileMachO &TLOFMacho =
600 static_cast<const TargetLoweringObjectFileMachO &>(
601 getObjFileLowering());
603 // Collect the set of sections our functions will go into.
604 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
605 SmallPtrSet<const MCSection *, 8> > TextSections;
606 // Default text section comes first.
607 TextSections.insert(TLOFMacho.getTextSection());
608 // Now any user defined text sections from function attributes.
609 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
610 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
611 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
612 // Now the coalescable sections.
613 TextSections.insert(TLOFMacho.getTextCoalSection());
614 TextSections.insert(TLOFMacho.getConstTextCoalSection());
616 // Emit the sections in the .s file header to fix the order.
617 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
618 OutStreamer.SwitchSection(TextSections[i]);
620 if (RelocM == Reloc::DynamicNoPIC) {
621 const MCSection *sect =
622 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
623 MCSectionMachO::S_SYMBOL_STUBS,
624 12, SectionKind::getText());
625 OutStreamer.SwitchSection(sect);
627 const MCSection *sect =
628 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
629 MCSectionMachO::S_SYMBOL_STUBS,
630 16, SectionKind::getText());
631 OutStreamer.SwitchSection(sect);
633 const MCSection *StaticInitSect =
634 OutContext.getMachOSection("__TEXT", "__StaticInit",
635 MCSectionMachO::S_REGULAR |
636 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
637 SectionKind::getText());
638 OutStreamer.SwitchSection(StaticInitSect);
642 // Use unified assembler syntax.
643 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
645 // Emit ARM Build Attributes
646 if (Subtarget->isTargetELF())
651 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
652 if (Subtarget->isTargetDarwin()) {
653 // All darwin targets use mach-o.
654 const TargetLoweringObjectFileMachO &TLOFMacho =
655 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
656 MachineModuleInfoMachO &MMIMacho =
657 MMI->getObjFileInfo<MachineModuleInfoMachO>();
659 // Output non-lazy-pointers for external and common global variables.
660 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
662 if (!Stubs.empty()) {
663 // Switch with ".non_lazy_symbol_pointer" directive.
664 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
666 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
668 OutStreamer.EmitLabel(Stubs[i].first);
669 // .indirect_symbol _foo
670 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
671 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
674 // External to current translation unit.
675 OutStreamer.EmitIntValue(0, 4/*size*/);
677 // Internal to current translation unit.
679 // When we place the LSDA into the TEXT section, the type info
680 // pointers need to be indirect and pc-rel. We accomplish this by
681 // using NLPs; however, sometimes the types are local to the file.
682 // We need to fill in the value for the NLP in those cases.
683 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
689 OutStreamer.AddBlankLine();
692 Stubs = MMIMacho.GetHiddenGVStubList();
693 if (!Stubs.empty()) {
694 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
696 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
698 OutStreamer.EmitLabel(Stubs[i].first);
700 OutStreamer.EmitValue(MCSymbolRefExpr::
701 Create(Stubs[i].second.getPointer(),
707 OutStreamer.AddBlankLine();
710 // Funny Darwin hack: This flag tells the linker that no global symbols
711 // contain code that falls through to other global symbols (e.g. the obvious
712 // implementation of multiple entry points). If this doesn't occur, the
713 // linker can safely perform dead code stripping. Since LLVM never
714 // generates code that does this, it is always safe to set.
715 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
717 // FIXME: This should eventually end up somewhere else where more
718 // intelligent flag decisions can be made. For now we are just maintaining
719 // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
720 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&OutStreamer))
721 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
724 //===----------------------------------------------------------------------===//
725 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
727 // The following seem like one-off assembler flags, but they actually need
728 // to appear in the .ARM.attributes section in ELF.
729 // Instead of subclassing the MCELFStreamer, we do the work here.
731 void ARMAsmPrinter::emitAttributes() {
733 emitARMAttributeSection();
735 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
736 bool emitFPU = false;
737 AttributeEmitter *AttrEmitter;
738 if (OutStreamer.hasRawTextSupport()) {
739 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
742 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
743 AttrEmitter = new ObjectAttributeEmitter(O);
746 AttrEmitter->MaybeSwitchVendor("aeabi");
748 std::string CPUString = Subtarget->getCPUString();
750 if (CPUString == "cortex-a8" ||
751 Subtarget->isCortexA8()) {
752 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
753 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
754 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
755 ARMBuildAttrs::ApplicationProfile);
756 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
757 ARMBuildAttrs::Allowed);
758 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
759 ARMBuildAttrs::AllowThumb32);
760 // Fixme: figure out when this is emitted.
761 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
762 // ARMBuildAttrs::AllowWMMXv1);
765 /// ADD additional Else-cases here!
766 } else if (CPUString == "xscale") {
767 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
768 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
769 ARMBuildAttrs::Allowed);
770 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
771 ARMBuildAttrs::Allowed);
772 } else if (Subtarget->hasV8Ops())
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v8);
774 else if (Subtarget->hasV7Ops()) {
775 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
776 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
777 ARMBuildAttrs::AllowThumb32);
778 } else if (Subtarget->hasV6T2Ops())
779 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2);
780 else if (Subtarget->hasV6Ops())
781 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6);
782 else if (Subtarget->hasV5TEOps())
783 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE);
784 else if (Subtarget->hasV5TOps())
785 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T);
786 else if (Subtarget->hasV4TOps())
787 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
789 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4);
791 if (Subtarget->hasNEON() && emitFPU) {
792 /* NEON is not exactly a VFP architecture, but GAS emit one of
793 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
794 if (Subtarget->hasVFP4())
795 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
798 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
799 /* If emitted for NEON, omit from VFP below, since you can have both
800 * NEON and VFP in build attributes but only one .fpu */
805 if (Subtarget->hasV8FP()) {
806 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
807 ARMBuildAttrs::AllowV8FPA);
809 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "v8fp");
811 } else if (Subtarget->hasVFP4()) {
812 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
813 ARMBuildAttrs::AllowFPv4A);
815 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
818 } else if (Subtarget->hasVFP3()) {
819 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
820 ARMBuildAttrs::AllowFPv3A);
822 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
825 } else if (Subtarget->hasVFP2()) {
826 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
827 ARMBuildAttrs::AllowFPv2);
829 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
832 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
833 * since NEON can have 1 (allowed) or 2 (MAC operations) */
834 if (Subtarget->hasNEON()) {
835 if (Subtarget->hasV8Ops())
836 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
837 ARMBuildAttrs::AllowedNeonV8);
839 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
840 ARMBuildAttrs::Allowed);
843 // Signal various FP modes.
844 if (!TM.Options.UnsafeFPMath) {
845 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
846 ARMBuildAttrs::Allowed);
847 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
848 ARMBuildAttrs::Allowed);
851 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
852 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
853 ARMBuildAttrs::Allowed);
855 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
856 ARMBuildAttrs::AllowIEE754);
858 // FIXME: add more flags to ARMBuildAttrs.h
859 // 8-bytes alignment stuff.
860 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
861 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
863 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
864 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
865 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
866 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
868 // FIXME: Should we signal R9 usage?
870 if (Subtarget->hasDivide())
871 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
873 AttrEmitter->Finish();
877 void ARMAsmPrinter::emitARMAttributeSection() {
879 // [ <section-length> "vendor-name"
880 // [ <file-tag> <size> <attribute>*
881 // | <section-tag> <size> <section-number>* 0 <attribute>*
882 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
886 if (OutStreamer.hasRawTextSupport())
889 const ARMElfTargetObjectFile &TLOFELF =
890 static_cast<const ARMElfTargetObjectFile &>
891 (getObjFileLowering());
893 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
896 OutStreamer.EmitIntValue(0x41, 1);
899 //===----------------------------------------------------------------------===//
901 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
902 unsigned LabelId, MCContext &Ctx) {
904 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
905 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
909 static MCSymbolRefExpr::VariantKind
910 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
912 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
913 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
914 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
915 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
916 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
917 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
919 llvm_unreachable("Invalid ARMCPModifier!");
922 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
923 bool isIndirect = Subtarget->isTargetDarwin() &&
924 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
926 return Mang->getSymbol(GV);
928 // FIXME: Remove this when Darwin transition to @GOT like syntax.
929 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
930 MachineModuleInfoMachO &MMIMachO =
931 MMI->getObjFileInfo<MachineModuleInfoMachO>();
932 MachineModuleInfoImpl::StubValueTy &StubSym =
933 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
934 MMIMachO.getGVStubEntry(MCSym);
935 if (StubSym.getPointer() == 0)
936 StubSym = MachineModuleInfoImpl::
937 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
942 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
943 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
945 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
948 if (ACPV->isLSDA()) {
949 SmallString<128> Str;
950 raw_svector_ostream OS(Str);
951 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
952 MCSym = OutContext.GetOrCreateSymbol(OS.str());
953 } else if (ACPV->isBlockAddress()) {
954 const BlockAddress *BA =
955 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
956 MCSym = GetBlockAddressSymbol(BA);
957 } else if (ACPV->isGlobalValue()) {
958 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
959 MCSym = GetARMGVSymbol(GV);
960 } else if (ACPV->isMachineBasicBlock()) {
961 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
962 MCSym = MBB->getSymbol();
964 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
965 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
966 MCSym = GetExternalSymbolSymbol(Sym);
969 // Create an MCSymbol for the reference.
971 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
974 if (ACPV->getPCAdjustment()) {
975 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
979 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
981 MCBinaryExpr::CreateAdd(PCRelExpr,
982 MCConstantExpr::Create(ACPV->getPCAdjustment(),
985 if (ACPV->mustAddCurrentAddress()) {
986 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
987 // label, so just emit a local label end reference that instead.
988 MCSymbol *DotSym = OutContext.CreateTempSymbol();
989 OutStreamer.EmitLabel(DotSym);
990 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
991 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
993 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
995 OutStreamer.EmitValue(Expr, Size);
998 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
999 unsigned Opcode = MI->getOpcode();
1001 if (Opcode == ARM::BR_JTadd)
1003 else if (Opcode == ARM::BR_JTm)
1006 const MachineOperand &MO1 = MI->getOperand(OpNum);
1007 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1008 unsigned JTI = MO1.getIndex();
1010 // Emit a label for the jump table.
1011 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1012 OutStreamer.EmitLabel(JTISymbol);
1014 // Mark the jump table as data-in-code.
1015 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
1017 // Emit each entry of the table.
1018 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1019 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1020 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1022 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1023 MachineBasicBlock *MBB = JTBBs[i];
1024 // Construct an MCExpr for the entry. We want a value of the form:
1025 // (BasicBlockAddr - TableBeginAddr)
1027 // For example, a table with entries jumping to basic blocks BB0 and BB1
1030 // .word (LBB0 - LJTI_0_0)
1031 // .word (LBB1 - LJTI_0_0)
1032 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1034 if (TM.getRelocationModel() == Reloc::PIC_)
1035 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1038 // If we're generating a table of Thumb addresses in static relocation
1039 // model, we need to add one to keep interworking correctly.
1040 else if (AFI->isThumbFunction())
1041 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1043 OutStreamer.EmitValue(Expr, 4);
1045 // Mark the end of jump table data-in-code region.
1046 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1049 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1050 unsigned Opcode = MI->getOpcode();
1051 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1052 const MachineOperand &MO1 = MI->getOperand(OpNum);
1053 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1054 unsigned JTI = MO1.getIndex();
1056 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1057 OutStreamer.EmitLabel(JTISymbol);
1059 // Emit each entry of the table.
1060 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1061 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1062 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1063 unsigned OffsetWidth = 4;
1064 if (MI->getOpcode() == ARM::t2TBB_JT) {
1066 // Mark the jump table as data-in-code.
1067 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1068 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1070 // Mark the jump table as data-in-code.
1071 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1074 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1075 MachineBasicBlock *MBB = JTBBs[i];
1076 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1078 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1079 if (OffsetWidth == 4) {
1080 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
1081 .addExpr(MBBSymbolExpr)
1086 // Otherwise it's an offset from the dispatch instruction. Construct an
1087 // MCExpr for the entry. We want a value of the form:
1088 // (BasicBlockAddr - TableBeginAddr) / 2
1090 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1093 // .byte (LBB0 - LJTI_0_0) / 2
1094 // .byte (LBB1 - LJTI_0_0) / 2
1095 const MCExpr *Expr =
1096 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1097 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1099 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1101 OutStreamer.EmitValue(Expr, OffsetWidth);
1103 // Mark the end of jump table data-in-code region. 32-bit offsets use
1104 // actual branch instructions here, so we don't mark those as a data-region
1106 if (OffsetWidth != 4)
1107 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1110 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1111 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1112 "Only instruction which are involved into frame setup code are allowed");
1114 const MachineFunction &MF = *MI->getParent()->getParent();
1115 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1116 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1118 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1119 unsigned Opc = MI->getOpcode();
1120 unsigned SrcReg, DstReg;
1122 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1123 // Two special cases:
1124 // 1) tPUSH does not have src/dst regs.
1125 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1126 // load. Yes, this is pretty fragile, but for now I don't see better
1128 SrcReg = DstReg = ARM::SP;
1130 SrcReg = MI->getOperand(1).getReg();
1131 DstReg = MI->getOperand(0).getReg();
1134 // Try to figure out the unwinding opcode out of src / dst regs.
1135 if (MI->mayStore()) {
1137 assert(DstReg == ARM::SP &&
1138 "Only stack pointer as a destination reg is supported");
1140 SmallVector<unsigned, 4> RegList;
1141 // Skip src & dst reg, and pred ops.
1142 unsigned StartOp = 2 + 2;
1143 // Use all the operands.
1144 unsigned NumOffset = 0;
1149 llvm_unreachable("Unsupported opcode for unwinding information");
1151 // Special case here: no src & dst reg, but two extra imp ops.
1152 StartOp = 2; NumOffset = 2;
1153 case ARM::STMDB_UPD:
1154 case ARM::t2STMDB_UPD:
1155 case ARM::VSTMDDB_UPD:
1156 assert(SrcReg == ARM::SP &&
1157 "Only stack pointer as a source reg is supported");
1158 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1160 const MachineOperand &MO = MI->getOperand(i);
1161 // Actually, there should never be any impdef stuff here. Skip it
1162 // temporary to workaround PR11902.
1163 if (MO.isImplicit())
1165 RegList.push_back(MO.getReg());
1168 case ARM::STR_PRE_IMM:
1169 case ARM::STR_PRE_REG:
1170 case ARM::t2STR_PRE:
1171 assert(MI->getOperand(2).getReg() == ARM::SP &&
1172 "Only stack pointer as a source reg is supported");
1173 RegList.push_back(SrcReg);
1176 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1178 // Changes of stack / frame pointer.
1179 if (SrcReg == ARM::SP) {
1184 llvm_unreachable("Unsupported opcode for unwinding information");
1190 Offset = -MI->getOperand(2).getImm();
1194 Offset = MI->getOperand(2).getImm();
1197 Offset = MI->getOperand(2).getImm()*4;
1201 Offset = -MI->getOperand(2).getImm()*4;
1203 case ARM::tLDRpci: {
1204 // Grab the constpool index and check, whether it corresponds to
1205 // original or cloned constpool entry.
1206 unsigned CPI = MI->getOperand(1).getIndex();
1207 const MachineConstantPool *MCP = MF.getConstantPool();
1208 if (CPI >= MCP->getConstants().size())
1209 CPI = AFI.getOriginalCPIdx(CPI);
1210 assert(CPI != -1U && "Invalid constpool index");
1212 // Derive the actual offset.
1213 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1214 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1215 // FIXME: Check for user, it should be "add" instruction!
1216 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1221 if (DstReg == FramePtr && FramePtr != ARM::SP)
1222 // Set-up of the frame pointer. Positive values correspond to "add"
1224 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1225 else if (DstReg == ARM::SP) {
1226 // Change of SP by an offset. Positive values correspond to "sub"
1228 OutStreamer.EmitPad(Offset);
1231 llvm_unreachable("Unsupported opcode for unwinding information");
1233 } else if (DstReg == ARM::SP) {
1234 // FIXME: .movsp goes here
1236 llvm_unreachable("Unsupported opcode for unwinding information");
1240 llvm_unreachable("Unsupported opcode for unwinding information");
1245 extern cl::opt<bool> EnableARMEHABI;
1247 // Simple pseudo-instructions have their lowering (with expansion to real
1248 // instructions) auto-generated.
1249 #include "ARMGenMCPseudoLowering.inc"
1251 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1252 // If we just ended a constant pool, mark it as such.
1253 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1254 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1255 InConstantPool = false;
1258 // Emit unwinding stuff for frame-related instructions
1259 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1260 EmitUnwindingInstruction(MI);
1262 // Do any auto-generated pseudo lowerings.
1263 if (emitPseudoExpansionLowering(OutStreamer, MI))
1266 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1267 "Pseudo flag setting opcode should be expanded early");
1269 // Check for manual lowerings.
1270 unsigned Opc = MI->getOpcode();
1272 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1273 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1275 case ARM::tLEApcrel:
1276 case ARM::t2LEApcrel: {
1277 // FIXME: Need to also handle globals and externals
1278 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1279 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1280 ARM::t2LEApcrel ? ARM::t2ADR
1281 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1283 .addReg(MI->getOperand(0).getReg())
1284 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1285 // Add predicate operands.
1286 .addImm(MI->getOperand(2).getImm())
1287 .addReg(MI->getOperand(3).getReg()));
1290 case ARM::LEApcrelJT:
1291 case ARM::tLEApcrelJT:
1292 case ARM::t2LEApcrelJT: {
1293 MCSymbol *JTIPICSymbol =
1294 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1295 MI->getOperand(2).getImm());
1296 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1297 ARM::t2LEApcrelJT ? ARM::t2ADR
1298 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1300 .addReg(MI->getOperand(0).getReg())
1301 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1302 // Add predicate operands.
1303 .addImm(MI->getOperand(3).getImm())
1304 .addReg(MI->getOperand(4).getReg()));
1307 // Darwin call instructions are just normal call instructions with different
1308 // clobber semantics (they clobber R9).
1309 case ARM::BX_CALL: {
1310 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1313 // Add predicate operands.
1316 // Add 's' bit operand (always reg0 for this)
1319 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1320 .addReg(MI->getOperand(0).getReg()));
1323 case ARM::tBX_CALL: {
1324 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1327 // Add predicate operands.
1331 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1332 .addReg(MI->getOperand(0).getReg())
1333 // Add predicate operands.
1338 case ARM::BMOVPCRX_CALL: {
1339 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1342 // Add predicate operands.
1345 // Add 's' bit operand (always reg0 for this)
1348 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1350 .addReg(MI->getOperand(0).getReg())
1351 // Add predicate operands.
1354 // Add 's' bit operand (always reg0 for this)
1358 case ARM::BMOVPCB_CALL: {
1359 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1362 // Add predicate operands.
1365 // Add 's' bit operand (always reg0 for this)
1368 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1369 MCSymbol *GVSym = Mang->getSymbol(GV);
1370 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1371 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1373 // Add predicate operands.
1378 case ARM::MOVi16_ga_pcrel:
1379 case ARM::t2MOVi16_ga_pcrel: {
1381 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1382 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1384 unsigned TF = MI->getOperand(1).getTargetFlags();
1385 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1386 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1387 MCSymbol *GVSym = GetARMGVSymbol(GV);
1388 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1390 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1391 getFunctionNumber(),
1392 MI->getOperand(2).getImm(), OutContext);
1393 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1394 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1395 const MCExpr *PCRelExpr =
1396 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1397 MCBinaryExpr::CreateAdd(LabelSymExpr,
1398 MCConstantExpr::Create(PCAdj, OutContext),
1399 OutContext), OutContext), OutContext);
1400 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1402 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1403 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1406 // Add predicate operands.
1407 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1408 TmpInst.addOperand(MCOperand::CreateReg(0));
1409 // Add 's' bit operand (always reg0 for this)
1410 TmpInst.addOperand(MCOperand::CreateReg(0));
1411 OutStreamer.EmitInstruction(TmpInst);
1414 case ARM::MOVTi16_ga_pcrel:
1415 case ARM::t2MOVTi16_ga_pcrel: {
1417 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1418 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1419 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1420 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1422 unsigned TF = MI->getOperand(2).getTargetFlags();
1423 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1424 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1425 MCSymbol *GVSym = GetARMGVSymbol(GV);
1426 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1428 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1429 getFunctionNumber(),
1430 MI->getOperand(3).getImm(), OutContext);
1431 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1432 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1433 const MCExpr *PCRelExpr =
1434 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1435 MCBinaryExpr::CreateAdd(LabelSymExpr,
1436 MCConstantExpr::Create(PCAdj, OutContext),
1437 OutContext), OutContext), OutContext);
1438 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1440 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1441 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1443 // Add predicate operands.
1444 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1445 TmpInst.addOperand(MCOperand::CreateReg(0));
1446 // Add 's' bit operand (always reg0 for this)
1447 TmpInst.addOperand(MCOperand::CreateReg(0));
1448 OutStreamer.EmitInstruction(TmpInst);
1451 case ARM::tPICADD: {
1452 // This is a pseudo op for a label + instruction sequence, which looks like:
1455 // This adds the address of LPC0 to r0.
1458 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1459 getFunctionNumber(), MI->getOperand(2).getImm(),
1462 // Form and emit the add.
1463 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1464 .addReg(MI->getOperand(0).getReg())
1465 .addReg(MI->getOperand(0).getReg())
1467 // Add predicate operands.
1473 // This is a pseudo op for a label + instruction sequence, which looks like:
1476 // This adds the address of LPC0 to r0.
1479 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1480 getFunctionNumber(), MI->getOperand(2).getImm(),
1483 // Form and emit the add.
1484 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1485 .addReg(MI->getOperand(0).getReg())
1487 .addReg(MI->getOperand(1).getReg())
1488 // Add predicate operands.
1489 .addImm(MI->getOperand(3).getImm())
1490 .addReg(MI->getOperand(4).getReg())
1491 // Add 's' bit operand (always reg0 for this)
1502 case ARM::PICLDRSH: {
1503 // This is a pseudo op for a label + instruction sequence, which looks like:
1506 // The LCP0 label is referenced by a constant pool entry in order to get
1507 // a PC-relative address at the ldr instruction.
1510 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1511 getFunctionNumber(), MI->getOperand(2).getImm(),
1514 // Form and emit the load
1516 switch (MI->getOpcode()) {
1518 llvm_unreachable("Unexpected opcode!");
1519 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1520 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1521 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1522 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1523 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1524 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1525 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1526 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1528 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1529 .addReg(MI->getOperand(0).getReg())
1531 .addReg(MI->getOperand(1).getReg())
1533 // Add predicate operands.
1534 .addImm(MI->getOperand(3).getImm())
1535 .addReg(MI->getOperand(4).getReg()));
1539 case ARM::CONSTPOOL_ENTRY: {
1540 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1541 /// in the function. The first operand is the ID# for this instruction, the
1542 /// second is the index into the MachineConstantPool that this is, the third
1543 /// is the size in bytes of this constant pool entry.
1544 /// The required alignment is specified on the basic block holding this MI.
1545 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1546 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1548 // If this is the first entry of the pool, mark it.
1549 if (!InConstantPool) {
1550 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1551 InConstantPool = true;
1554 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1556 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1557 if (MCPE.isMachineConstantPoolEntry())
1558 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1560 EmitGlobalConstant(MCPE.Val.ConstVal);
1563 case ARM::t2BR_JT: {
1564 // Lower and emit the instruction itself, then the jump table following it.
1565 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1567 .addReg(MI->getOperand(0).getReg())
1568 // Add predicate operands.
1572 // Output the data for the jump table itself
1576 case ARM::t2TBB_JT: {
1577 // Lower and emit the instruction itself, then the jump table following it.
1578 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1580 .addReg(MI->getOperand(0).getReg())
1581 // Add predicate operands.
1585 // Output the data for the jump table itself
1587 // Make sure the next instruction is 2-byte aligned.
1591 case ARM::t2TBH_JT: {
1592 // Lower and emit the instruction itself, then the jump table following it.
1593 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1595 .addReg(MI->getOperand(0).getReg())
1596 // Add predicate operands.
1600 // Output the data for the jump table itself
1606 // Lower and emit the instruction itself, then the jump table following it.
1609 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1610 ARM::MOVr : ARM::tMOVr;
1611 TmpInst.setOpcode(Opc);
1612 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1613 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1614 // Add predicate operands.
1615 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1616 TmpInst.addOperand(MCOperand::CreateReg(0));
1617 // Add 's' bit operand (always reg0 for this)
1618 if (Opc == ARM::MOVr)
1619 TmpInst.addOperand(MCOperand::CreateReg(0));
1620 OutStreamer.EmitInstruction(TmpInst);
1622 // Make sure the Thumb jump table is 4-byte aligned.
1623 if (Opc == ARM::tMOVr)
1626 // Output the data for the jump table itself
1631 // Lower and emit the instruction itself, then the jump table following it.
1634 if (MI->getOperand(1).getReg() == 0) {
1636 TmpInst.setOpcode(ARM::LDRi12);
1637 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1638 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1639 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1641 TmpInst.setOpcode(ARM::LDRrs);
1642 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1643 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1644 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1645 TmpInst.addOperand(MCOperand::CreateImm(0));
1647 // Add predicate operands.
1648 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1649 TmpInst.addOperand(MCOperand::CreateReg(0));
1650 OutStreamer.EmitInstruction(TmpInst);
1652 // Output the data for the jump table itself
1656 case ARM::BR_JTadd: {
1657 // Lower and emit the instruction itself, then the jump table following it.
1658 // add pc, target, idx
1659 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1661 .addReg(MI->getOperand(0).getReg())
1662 .addReg(MI->getOperand(1).getReg())
1663 // Add predicate operands.
1666 // Add 's' bit operand (always reg0 for this)
1669 // Output the data for the jump table itself
1674 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1675 // FIXME: Remove this special case when they do.
1676 if (!Subtarget->isTargetDarwin()) {
1677 //.long 0xe7ffdefe @ trap
1678 uint32_t Val = 0xe7ffdefeUL;
1679 OutStreamer.AddComment("trap");
1680 OutStreamer.EmitIntValue(Val, 4);
1685 case ARM::TRAPNaCl: {
1686 //.long 0xe7fedef0 @ trap
1687 uint32_t Val = 0xe7fedef0UL;
1688 OutStreamer.AddComment("trap");
1689 OutStreamer.EmitIntValue(Val, 4);
1693 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1694 // FIXME: Remove this special case when they do.
1695 if (!Subtarget->isTargetDarwin()) {
1696 //.short 57086 @ trap
1697 uint16_t Val = 0xdefe;
1698 OutStreamer.AddComment("trap");
1699 OutStreamer.EmitIntValue(Val, 2);
1704 case ARM::t2Int_eh_sjlj_setjmp:
1705 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1706 case ARM::tInt_eh_sjlj_setjmp: {
1707 // Two incoming args: GPR:$src, GPR:$val
1710 // str $val, [$src, #4]
1715 unsigned SrcReg = MI->getOperand(0).getReg();
1716 unsigned ValReg = MI->getOperand(1).getReg();
1717 MCSymbol *Label = GetARMSJLJEHLabel();
1718 OutStreamer.AddComment("eh_setjmp begin");
1719 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1726 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1739 // The offset immediate is #4. The operand value is scaled by 4 for the
1740 // tSTR instruction.
1746 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1754 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1755 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1756 .addExpr(SymbolExpr)
1760 OutStreamer.AddComment("eh_setjmp end");
1761 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1769 OutStreamer.EmitLabel(Label);
1773 case ARM::Int_eh_sjlj_setjmp_nofp:
1774 case ARM::Int_eh_sjlj_setjmp: {
1775 // Two incoming args: GPR:$src, GPR:$val
1777 // str $val, [$src, #+4]
1781 unsigned SrcReg = MI->getOperand(0).getReg();
1782 unsigned ValReg = MI->getOperand(1).getReg();
1784 OutStreamer.AddComment("eh_setjmp begin");
1785 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1792 // 's' bit operand (always reg0 for this).
1795 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1803 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1809 // 's' bit operand (always reg0 for this).
1812 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1819 // 's' bit operand (always reg0 for this).
1822 OutStreamer.AddComment("eh_setjmp end");
1823 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1829 // 's' bit operand (always reg0 for this).
1833 case ARM::Int_eh_sjlj_longjmp: {
1834 // ldr sp, [$src, #8]
1835 // ldr $scratch, [$src, #4]
1838 unsigned SrcReg = MI->getOperand(0).getReg();
1839 unsigned ScratchReg = MI->getOperand(1).getReg();
1840 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1848 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1856 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1864 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1871 case ARM::tInt_eh_sjlj_longjmp: {
1872 // ldr $scratch, [$src, #8]
1874 // ldr $scratch, [$src, #4]
1877 unsigned SrcReg = MI->getOperand(0).getReg();
1878 unsigned ScratchReg = MI->getOperand(1).getReg();
1879 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1882 // The offset immediate is #8. The operand value is scaled by 4 for the
1883 // tLDR instruction.
1889 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1896 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1904 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1912 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1922 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1924 OutStreamer.EmitInstruction(TmpInst);
1927 //===----------------------------------------------------------------------===//
1928 // Target Registry Stuff
1929 //===----------------------------------------------------------------------===//
1931 // Force static initialization.
1932 extern "C" void LLVMInitializeARMAsmPrinter() {
1933 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1934 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);