1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
21 #include "InstPrinter/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DebugInfo.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ARMBuildAttributes.h"
46 #include "llvm/Support/TargetParser.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
61 std::unique_ptr<MCStreamer> Streamer)
62 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
63 InConstantPool(false) {}
65 void ARMAsmPrinter::EmitFunctionBodyEnd() {
66 // Make sure to terminate any constant pools that were at the end
70 InConstantPool = false;
71 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
74 void ARMAsmPrinter::EmitFunctionEntryLabel() {
75 if (AFI->isThumbFunction()) {
76 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
77 OutStreamer->EmitThumbFunc(CurrentFnSym);
80 OutStreamer->EmitLabel(CurrentFnSym);
83 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
84 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!");
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!");
90 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
97 OutStreamer->EmitValue(E, Size);
100 /// runOnMachineFunction - This uses the EmitInstruction()
101 /// method to print assembly for each instruction.
103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
104 AFI = MF.getInfo<ARMFunctionInfo>();
105 MCP = MF.getConstantPool();
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
108 SetupMachineFunction(MF);
110 if (Subtarget->isTargetCOFF()) {
111 bool Internal = MF.getFunction()->hasInternalLinkage();
112 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
113 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
114 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
116 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
117 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
118 OutStreamer->EmitCOFFSymbolType(Type);
119 OutStreamer->EndCOFFSymbolDef();
122 // Emit the rest of the function body.
125 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
126 // These are created per function, rather than per TU, since it's
127 // relatively easy to exceed the thumb branch range within a TU.
128 if (! ThumbIndirectPads.empty()) {
129 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
131 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
132 OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
133 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
134 .addReg(ThumbIndirectPads[i].first)
135 // Add predicate operands.
139 ThumbIndirectPads.clear();
142 // We didn't modify anything.
146 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
148 const MachineOperand &MO = MI->getOperand(OpNum);
149 unsigned TF = MO.getTargetFlags();
151 switch (MO.getType()) {
152 default: llvm_unreachable("<unknown operand type>");
153 case MachineOperand::MO_Register: {
154 unsigned Reg = MO.getReg();
155 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
156 assert(!MO.getSubReg() && "Subregs should be eliminated!");
157 if(ARM::GPRPairRegClass.contains(Reg)) {
158 const MachineFunction &MF = *MI->getParent()->getParent();
159 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
160 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
162 O << ARMInstPrinter::getRegisterName(Reg);
165 case MachineOperand::MO_Immediate: {
166 int64_t Imm = MO.getImm();
168 if (TF == ARMII::MO_LO16)
170 else if (TF == ARMII::MO_HI16)
175 case MachineOperand::MO_MachineBasicBlock:
176 O << *MO.getMBB()->getSymbol();
178 case MachineOperand::MO_GlobalAddress: {
179 const GlobalValue *GV = MO.getGlobal();
180 if (TF & ARMII::MO_LO16)
182 else if (TF & ARMII::MO_HI16)
184 O << *GetARMGVSymbol(GV, TF);
186 printOffset(MO.getOffset(), O);
187 if (TF == ARMII::MO_PLT)
191 case MachineOperand::MO_ConstantPoolIndex:
192 O << *GetCPISymbol(MO.getIndex());
197 //===--------------------------------------------------------------------===//
199 MCSymbol *ARMAsmPrinter::
200 GetARMJTIPICJumpTableLabel(unsigned uid) const {
201 const DataLayout *DL = TM.getDataLayout();
202 SmallString<60> Name;
203 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
204 << getFunctionNumber() << '_' << uid;
205 return OutContext.GetOrCreateSymbol(Name);
209 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
210 const DataLayout *DL = TM.getDataLayout();
211 SmallString<60> Name;
212 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
213 << getFunctionNumber();
214 return OutContext.GetOrCreateSymbol(Name);
217 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
218 unsigned AsmVariant, const char *ExtraCode,
220 // Does this asm operand have a single letter operand modifier?
221 if (ExtraCode && ExtraCode[0]) {
222 if (ExtraCode[1] != 0) return true; // Unknown modifier.
224 switch (ExtraCode[0]) {
226 // See if this is a generic print operand
227 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
228 case 'a': // Print as a memory address.
229 if (MI->getOperand(OpNum).isReg()) {
231 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
236 case 'c': // Don't print "#" before an immediate operand.
237 if (!MI->getOperand(OpNum).isImm())
239 O << MI->getOperand(OpNum).getImm();
241 case 'P': // Print a VFP double precision register.
242 case 'q': // Print a NEON quad precision register.
243 printOperand(MI, OpNum, O);
245 case 'y': // Print a VFP single precision register as indexed double.
246 if (MI->getOperand(OpNum).isReg()) {
247 unsigned Reg = MI->getOperand(OpNum).getReg();
248 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
249 // Find the 'd' register that has this 's' register as a sub-register,
250 // and determine the lane number.
251 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
252 if (!ARM::DPRRegClass.contains(*SR))
254 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
255 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
260 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
261 if (!MI->getOperand(OpNum).isImm())
263 O << ~(MI->getOperand(OpNum).getImm());
265 case 'L': // The low 16 bits of an immediate constant.
266 if (!MI->getOperand(OpNum).isImm())
268 O << (MI->getOperand(OpNum).getImm() & 0xffff);
270 case 'M': { // A register range suitable for LDM/STM.
271 if (!MI->getOperand(OpNum).isReg())
273 const MachineOperand &MO = MI->getOperand(OpNum);
274 unsigned RegBegin = MO.getReg();
275 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
276 // already got the operands in registers that are operands to the
277 // inline asm statement.
279 if (ARM::GPRPairRegClass.contains(RegBegin)) {
280 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
281 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
282 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
283 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
285 O << ARMInstPrinter::getRegisterName(RegBegin);
287 // FIXME: The register allocator not only may not have given us the
288 // registers in sequence, but may not be in ascending registers. This
289 // will require changes in the register allocator that'll need to be
290 // propagated down here if the operands change.
291 unsigned RegOps = OpNum + 1;
292 while (MI->getOperand(RegOps).isReg()) {
294 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
302 case 'R': // The most significant register of a pair.
303 case 'Q': { // The least significant register of a pair.
306 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
307 if (!FlagsOP.isImm())
309 unsigned Flags = FlagsOP.getImm();
311 // This operand may not be the one that actually provides the register. If
312 // it's tied to a previous one then we should refer instead to that one
313 // for registers and their classes.
315 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
316 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
317 unsigned OpFlags = MI->getOperand(OpNum).getImm();
318 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
320 Flags = MI->getOperand(OpNum).getImm();
322 // Later code expects OpNum to be pointing at the register rather than
327 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
329 InlineAsm::hasRegClassConstraint(Flags, RC);
330 if (RC == ARM::GPRPairRegClassID) {
333 const MachineOperand &MO = MI->getOperand(OpNum);
336 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
337 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
338 ARM::gsub_0 : ARM::gsub_1);
339 O << ARMInstPrinter::getRegisterName(Reg);
344 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
345 if (RegOp >= MI->getNumOperands())
347 const MachineOperand &MO = MI->getOperand(RegOp);
350 unsigned Reg = MO.getReg();
351 O << ARMInstPrinter::getRegisterName(Reg);
355 case 'e': // The low doubleword register of a NEON quad register.
356 case 'f': { // The high doubleword register of a NEON quad register.
357 if (!MI->getOperand(OpNum).isReg())
359 unsigned Reg = MI->getOperand(OpNum).getReg();
360 if (!ARM::QPRRegClass.contains(Reg))
362 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
363 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
364 ARM::dsub_0 : ARM::dsub_1);
365 O << ARMInstPrinter::getRegisterName(SubReg);
369 // This modifier is not yet supported.
370 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
372 case 'H': { // The highest-numbered register of a pair.
373 const MachineOperand &MO = MI->getOperand(OpNum);
376 const MachineFunction &MF = *MI->getParent()->getParent();
377 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
378 unsigned Reg = MO.getReg();
379 if(!ARM::GPRPairRegClass.contains(Reg))
381 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
382 O << ARMInstPrinter::getRegisterName(Reg);
388 printOperand(MI, OpNum, O);
392 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
393 unsigned OpNum, unsigned AsmVariant,
394 const char *ExtraCode,
396 // Does this asm operand have a single letter operand modifier?
397 if (ExtraCode && ExtraCode[0]) {
398 if (ExtraCode[1] != 0) return true; // Unknown modifier.
400 switch (ExtraCode[0]) {
401 case 'A': // A memory operand for a VLD1/VST1 instruction.
402 default: return true; // Unknown modifier.
403 case 'm': // The base register of a memory operand.
404 if (!MI->getOperand(OpNum).isReg())
406 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
411 const MachineOperand &MO = MI->getOperand(OpNum);
412 assert(MO.isReg() && "unexpected inline asm memory operand");
413 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
417 static bool isThumb(const MCSubtargetInfo& STI) {
418 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
421 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
422 const MCSubtargetInfo *EndInfo) const {
423 // If either end mode is unknown (EndInfo == NULL) or different than
424 // the start mode, then restore the start mode.
425 const bool WasThumb = isThumb(StartInfo);
426 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
427 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
431 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
432 Triple TT(TM.getTargetTriple());
433 // Use unified assembler syntax.
434 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
436 // Emit ARM Build Attributes
437 if (TT.isOSBinFormatELF())
440 // Use the triple's architecture and subarchitecture to determine
441 // if we're thumb for the purposes of the top level code16 assembler
443 bool isThumb = TT.getArch() == Triple::thumb ||
444 TT.getArch() == Triple::thumbeb ||
445 TT.getSubArch() == Triple::ARMSubArch_v7m ||
446 TT.getSubArch() == Triple::ARMSubArch_v6m;
447 if (!M.getModuleInlineAsm().empty() && isThumb)
448 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
452 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
453 MachineModuleInfoImpl::StubValueTy &MCSym) {
455 OutStreamer.EmitLabel(StubLabel);
456 // .indirect_symbol _foo
457 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
460 // External to current translation unit.
461 OutStreamer.EmitIntValue(0, 4/*size*/);
463 // Internal to current translation unit.
465 // When we place the LSDA into the TEXT section, the type info
466 // pointers need to be indirect and pc-rel. We accomplish this by
467 // using NLPs; however, sometimes the types are local to the file.
468 // We need to fill in the value for the NLP in those cases.
469 OutStreamer.EmitValue(
470 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
475 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
476 Triple TT(TM.getTargetTriple());
477 if (TT.isOSBinFormatMachO()) {
478 // All darwin targets use mach-o.
479 const TargetLoweringObjectFileMachO &TLOFMacho =
480 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
481 MachineModuleInfoMachO &MMIMacho =
482 MMI->getObjFileInfo<MachineModuleInfoMachO>();
484 // Output non-lazy-pointers for external and common global variables.
485 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
487 if (!Stubs.empty()) {
488 // Switch with ".non_lazy_symbol_pointer" directive.
489 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
492 for (auto &Stub : Stubs)
493 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
496 OutStreamer->AddBlankLine();
499 Stubs = MMIMacho.GetHiddenGVStubList();
500 if (!Stubs.empty()) {
501 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
504 for (auto &Stub : Stubs)
505 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
508 OutStreamer->AddBlankLine();
511 // Funny Darwin hack: This flag tells the linker that no global symbols
512 // contain code that falls through to other global symbols (e.g. the obvious
513 // implementation of multiple entry points). If this doesn't occur, the
514 // linker can safely perform dead code stripping. Since LLVM never
515 // generates code that does this, it is always safe to set.
516 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
520 //===----------------------------------------------------------------------===//
521 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
523 // The following seem like one-off assembler flags, but they actually need
524 // to appear in the .ARM.attributes section in ELF.
525 // Instead of subclassing the MCELFStreamer, we do the work here.
527 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
528 const ARMSubtarget *Subtarget) {
530 return ARMBuildAttrs::v5TEJ;
532 if (Subtarget->hasV8Ops())
533 return ARMBuildAttrs::v8;
534 else if (Subtarget->hasV7Ops()) {
535 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
536 return ARMBuildAttrs::v7E_M;
537 return ARMBuildAttrs::v7;
538 } else if (Subtarget->hasV6T2Ops())
539 return ARMBuildAttrs::v6T2;
540 else if (Subtarget->hasV6MOps())
541 return ARMBuildAttrs::v6S_M;
542 else if (Subtarget->hasV6Ops())
543 return ARMBuildAttrs::v6;
544 else if (Subtarget->hasV5TEOps())
545 return ARMBuildAttrs::v5TE;
546 else if (Subtarget->hasV5TOps())
547 return ARMBuildAttrs::v5T;
548 else if (Subtarget->hasV4TOps())
549 return ARMBuildAttrs::v4T;
551 return ARMBuildAttrs::v4;
554 void ARMAsmPrinter::emitAttributes() {
555 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
556 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
558 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
560 ATS.switchVendor("aeabi");
562 // Compute ARM ELF Attributes based on the default subtarget that
563 // we'd have constructed. The existing ARM behavior isn't LTO clean
565 // FIXME: For ifunc related functions we could iterate over and look
566 // for a feature string that doesn't match the default one.
567 StringRef TT = TM.getTargetTriple();
568 StringRef CPU = TM.getTargetCPU();
569 StringRef FS = TM.getTargetFeatureString();
570 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
573 ArchFS = (Twine(ArchFS) + "," + FS).str();
577 const ARMBaseTargetMachine &ATM =
578 static_cast<const ARMBaseTargetMachine &>(TM);
579 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
581 std::string CPUString = STI.getCPUString();
583 if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
584 // FIXME: remove krait check when GNU tools support krait cpu
586 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
587 // We consider krait as a "cortex-a9" + hwdiv CPU
588 // Enable hwdiv through ".arch_extension idiv"
589 if (STI.hasDivide() || STI.hasDivideInARMMode())
590 ATS.emitArchExtension(ARM::AEK_HWDIV);
592 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
595 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
597 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
598 // profile is not applicable (e.g. pre v7, or cross-profile code)".
599 if (STI.hasV7Ops()) {
600 if (STI.isAClass()) {
601 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
602 ARMBuildAttrs::ApplicationProfile);
603 } else if (STI.isRClass()) {
604 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
605 ARMBuildAttrs::RealTimeProfile);
606 } else if (STI.isMClass()) {
607 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
608 ARMBuildAttrs::MicroControllerProfile);
612 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
613 STI.hasARMOps() ? ARMBuildAttrs::Allowed
614 : ARMBuildAttrs::Not_Allowed);
615 if (STI.isThumb1Only()) {
616 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
617 } else if (STI.hasThumb2()) {
618 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
619 ARMBuildAttrs::AllowThumb32);
623 /* NEON is not exactly a VFP architecture, but GAS emit one of
624 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
625 if (STI.hasFPARMv8()) {
627 ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
629 ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
630 } else if (STI.hasVFP4())
631 ATS.emitFPU(ARM::FK_NEON_VFPV4);
633 ATS.emitFPU(ARM::FK_NEON);
634 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
636 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
637 STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
638 ARMBuildAttrs::AllowNeonARMv8);
640 if (STI.hasFPARMv8())
641 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
642 // FPU, but there are two different names for it depending on the CPU.
643 ATS.emitFPU(STI.hasD16() ? ARM::FK_FPV5_D16 : ARM::FK_FP_ARMV8);
644 else if (STI.hasVFP4())
645 ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV4_D16 : ARM::FK_VFPV4);
646 else if (STI.hasVFP3())
647 ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV3_D16 : ARM::FK_VFPV3);
648 else if (STI.hasVFP2())
649 ATS.emitFPU(ARM::FK_VFPV2);
652 if (TM.getRelocationModel() == Reloc::PIC_) {
653 // PIC specific attributes.
654 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
655 ARMBuildAttrs::AddressRWPCRel);
656 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
657 ARMBuildAttrs::AddressROPCRel);
658 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
659 ARMBuildAttrs::AddressGOT);
661 // Allow direct addressing of imported data for all other relocation models.
662 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
663 ARMBuildAttrs::AddressDirect);
666 // Signal various FP modes.
667 if (!TM.Options.UnsafeFPMath) {
668 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
669 ARMBuildAttrs::IEEEDenormals);
670 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
672 // If the user has permitted this code to choose the IEEE 754
673 // rounding at run-time, emit the rounding attribute.
674 if (TM.Options.HonorSignDependentRoundingFPMathOption)
675 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
677 if (!STI.hasVFP2()) {
678 // When the target doesn't have an FPU (by design or
679 // intention), the assumptions made on the software support
680 // mirror that of the equivalent hardware support *if it
681 // existed*. For v7 and better we indicate that denormals are
682 // flushed preserving sign, and for V6 we indicate that
683 // denormals are flushed to positive zero.
685 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
686 ARMBuildAttrs::PreserveFPSign);
687 } else if (STI.hasVFP3()) {
688 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
689 // the sign bit of the zero matches the sign bit of the input or
690 // result that is being flushed to zero.
691 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
692 ARMBuildAttrs::PreserveFPSign);
694 // For VFPv2 implementations it is implementation defined as
695 // to whether denormals are flushed to positive zero or to
696 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
697 // LLVM has chosen to flush this to positive zero (most likely for
698 // GCC compatibility), so that's the chosen value here (the
699 // absence of its emission implies zero).
702 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
703 // equivalent of GCC's -ffinite-math-only flag.
704 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
705 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
706 ARMBuildAttrs::Allowed);
708 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
709 ARMBuildAttrs::AllowIEE754);
711 if (STI.allowsUnalignedMem())
712 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
713 ARMBuildAttrs::Allowed);
715 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
716 ARMBuildAttrs::Not_Allowed);
718 // FIXME: add more flags to ARMBuildAttributes.h
719 // 8-bytes alignment stuff.
720 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
721 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
723 // ABI_HardFP_use attribute to indicate single precision FP.
724 if (STI.isFPOnlySP())
725 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
726 ARMBuildAttrs::HardFPSinglePrecision);
728 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
729 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
730 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
732 // FIXME: Should we signal R9 usage?
735 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
737 // FIXME: To support emitting this build attribute as GCC does, the
738 // -mfp16-format option and associated plumbing must be
739 // supported. For now the __fp16 type is exposed by default, so this
740 // attribute should be emitted with value 1.
741 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
742 ARMBuildAttrs::FP16FormatIEEE);
744 if (STI.hasMPExtension())
745 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
747 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
748 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
749 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
750 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
751 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
752 // otherwise, the default value (AllowDIVIfExists) applies.
753 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
754 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
757 if (const Module *SourceModule = MMI->getModule()) {
758 // ABI_PCS_wchar_t to indicate wchar_t width
759 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
760 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
761 SourceModule->getModuleFlag("wchar_size"))) {
762 int WCharWidth = WCharWidthValue->getZExtValue();
763 assert((WCharWidth == 2 || WCharWidth == 4) &&
764 "wchar_t width must be 2 or 4 bytes");
765 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
768 // ABI_enum_size to indicate enum width
769 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
770 // (all enums contain a value needing 32 bits to encode).
771 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
772 SourceModule->getModuleFlag("min_enum_size"))) {
773 int EnumWidth = EnumWidthValue->getZExtValue();
774 assert((EnumWidth == 1 || EnumWidth == 4) &&
775 "Minimum enum width must be 1 or 4 bytes");
776 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
777 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
782 // TODO: We currently only support either reserving the register, or treating
783 // it as another callee-saved register, but not as SB or a TLS pointer; It
784 // would instead be nicer to push this from the frontend as metadata, as we do
785 // for the wchar and enum size tags
786 if (STI.isR9Reserved())
787 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
789 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
791 if (STI.hasTrustZone() && STI.hasVirtualization())
792 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
793 ARMBuildAttrs::AllowTZVirtualization);
794 else if (STI.hasTrustZone())
795 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
796 ARMBuildAttrs::AllowTZ);
797 else if (STI.hasVirtualization())
798 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
799 ARMBuildAttrs::AllowVirtualization);
801 ATS.finishAttributeSection();
804 //===----------------------------------------------------------------------===//
806 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
807 unsigned LabelId, MCContext &Ctx) {
809 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
810 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
814 static MCSymbolRefExpr::VariantKind
815 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
817 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
818 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
819 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
820 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
821 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
822 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
824 llvm_unreachable("Invalid ARMCPModifier!");
827 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
828 unsigned char TargetFlags) {
829 if (Subtarget->isTargetMachO()) {
830 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
831 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
834 return getSymbol(GV);
836 // FIXME: Remove this when Darwin transition to @GOT like syntax.
837 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
838 MachineModuleInfoMachO &MMIMachO =
839 MMI->getObjFileInfo<MachineModuleInfoMachO>();
840 MachineModuleInfoImpl::StubValueTy &StubSym =
841 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
842 : MMIMachO.getGVStubEntry(MCSym);
843 if (!StubSym.getPointer())
844 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
845 !GV->hasInternalLinkage());
847 } else if (Subtarget->isTargetCOFF()) {
848 assert(Subtarget->isTargetWindows() &&
849 "Windows is the only supported COFF target");
851 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
853 return getSymbol(GV);
855 SmallString<128> Name;
857 getNameWithPrefix(Name, GV);
859 return OutContext.GetOrCreateSymbol(Name);
860 } else if (Subtarget->isTargetELF()) {
861 return getSymbol(GV);
863 llvm_unreachable("unexpected target");
867 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
868 const DataLayout *DL = TM.getDataLayout();
869 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
871 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
874 if (ACPV->isLSDA()) {
875 MCSym = getCurExceptionSym();
876 } else if (ACPV->isBlockAddress()) {
877 const BlockAddress *BA =
878 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
879 MCSym = GetBlockAddressSymbol(BA);
880 } else if (ACPV->isGlobalValue()) {
881 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
883 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
884 // flag the global as MO_NONLAZY.
885 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
886 MCSym = GetARMGVSymbol(GV, TF);
887 } else if (ACPV->isMachineBasicBlock()) {
888 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
889 MCSym = MBB->getSymbol();
891 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
892 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
893 MCSym = GetExternalSymbolSymbol(Sym);
896 // Create an MCSymbol for the reference.
898 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
901 if (ACPV->getPCAdjustment()) {
902 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
906 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
908 MCBinaryExpr::CreateAdd(PCRelExpr,
909 MCConstantExpr::Create(ACPV->getPCAdjustment(),
912 if (ACPV->mustAddCurrentAddress()) {
913 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
914 // label, so just emit a local label end reference that instead.
915 MCSymbol *DotSym = OutContext.CreateTempSymbol();
916 OutStreamer->EmitLabel(DotSym);
917 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
918 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
920 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
922 OutStreamer->EmitValue(Expr, Size);
925 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
926 unsigned Opcode = MI->getOpcode();
928 if (Opcode == ARM::BR_JTadd)
930 else if (Opcode == ARM::BR_JTm)
933 const MachineOperand &MO1 = MI->getOperand(OpNum);
934 unsigned JTI = MO1.getIndex();
936 // Emit a label for the jump table.
937 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
938 OutStreamer->EmitLabel(JTISymbol);
940 // Mark the jump table as data-in-code.
941 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
943 // Emit each entry of the table.
944 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
945 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
946 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
948 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
949 MachineBasicBlock *MBB = JTBBs[i];
950 // Construct an MCExpr for the entry. We want a value of the form:
951 // (BasicBlockAddr - TableBeginAddr)
953 // For example, a table with entries jumping to basic blocks BB0 and BB1
956 // .word (LBB0 - LJTI_0_0)
957 // .word (LBB1 - LJTI_0_0)
958 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
960 if (TM.getRelocationModel() == Reloc::PIC_)
961 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
964 // If we're generating a table of Thumb addresses in static relocation
965 // model, we need to add one to keep interworking correctly.
966 else if (AFI->isThumbFunction())
967 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
969 OutStreamer->EmitValue(Expr, 4);
971 // Mark the end of jump table data-in-code region.
972 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
975 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
976 unsigned Opcode = MI->getOpcode();
977 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
978 const MachineOperand &MO1 = MI->getOperand(OpNum);
979 unsigned JTI = MO1.getIndex();
981 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
982 OutStreamer->EmitLabel(JTISymbol);
984 // Emit each entry of the table.
985 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
986 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
987 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
988 unsigned OffsetWidth = 4;
989 if (MI->getOpcode() == ARM::t2TBB_JT) {
991 // Mark the jump table as data-in-code.
992 OutStreamer->EmitDataRegion(MCDR_DataRegionJT8);
993 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
995 // Mark the jump table as data-in-code.
996 OutStreamer->EmitDataRegion(MCDR_DataRegionJT16);
999 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1000 MachineBasicBlock *MBB = JTBBs[i];
1001 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1003 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1004 if (OffsetWidth == 4) {
1005 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
1006 .addExpr(MBBSymbolExpr)
1011 // Otherwise it's an offset from the dispatch instruction. Construct an
1012 // MCExpr for the entry. We want a value of the form:
1013 // (BasicBlockAddr - TableBeginAddr) / 2
1015 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1018 // .byte (LBB0 - LJTI_0_0) / 2
1019 // .byte (LBB1 - LJTI_0_0) / 2
1020 const MCExpr *Expr =
1021 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1022 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1024 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1026 OutStreamer->EmitValue(Expr, OffsetWidth);
1028 // Mark the end of jump table data-in-code region. 32-bit offsets use
1029 // actual branch instructions here, so we don't mark those as a data-region
1031 if (OffsetWidth != 4)
1032 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1035 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1036 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1037 "Only instruction which are involved into frame setup code are allowed");
1039 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1040 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1041 const MachineFunction &MF = *MI->getParent()->getParent();
1042 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1043 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1045 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1046 unsigned Opc = MI->getOpcode();
1047 unsigned SrcReg, DstReg;
1049 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1050 // Two special cases:
1051 // 1) tPUSH does not have src/dst regs.
1052 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1053 // load. Yes, this is pretty fragile, but for now I don't see better
1055 SrcReg = DstReg = ARM::SP;
1057 SrcReg = MI->getOperand(1).getReg();
1058 DstReg = MI->getOperand(0).getReg();
1061 // Try to figure out the unwinding opcode out of src / dst regs.
1062 if (MI->mayStore()) {
1064 assert(DstReg == ARM::SP &&
1065 "Only stack pointer as a destination reg is supported");
1067 SmallVector<unsigned, 4> RegList;
1068 // Skip src & dst reg, and pred ops.
1069 unsigned StartOp = 2 + 2;
1070 // Use all the operands.
1071 unsigned NumOffset = 0;
1076 llvm_unreachable("Unsupported opcode for unwinding information");
1078 // Special case here: no src & dst reg, but two extra imp ops.
1079 StartOp = 2; NumOffset = 2;
1080 case ARM::STMDB_UPD:
1081 case ARM::t2STMDB_UPD:
1082 case ARM::VSTMDDB_UPD:
1083 assert(SrcReg == ARM::SP &&
1084 "Only stack pointer as a source reg is supported");
1085 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1087 const MachineOperand &MO = MI->getOperand(i);
1088 // Actually, there should never be any impdef stuff here. Skip it
1089 // temporary to workaround PR11902.
1090 if (MO.isImplicit())
1092 RegList.push_back(MO.getReg());
1095 case ARM::STR_PRE_IMM:
1096 case ARM::STR_PRE_REG:
1097 case ARM::t2STR_PRE:
1098 assert(MI->getOperand(2).getReg() == ARM::SP &&
1099 "Only stack pointer as a source reg is supported");
1100 RegList.push_back(SrcReg);
1103 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1104 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1106 // Changes of stack / frame pointer.
1107 if (SrcReg == ARM::SP) {
1112 llvm_unreachable("Unsupported opcode for unwinding information");
1118 Offset = -MI->getOperand(2).getImm();
1122 Offset = MI->getOperand(2).getImm();
1125 Offset = MI->getOperand(2).getImm()*4;
1129 Offset = -MI->getOperand(2).getImm()*4;
1131 case ARM::tLDRpci: {
1132 // Grab the constpool index and check, whether it corresponds to
1133 // original or cloned constpool entry.
1134 unsigned CPI = MI->getOperand(1).getIndex();
1135 const MachineConstantPool *MCP = MF.getConstantPool();
1136 if (CPI >= MCP->getConstants().size())
1137 CPI = AFI.getOriginalCPIdx(CPI);
1138 assert(CPI != -1U && "Invalid constpool index");
1140 // Derive the actual offset.
1141 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1142 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1143 // FIXME: Check for user, it should be "add" instruction!
1144 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1149 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1150 if (DstReg == FramePtr && FramePtr != ARM::SP)
1151 // Set-up of the frame pointer. Positive values correspond to "add"
1153 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1154 else if (DstReg == ARM::SP) {
1155 // Change of SP by an offset. Positive values correspond to "sub"
1157 ATS.emitPad(Offset);
1159 // Move of SP to a register. Positive values correspond to an "add"
1161 ATS.emitMovSP(DstReg, -Offset);
1164 } else if (DstReg == ARM::SP) {
1166 llvm_unreachable("Unsupported opcode for unwinding information");
1170 llvm_unreachable("Unsupported opcode for unwinding information");
1175 // Simple pseudo-instructions have their lowering (with expansion to real
1176 // instructions) auto-generated.
1177 #include "ARMGenMCPseudoLowering.inc"
1179 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1180 const DataLayout *DL = TM.getDataLayout();
1182 // If we just ended a constant pool, mark it as such.
1183 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1184 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1185 InConstantPool = false;
1188 // Emit unwinding stuff for frame-related instructions
1189 if (Subtarget->isTargetEHABICompatible() &&
1190 MI->getFlag(MachineInstr::FrameSetup))
1191 EmitUnwindingInstruction(MI);
1193 // Do any auto-generated pseudo lowerings.
1194 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1197 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1198 "Pseudo flag setting opcode should be expanded early");
1200 // Check for manual lowerings.
1201 unsigned Opc = MI->getOpcode();
1203 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1204 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1206 case ARM::tLEApcrel:
1207 case ARM::t2LEApcrel: {
1208 // FIXME: Need to also handle globals and externals
1209 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1210 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1211 ARM::t2LEApcrel ? ARM::t2ADR
1212 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1214 .addReg(MI->getOperand(0).getReg())
1215 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1216 // Add predicate operands.
1217 .addImm(MI->getOperand(2).getImm())
1218 .addReg(MI->getOperand(3).getReg()));
1221 case ARM::LEApcrelJT:
1222 case ARM::tLEApcrelJT:
1223 case ARM::t2LEApcrelJT: {
1224 MCSymbol *JTIPICSymbol =
1225 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1226 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1227 ARM::t2LEApcrelJT ? ARM::t2ADR
1228 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1230 .addReg(MI->getOperand(0).getReg())
1231 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1232 // Add predicate operands.
1233 .addImm(MI->getOperand(2).getImm())
1234 .addReg(MI->getOperand(3).getReg()));
1237 // Darwin call instructions are just normal call instructions with different
1238 // clobber semantics (they clobber R9).
1239 case ARM::BX_CALL: {
1240 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1243 // Add predicate operands.
1246 // Add 's' bit operand (always reg0 for this)
1249 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1250 .addReg(MI->getOperand(0).getReg()));
1253 case ARM::tBX_CALL: {
1254 if (Subtarget->hasV5TOps())
1255 llvm_unreachable("Expected BLX to be selected for v5t+");
1257 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1258 // that the saved lr has its LSB set correctly (the arch doesn't
1260 // So here we generate a bl to a small jump pad that does bx rN.
1261 // The jump pads are emitted after the function body.
1263 unsigned TReg = MI->getOperand(0).getReg();
1264 MCSymbol *TRegSym = nullptr;
1265 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1266 if (ThumbIndirectPads[i].first == TReg) {
1267 TRegSym = ThumbIndirectPads[i].second;
1273 TRegSym = OutContext.CreateTempSymbol();
1274 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1277 // Create a link-saving branch to the Reg Indirect Jump Pad.
1278 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1279 // Predicate comes first here.
1280 .addImm(ARMCC::AL).addReg(0)
1281 .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
1284 case ARM::BMOVPCRX_CALL: {
1285 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1288 // Add predicate operands.
1291 // Add 's' bit operand (always reg0 for this)
1294 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1296 .addReg(MI->getOperand(0).getReg())
1297 // Add predicate operands.
1300 // Add 's' bit operand (always reg0 for this)
1304 case ARM::BMOVPCB_CALL: {
1305 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1308 // Add predicate operands.
1311 // Add 's' bit operand (always reg0 for this)
1314 const MachineOperand &Op = MI->getOperand(0);
1315 const GlobalValue *GV = Op.getGlobal();
1316 const unsigned TF = Op.getTargetFlags();
1317 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1318 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1319 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1321 // Add predicate operands.
1326 case ARM::MOVi16_ga_pcrel:
1327 case ARM::t2MOVi16_ga_pcrel: {
1329 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1330 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1332 unsigned TF = MI->getOperand(1).getTargetFlags();
1333 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1334 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1335 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1337 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1338 getFunctionNumber(),
1339 MI->getOperand(2).getImm(), OutContext);
1340 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1341 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1342 const MCExpr *PCRelExpr =
1343 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1344 MCBinaryExpr::CreateAdd(LabelSymExpr,
1345 MCConstantExpr::Create(PCAdj, OutContext),
1346 OutContext), OutContext), OutContext);
1347 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1349 // Add predicate operands.
1350 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1351 TmpInst.addOperand(MCOperand::createReg(0));
1352 // Add 's' bit operand (always reg0 for this)
1353 TmpInst.addOperand(MCOperand::createReg(0));
1354 EmitToStreamer(*OutStreamer, TmpInst);
1357 case ARM::MOVTi16_ga_pcrel:
1358 case ARM::t2MOVTi16_ga_pcrel: {
1360 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1361 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1362 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1363 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1365 unsigned TF = MI->getOperand(2).getTargetFlags();
1366 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1367 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1368 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1370 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1371 getFunctionNumber(),
1372 MI->getOperand(3).getImm(), OutContext);
1373 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1374 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1375 const MCExpr *PCRelExpr =
1376 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1377 MCBinaryExpr::CreateAdd(LabelSymExpr,
1378 MCConstantExpr::Create(PCAdj, OutContext),
1379 OutContext), OutContext), OutContext);
1380 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1381 // Add predicate operands.
1382 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1383 TmpInst.addOperand(MCOperand::createReg(0));
1384 // Add 's' bit operand (always reg0 for this)
1385 TmpInst.addOperand(MCOperand::createReg(0));
1386 EmitToStreamer(*OutStreamer, TmpInst);
1389 case ARM::tPICADD: {
1390 // This is a pseudo op for a label + instruction sequence, which looks like:
1393 // This adds the address of LPC0 to r0.
1396 OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1397 getFunctionNumber(),
1398 MI->getOperand(2).getImm(),
1401 // Form and emit the add.
1402 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1403 .addReg(MI->getOperand(0).getReg())
1404 .addReg(MI->getOperand(0).getReg())
1406 // Add predicate operands.
1412 // This is a pseudo op for a label + instruction sequence, which looks like:
1415 // This adds the address of LPC0 to r0.
1418 OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1419 getFunctionNumber(),
1420 MI->getOperand(2).getImm(),
1423 // Form and emit the add.
1424 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1425 .addReg(MI->getOperand(0).getReg())
1427 .addReg(MI->getOperand(1).getReg())
1428 // Add predicate operands.
1429 .addImm(MI->getOperand(3).getImm())
1430 .addReg(MI->getOperand(4).getReg())
1431 // Add 's' bit operand (always reg0 for this)
1442 case ARM::PICLDRSH: {
1443 // This is a pseudo op for a label + instruction sequence, which looks like:
1446 // The LCP0 label is referenced by a constant pool entry in order to get
1447 // a PC-relative address at the ldr instruction.
1450 OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1451 getFunctionNumber(),
1452 MI->getOperand(2).getImm(),
1455 // Form and emit the load
1457 switch (MI->getOpcode()) {
1459 llvm_unreachable("Unexpected opcode!");
1460 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1461 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1462 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1463 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1464 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1465 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1466 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1467 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1469 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1470 .addReg(MI->getOperand(0).getReg())
1472 .addReg(MI->getOperand(1).getReg())
1474 // Add predicate operands.
1475 .addImm(MI->getOperand(3).getImm())
1476 .addReg(MI->getOperand(4).getReg()));
1480 case ARM::CONSTPOOL_ENTRY: {
1481 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1482 /// in the function. The first operand is the ID# for this instruction, the
1483 /// second is the index into the MachineConstantPool that this is, the third
1484 /// is the size in bytes of this constant pool entry.
1485 /// The required alignment is specified on the basic block holding this MI.
1486 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1487 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1489 // If this is the first entry of the pool, mark it.
1490 if (!InConstantPool) {
1491 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1492 InConstantPool = true;
1495 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1497 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1498 if (MCPE.isMachineConstantPoolEntry())
1499 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1501 EmitGlobalConstant(MCPE.Val.ConstVal);
1504 case ARM::t2BR_JT: {
1505 // Lower and emit the instruction itself, then the jump table following it.
1506 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1508 .addReg(MI->getOperand(0).getReg())
1509 // Add predicate operands.
1513 // Output the data for the jump table itself
1517 case ARM::t2TBB_JT: {
1518 // Lower and emit the instruction itself, then the jump table following it.
1519 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2TBB)
1521 .addReg(MI->getOperand(0).getReg())
1522 // Add predicate operands.
1526 // Output the data for the jump table itself
1528 // Make sure the next instruction is 2-byte aligned.
1532 case ARM::t2TBH_JT: {
1533 // Lower and emit the instruction itself, then the jump table following it.
1534 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2TBH)
1536 .addReg(MI->getOperand(0).getReg())
1537 // Add predicate operands.
1541 // Output the data for the jump table itself
1547 // Lower and emit the instruction itself, then the jump table following it.
1550 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1551 ARM::MOVr : ARM::tMOVr;
1552 TmpInst.setOpcode(Opc);
1553 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1554 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1555 // Add predicate operands.
1556 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1557 TmpInst.addOperand(MCOperand::createReg(0));
1558 // Add 's' bit operand (always reg0 for this)
1559 if (Opc == ARM::MOVr)
1560 TmpInst.addOperand(MCOperand::createReg(0));
1561 EmitToStreamer(*OutStreamer, TmpInst);
1563 // Make sure the Thumb jump table is 4-byte aligned.
1564 if (Opc == ARM::tMOVr)
1567 // Output the data for the jump table itself
1572 // Lower and emit the instruction itself, then the jump table following it.
1575 if (MI->getOperand(1).getReg() == 0) {
1577 TmpInst.setOpcode(ARM::LDRi12);
1578 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1579 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1580 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1582 TmpInst.setOpcode(ARM::LDRrs);
1583 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1584 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1585 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1586 TmpInst.addOperand(MCOperand::createImm(0));
1588 // Add predicate operands.
1589 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1590 TmpInst.addOperand(MCOperand::createReg(0));
1591 EmitToStreamer(*OutStreamer, TmpInst);
1593 // Output the data for the jump table itself
1597 case ARM::BR_JTadd: {
1598 // Lower and emit the instruction itself, then the jump table following it.
1599 // add pc, target, idx
1600 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1602 .addReg(MI->getOperand(0).getReg())
1603 .addReg(MI->getOperand(1).getReg())
1604 // Add predicate operands.
1607 // Add 's' bit operand (always reg0 for this)
1610 // Output the data for the jump table itself
1615 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1618 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1619 // FIXME: Remove this special case when they do.
1620 if (!Subtarget->isTargetMachO()) {
1621 //.long 0xe7ffdefe @ trap
1622 uint32_t Val = 0xe7ffdefeUL;
1623 OutStreamer->AddComment("trap");
1624 OutStreamer->EmitIntValue(Val, 4);
1629 case ARM::TRAPNaCl: {
1630 //.long 0xe7fedef0 @ trap
1631 uint32_t Val = 0xe7fedef0UL;
1632 OutStreamer->AddComment("trap");
1633 OutStreamer->EmitIntValue(Val, 4);
1637 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1638 // FIXME: Remove this special case when they do.
1639 if (!Subtarget->isTargetMachO()) {
1640 //.short 57086 @ trap
1641 uint16_t Val = 0xdefe;
1642 OutStreamer->AddComment("trap");
1643 OutStreamer->EmitIntValue(Val, 2);
1648 case ARM::t2Int_eh_sjlj_setjmp:
1649 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1650 case ARM::tInt_eh_sjlj_setjmp: {
1651 // Two incoming args: GPR:$src, GPR:$val
1654 // str $val, [$src, #4]
1659 unsigned SrcReg = MI->getOperand(0).getReg();
1660 unsigned ValReg = MI->getOperand(1).getReg();
1661 MCSymbol *Label = GetARMSJLJEHLabel();
1662 OutStreamer->AddComment("eh_setjmp begin");
1663 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1670 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1680 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1683 // The offset immediate is #4. The operand value is scaled by 4 for the
1684 // tSTR instruction.
1690 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1698 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1699 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1700 .addExpr(SymbolExpr)
1704 OutStreamer->AddComment("eh_setjmp end");
1705 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1713 OutStreamer->EmitLabel(Label);
1717 case ARM::Int_eh_sjlj_setjmp_nofp:
1718 case ARM::Int_eh_sjlj_setjmp: {
1719 // Two incoming args: GPR:$src, GPR:$val
1721 // str $val, [$src, #+4]
1725 unsigned SrcReg = MI->getOperand(0).getReg();
1726 unsigned ValReg = MI->getOperand(1).getReg();
1728 OutStreamer->AddComment("eh_setjmp begin");
1729 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1736 // 's' bit operand (always reg0 for this).
1739 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1747 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1753 // 's' bit operand (always reg0 for this).
1756 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1763 // 's' bit operand (always reg0 for this).
1766 OutStreamer->AddComment("eh_setjmp end");
1767 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1773 // 's' bit operand (always reg0 for this).
1777 case ARM::Int_eh_sjlj_longjmp: {
1778 // ldr sp, [$src, #8]
1779 // ldr $scratch, [$src, #4]
1782 unsigned SrcReg = MI->getOperand(0).getReg();
1783 unsigned ScratchReg = MI->getOperand(1).getReg();
1784 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1792 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1800 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1808 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1815 case ARM::tInt_eh_sjlj_longjmp: {
1816 // ldr $scratch, [$src, #8]
1818 // ldr $scratch, [$src, #4]
1821 unsigned SrcReg = MI->getOperand(0).getReg();
1822 unsigned ScratchReg = MI->getOperand(1).getReg();
1823 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1826 // The offset immediate is #8. The operand value is scaled by 4 for the
1827 // tLDR instruction.
1833 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1840 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1848 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1856 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
1866 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1868 EmitToStreamer(*OutStreamer, TmpInst);
1871 //===----------------------------------------------------------------------===//
1872 // Target Registry Stuff
1873 //===----------------------------------------------------------------------===//
1875 // Force static initialization.
1876 extern "C" void LLVMInitializeARMAsmPrinter() {
1877 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1878 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1879 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1880 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);