1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMArchExtName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/DebugInfo.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/COFF.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ELF.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetMachine.h"
59 #define DEBUG_TYPE "asm-printer"
61 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
62 std::unique_ptr<MCStreamer> Streamer)
63 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
64 InConstantPool(false) {}
66 void ARMAsmPrinter::EmitFunctionBodyEnd() {
67 // Make sure to terminate any constant pools that were at the end
71 InConstantPool = false;
72 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
75 void ARMAsmPrinter::EmitFunctionEntryLabel() {
76 if (AFI->isThumbFunction()) {
77 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
78 OutStreamer.EmitThumbFunc(CurrentFnSym);
81 OutStreamer.EmitLabel(CurrentFnSym);
84 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
85 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
86 assert(Size && "C++ constructor pointer had zero size!");
88 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
89 assert(GV && "C++ constructor pointer was not a GlobalValue!");
91 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
93 (Subtarget->isTargetELF()
94 ? MCSymbolRefExpr::VK_ARM_TARGET1
95 : MCSymbolRefExpr::VK_None),
98 OutStreamer.EmitValue(E, Size);
101 /// runOnMachineFunction - This uses the EmitInstruction()
102 /// method to print assembly for each instruction.
104 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
105 AFI = MF.getInfo<ARMFunctionInfo>();
106 MCP = MF.getConstantPool();
107 Subtarget = &MF.getSubtarget<ARMSubtarget>();
109 SetupMachineFunction(MF);
111 if (Subtarget->isTargetCOFF()) {
112 bool Internal = MF.getFunction()->hasInternalLinkage();
113 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
114 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
115 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
117 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
118 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
119 OutStreamer.EmitCOFFSymbolType(Type);
120 OutStreamer.EndCOFFSymbolDef();
123 // Have common code print out the function header with linkage info etc.
124 EmitFunctionHeader();
126 // Emit the rest of the function body.
129 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
130 // These are created per function, rather than per TU, since it's
131 // relatively easy to exceed the thumb branch range within a TU.
132 if (! ThumbIndirectPads.empty()) {
133 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
135 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
136 OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
137 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
138 .addReg(ThumbIndirectPads[i].first)
139 // Add predicate operands.
143 ThumbIndirectPads.clear();
146 // We didn't modify anything.
150 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
151 raw_ostream &O, const char *Modifier) {
152 const MachineOperand &MO = MI->getOperand(OpNum);
153 unsigned TF = MO.getTargetFlags();
155 switch (MO.getType()) {
156 default: llvm_unreachable("<unknown operand type>");
157 case MachineOperand::MO_Register: {
158 unsigned Reg = MO.getReg();
159 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
160 assert(!MO.getSubReg() && "Subregs should be eliminated!");
161 if(ARM::GPRPairRegClass.contains(Reg)) {
162 const MachineFunction &MF = *MI->getParent()->getParent();
163 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
164 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
166 O << ARMInstPrinter::getRegisterName(Reg);
169 case MachineOperand::MO_Immediate: {
170 int64_t Imm = MO.getImm();
172 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
173 (TF == ARMII::MO_LO16))
175 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
176 (TF == ARMII::MO_HI16))
181 case MachineOperand::MO_MachineBasicBlock:
182 O << *MO.getMBB()->getSymbol();
184 case MachineOperand::MO_GlobalAddress: {
185 const GlobalValue *GV = MO.getGlobal();
186 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
187 (TF & ARMII::MO_LO16))
189 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
190 (TF & ARMII::MO_HI16))
192 O << *GetARMGVSymbol(GV, TF);
194 printOffset(MO.getOffset(), O);
195 if (TF == ARMII::MO_PLT)
199 case MachineOperand::MO_ConstantPoolIndex:
200 O << *GetCPISymbol(MO.getIndex());
205 //===--------------------------------------------------------------------===//
207 MCSymbol *ARMAsmPrinter::
208 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
209 const DataLayout *DL = TM.getDataLayout();
210 SmallString<60> Name;
211 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
212 << getFunctionNumber() << '_' << uid << '_' << uid2;
213 return OutContext.GetOrCreateSymbol(Name.str());
217 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
218 const DataLayout *DL = TM.getDataLayout();
219 SmallString<60> Name;
220 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
221 << getFunctionNumber();
222 return OutContext.GetOrCreateSymbol(Name.str());
225 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
226 unsigned AsmVariant, const char *ExtraCode,
228 // Does this asm operand have a single letter operand modifier?
229 if (ExtraCode && ExtraCode[0]) {
230 if (ExtraCode[1] != 0) return true; // Unknown modifier.
232 switch (ExtraCode[0]) {
234 // See if this is a generic print operand
235 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
236 case 'a': // Print as a memory address.
237 if (MI->getOperand(OpNum).isReg()) {
239 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
244 case 'c': // Don't print "#" before an immediate operand.
245 if (!MI->getOperand(OpNum).isImm())
247 O << MI->getOperand(OpNum).getImm();
249 case 'P': // Print a VFP double precision register.
250 case 'q': // Print a NEON quad precision register.
251 printOperand(MI, OpNum, O);
253 case 'y': // Print a VFP single precision register as indexed double.
254 if (MI->getOperand(OpNum).isReg()) {
255 unsigned Reg = MI->getOperand(OpNum).getReg();
256 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
257 // Find the 'd' register that has this 's' register as a sub-register,
258 // and determine the lane number.
259 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
260 if (!ARM::DPRRegClass.contains(*SR))
262 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
263 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
268 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
269 if (!MI->getOperand(OpNum).isImm())
271 O << ~(MI->getOperand(OpNum).getImm());
273 case 'L': // The low 16 bits of an immediate constant.
274 if (!MI->getOperand(OpNum).isImm())
276 O << (MI->getOperand(OpNum).getImm() & 0xffff);
278 case 'M': { // A register range suitable for LDM/STM.
279 if (!MI->getOperand(OpNum).isReg())
281 const MachineOperand &MO = MI->getOperand(OpNum);
282 unsigned RegBegin = MO.getReg();
283 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
284 // already got the operands in registers that are operands to the
285 // inline asm statement.
287 if (ARM::GPRPairRegClass.contains(RegBegin)) {
288 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
289 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
290 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
291 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
293 O << ARMInstPrinter::getRegisterName(RegBegin);
295 // FIXME: The register allocator not only may not have given us the
296 // registers in sequence, but may not be in ascending registers. This
297 // will require changes in the register allocator that'll need to be
298 // propagated down here if the operands change.
299 unsigned RegOps = OpNum + 1;
300 while (MI->getOperand(RegOps).isReg()) {
302 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
310 case 'R': // The most significant register of a pair.
311 case 'Q': { // The least significant register of a pair.
314 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
315 if (!FlagsOP.isImm())
317 unsigned Flags = FlagsOP.getImm();
319 // This operand may not be the one that actually provides the register. If
320 // it's tied to a previous one then we should refer instead to that one
321 // for registers and their classes.
323 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
324 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
325 unsigned OpFlags = MI->getOperand(OpNum).getImm();
326 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
328 Flags = MI->getOperand(OpNum).getImm();
330 // Later code expects OpNum to be pointing at the register rather than
335 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
337 InlineAsm::hasRegClassConstraint(Flags, RC);
338 if (RC == ARM::GPRPairRegClassID) {
341 const MachineOperand &MO = MI->getOperand(OpNum);
344 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
345 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
346 ARM::gsub_0 : ARM::gsub_1);
347 O << ARMInstPrinter::getRegisterName(Reg);
352 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
353 if (RegOp >= MI->getNumOperands())
355 const MachineOperand &MO = MI->getOperand(RegOp);
358 unsigned Reg = MO.getReg();
359 O << ARMInstPrinter::getRegisterName(Reg);
363 case 'e': // The low doubleword register of a NEON quad register.
364 case 'f': { // The high doubleword register of a NEON quad register.
365 if (!MI->getOperand(OpNum).isReg())
367 unsigned Reg = MI->getOperand(OpNum).getReg();
368 if (!ARM::QPRRegClass.contains(Reg))
370 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
371 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
372 ARM::dsub_0 : ARM::dsub_1);
373 O << ARMInstPrinter::getRegisterName(SubReg);
377 // This modifier is not yet supported.
378 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
380 case 'H': { // The highest-numbered register of a pair.
381 const MachineOperand &MO = MI->getOperand(OpNum);
384 const MachineFunction &MF = *MI->getParent()->getParent();
385 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
386 unsigned Reg = MO.getReg();
387 if(!ARM::GPRPairRegClass.contains(Reg))
389 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
390 O << ARMInstPrinter::getRegisterName(Reg);
396 printOperand(MI, OpNum, O);
400 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
401 unsigned OpNum, unsigned AsmVariant,
402 const char *ExtraCode,
404 // Does this asm operand have a single letter operand modifier?
405 if (ExtraCode && ExtraCode[0]) {
406 if (ExtraCode[1] != 0) return true; // Unknown modifier.
408 switch (ExtraCode[0]) {
409 case 'A': // A memory operand for a VLD1/VST1 instruction.
410 default: return true; // Unknown modifier.
411 case 'm': // The base register of a memory operand.
412 if (!MI->getOperand(OpNum).isReg())
414 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
419 const MachineOperand &MO = MI->getOperand(OpNum);
420 assert(MO.isReg() && "unexpected inline asm memory operand");
421 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
425 static bool isThumb(const MCSubtargetInfo& STI) {
426 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
429 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
430 const MCSubtargetInfo *EndInfo) const {
431 // If either end mode is unknown (EndInfo == NULL) or different than
432 // the start mode, then restore the start mode.
433 const bool WasThumb = isThumb(StartInfo);
434 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
435 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
439 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
440 Triple TT(TM.getTargetTriple());
441 if (TT.isOSBinFormatMachO()) {
442 Reloc::Model RelocM = TM.getRelocationModel();
443 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
444 // Declare all the text sections up front (before the DWARF sections
445 // emitted by AsmPrinter::doInitialization) so the assembler will keep
446 // them together at the beginning of the object file. This helps
447 // avoid out-of-range branches that are due a fundamental limitation of
448 // the way symbol offsets are encoded with the current Darwin ARM
450 const TargetLoweringObjectFileMachO &TLOFMacho =
451 static_cast<const TargetLoweringObjectFileMachO &>(
452 getObjFileLowering());
454 // Collect the set of sections our functions will go into.
455 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
456 SmallPtrSet<const MCSection *, 8> > TextSections;
457 // Default text section comes first.
458 TextSections.insert(TLOFMacho.getTextSection());
459 // Now any user defined text sections from function attributes.
460 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
461 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
462 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
463 // Now the coalescable sections.
464 TextSections.insert(TLOFMacho.getTextCoalSection());
465 TextSections.insert(TLOFMacho.getConstTextCoalSection());
467 // Emit the sections in the .s file header to fix the order.
468 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
469 OutStreamer.SwitchSection(TextSections[i]);
471 if (RelocM == Reloc::DynamicNoPIC) {
472 const MCSection *sect =
473 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
474 MachO::S_SYMBOL_STUBS,
475 12, SectionKind::getText());
476 OutStreamer.SwitchSection(sect);
478 const MCSection *sect =
479 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
480 MachO::S_SYMBOL_STUBS,
481 16, SectionKind::getText());
482 OutStreamer.SwitchSection(sect);
484 const MCSection *StaticInitSect =
485 OutContext.getMachOSection("__TEXT", "__StaticInit",
487 MachO::S_ATTR_PURE_INSTRUCTIONS,
488 SectionKind::getText());
489 OutStreamer.SwitchSection(StaticInitSect);
492 // Compiling with debug info should not affect the code
493 // generation. Ensure the cstring section comes before the
494 // optional __DWARF secion. Otherwise, PC-relative loads would
495 // have to use different instruction sequences at "-g" in order to
496 // reach global data in the same object file.
497 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
500 // Use unified assembler syntax.
501 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
503 // Emit ARM Build Attributes
504 if (TT.isOSBinFormatELF())
507 // Use the triple's architecture and subarchitecture to determine
508 // if we're thumb for the purposes of the top level code16 assembler
510 bool isThumb = TT.getArch() == Triple::thumb ||
511 TT.getArch() == Triple::thumbeb ||
512 TT.getSubArch() == Triple::ARMSubArch_v7m ||
513 TT.getSubArch() == Triple::ARMSubArch_v6m;
514 if (!M.getModuleInlineAsm().empty() && isThumb)
515 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
519 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
520 MachineModuleInfoImpl::StubValueTy &MCSym) {
522 OutStreamer.EmitLabel(StubLabel);
523 // .indirect_symbol _foo
524 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
527 // External to current translation unit.
528 OutStreamer.EmitIntValue(0, 4/*size*/);
530 // Internal to current translation unit.
532 // When we place the LSDA into the TEXT section, the type info
533 // pointers need to be indirect and pc-rel. We accomplish this by
534 // using NLPs; however, sometimes the types are local to the file.
535 // We need to fill in the value for the NLP in those cases.
536 OutStreamer.EmitValue(
537 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
542 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
543 Triple TT(TM.getTargetTriple());
544 if (TT.isOSBinFormatMachO()) {
545 // All darwin targets use mach-o.
546 const TargetLoweringObjectFileMachO &TLOFMacho =
547 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
548 MachineModuleInfoMachO &MMIMacho =
549 MMI->getObjFileInfo<MachineModuleInfoMachO>();
551 // Output non-lazy-pointers for external and common global variables.
552 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
554 if (!Stubs.empty()) {
555 // Switch with ".non_lazy_symbol_pointer" directive.
556 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
559 for (auto &Stub : Stubs)
560 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
563 OutStreamer.AddBlankLine();
566 Stubs = MMIMacho.GetHiddenGVStubList();
567 if (!Stubs.empty()) {
568 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
571 for (auto &Stub : Stubs)
572 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
575 OutStreamer.AddBlankLine();
578 // Funny Darwin hack: This flag tells the linker that no global symbols
579 // contain code that falls through to other global symbols (e.g. the obvious
580 // implementation of multiple entry points). If this doesn't occur, the
581 // linker can safely perform dead code stripping. Since LLVM never
582 // generates code that does this, it is always safe to set.
583 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
586 // Emit a .data.rel section containing any stubs that were created.
587 if (TT.isOSBinFormatELF()) {
588 const TargetLoweringObjectFileELF &TLOFELF =
589 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
591 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
593 // Output stubs for external and common global variables.
594 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
595 if (!Stubs.empty()) {
596 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
597 const DataLayout *TD = TM.getDataLayout();
599 for (auto &stub: Stubs) {
600 OutStreamer.EmitLabel(stub.first);
601 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
602 TD->getPointerSize(0));
609 //===----------------------------------------------------------------------===//
610 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
612 // The following seem like one-off assembler flags, but they actually need
613 // to appear in the .ARM.attributes section in ELF.
614 // Instead of subclassing the MCELFStreamer, we do the work here.
616 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
617 const ARMSubtarget *Subtarget) {
619 return ARMBuildAttrs::v5TEJ;
621 if (Subtarget->hasV8Ops())
622 return ARMBuildAttrs::v8;
623 else if (Subtarget->hasV7Ops()) {
624 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
625 return ARMBuildAttrs::v7E_M;
626 return ARMBuildAttrs::v7;
627 } else if (Subtarget->hasV6T2Ops())
628 return ARMBuildAttrs::v6T2;
629 else if (Subtarget->hasV6MOps())
630 return ARMBuildAttrs::v6S_M;
631 else if (Subtarget->hasV6Ops())
632 return ARMBuildAttrs::v6;
633 else if (Subtarget->hasV5TEOps())
634 return ARMBuildAttrs::v5TE;
635 else if (Subtarget->hasV5TOps())
636 return ARMBuildAttrs::v5T;
637 else if (Subtarget->hasV4TOps())
638 return ARMBuildAttrs::v4T;
640 return ARMBuildAttrs::v4;
643 void ARMAsmPrinter::emitAttributes() {
644 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
645 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
647 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
649 ATS.switchVendor("aeabi");
651 // Compute ARM ELF Attributes based on the default subtarget that
652 // we'd have constructed. The existing ARM behavior isn't LTO clean
654 // FIXME: For ifunc related functions we could iterate over and look
655 // for a feature string that doesn't match the default one.
656 StringRef TT = TM.getTargetTriple();
657 StringRef CPU = TM.getTargetCPU();
658 StringRef FS = TM.getTargetFeatureString();
659 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
662 ArchFS = ArchFS + "," + FS.str();
666 const ARMBaseTargetMachine &ATM =
667 static_cast<const ARMBaseTargetMachine &>(TM);
668 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
670 std::string CPUString = STI.getCPUString();
672 if (CPUString != "generic") {
673 // FIXME: remove krait check when GNU tools support krait cpu
675 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
676 // We consider krait as a "cortex-a9" + hwdiv CPU
677 // Enable hwdiv through ".arch_extension idiv"
678 if (STI.hasDivide() || STI.hasDivideInARMMode())
679 ATS.emitArchExtension(ARM::HWDIV);
681 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
684 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
686 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
687 // profile is not applicable (e.g. pre v7, or cross-profile code)".
688 if (STI.hasV7Ops()) {
689 if (STI.isAClass()) {
690 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
691 ARMBuildAttrs::ApplicationProfile);
692 } else if (STI.isRClass()) {
693 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
694 ARMBuildAttrs::RealTimeProfile);
695 } else if (STI.isMClass()) {
696 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
697 ARMBuildAttrs::MicroControllerProfile);
701 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
702 STI.hasARMOps() ? ARMBuildAttrs::Allowed
703 : ARMBuildAttrs::Not_Allowed);
704 if (STI.isThumb1Only()) {
705 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
706 } else if (STI.hasThumb2()) {
707 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
708 ARMBuildAttrs::AllowThumb32);
712 /* NEON is not exactly a VFP architecture, but GAS emit one of
713 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
714 if (STI.hasFPARMv8()) {
716 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
718 ATS.emitFPU(ARM::NEON_FP_ARMV8);
719 } else if (STI.hasVFP4())
720 ATS.emitFPU(ARM::NEON_VFPV4);
722 ATS.emitFPU(ARM::NEON);
723 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
725 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
726 ARMBuildAttrs::AllowNeonARMv8);
728 if (STI.hasFPARMv8())
729 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
730 // FPU, but there are two different names for it depending on the CPU.
731 ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
732 else if (STI.hasVFP4())
733 ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
734 else if (STI.hasVFP3())
735 ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
736 else if (STI.hasVFP2())
737 ATS.emitFPU(ARM::VFPV2);
740 if (TM.getRelocationModel() == Reloc::PIC_) {
741 // PIC specific attributes.
742 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
743 ARMBuildAttrs::AddressRWPCRel);
744 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
745 ARMBuildAttrs::AddressROPCRel);
746 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
747 ARMBuildAttrs::AddressGOT);
749 // Allow direct addressing of imported data for all other relocation models.
750 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
751 ARMBuildAttrs::AddressDirect);
754 // Signal various FP modes.
755 if (!TM.Options.UnsafeFPMath) {
756 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
757 ARMBuildAttrs::IEEEDenormals);
758 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
760 // If the user has permitted this code to choose the IEEE 754
761 // rounding at run-time, emit the rounding attribute.
762 if (TM.Options.HonorSignDependentRoundingFPMathOption)
763 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
765 if (!STI.hasVFP2()) {
766 // When the target doesn't have an FPU (by design or
767 // intention), the assumptions made on the software support
768 // mirror that of the equivalent hardware support *if it
769 // existed*. For v7 and better we indicate that denormals are
770 // flushed preserving sign, and for V6 we indicate that
771 // denormals are flushed to positive zero.
773 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
774 ARMBuildAttrs::PreserveFPSign);
775 } else if (STI.hasVFP3()) {
776 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
777 // the sign bit of the zero matches the sign bit of the input or
778 // result that is being flushed to zero.
779 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
780 ARMBuildAttrs::PreserveFPSign);
782 // For VFPv2 implementations it is implementation defined as
783 // to whether denormals are flushed to positive zero or to
784 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
785 // LLVM has chosen to flush this to positive zero (most likely for
786 // GCC compatibility), so that's the chosen value here (the
787 // absence of its emission implies zero).
790 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
791 // equivalent of GCC's -ffinite-math-only flag.
792 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
793 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
794 ARMBuildAttrs::Allowed);
796 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
797 ARMBuildAttrs::AllowIEE754);
799 if (STI.allowsUnalignedMem())
800 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
801 ARMBuildAttrs::Allowed);
803 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
804 ARMBuildAttrs::Not_Allowed);
806 // FIXME: add more flags to ARMBuildAttributes.h
807 // 8-bytes alignment stuff.
808 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
809 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
811 // ABI_HardFP_use attribute to indicate single precision FP.
812 if (STI.isFPOnlySP())
813 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
814 ARMBuildAttrs::HardFPSinglePrecision);
816 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
817 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
818 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
820 // FIXME: Should we signal R9 usage?
823 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
825 // FIXME: To support emitting this build attribute as GCC does, the
826 // -mfp16-format option and associated plumbing must be
827 // supported. For now the __fp16 type is exposed by default, so this
828 // attribute should be emitted with value 1.
829 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
830 ARMBuildAttrs::FP16FormatIEEE);
832 if (STI.hasMPExtension())
833 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
835 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
836 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
837 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
838 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
839 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
840 // otherwise, the default value (AllowDIVIfExists) applies.
841 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
842 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
845 if (const Module *SourceModule = MMI->getModule()) {
846 // ABI_PCS_wchar_t to indicate wchar_t width
847 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
848 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
849 SourceModule->getModuleFlag("wchar_size"))) {
850 int WCharWidth = WCharWidthValue->getZExtValue();
851 assert((WCharWidth == 2 || WCharWidth == 4) &&
852 "wchar_t width must be 2 or 4 bytes");
853 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
856 // ABI_enum_size to indicate enum width
857 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
858 // (all enums contain a value needing 32 bits to encode).
859 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
860 SourceModule->getModuleFlag("min_enum_size"))) {
861 int EnumWidth = EnumWidthValue->getZExtValue();
862 assert((EnumWidth == 1 || EnumWidth == 4) &&
863 "Minimum enum width must be 1 or 4 bytes");
864 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
865 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
870 // TODO: We currently only support either reserving the register, or treating
871 // it as another callee-saved register, but not as SB or a TLS pointer; It
872 // would instead be nicer to push this from the frontend as metadata, as we do
873 // for the wchar and enum size tags
874 if (STI.isR9Reserved())
875 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
877 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
879 if (STI.hasTrustZone() && STI.hasVirtualization())
880 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
881 ARMBuildAttrs::AllowTZVirtualization);
882 else if (STI.hasTrustZone())
883 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
884 ARMBuildAttrs::AllowTZ);
885 else if (STI.hasVirtualization())
886 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
887 ARMBuildAttrs::AllowVirtualization);
889 ATS.finishAttributeSection();
892 //===----------------------------------------------------------------------===//
894 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
895 unsigned LabelId, MCContext &Ctx) {
897 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
898 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
902 static MCSymbolRefExpr::VariantKind
903 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
905 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
906 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
907 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
908 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
909 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
910 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
912 llvm_unreachable("Invalid ARMCPModifier!");
915 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
916 unsigned char TargetFlags) {
917 if (Subtarget->isTargetMachO()) {
918 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
919 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
922 return getSymbol(GV);
924 // FIXME: Remove this when Darwin transition to @GOT like syntax.
925 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
926 MachineModuleInfoMachO &MMIMachO =
927 MMI->getObjFileInfo<MachineModuleInfoMachO>();
928 MachineModuleInfoImpl::StubValueTy &StubSym =
929 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
930 : MMIMachO.getGVStubEntry(MCSym);
931 if (!StubSym.getPointer())
932 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
933 !GV->hasInternalLinkage());
935 } else if (Subtarget->isTargetCOFF()) {
936 assert(Subtarget->isTargetWindows() &&
937 "Windows is the only supported COFF target");
939 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
941 return getSymbol(GV);
943 SmallString<128> Name;
945 getNameWithPrefix(Name, GV);
947 return OutContext.GetOrCreateSymbol(Name);
948 } else if (Subtarget->isTargetELF()) {
949 return getSymbol(GV);
951 llvm_unreachable("unexpected target");
955 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
956 const DataLayout *DL = TM.getDataLayout();
957 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
959 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
962 if (ACPV->isLSDA()) {
963 SmallString<128> Str;
964 raw_svector_ostream OS(Str);
965 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
966 MCSym = OutContext.GetOrCreateSymbol(OS.str());
967 } else if (ACPV->isBlockAddress()) {
968 const BlockAddress *BA =
969 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
970 MCSym = GetBlockAddressSymbol(BA);
971 } else if (ACPV->isGlobalValue()) {
972 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
974 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
975 // flag the global as MO_NONLAZY.
976 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
977 MCSym = GetARMGVSymbol(GV, TF);
978 } else if (ACPV->isMachineBasicBlock()) {
979 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
980 MCSym = MBB->getSymbol();
982 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
983 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
984 MCSym = GetExternalSymbolSymbol(Sym);
987 // Create an MCSymbol for the reference.
989 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
992 if (ACPV->getPCAdjustment()) {
993 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
997 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
999 MCBinaryExpr::CreateAdd(PCRelExpr,
1000 MCConstantExpr::Create(ACPV->getPCAdjustment(),
1003 if (ACPV->mustAddCurrentAddress()) {
1004 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
1005 // label, so just emit a local label end reference that instead.
1006 MCSymbol *DotSym = OutContext.CreateTempSymbol();
1007 OutStreamer.EmitLabel(DotSym);
1008 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
1009 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
1011 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
1013 OutStreamer.EmitValue(Expr, Size);
1016 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
1017 unsigned Opcode = MI->getOpcode();
1019 if (Opcode == ARM::BR_JTadd)
1021 else if (Opcode == ARM::BR_JTm)
1024 const MachineOperand &MO1 = MI->getOperand(OpNum);
1025 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1026 unsigned JTI = MO1.getIndex();
1028 // Emit a label for the jump table.
1029 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1030 OutStreamer.EmitLabel(JTISymbol);
1032 // Mark the jump table as data-in-code.
1033 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
1035 // Emit each entry of the table.
1036 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1037 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1038 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1040 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1041 MachineBasicBlock *MBB = JTBBs[i];
1042 // Construct an MCExpr for the entry. We want a value of the form:
1043 // (BasicBlockAddr - TableBeginAddr)
1045 // For example, a table with entries jumping to basic blocks BB0 and BB1
1048 // .word (LBB0 - LJTI_0_0)
1049 // .word (LBB1 - LJTI_0_0)
1050 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1052 if (TM.getRelocationModel() == Reloc::PIC_)
1053 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1056 // If we're generating a table of Thumb addresses in static relocation
1057 // model, we need to add one to keep interworking correctly.
1058 else if (AFI->isThumbFunction())
1059 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1061 OutStreamer.EmitValue(Expr, 4);
1063 // Mark the end of jump table data-in-code region.
1064 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1067 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1068 unsigned Opcode = MI->getOpcode();
1069 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1070 const MachineOperand &MO1 = MI->getOperand(OpNum);
1071 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1072 unsigned JTI = MO1.getIndex();
1074 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1075 OutStreamer.EmitLabel(JTISymbol);
1077 // Emit each entry of the table.
1078 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1079 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1080 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1081 unsigned OffsetWidth = 4;
1082 if (MI->getOpcode() == ARM::t2TBB_JT) {
1084 // Mark the jump table as data-in-code.
1085 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1086 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1088 // Mark the jump table as data-in-code.
1089 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1092 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1093 MachineBasicBlock *MBB = JTBBs[i];
1094 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1096 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1097 if (OffsetWidth == 4) {
1098 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
1099 .addExpr(MBBSymbolExpr)
1104 // Otherwise it's an offset from the dispatch instruction. Construct an
1105 // MCExpr for the entry. We want a value of the form:
1106 // (BasicBlockAddr - TableBeginAddr) / 2
1108 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1111 // .byte (LBB0 - LJTI_0_0) / 2
1112 // .byte (LBB1 - LJTI_0_0) / 2
1113 const MCExpr *Expr =
1114 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1115 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1117 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1119 OutStreamer.EmitValue(Expr, OffsetWidth);
1121 // Mark the end of jump table data-in-code region. 32-bit offsets use
1122 // actual branch instructions here, so we don't mark those as a data-region
1124 if (OffsetWidth != 4)
1125 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1128 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1129 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1130 "Only instruction which are involved into frame setup code are allowed");
1132 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1133 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1134 const MachineFunction &MF = *MI->getParent()->getParent();
1135 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1136 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1138 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1139 unsigned Opc = MI->getOpcode();
1140 unsigned SrcReg, DstReg;
1142 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1143 // Two special cases:
1144 // 1) tPUSH does not have src/dst regs.
1145 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1146 // load. Yes, this is pretty fragile, but for now I don't see better
1148 SrcReg = DstReg = ARM::SP;
1150 SrcReg = MI->getOperand(1).getReg();
1151 DstReg = MI->getOperand(0).getReg();
1154 // Try to figure out the unwinding opcode out of src / dst regs.
1155 if (MI->mayStore()) {
1157 assert(DstReg == ARM::SP &&
1158 "Only stack pointer as a destination reg is supported");
1160 SmallVector<unsigned, 4> RegList;
1161 // Skip src & dst reg, and pred ops.
1162 unsigned StartOp = 2 + 2;
1163 // Use all the operands.
1164 unsigned NumOffset = 0;
1169 llvm_unreachable("Unsupported opcode for unwinding information");
1171 // Special case here: no src & dst reg, but two extra imp ops.
1172 StartOp = 2; NumOffset = 2;
1173 case ARM::STMDB_UPD:
1174 case ARM::t2STMDB_UPD:
1175 case ARM::VSTMDDB_UPD:
1176 assert(SrcReg == ARM::SP &&
1177 "Only stack pointer as a source reg is supported");
1178 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1180 const MachineOperand &MO = MI->getOperand(i);
1181 // Actually, there should never be any impdef stuff here. Skip it
1182 // temporary to workaround PR11902.
1183 if (MO.isImplicit())
1185 RegList.push_back(MO.getReg());
1188 case ARM::STR_PRE_IMM:
1189 case ARM::STR_PRE_REG:
1190 case ARM::t2STR_PRE:
1191 assert(MI->getOperand(2).getReg() == ARM::SP &&
1192 "Only stack pointer as a source reg is supported");
1193 RegList.push_back(SrcReg);
1196 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1197 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1199 // Changes of stack / frame pointer.
1200 if (SrcReg == ARM::SP) {
1205 llvm_unreachable("Unsupported opcode for unwinding information");
1211 Offset = -MI->getOperand(2).getImm();
1215 Offset = MI->getOperand(2).getImm();
1218 Offset = MI->getOperand(2).getImm()*4;
1222 Offset = -MI->getOperand(2).getImm()*4;
1224 case ARM::tLDRpci: {
1225 // Grab the constpool index and check, whether it corresponds to
1226 // original or cloned constpool entry.
1227 unsigned CPI = MI->getOperand(1).getIndex();
1228 const MachineConstantPool *MCP = MF.getConstantPool();
1229 if (CPI >= MCP->getConstants().size())
1230 CPI = AFI.getOriginalCPIdx(CPI);
1231 assert(CPI != -1U && "Invalid constpool index");
1233 // Derive the actual offset.
1234 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1235 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1236 // FIXME: Check for user, it should be "add" instruction!
1237 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1242 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1243 if (DstReg == FramePtr && FramePtr != ARM::SP)
1244 // Set-up of the frame pointer. Positive values correspond to "add"
1246 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1247 else if (DstReg == ARM::SP) {
1248 // Change of SP by an offset. Positive values correspond to "sub"
1250 ATS.emitPad(Offset);
1252 // Move of SP to a register. Positive values correspond to an "add"
1254 ATS.emitMovSP(DstReg, -Offset);
1257 } else if (DstReg == ARM::SP) {
1259 llvm_unreachable("Unsupported opcode for unwinding information");
1263 llvm_unreachable("Unsupported opcode for unwinding information");
1268 // Simple pseudo-instructions have their lowering (with expansion to real
1269 // instructions) auto-generated.
1270 #include "ARMGenMCPseudoLowering.inc"
1272 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1273 const DataLayout *DL = TM.getDataLayout();
1275 // If we just ended a constant pool, mark it as such.
1276 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1277 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1278 InConstantPool = false;
1281 // Emit unwinding stuff for frame-related instructions
1282 if (Subtarget->isTargetEHABICompatible() &&
1283 MI->getFlag(MachineInstr::FrameSetup))
1284 EmitUnwindingInstruction(MI);
1286 // Do any auto-generated pseudo lowerings.
1287 if (emitPseudoExpansionLowering(OutStreamer, MI))
1290 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1291 "Pseudo flag setting opcode should be expanded early");
1293 // Check for manual lowerings.
1294 unsigned Opc = MI->getOpcode();
1296 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1297 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1299 case ARM::tLEApcrel:
1300 case ARM::t2LEApcrel: {
1301 // FIXME: Need to also handle globals and externals
1302 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1303 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1304 ARM::t2LEApcrel ? ARM::t2ADR
1305 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1307 .addReg(MI->getOperand(0).getReg())
1308 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1309 // Add predicate operands.
1310 .addImm(MI->getOperand(2).getImm())
1311 .addReg(MI->getOperand(3).getReg()));
1314 case ARM::LEApcrelJT:
1315 case ARM::tLEApcrelJT:
1316 case ARM::t2LEApcrelJT: {
1317 MCSymbol *JTIPICSymbol =
1318 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1319 MI->getOperand(2).getImm());
1320 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1321 ARM::t2LEApcrelJT ? ARM::t2ADR
1322 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1324 .addReg(MI->getOperand(0).getReg())
1325 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1326 // Add predicate operands.
1327 .addImm(MI->getOperand(3).getImm())
1328 .addReg(MI->getOperand(4).getReg()));
1331 // Darwin call instructions are just normal call instructions with different
1332 // clobber semantics (they clobber R9).
1333 case ARM::BX_CALL: {
1334 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1337 // Add predicate operands.
1340 // Add 's' bit operand (always reg0 for this)
1343 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1344 .addReg(MI->getOperand(0).getReg()));
1347 case ARM::tBX_CALL: {
1348 if (Subtarget->hasV5TOps())
1349 llvm_unreachable("Expected BLX to be selected for v5t+");
1351 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1352 // that the saved lr has its LSB set correctly (the arch doesn't
1354 // So here we generate a bl to a small jump pad that does bx rN.
1355 // The jump pads are emitted after the function body.
1357 unsigned TReg = MI->getOperand(0).getReg();
1358 MCSymbol *TRegSym = nullptr;
1359 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1360 if (ThumbIndirectPads[i].first == TReg) {
1361 TRegSym = ThumbIndirectPads[i].second;
1367 TRegSym = OutContext.CreateTempSymbol();
1368 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1371 // Create a link-saving branch to the Reg Indirect Jump Pad.
1372 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
1373 // Predicate comes first here.
1374 .addImm(ARMCC::AL).addReg(0)
1375 .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
1378 case ARM::BMOVPCRX_CALL: {
1379 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1382 // Add predicate operands.
1385 // Add 's' bit operand (always reg0 for this)
1388 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1390 .addReg(MI->getOperand(0).getReg())
1391 // Add predicate operands.
1394 // Add 's' bit operand (always reg0 for this)
1398 case ARM::BMOVPCB_CALL: {
1399 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1402 // Add predicate operands.
1405 // Add 's' bit operand (always reg0 for this)
1408 const MachineOperand &Op = MI->getOperand(0);
1409 const GlobalValue *GV = Op.getGlobal();
1410 const unsigned TF = Op.getTargetFlags();
1411 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1412 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1413 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1415 // Add predicate operands.
1420 case ARM::MOVi16_ga_pcrel:
1421 case ARM::t2MOVi16_ga_pcrel: {
1423 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1424 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1426 unsigned TF = MI->getOperand(1).getTargetFlags();
1427 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1428 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1429 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1431 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1432 getFunctionNumber(),
1433 MI->getOperand(2).getImm(), OutContext);
1434 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1435 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1436 const MCExpr *PCRelExpr =
1437 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1438 MCBinaryExpr::CreateAdd(LabelSymExpr,
1439 MCConstantExpr::Create(PCAdj, OutContext),
1440 OutContext), OutContext), OutContext);
1441 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1443 // Add predicate operands.
1444 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1445 TmpInst.addOperand(MCOperand::CreateReg(0));
1446 // Add 's' bit operand (always reg0 for this)
1447 TmpInst.addOperand(MCOperand::CreateReg(0));
1448 EmitToStreamer(OutStreamer, TmpInst);
1451 case ARM::MOVTi16_ga_pcrel:
1452 case ARM::t2MOVTi16_ga_pcrel: {
1454 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1455 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1456 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1457 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1459 unsigned TF = MI->getOperand(2).getTargetFlags();
1460 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1461 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1462 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1464 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1465 getFunctionNumber(),
1466 MI->getOperand(3).getImm(), OutContext);
1467 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1468 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1469 const MCExpr *PCRelExpr =
1470 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1471 MCBinaryExpr::CreateAdd(LabelSymExpr,
1472 MCConstantExpr::Create(PCAdj, OutContext),
1473 OutContext), OutContext), OutContext);
1474 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1475 // Add predicate operands.
1476 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1477 TmpInst.addOperand(MCOperand::CreateReg(0));
1478 // Add 's' bit operand (always reg0 for this)
1479 TmpInst.addOperand(MCOperand::CreateReg(0));
1480 EmitToStreamer(OutStreamer, TmpInst);
1483 case ARM::tPICADD: {
1484 // This is a pseudo op for a label + instruction sequence, which looks like:
1487 // This adds the address of LPC0 to r0.
1490 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1491 getFunctionNumber(), MI->getOperand(2).getImm(),
1494 // Form and emit the add.
1495 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1496 .addReg(MI->getOperand(0).getReg())
1497 .addReg(MI->getOperand(0).getReg())
1499 // Add predicate operands.
1505 // This is a pseudo op for a label + instruction sequence, which looks like:
1508 // This adds the address of LPC0 to r0.
1511 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1512 getFunctionNumber(), MI->getOperand(2).getImm(),
1515 // Form and emit the add.
1516 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1517 .addReg(MI->getOperand(0).getReg())
1519 .addReg(MI->getOperand(1).getReg())
1520 // Add predicate operands.
1521 .addImm(MI->getOperand(3).getImm())
1522 .addReg(MI->getOperand(4).getReg())
1523 // Add 's' bit operand (always reg0 for this)
1534 case ARM::PICLDRSH: {
1535 // This is a pseudo op for a label + instruction sequence, which looks like:
1538 // The LCP0 label is referenced by a constant pool entry in order to get
1539 // a PC-relative address at the ldr instruction.
1542 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1543 getFunctionNumber(), MI->getOperand(2).getImm(),
1546 // Form and emit the load
1548 switch (MI->getOpcode()) {
1550 llvm_unreachable("Unexpected opcode!");
1551 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1552 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1553 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1554 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1555 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1556 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1557 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1558 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1560 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1561 .addReg(MI->getOperand(0).getReg())
1563 .addReg(MI->getOperand(1).getReg())
1565 // Add predicate operands.
1566 .addImm(MI->getOperand(3).getImm())
1567 .addReg(MI->getOperand(4).getReg()));
1571 case ARM::CONSTPOOL_ENTRY: {
1572 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1573 /// in the function. The first operand is the ID# for this instruction, the
1574 /// second is the index into the MachineConstantPool that this is, the third
1575 /// is the size in bytes of this constant pool entry.
1576 /// The required alignment is specified on the basic block holding this MI.
1577 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1578 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1580 // If this is the first entry of the pool, mark it.
1581 if (!InConstantPool) {
1582 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1583 InConstantPool = true;
1586 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1588 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1589 if (MCPE.isMachineConstantPoolEntry())
1590 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1592 EmitGlobalConstant(MCPE.Val.ConstVal);
1595 case ARM::t2BR_JT: {
1596 // Lower and emit the instruction itself, then the jump table following it.
1597 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1599 .addReg(MI->getOperand(0).getReg())
1600 // Add predicate operands.
1604 // Output the data for the jump table itself
1608 case ARM::t2TBB_JT: {
1609 // Lower and emit the instruction itself, then the jump table following it.
1610 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1612 .addReg(MI->getOperand(0).getReg())
1613 // Add predicate operands.
1617 // Output the data for the jump table itself
1619 // Make sure the next instruction is 2-byte aligned.
1623 case ARM::t2TBH_JT: {
1624 // Lower and emit the instruction itself, then the jump table following it.
1625 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1627 .addReg(MI->getOperand(0).getReg())
1628 // Add predicate operands.
1632 // Output the data for the jump table itself
1638 // Lower and emit the instruction itself, then the jump table following it.
1641 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1642 ARM::MOVr : ARM::tMOVr;
1643 TmpInst.setOpcode(Opc);
1644 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1645 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1646 // Add predicate operands.
1647 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1648 TmpInst.addOperand(MCOperand::CreateReg(0));
1649 // Add 's' bit operand (always reg0 for this)
1650 if (Opc == ARM::MOVr)
1651 TmpInst.addOperand(MCOperand::CreateReg(0));
1652 EmitToStreamer(OutStreamer, TmpInst);
1654 // Make sure the Thumb jump table is 4-byte aligned.
1655 if (Opc == ARM::tMOVr)
1658 // Output the data for the jump table itself
1663 // Lower and emit the instruction itself, then the jump table following it.
1666 if (MI->getOperand(1).getReg() == 0) {
1668 TmpInst.setOpcode(ARM::LDRi12);
1669 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1670 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1671 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1673 TmpInst.setOpcode(ARM::LDRrs);
1674 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1675 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1676 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1677 TmpInst.addOperand(MCOperand::CreateImm(0));
1679 // Add predicate operands.
1680 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1681 TmpInst.addOperand(MCOperand::CreateReg(0));
1682 EmitToStreamer(OutStreamer, TmpInst);
1684 // Output the data for the jump table itself
1688 case ARM::BR_JTadd: {
1689 // Lower and emit the instruction itself, then the jump table following it.
1690 // add pc, target, idx
1691 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1693 .addReg(MI->getOperand(0).getReg())
1694 .addReg(MI->getOperand(1).getReg())
1695 // Add predicate operands.
1698 // Add 's' bit operand (always reg0 for this)
1701 // Output the data for the jump table itself
1706 OutStreamer.EmitZeros(MI->getOperand(1).getImm());
1709 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1710 // FIXME: Remove this special case when they do.
1711 if (!Subtarget->isTargetMachO()) {
1712 //.long 0xe7ffdefe @ trap
1713 uint32_t Val = 0xe7ffdefeUL;
1714 OutStreamer.AddComment("trap");
1715 OutStreamer.EmitIntValue(Val, 4);
1720 case ARM::TRAPNaCl: {
1721 //.long 0xe7fedef0 @ trap
1722 uint32_t Val = 0xe7fedef0UL;
1723 OutStreamer.AddComment("trap");
1724 OutStreamer.EmitIntValue(Val, 4);
1728 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1729 // FIXME: Remove this special case when they do.
1730 if (!Subtarget->isTargetMachO()) {
1731 //.short 57086 @ trap
1732 uint16_t Val = 0xdefe;
1733 OutStreamer.AddComment("trap");
1734 OutStreamer.EmitIntValue(Val, 2);
1739 case ARM::t2Int_eh_sjlj_setjmp:
1740 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1741 case ARM::tInt_eh_sjlj_setjmp: {
1742 // Two incoming args: GPR:$src, GPR:$val
1745 // str $val, [$src, #4]
1750 unsigned SrcReg = MI->getOperand(0).getReg();
1751 unsigned ValReg = MI->getOperand(1).getReg();
1752 MCSymbol *Label = GetARMSJLJEHLabel();
1753 OutStreamer.AddComment("eh_setjmp begin");
1754 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1761 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1771 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1774 // The offset immediate is #4. The operand value is scaled by 4 for the
1775 // tSTR instruction.
1781 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1789 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1790 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1791 .addExpr(SymbolExpr)
1795 OutStreamer.AddComment("eh_setjmp end");
1796 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1804 OutStreamer.EmitLabel(Label);
1808 case ARM::Int_eh_sjlj_setjmp_nofp:
1809 case ARM::Int_eh_sjlj_setjmp: {
1810 // Two incoming args: GPR:$src, GPR:$val
1812 // str $val, [$src, #+4]
1816 unsigned SrcReg = MI->getOperand(0).getReg();
1817 unsigned ValReg = MI->getOperand(1).getReg();
1819 OutStreamer.AddComment("eh_setjmp begin");
1820 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1827 // 's' bit operand (always reg0 for this).
1830 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1838 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1844 // 's' bit operand (always reg0 for this).
1847 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1854 // 's' bit operand (always reg0 for this).
1857 OutStreamer.AddComment("eh_setjmp end");
1858 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1864 // 's' bit operand (always reg0 for this).
1868 case ARM::Int_eh_sjlj_longjmp: {
1869 // ldr sp, [$src, #8]
1870 // ldr $scratch, [$src, #4]
1873 unsigned SrcReg = MI->getOperand(0).getReg();
1874 unsigned ScratchReg = MI->getOperand(1).getReg();
1875 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1883 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1891 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1899 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1906 case ARM::tInt_eh_sjlj_longjmp: {
1907 // ldr $scratch, [$src, #8]
1909 // ldr $scratch, [$src, #4]
1912 unsigned SrcReg = MI->getOperand(0).getReg();
1913 unsigned ScratchReg = MI->getOperand(1).getReg();
1914 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1917 // The offset immediate is #8. The operand value is scaled by 4 for the
1918 // tLDR instruction.
1924 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1931 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1939 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1947 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1957 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1959 EmitToStreamer(OutStreamer, TmpInst);
1962 //===----------------------------------------------------------------------===//
1963 // Target Registry Stuff
1964 //===----------------------------------------------------------------------===//
1966 // Force static initialization.
1967 extern "C" void LLVMInitializeARMAsmPrinter() {
1968 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1969 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1970 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1971 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);