1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMTargetObjectFile.h"
22 #include "InstPrinter/ARMInstPrinter.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMMCExpr.h"
25 #include "llvm/ADT/SetVector.h"
26 #include "llvm/ADT/SmallString.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/IR/Type.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCInst.h"
41 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCObjectStreamer.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ARMBuildAttributes.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 void ARMAsmPrinter::EmitFunctionBodyEnd() {
61 // Make sure to terminate any constant pools that were at the end
65 InConstantPool = false;
66 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
69 void ARMAsmPrinter::EmitFunctionEntryLabel() {
70 if (AFI->isThumbFunction()) {
71 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
72 OutStreamer.EmitThumbFunc(CurrentFnSym);
75 OutStreamer.EmitLabel(CurrentFnSym);
78 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
80 TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
81 assert(Size && "C++ constructor pointer had zero size!");
83 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
84 assert(GV && "C++ constructor pointer was not a GlobalValue!");
86 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
88 (Subtarget->isTargetELF()
89 ? MCSymbolRefExpr::VK_ARM_TARGET1
90 : MCSymbolRefExpr::VK_None),
93 OutStreamer.EmitValue(E, Size);
96 /// runOnMachineFunction - This uses the EmitInstruction()
97 /// method to print assembly for each instruction.
99 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
100 AFI = MF.getInfo<ARMFunctionInfo>();
101 MCP = MF.getConstantPool();
103 SetupMachineFunction(MF);
105 if (Subtarget->isTargetCOFF()) {
106 bool Internal = MF.getFunction()->hasInternalLinkage();
107 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
108 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
109 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
111 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
112 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
113 OutStreamer.EmitCOFFSymbolType(Type);
114 OutStreamer.EndCOFFSymbolDef();
117 // Have common code print out the function header with linkage info etc.
118 EmitFunctionHeader();
120 // Emit the rest of the function body.
123 // We didn't modify anything.
127 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
128 raw_ostream &O, const char *Modifier) {
129 const MachineOperand &MO = MI->getOperand(OpNum);
130 unsigned TF = MO.getTargetFlags();
132 switch (MO.getType()) {
133 default: llvm_unreachable("<unknown operand type>");
134 case MachineOperand::MO_Register: {
135 unsigned Reg = MO.getReg();
136 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
137 assert(!MO.getSubReg() && "Subregs should be eliminated!");
138 if(ARM::GPRPairRegClass.contains(Reg)) {
139 const MachineFunction &MF = *MI->getParent()->getParent();
140 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
141 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
143 O << ARMInstPrinter::getRegisterName(Reg);
146 case MachineOperand::MO_Immediate: {
147 int64_t Imm = MO.getImm();
149 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
150 (TF == ARMII::MO_LO16))
152 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
153 (TF == ARMII::MO_HI16))
158 case MachineOperand::MO_MachineBasicBlock:
159 O << *MO.getMBB()->getSymbol();
161 case MachineOperand::MO_GlobalAddress: {
162 const GlobalValue *GV = MO.getGlobal();
163 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
164 (TF & ARMII::MO_LO16))
166 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
167 (TF & ARMII::MO_HI16))
169 O << *GetARMGVSymbol(GV, TF);
171 printOffset(MO.getOffset(), O);
172 if (TF == ARMII::MO_PLT)
176 case MachineOperand::MO_ConstantPoolIndex:
177 O << *GetCPISymbol(MO.getIndex());
182 //===--------------------------------------------------------------------===//
184 MCSymbol *ARMAsmPrinter::
185 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
186 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
187 SmallString<60> Name;
188 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
189 << getFunctionNumber() << '_' << uid << '_' << uid2;
190 return OutContext.GetOrCreateSymbol(Name.str());
194 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
195 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
196 SmallString<60> Name;
197 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
198 << getFunctionNumber();
199 return OutContext.GetOrCreateSymbol(Name.str());
202 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
203 unsigned AsmVariant, const char *ExtraCode,
205 // Does this asm operand have a single letter operand modifier?
206 if (ExtraCode && ExtraCode[0]) {
207 if (ExtraCode[1] != 0) return true; // Unknown modifier.
209 switch (ExtraCode[0]) {
211 // See if this is a generic print operand
212 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
213 case 'a': // Print as a memory address.
214 if (MI->getOperand(OpNum).isReg()) {
216 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
221 case 'c': // Don't print "#" before an immediate operand.
222 if (!MI->getOperand(OpNum).isImm())
224 O << MI->getOperand(OpNum).getImm();
226 case 'P': // Print a VFP double precision register.
227 case 'q': // Print a NEON quad precision register.
228 printOperand(MI, OpNum, O);
230 case 'y': // Print a VFP single precision register as indexed double.
231 if (MI->getOperand(OpNum).isReg()) {
232 unsigned Reg = MI->getOperand(OpNum).getReg();
233 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
234 // Find the 'd' register that has this 's' register as a sub-register,
235 // and determine the lane number.
236 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
237 if (!ARM::DPRRegClass.contains(*SR))
239 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
240 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
245 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
246 if (!MI->getOperand(OpNum).isImm())
248 O << ~(MI->getOperand(OpNum).getImm());
250 case 'L': // The low 16 bits of an immediate constant.
251 if (!MI->getOperand(OpNum).isImm())
253 O << (MI->getOperand(OpNum).getImm() & 0xffff);
255 case 'M': { // A register range suitable for LDM/STM.
256 if (!MI->getOperand(OpNum).isReg())
258 const MachineOperand &MO = MI->getOperand(OpNum);
259 unsigned RegBegin = MO.getReg();
260 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
261 // already got the operands in registers that are operands to the
262 // inline asm statement.
264 if (ARM::GPRPairRegClass.contains(RegBegin)) {
265 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
266 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
267 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
268 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
270 O << ARMInstPrinter::getRegisterName(RegBegin);
272 // FIXME: The register allocator not only may not have given us the
273 // registers in sequence, but may not be in ascending registers. This
274 // will require changes in the register allocator that'll need to be
275 // propagated down here if the operands change.
276 unsigned RegOps = OpNum + 1;
277 while (MI->getOperand(RegOps).isReg()) {
279 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
287 case 'R': // The most significant register of a pair.
288 case 'Q': { // The least significant register of a pair.
291 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
292 if (!FlagsOP.isImm())
294 unsigned Flags = FlagsOP.getImm();
296 // This operand may not be the one that actually provides the register. If
297 // it's tied to a previous one then we should refer instead to that one
298 // for registers and their classes.
300 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
301 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
302 unsigned OpFlags = MI->getOperand(OpNum).getImm();
303 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
305 Flags = MI->getOperand(OpNum).getImm();
307 // Later code expects OpNum to be pointing at the register rather than
312 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
314 InlineAsm::hasRegClassConstraint(Flags, RC);
315 if (RC == ARM::GPRPairRegClassID) {
318 const MachineOperand &MO = MI->getOperand(OpNum);
321 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
322 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
323 ARM::gsub_0 : ARM::gsub_1);
324 O << ARMInstPrinter::getRegisterName(Reg);
329 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
330 if (RegOp >= MI->getNumOperands())
332 const MachineOperand &MO = MI->getOperand(RegOp);
335 unsigned Reg = MO.getReg();
336 O << ARMInstPrinter::getRegisterName(Reg);
340 case 'e': // The low doubleword register of a NEON quad register.
341 case 'f': { // The high doubleword register of a NEON quad register.
342 if (!MI->getOperand(OpNum).isReg())
344 unsigned Reg = MI->getOperand(OpNum).getReg();
345 if (!ARM::QPRRegClass.contains(Reg))
347 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
348 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
349 ARM::dsub_0 : ARM::dsub_1);
350 O << ARMInstPrinter::getRegisterName(SubReg);
354 // This modifier is not yet supported.
355 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
357 case 'H': { // The highest-numbered register of a pair.
358 const MachineOperand &MO = MI->getOperand(OpNum);
361 const MachineFunction &MF = *MI->getParent()->getParent();
362 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
363 unsigned Reg = MO.getReg();
364 if(!ARM::GPRPairRegClass.contains(Reg))
366 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
367 O << ARMInstPrinter::getRegisterName(Reg);
373 printOperand(MI, OpNum, O);
377 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
378 unsigned OpNum, unsigned AsmVariant,
379 const char *ExtraCode,
381 // Does this asm operand have a single letter operand modifier?
382 if (ExtraCode && ExtraCode[0]) {
383 if (ExtraCode[1] != 0) return true; // Unknown modifier.
385 switch (ExtraCode[0]) {
386 case 'A': // A memory operand for a VLD1/VST1 instruction.
387 default: return true; // Unknown modifier.
388 case 'm': // The base register of a memory operand.
389 if (!MI->getOperand(OpNum).isReg())
391 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
396 const MachineOperand &MO = MI->getOperand(OpNum);
397 assert(MO.isReg() && "unexpected inline asm memory operand");
398 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
402 static bool isThumb(const MCSubtargetInfo& STI) {
403 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
406 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
407 const MCSubtargetInfo *EndInfo) const {
408 // If either end mode is unknown (EndInfo == NULL) or different than
409 // the start mode, then restore the start mode.
410 const bool WasThumb = isThumb(StartInfo);
411 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
412 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
416 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
417 if (Subtarget->isTargetMachO()) {
418 Reloc::Model RelocM = TM.getRelocationModel();
419 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
420 // Declare all the text sections up front (before the DWARF sections
421 // emitted by AsmPrinter::doInitialization) so the assembler will keep
422 // them together at the beginning of the object file. This helps
423 // avoid out-of-range branches that are due a fundamental limitation of
424 // the way symbol offsets are encoded with the current Darwin ARM
426 const TargetLoweringObjectFileMachO &TLOFMacho =
427 static_cast<const TargetLoweringObjectFileMachO &>(
428 getObjFileLowering());
430 // Collect the set of sections our functions will go into.
431 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
432 SmallPtrSet<const MCSection *, 8> > TextSections;
433 // Default text section comes first.
434 TextSections.insert(TLOFMacho.getTextSection());
435 // Now any user defined text sections from function attributes.
436 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
437 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
438 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
439 // Now the coalescable sections.
440 TextSections.insert(TLOFMacho.getTextCoalSection());
441 TextSections.insert(TLOFMacho.getConstTextCoalSection());
443 // Emit the sections in the .s file header to fix the order.
444 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
445 OutStreamer.SwitchSection(TextSections[i]);
447 if (RelocM == Reloc::DynamicNoPIC) {
448 const MCSection *sect =
449 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
450 MachO::S_SYMBOL_STUBS,
451 12, SectionKind::getText());
452 OutStreamer.SwitchSection(sect);
454 const MCSection *sect =
455 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
456 MachO::S_SYMBOL_STUBS,
457 16, SectionKind::getText());
458 OutStreamer.SwitchSection(sect);
460 const MCSection *StaticInitSect =
461 OutContext.getMachOSection("__TEXT", "__StaticInit",
463 MachO::S_ATTR_PURE_INSTRUCTIONS,
464 SectionKind::getText());
465 OutStreamer.SwitchSection(StaticInitSect);
468 // Compiling with debug info should not affect the code
469 // generation. Ensure the cstring section comes before the
470 // optional __DWARF secion. Otherwise, PC-relative loads would
471 // have to use different instruction sequences at "-g" in order to
472 // reach global data in the same object file.
473 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
476 // Use unified assembler syntax.
477 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
479 // Emit ARM Build Attributes
480 if (Subtarget->isTargetELF())
483 if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
484 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
488 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
489 MachineModuleInfoImpl::StubValueTy &MCSym) {
491 OutStreamer.EmitLabel(StubLabel);
492 // .indirect_symbol _foo
493 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
496 // External to current translation unit.
497 OutStreamer.EmitIntValue(0, 4/*size*/);
499 // Internal to current translation unit.
501 // When we place the LSDA into the TEXT section, the type info
502 // pointers need to be indirect and pc-rel. We accomplish this by
503 // using NLPs; however, sometimes the types are local to the file.
504 // We need to fill in the value for the NLP in those cases.
505 OutStreamer.EmitValue(
506 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 if (Subtarget->isTargetMachO()) {
513 // All darwin targets use mach-o.
514 const TargetLoweringObjectFileMachO &TLOFMacho =
515 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516 MachineModuleInfoMachO &MMIMacho =
517 MMI->getObjFileInfo<MachineModuleInfoMachO>();
519 // Output non-lazy-pointers for external and common global variables.
520 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
522 if (!Stubs.empty()) {
523 // Switch with ".non_lazy_symbol_pointer" directive.
524 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
527 for (auto &Stub : Stubs)
528 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
531 OutStreamer.AddBlankLine();
534 Stubs = MMIMacho.GetHiddenGVStubList();
535 if (!Stubs.empty()) {
536 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
539 for (auto &Stub : Stubs)
540 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
543 OutStreamer.AddBlankLine();
546 // Funny Darwin hack: This flag tells the linker that no global symbols
547 // contain code that falls through to other global symbols (e.g. the obvious
548 // implementation of multiple entry points). If this doesn't occur, the
549 // linker can safely perform dead code stripping. Since LLVM never
550 // generates code that does this, it is always safe to set.
551 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
554 // Emit a .data.rel section containing any stubs that were created.
555 if (Subtarget->isTargetELF()) {
556 const TargetLoweringObjectFileELF &TLOFELF =
557 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
559 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
561 // Output stubs for external and common global variables.
562 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
563 if (!Stubs.empty()) {
564 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
565 const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
567 for (auto &stub: Stubs) {
568 OutStreamer.EmitLabel(stub.first);
569 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
570 TD->getPointerSize(0));
577 //===----------------------------------------------------------------------===//
578 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
580 // The following seem like one-off assembler flags, but they actually need
581 // to appear in the .ARM.attributes section in ELF.
582 // Instead of subclassing the MCELFStreamer, we do the work here.
584 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
585 const ARMSubtarget *Subtarget) {
587 return ARMBuildAttrs::v5TEJ;
589 if (Subtarget->hasV8Ops())
590 return ARMBuildAttrs::v8;
591 else if (Subtarget->hasV7Ops()) {
592 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
593 return ARMBuildAttrs::v7E_M;
594 return ARMBuildAttrs::v7;
595 } else if (Subtarget->hasV6T2Ops())
596 return ARMBuildAttrs::v6T2;
597 else if (Subtarget->hasV6MOps())
598 return ARMBuildAttrs::v6S_M;
599 else if (Subtarget->hasV6Ops())
600 return ARMBuildAttrs::v6;
601 else if (Subtarget->hasV5TEOps())
602 return ARMBuildAttrs::v5TE;
603 else if (Subtarget->hasV5TOps())
604 return ARMBuildAttrs::v5T;
605 else if (Subtarget->hasV4TOps())
606 return ARMBuildAttrs::v4T;
608 return ARMBuildAttrs::v4;
611 void ARMAsmPrinter::emitAttributes() {
612 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
613 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
615 ATS.switchVendor("aeabi");
617 std::string CPUString = Subtarget->getCPUString();
619 // FIXME: remove krait check when GNU tools support krait cpu
620 if (CPUString != "generic" && CPUString != "krait")
621 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
623 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
624 getArchForCPU(CPUString, Subtarget));
626 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
627 // profile is not applicable (e.g. pre v7, or cross-profile code)".
628 if (Subtarget->hasV7Ops()) {
629 if (Subtarget->isAClass()) {
630 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
631 ARMBuildAttrs::ApplicationProfile);
632 } else if (Subtarget->isRClass()) {
633 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
634 ARMBuildAttrs::RealTimeProfile);
635 } else if (Subtarget->isMClass()) {
636 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
637 ARMBuildAttrs::MicroControllerProfile);
641 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
642 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
643 if (Subtarget->isThumb1Only()) {
644 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
645 ARMBuildAttrs::Allowed);
646 } else if (Subtarget->hasThumb2()) {
647 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
648 ARMBuildAttrs::AllowThumb32);
651 if (Subtarget->hasNEON()) {
652 /* NEON is not exactly a VFP architecture, but GAS emit one of
653 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
654 if (Subtarget->hasFPARMv8()) {
655 if (Subtarget->hasCrypto())
656 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
658 ATS.emitFPU(ARM::NEON_FP_ARMV8);
660 else if (Subtarget->hasVFP4())
661 ATS.emitFPU(ARM::NEON_VFPV4);
663 ATS.emitFPU(ARM::NEON);
664 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
665 if (Subtarget->hasV8Ops())
666 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
667 ARMBuildAttrs::AllowNeonARMv8);
669 if (Subtarget->hasFPARMv8())
670 ATS.emitFPU(ARM::FP_ARMV8);
671 else if (Subtarget->hasVFP4())
672 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
673 else if (Subtarget->hasVFP3())
674 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
675 else if (Subtarget->hasVFP2())
676 ATS.emitFPU(ARM::VFPV2);
679 if (TM.getRelocationModel() == Reloc::PIC_) {
680 // PIC specific attributes.
681 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
682 ARMBuildAttrs::AddressRWPCRel);
683 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
684 ARMBuildAttrs::AddressROPCRel);
685 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
686 ARMBuildAttrs::AddressGOT);
688 // Allow direct addressing of imported data for all other relocation models.
689 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
690 ARMBuildAttrs::AddressDirect);
693 // Signal various FP modes.
694 if (!TM.Options.UnsafeFPMath) {
695 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
696 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
697 ARMBuildAttrs::Allowed);
700 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
701 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
702 ARMBuildAttrs::Allowed);
704 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
705 ARMBuildAttrs::AllowIEE754);
707 // FIXME: add more flags to ARMBuildAttributes.h
708 // 8-bytes alignment stuff.
709 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
710 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
712 // ABI_HardFP_use attribute to indicate single precision FP.
713 if (Subtarget->isFPOnlySP())
714 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
715 ARMBuildAttrs::HardFPSinglePrecision);
717 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
718 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
719 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
721 // FIXME: Should we signal R9 usage?
723 if (Subtarget->hasFP16())
724 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
726 if (Subtarget->hasMPExtension())
727 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
729 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
730 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
731 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
732 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
733 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
734 // otherwise, the default value (AllowDIVIfExists) applies.
735 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
736 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
739 if (const Module *SourceModule = MMI->getModule()) {
740 // ABI_PCS_wchar_t to indicate wchar_t width
741 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
742 if (auto WCharWidthValue = cast_or_null<ConstantInt>(
743 SourceModule->getModuleFlag("wchar_size"))) {
744 int WCharWidth = WCharWidthValue->getZExtValue();
745 assert((WCharWidth == 2 || WCharWidth == 4) &&
746 "wchar_t width must be 2 or 4 bytes");
747 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
750 // ABI_enum_size to indicate enum width
751 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
752 // (all enums contain a value needing 32 bits to encode).
753 if (auto EnumWidthValue = cast_or_null<ConstantInt>(
754 SourceModule->getModuleFlag("min_enum_size"))) {
755 int EnumWidth = EnumWidthValue->getZExtValue();
756 assert((EnumWidth == 1 || EnumWidth == 4) &&
757 "Minimum enum width must be 1 or 4 bytes");
758 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
759 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
764 // TODO: We currently only support either reserving the register, or treating
765 // it as another callee-saved register, but not as SB or a TLS pointer; It
766 // would instead be nicer to push this from the frontend as metadata, as we do
767 // for the wchar and enum size tags
768 if (Subtarget->isR9Reserved())
769 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
770 ARMBuildAttrs::R9Reserved);
772 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
773 ARMBuildAttrs::R9IsGPR);
775 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
776 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
777 ARMBuildAttrs::AllowTZVirtualization);
778 else if (Subtarget->hasTrustZone())
779 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
780 ARMBuildAttrs::AllowTZ);
781 else if (Subtarget->hasVirtualization())
782 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
783 ARMBuildAttrs::AllowVirtualization);
785 ATS.finishAttributeSection();
788 //===----------------------------------------------------------------------===//
790 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
791 unsigned LabelId, MCContext &Ctx) {
793 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
794 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
798 static MCSymbolRefExpr::VariantKind
799 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
801 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
802 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
803 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
804 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
805 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
806 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
808 llvm_unreachable("Invalid ARMCPModifier!");
811 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
812 unsigned char TargetFlags) {
813 if (Subtarget->isTargetMachO()) {
814 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
815 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
818 return getSymbol(GV);
820 // FIXME: Remove this when Darwin transition to @GOT like syntax.
821 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
822 MachineModuleInfoMachO &MMIMachO =
823 MMI->getObjFileInfo<MachineModuleInfoMachO>();
824 MachineModuleInfoImpl::StubValueTy &StubSym =
825 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
826 : MMIMachO.getGVStubEntry(MCSym);
827 if (!StubSym.getPointer())
828 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
829 !GV->hasInternalLinkage());
831 } else if (Subtarget->isTargetCOFF()) {
832 assert(Subtarget->isTargetWindows() &&
833 "Windows is the only supported COFF target");
835 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
837 return getSymbol(GV);
839 SmallString<128> Name;
841 getNameWithPrefix(Name, GV);
843 return OutContext.GetOrCreateSymbol(Name);
844 } else if (Subtarget->isTargetELF()) {
845 return getSymbol(GV);
847 llvm_unreachable("unexpected target");
851 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
852 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
854 TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
856 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
859 if (ACPV->isLSDA()) {
860 SmallString<128> Str;
861 raw_svector_ostream OS(Str);
862 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
863 MCSym = OutContext.GetOrCreateSymbol(OS.str());
864 } else if (ACPV->isBlockAddress()) {
865 const BlockAddress *BA =
866 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
867 MCSym = GetBlockAddressSymbol(BA);
868 } else if (ACPV->isGlobalValue()) {
869 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
871 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
872 // flag the global as MO_NONLAZY.
873 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
874 MCSym = GetARMGVSymbol(GV, TF);
875 } else if (ACPV->isMachineBasicBlock()) {
876 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
877 MCSym = MBB->getSymbol();
879 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
880 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
881 MCSym = GetExternalSymbolSymbol(Sym);
884 // Create an MCSymbol for the reference.
886 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
889 if (ACPV->getPCAdjustment()) {
890 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
894 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
896 MCBinaryExpr::CreateAdd(PCRelExpr,
897 MCConstantExpr::Create(ACPV->getPCAdjustment(),
900 if (ACPV->mustAddCurrentAddress()) {
901 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
902 // label, so just emit a local label end reference that instead.
903 MCSymbol *DotSym = OutContext.CreateTempSymbol();
904 OutStreamer.EmitLabel(DotSym);
905 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
906 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
908 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
910 OutStreamer.EmitValue(Expr, Size);
913 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
914 unsigned Opcode = MI->getOpcode();
916 if (Opcode == ARM::BR_JTadd)
918 else if (Opcode == ARM::BR_JTm)
921 const MachineOperand &MO1 = MI->getOperand(OpNum);
922 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
923 unsigned JTI = MO1.getIndex();
925 // Emit a label for the jump table.
926 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
927 OutStreamer.EmitLabel(JTISymbol);
929 // Mark the jump table as data-in-code.
930 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
932 // Emit each entry of the table.
933 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
934 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
935 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
937 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
938 MachineBasicBlock *MBB = JTBBs[i];
939 // Construct an MCExpr for the entry. We want a value of the form:
940 // (BasicBlockAddr - TableBeginAddr)
942 // For example, a table with entries jumping to basic blocks BB0 and BB1
945 // .word (LBB0 - LJTI_0_0)
946 // .word (LBB1 - LJTI_0_0)
947 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
949 if (TM.getRelocationModel() == Reloc::PIC_)
950 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
953 // If we're generating a table of Thumb addresses in static relocation
954 // model, we need to add one to keep interworking correctly.
955 else if (AFI->isThumbFunction())
956 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
958 OutStreamer.EmitValue(Expr, 4);
960 // Mark the end of jump table data-in-code region.
961 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
964 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
965 unsigned Opcode = MI->getOpcode();
966 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
967 const MachineOperand &MO1 = MI->getOperand(OpNum);
968 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
969 unsigned JTI = MO1.getIndex();
971 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
972 OutStreamer.EmitLabel(JTISymbol);
974 // Emit each entry of the table.
975 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
976 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
977 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
978 unsigned OffsetWidth = 4;
979 if (MI->getOpcode() == ARM::t2TBB_JT) {
981 // Mark the jump table as data-in-code.
982 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
983 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
985 // Mark the jump table as data-in-code.
986 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
989 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
990 MachineBasicBlock *MBB = JTBBs[i];
991 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
993 // If this isn't a TBB or TBH, the entries are direct branch instructions.
994 if (OffsetWidth == 4) {
995 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
996 .addExpr(MBBSymbolExpr)
1001 // Otherwise it's an offset from the dispatch instruction. Construct an
1002 // MCExpr for the entry. We want a value of the form:
1003 // (BasicBlockAddr - TableBeginAddr) / 2
1005 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1008 // .byte (LBB0 - LJTI_0_0) / 2
1009 // .byte (LBB1 - LJTI_0_0) / 2
1010 const MCExpr *Expr =
1011 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1012 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1014 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1016 OutStreamer.EmitValue(Expr, OffsetWidth);
1018 // Mark the end of jump table data-in-code region. 32-bit offsets use
1019 // actual branch instructions here, so we don't mark those as a data-region
1021 if (OffsetWidth != 4)
1022 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1025 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1026 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1027 "Only instruction which are involved into frame setup code are allowed");
1029 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1030 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1031 const MachineFunction &MF = *MI->getParent()->getParent();
1032 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1033 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1035 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1036 unsigned Opc = MI->getOpcode();
1037 unsigned SrcReg, DstReg;
1039 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1040 // Two special cases:
1041 // 1) tPUSH does not have src/dst regs.
1042 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1043 // load. Yes, this is pretty fragile, but for now I don't see better
1045 SrcReg = DstReg = ARM::SP;
1047 SrcReg = MI->getOperand(1).getReg();
1048 DstReg = MI->getOperand(0).getReg();
1051 // Try to figure out the unwinding opcode out of src / dst regs.
1052 if (MI->mayStore()) {
1054 assert(DstReg == ARM::SP &&
1055 "Only stack pointer as a destination reg is supported");
1057 SmallVector<unsigned, 4> RegList;
1058 // Skip src & dst reg, and pred ops.
1059 unsigned StartOp = 2 + 2;
1060 // Use all the operands.
1061 unsigned NumOffset = 0;
1066 llvm_unreachable("Unsupported opcode for unwinding information");
1068 // Special case here: no src & dst reg, but two extra imp ops.
1069 StartOp = 2; NumOffset = 2;
1070 case ARM::STMDB_UPD:
1071 case ARM::t2STMDB_UPD:
1072 case ARM::VSTMDDB_UPD:
1073 assert(SrcReg == ARM::SP &&
1074 "Only stack pointer as a source reg is supported");
1075 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1077 const MachineOperand &MO = MI->getOperand(i);
1078 // Actually, there should never be any impdef stuff here. Skip it
1079 // temporary to workaround PR11902.
1080 if (MO.isImplicit())
1082 RegList.push_back(MO.getReg());
1085 case ARM::STR_PRE_IMM:
1086 case ARM::STR_PRE_REG:
1087 case ARM::t2STR_PRE:
1088 assert(MI->getOperand(2).getReg() == ARM::SP &&
1089 "Only stack pointer as a source reg is supported");
1090 RegList.push_back(SrcReg);
1093 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1094 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1096 // Changes of stack / frame pointer.
1097 if (SrcReg == ARM::SP) {
1102 llvm_unreachable("Unsupported opcode for unwinding information");
1108 Offset = -MI->getOperand(2).getImm();
1112 Offset = MI->getOperand(2).getImm();
1115 Offset = MI->getOperand(2).getImm()*4;
1119 Offset = -MI->getOperand(2).getImm()*4;
1121 case ARM::tLDRpci: {
1122 // Grab the constpool index and check, whether it corresponds to
1123 // original or cloned constpool entry.
1124 unsigned CPI = MI->getOperand(1).getIndex();
1125 const MachineConstantPool *MCP = MF.getConstantPool();
1126 if (CPI >= MCP->getConstants().size())
1127 CPI = AFI.getOriginalCPIdx(CPI);
1128 assert(CPI != -1U && "Invalid constpool index");
1130 // Derive the actual offset.
1131 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1132 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1133 // FIXME: Check for user, it should be "add" instruction!
1134 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1139 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1140 if (DstReg == FramePtr && FramePtr != ARM::SP)
1141 // Set-up of the frame pointer. Positive values correspond to "add"
1143 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1144 else if (DstReg == ARM::SP) {
1145 // Change of SP by an offset. Positive values correspond to "sub"
1147 ATS.emitPad(Offset);
1149 // Move of SP to a register. Positive values correspond to an "add"
1151 ATS.emitMovSP(DstReg, -Offset);
1154 } else if (DstReg == ARM::SP) {
1156 llvm_unreachable("Unsupported opcode for unwinding information");
1160 llvm_unreachable("Unsupported opcode for unwinding information");
1165 // Simple pseudo-instructions have their lowering (with expansion to real
1166 // instructions) auto-generated.
1167 #include "ARMGenMCPseudoLowering.inc"
1169 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1170 const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
1172 // If we just ended a constant pool, mark it as such.
1173 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1174 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1175 InConstantPool = false;
1178 // Emit unwinding stuff for frame-related instructions
1179 if (Subtarget->isTargetEHABICompatible() &&
1180 MI->getFlag(MachineInstr::FrameSetup))
1181 EmitUnwindingInstruction(MI);
1183 // Do any auto-generated pseudo lowerings.
1184 if (emitPseudoExpansionLowering(OutStreamer, MI))
1187 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1188 "Pseudo flag setting opcode should be expanded early");
1190 // Check for manual lowerings.
1191 unsigned Opc = MI->getOpcode();
1193 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1194 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1196 case ARM::tLEApcrel:
1197 case ARM::t2LEApcrel: {
1198 // FIXME: Need to also handle globals and externals
1199 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1200 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1201 ARM::t2LEApcrel ? ARM::t2ADR
1202 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1204 .addReg(MI->getOperand(0).getReg())
1205 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1206 // Add predicate operands.
1207 .addImm(MI->getOperand(2).getImm())
1208 .addReg(MI->getOperand(3).getReg()));
1211 case ARM::LEApcrelJT:
1212 case ARM::tLEApcrelJT:
1213 case ARM::t2LEApcrelJT: {
1214 MCSymbol *JTIPICSymbol =
1215 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1216 MI->getOperand(2).getImm());
1217 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1218 ARM::t2LEApcrelJT ? ARM::t2ADR
1219 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1221 .addReg(MI->getOperand(0).getReg())
1222 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1223 // Add predicate operands.
1224 .addImm(MI->getOperand(3).getImm())
1225 .addReg(MI->getOperand(4).getReg()));
1228 // Darwin call instructions are just normal call instructions with different
1229 // clobber semantics (they clobber R9).
1230 case ARM::BX_CALL: {
1231 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1234 // Add predicate operands.
1237 // Add 's' bit operand (always reg0 for this)
1240 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1241 .addReg(MI->getOperand(0).getReg()));
1244 case ARM::tBX_CALL: {
1245 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1248 // Add predicate operands.
1252 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1253 .addReg(MI->getOperand(0).getReg())
1254 // Add predicate operands.
1259 case ARM::BMOVPCRX_CALL: {
1260 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1263 // Add predicate operands.
1266 // Add 's' bit operand (always reg0 for this)
1269 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1271 .addReg(MI->getOperand(0).getReg())
1272 // Add predicate operands.
1275 // Add 's' bit operand (always reg0 for this)
1279 case ARM::BMOVPCB_CALL: {
1280 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1283 // Add predicate operands.
1286 // Add 's' bit operand (always reg0 for this)
1289 const MachineOperand &Op = MI->getOperand(0);
1290 const GlobalValue *GV = Op.getGlobal();
1291 const unsigned TF = Op.getTargetFlags();
1292 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1293 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1294 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1296 // Add predicate operands.
1301 case ARM::MOVi16_ga_pcrel:
1302 case ARM::t2MOVi16_ga_pcrel: {
1304 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1305 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1307 unsigned TF = MI->getOperand(1).getTargetFlags();
1308 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1309 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1310 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1312 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1313 getFunctionNumber(),
1314 MI->getOperand(2).getImm(), OutContext);
1315 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1316 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1317 const MCExpr *PCRelExpr =
1318 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1319 MCBinaryExpr::CreateAdd(LabelSymExpr,
1320 MCConstantExpr::Create(PCAdj, OutContext),
1321 OutContext), OutContext), OutContext);
1322 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1324 // Add predicate operands.
1325 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 TmpInst.addOperand(MCOperand::CreateReg(0));
1327 // Add 's' bit operand (always reg0 for this)
1328 TmpInst.addOperand(MCOperand::CreateReg(0));
1329 EmitToStreamer(OutStreamer, TmpInst);
1332 case ARM::MOVTi16_ga_pcrel:
1333 case ARM::t2MOVTi16_ga_pcrel: {
1335 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1336 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1337 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1338 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1340 unsigned TF = MI->getOperand(2).getTargetFlags();
1341 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1342 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1343 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1345 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1346 getFunctionNumber(),
1347 MI->getOperand(3).getImm(), OutContext);
1348 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1349 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1350 const MCExpr *PCRelExpr =
1351 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1352 MCBinaryExpr::CreateAdd(LabelSymExpr,
1353 MCConstantExpr::Create(PCAdj, OutContext),
1354 OutContext), OutContext), OutContext);
1355 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1356 // Add predicate operands.
1357 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1358 TmpInst.addOperand(MCOperand::CreateReg(0));
1359 // Add 's' bit operand (always reg0 for this)
1360 TmpInst.addOperand(MCOperand::CreateReg(0));
1361 EmitToStreamer(OutStreamer, TmpInst);
1364 case ARM::tPICADD: {
1365 // This is a pseudo op for a label + instruction sequence, which looks like:
1368 // This adds the address of LPC0 to r0.
1371 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1372 getFunctionNumber(), MI->getOperand(2).getImm(),
1375 // Form and emit the add.
1376 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1377 .addReg(MI->getOperand(0).getReg())
1378 .addReg(MI->getOperand(0).getReg())
1380 // Add predicate operands.
1386 // This is a pseudo op for a label + instruction sequence, which looks like:
1389 // This adds the address of LPC0 to r0.
1392 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1393 getFunctionNumber(), MI->getOperand(2).getImm(),
1396 // Form and emit the add.
1397 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1398 .addReg(MI->getOperand(0).getReg())
1400 .addReg(MI->getOperand(1).getReg())
1401 // Add predicate operands.
1402 .addImm(MI->getOperand(3).getImm())
1403 .addReg(MI->getOperand(4).getReg())
1404 // Add 's' bit operand (always reg0 for this)
1415 case ARM::PICLDRSH: {
1416 // This is a pseudo op for a label + instruction sequence, which looks like:
1419 // The LCP0 label is referenced by a constant pool entry in order to get
1420 // a PC-relative address at the ldr instruction.
1423 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1424 getFunctionNumber(), MI->getOperand(2).getImm(),
1427 // Form and emit the load
1429 switch (MI->getOpcode()) {
1431 llvm_unreachable("Unexpected opcode!");
1432 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1433 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1434 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1435 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1436 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1437 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1438 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1439 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1441 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1442 .addReg(MI->getOperand(0).getReg())
1444 .addReg(MI->getOperand(1).getReg())
1446 // Add predicate operands.
1447 .addImm(MI->getOperand(3).getImm())
1448 .addReg(MI->getOperand(4).getReg()));
1452 case ARM::CONSTPOOL_ENTRY: {
1453 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1454 /// in the function. The first operand is the ID# for this instruction, the
1455 /// second is the index into the MachineConstantPool that this is, the third
1456 /// is the size in bytes of this constant pool entry.
1457 /// The required alignment is specified on the basic block holding this MI.
1458 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1459 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1461 // If this is the first entry of the pool, mark it.
1462 if (!InConstantPool) {
1463 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1464 InConstantPool = true;
1467 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1469 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1470 if (MCPE.isMachineConstantPoolEntry())
1471 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1473 EmitGlobalConstant(MCPE.Val.ConstVal);
1476 case ARM::t2BR_JT: {
1477 // Lower and emit the instruction itself, then the jump table following it.
1478 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1480 .addReg(MI->getOperand(0).getReg())
1481 // Add predicate operands.
1485 // Output the data for the jump table itself
1489 case ARM::t2TBB_JT: {
1490 // Lower and emit the instruction itself, then the jump table following it.
1491 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1493 .addReg(MI->getOperand(0).getReg())
1494 // Add predicate operands.
1498 // Output the data for the jump table itself
1500 // Make sure the next instruction is 2-byte aligned.
1504 case ARM::t2TBH_JT: {
1505 // Lower and emit the instruction itself, then the jump table following it.
1506 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1508 .addReg(MI->getOperand(0).getReg())
1509 // Add predicate operands.
1513 // Output the data for the jump table itself
1519 // Lower and emit the instruction itself, then the jump table following it.
1522 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1523 ARM::MOVr : ARM::tMOVr;
1524 TmpInst.setOpcode(Opc);
1525 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1526 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1527 // Add predicate operands.
1528 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1529 TmpInst.addOperand(MCOperand::CreateReg(0));
1530 // Add 's' bit operand (always reg0 for this)
1531 if (Opc == ARM::MOVr)
1532 TmpInst.addOperand(MCOperand::CreateReg(0));
1533 EmitToStreamer(OutStreamer, TmpInst);
1535 // Make sure the Thumb jump table is 4-byte aligned.
1536 if (Opc == ARM::tMOVr)
1539 // Output the data for the jump table itself
1544 // Lower and emit the instruction itself, then the jump table following it.
1547 if (MI->getOperand(1).getReg() == 0) {
1549 TmpInst.setOpcode(ARM::LDRi12);
1550 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1551 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1552 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1554 TmpInst.setOpcode(ARM::LDRrs);
1555 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1556 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1557 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1558 TmpInst.addOperand(MCOperand::CreateImm(0));
1560 // Add predicate operands.
1561 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1562 TmpInst.addOperand(MCOperand::CreateReg(0));
1563 EmitToStreamer(OutStreamer, TmpInst);
1565 // Output the data for the jump table itself
1569 case ARM::BR_JTadd: {
1570 // Lower and emit the instruction itself, then the jump table following it.
1571 // add pc, target, idx
1572 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1574 .addReg(MI->getOperand(0).getReg())
1575 .addReg(MI->getOperand(1).getReg())
1576 // Add predicate operands.
1579 // Add 's' bit operand (always reg0 for this)
1582 // Output the data for the jump table itself
1587 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1588 // FIXME: Remove this special case when they do.
1589 if (!Subtarget->isTargetMachO()) {
1590 //.long 0xe7ffdefe @ trap
1591 uint32_t Val = 0xe7ffdefeUL;
1592 OutStreamer.AddComment("trap");
1593 OutStreamer.EmitIntValue(Val, 4);
1598 case ARM::TRAPNaCl: {
1599 //.long 0xe7fedef0 @ trap
1600 uint32_t Val = 0xe7fedef0UL;
1601 OutStreamer.AddComment("trap");
1602 OutStreamer.EmitIntValue(Val, 4);
1606 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1607 // FIXME: Remove this special case when they do.
1608 if (!Subtarget->isTargetMachO()) {
1609 //.short 57086 @ trap
1610 uint16_t Val = 0xdefe;
1611 OutStreamer.AddComment("trap");
1612 OutStreamer.EmitIntValue(Val, 2);
1617 case ARM::t2Int_eh_sjlj_setjmp:
1618 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1619 case ARM::tInt_eh_sjlj_setjmp: {
1620 // Two incoming args: GPR:$src, GPR:$val
1623 // str $val, [$src, #4]
1628 unsigned SrcReg = MI->getOperand(0).getReg();
1629 unsigned ValReg = MI->getOperand(1).getReg();
1630 MCSymbol *Label = GetARMSJLJEHLabel();
1631 OutStreamer.AddComment("eh_setjmp begin");
1632 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1639 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1649 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1652 // The offset immediate is #4. The operand value is scaled by 4 for the
1653 // tSTR instruction.
1659 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1667 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1668 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1669 .addExpr(SymbolExpr)
1673 OutStreamer.AddComment("eh_setjmp end");
1674 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1682 OutStreamer.EmitLabel(Label);
1686 case ARM::Int_eh_sjlj_setjmp_nofp:
1687 case ARM::Int_eh_sjlj_setjmp: {
1688 // Two incoming args: GPR:$src, GPR:$val
1690 // str $val, [$src, #+4]
1694 unsigned SrcReg = MI->getOperand(0).getReg();
1695 unsigned ValReg = MI->getOperand(1).getReg();
1697 OutStreamer.AddComment("eh_setjmp begin");
1698 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1705 // 's' bit operand (always reg0 for this).
1708 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1716 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1722 // 's' bit operand (always reg0 for this).
1725 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1732 // 's' bit operand (always reg0 for this).
1735 OutStreamer.AddComment("eh_setjmp end");
1736 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1742 // 's' bit operand (always reg0 for this).
1746 case ARM::Int_eh_sjlj_longjmp: {
1747 // ldr sp, [$src, #8]
1748 // ldr $scratch, [$src, #4]
1751 unsigned SrcReg = MI->getOperand(0).getReg();
1752 unsigned ScratchReg = MI->getOperand(1).getReg();
1753 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1761 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1769 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1777 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1784 case ARM::tInt_eh_sjlj_longjmp: {
1785 // ldr $scratch, [$src, #8]
1787 // ldr $scratch, [$src, #4]
1790 unsigned SrcReg = MI->getOperand(0).getReg();
1791 unsigned ScratchReg = MI->getOperand(1).getReg();
1792 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1795 // The offset immediate is #8. The operand value is scaled by 4 for the
1796 // tLDR instruction.
1802 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1809 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1817 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1825 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1835 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1837 EmitToStreamer(OutStreamer, TmpInst);
1840 //===----------------------------------------------------------------------===//
1841 // Target Registry Stuff
1842 //===----------------------------------------------------------------------===//
1844 // Force static initialization.
1845 extern "C" void LLVMInitializeARMAsmPrinter() {
1846 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1847 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1848 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1849 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);