1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DebugInfo.h"
30 #include "llvm/Module.h"
31 #include "llvm/Type.h"
32 #include "llvm/Assembly/Writer.h"
33 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/DataLayout.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/TargetRegistry.h"
51 #include "llvm/Support/raw_ostream.h"
57 // Per section and per symbol attributes are not supported.
58 // To implement them we would need the ability to delay this emission
59 // until the assembly file is fully parsed/generated as only then do we
60 // know the symbol and section numbers.
61 class AttributeEmitter {
63 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
64 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
65 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
66 virtual void Finish() = 0;
67 virtual ~AttributeEmitter() {}
70 class AsmAttributeEmitter : public AttributeEmitter {
74 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
75 void MaybeSwitchVendor(StringRef Vendor) { }
77 void EmitAttribute(unsigned Attribute, unsigned Value) {
78 Streamer.EmitRawText("\t.eabi_attribute " +
79 Twine(Attribute) + ", " + Twine(Value));
82 void EmitTextAttribute(unsigned Attribute, StringRef String) {
84 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
85 case ARMBuildAttrs::CPU_name:
86 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
88 /* GAS requires .fpu to be emitted regardless of EABI attribute */
89 case ARMBuildAttrs::Advanced_SIMD_arch:
90 case ARMBuildAttrs::VFP_arch:
91 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
98 class ObjectAttributeEmitter : public AttributeEmitter {
99 // This structure holds all attributes, accounting for
100 // their string/numeric value, so we can later emmit them
101 // in declaration order, keeping all in the same vector
102 struct AttributeItemType {
110 StringRef StringValue;
113 MCObjectStreamer &Streamer;
114 StringRef CurrentVendor;
115 SmallVector<AttributeItemType, 64> Contents;
117 // Account for the ULEB/String size of each item,
118 // not just the number of items
120 // FIXME: this should be in a more generic place, but
121 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
122 size_t getULEBSize(int Value) {
126 Size += sizeof(int8_t); // Is this really necessary?
132 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
133 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
135 void MaybeSwitchVendor(StringRef Vendor) {
136 assert(!Vendor.empty() && "Vendor cannot be empty.");
138 if (CurrentVendor.empty())
139 CurrentVendor = Vendor;
140 else if (CurrentVendor == Vendor)
145 CurrentVendor = Vendor;
147 assert(Contents.size() == 0);
150 void EmitAttribute(unsigned Attribute, unsigned Value) {
151 AttributeItemType attr = {
152 AttributeItemType::NumericAttribute,
157 ContentsSize += getULEBSize(Attribute);
158 ContentsSize += getULEBSize(Value);
159 Contents.push_back(attr);
162 void EmitTextAttribute(unsigned Attribute, StringRef String) {
163 AttributeItemType attr = {
164 AttributeItemType::TextAttribute,
169 ContentsSize += getULEBSize(Attribute);
171 ContentsSize += String.size()+1;
173 Contents.push_back(attr);
177 // Vendor size + Vendor name + '\0'
178 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
181 const size_t TagHeaderSize = 1 + 4;
183 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
184 Streamer.EmitBytes(CurrentVendor, 0);
185 Streamer.EmitIntValue(0, 1); // '\0'
187 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
188 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
190 // Size should have been accounted for already, now
191 // emit each field as its type (ULEB or String)
192 for (unsigned int i=0; i<Contents.size(); ++i) {
193 AttributeItemType item = Contents[i];
194 Streamer.EmitULEB128IntValue(item.Tag, 0);
196 default: llvm_unreachable("Invalid attribute type");
197 case AttributeItemType::NumericAttribute:
198 Streamer.EmitULEB128IntValue(item.IntValue, 0);
200 case AttributeItemType::TextAttribute:
201 Streamer.EmitBytes(item.StringValue.upper(), 0);
202 Streamer.EmitIntValue(0, 1); // '\0'
211 } // end of anonymous namespace
213 MachineLocation ARMAsmPrinter::
214 getDebugValueLocation(const MachineInstr *MI) const {
215 MachineLocation Location;
216 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
217 // Frame address. Currently handles register +- offset only.
218 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
219 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
221 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
226 /// EmitDwarfRegOp - Emit dwarf register operation.
227 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
228 const TargetRegisterInfo *RI = TM.getRegisterInfo();
229 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
230 AsmPrinter::EmitDwarfRegOp(MLoc);
232 unsigned Reg = MLoc.getReg();
233 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
234 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
235 // S registers are described as bit-pieces of a register
236 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
237 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
239 unsigned SReg = Reg - ARM::S0;
240 bool odd = SReg & 0x1;
241 unsigned Rx = 256 + (SReg >> 1);
243 OutStreamer.AddComment("DW_OP_regx for S register");
244 EmitInt8(dwarf::DW_OP_regx);
246 OutStreamer.AddComment(Twine(SReg));
250 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
251 EmitInt8(dwarf::DW_OP_bit_piece);
255 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
261 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
262 // Q registers Q0-Q15 are described by composing two D registers together.
263 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
266 unsigned QReg = Reg - ARM::Q0;
267 unsigned D1 = 256 + 2 * QReg;
268 unsigned D2 = D1 + 1;
270 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
271 EmitInt8(dwarf::DW_OP_regx);
273 OutStreamer.AddComment("DW_OP_piece 8");
274 EmitInt8(dwarf::DW_OP_piece);
277 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
278 EmitInt8(dwarf::DW_OP_regx);
280 OutStreamer.AddComment("DW_OP_piece 8");
281 EmitInt8(dwarf::DW_OP_piece);
287 void ARMAsmPrinter::EmitFunctionBodyEnd() {
288 // Make sure to terminate any constant pools that were at the end
292 InConstantPool = false;
293 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
296 void ARMAsmPrinter::EmitFunctionEntryLabel() {
297 if (AFI->isThumbFunction()) {
298 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
299 OutStreamer.EmitThumbFunc(CurrentFnSym);
302 OutStreamer.EmitLabel(CurrentFnSym);
305 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
306 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
307 assert(Size && "C++ constructor pointer had zero size!");
309 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
310 assert(GV && "C++ constructor pointer was not a GlobalValue!");
312 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
313 (Subtarget->isTargetDarwin()
314 ? MCSymbolRefExpr::VK_None
315 : MCSymbolRefExpr::VK_ARM_TARGET1),
318 OutStreamer.EmitValue(E, Size);
321 /// runOnMachineFunction - This uses the EmitInstruction()
322 /// method to print assembly for each instruction.
324 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
325 AFI = MF.getInfo<ARMFunctionInfo>();
326 MCP = MF.getConstantPool();
328 return AsmPrinter::runOnMachineFunction(MF);
331 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
332 raw_ostream &O, const char *Modifier) {
333 const MachineOperand &MO = MI->getOperand(OpNum);
334 unsigned TF = MO.getTargetFlags();
336 switch (MO.getType()) {
337 default: llvm_unreachable("<unknown operand type>");
338 case MachineOperand::MO_Register: {
339 unsigned Reg = MO.getReg();
340 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
341 assert(!MO.getSubReg() && "Subregs should be eliminated!");
342 O << ARMInstPrinter::getRegisterName(Reg);
345 case MachineOperand::MO_Immediate: {
346 int64_t Imm = MO.getImm();
348 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
349 (TF == ARMII::MO_LO16))
351 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
352 (TF == ARMII::MO_HI16))
357 case MachineOperand::MO_MachineBasicBlock:
358 O << *MO.getMBB()->getSymbol();
360 case MachineOperand::MO_GlobalAddress: {
361 const GlobalValue *GV = MO.getGlobal();
362 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
363 (TF & ARMII::MO_LO16))
365 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
366 (TF & ARMII::MO_HI16))
368 O << *Mang->getSymbol(GV);
370 printOffset(MO.getOffset(), O);
371 if (TF == ARMII::MO_PLT)
375 case MachineOperand::MO_ExternalSymbol: {
376 O << *GetExternalSymbolSymbol(MO.getSymbolName());
377 if (TF == ARMII::MO_PLT)
381 case MachineOperand::MO_ConstantPoolIndex:
382 O << *GetCPISymbol(MO.getIndex());
384 case MachineOperand::MO_JumpTableIndex:
385 O << *GetJTISymbol(MO.getIndex());
390 //===--------------------------------------------------------------------===//
392 MCSymbol *ARMAsmPrinter::
393 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
396 << getFunctionNumber() << '_' << uid << '_' << uid2;
397 return OutContext.GetOrCreateSymbol(Name.str());
401 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
402 SmallString<60> Name;
403 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
404 << getFunctionNumber();
405 return OutContext.GetOrCreateSymbol(Name.str());
408 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
409 unsigned AsmVariant, const char *ExtraCode,
411 // Does this asm operand have a single letter operand modifier?
412 if (ExtraCode && ExtraCode[0]) {
413 if (ExtraCode[1] != 0) return true; // Unknown modifier.
415 switch (ExtraCode[0]) {
417 // See if this is a generic print operand
418 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
419 case 'a': // Print as a memory address.
420 if (MI->getOperand(OpNum).isReg()) {
422 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
427 case 'c': // Don't print "#" before an immediate operand.
428 if (!MI->getOperand(OpNum).isImm())
430 O << MI->getOperand(OpNum).getImm();
432 case 'P': // Print a VFP double precision register.
433 case 'q': // Print a NEON quad precision register.
434 printOperand(MI, OpNum, O);
436 case 'y': // Print a VFP single precision register as indexed double.
437 if (MI->getOperand(OpNum).isReg()) {
438 unsigned Reg = MI->getOperand(OpNum).getReg();
439 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
440 // Find the 'd' register that has this 's' register as a sub-register,
441 // and determine the lane number.
442 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
443 if (!ARM::DPRRegClass.contains(*SR))
445 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
446 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
451 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
452 if (!MI->getOperand(OpNum).isImm())
454 O << ~(MI->getOperand(OpNum).getImm());
456 case 'L': // The low 16 bits of an immediate constant.
457 if (!MI->getOperand(OpNum).isImm())
459 O << (MI->getOperand(OpNum).getImm() & 0xffff);
461 case 'M': { // A register range suitable for LDM/STM.
462 if (!MI->getOperand(OpNum).isReg())
464 const MachineOperand &MO = MI->getOperand(OpNum);
465 unsigned RegBegin = MO.getReg();
466 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
467 // already got the operands in registers that are operands to the
468 // inline asm statement.
470 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
472 // FIXME: The register allocator not only may not have given us the
473 // registers in sequence, but may not be in ascending registers. This
474 // will require changes in the register allocator that'll need to be
475 // propagated down here if the operands change.
476 unsigned RegOps = OpNum + 1;
477 while (MI->getOperand(RegOps).isReg()) {
479 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
487 case 'R': // The most significant register of a pair.
488 case 'Q': { // The least significant register of a pair.
491 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
492 if (!FlagsOP.isImm())
494 unsigned Flags = FlagsOP.getImm();
495 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
498 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
499 if (RegOp >= MI->getNumOperands())
501 const MachineOperand &MO = MI->getOperand(RegOp);
504 unsigned Reg = MO.getReg();
505 O << ARMInstPrinter::getRegisterName(Reg);
509 case 'e': // The low doubleword register of a NEON quad register.
510 case 'f': { // The high doubleword register of a NEON quad register.
511 if (!MI->getOperand(OpNum).isReg())
513 unsigned Reg = MI->getOperand(OpNum).getReg();
514 if (!ARM::QPRRegClass.contains(Reg))
516 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
517 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
518 ARM::dsub_0 : ARM::dsub_1);
519 O << ARMInstPrinter::getRegisterName(SubReg);
523 // This modifier is not yet supported.
524 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
526 case 'H': { // The highest-numbered register of a pair.
527 const MachineOperand &MO = MI->getOperand(OpNum);
530 const TargetRegisterClass &RC = ARM::GPRRegClass;
531 const MachineFunction &MF = *MI->getParent()->getParent();
532 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
534 unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
535 RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
537 unsigned Reg = RC.getRegister(RegIdx);
538 O << ARMInstPrinter::getRegisterName(Reg);
544 printOperand(MI, OpNum, O);
548 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
549 unsigned OpNum, unsigned AsmVariant,
550 const char *ExtraCode,
552 // Does this asm operand have a single letter operand modifier?
553 if (ExtraCode && ExtraCode[0]) {
554 if (ExtraCode[1] != 0) return true; // Unknown modifier.
556 switch (ExtraCode[0]) {
557 case 'A': // A memory operand for a VLD1/VST1 instruction.
558 default: return true; // Unknown modifier.
559 case 'm': // The base register of a memory operand.
560 if (!MI->getOperand(OpNum).isReg())
562 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
567 const MachineOperand &MO = MI->getOperand(OpNum);
568 assert(MO.isReg() && "unexpected inline asm memory operand");
569 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
573 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
574 if (Subtarget->isTargetDarwin()) {
575 Reloc::Model RelocM = TM.getRelocationModel();
576 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
577 // Declare all the text sections up front (before the DWARF sections
578 // emitted by AsmPrinter::doInitialization) so the assembler will keep
579 // them together at the beginning of the object file. This helps
580 // avoid out-of-range branches that are due a fundamental limitation of
581 // the way symbol offsets are encoded with the current Darwin ARM
583 const TargetLoweringObjectFileMachO &TLOFMacho =
584 static_cast<const TargetLoweringObjectFileMachO &>(
585 getObjFileLowering());
587 // Collect the set of sections our functions will go into.
588 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
589 SmallPtrSet<const MCSection *, 8> > TextSections;
590 // Default text section comes first.
591 TextSections.insert(TLOFMacho.getTextSection());
592 // Now any user defined text sections from function attributes.
593 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
594 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
595 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
596 // Now the coalescable sections.
597 TextSections.insert(TLOFMacho.getTextCoalSection());
598 TextSections.insert(TLOFMacho.getConstTextCoalSection());
600 // Emit the sections in the .s file header to fix the order.
601 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
602 OutStreamer.SwitchSection(TextSections[i]);
604 if (RelocM == Reloc::DynamicNoPIC) {
605 const MCSection *sect =
606 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
607 MCSectionMachO::S_SYMBOL_STUBS,
608 12, SectionKind::getText());
609 OutStreamer.SwitchSection(sect);
611 const MCSection *sect =
612 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
613 MCSectionMachO::S_SYMBOL_STUBS,
614 16, SectionKind::getText());
615 OutStreamer.SwitchSection(sect);
617 const MCSection *StaticInitSect =
618 OutContext.getMachOSection("__TEXT", "__StaticInit",
619 MCSectionMachO::S_REGULAR |
620 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
621 SectionKind::getText());
622 OutStreamer.SwitchSection(StaticInitSect);
626 // Use unified assembler syntax.
627 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
629 // Emit ARM Build Attributes
630 if (Subtarget->isTargetELF())
635 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
636 if (Subtarget->isTargetDarwin()) {
637 // All darwin targets use mach-o.
638 const TargetLoweringObjectFileMachO &TLOFMacho =
639 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
640 MachineModuleInfoMachO &MMIMacho =
641 MMI->getObjFileInfo<MachineModuleInfoMachO>();
643 // Output non-lazy-pointers for external and common global variables.
644 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
646 if (!Stubs.empty()) {
647 // Switch with ".non_lazy_symbol_pointer" directive.
648 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
650 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
652 OutStreamer.EmitLabel(Stubs[i].first);
653 // .indirect_symbol _foo
654 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
655 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
658 // External to current translation unit.
659 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
661 // Internal to current translation unit.
663 // When we place the LSDA into the TEXT section, the type info
664 // pointers need to be indirect and pc-rel. We accomplish this by
665 // using NLPs; however, sometimes the types are local to the file.
666 // We need to fill in the value for the NLP in those cases.
667 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
669 4/*size*/, 0/*addrspace*/);
673 OutStreamer.AddBlankLine();
676 Stubs = MMIMacho.GetHiddenGVStubList();
677 if (!Stubs.empty()) {
678 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
680 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
682 OutStreamer.EmitLabel(Stubs[i].first);
684 OutStreamer.EmitValue(MCSymbolRefExpr::
685 Create(Stubs[i].second.getPointer(),
687 4/*size*/, 0/*addrspace*/);
691 OutStreamer.AddBlankLine();
694 // Funny Darwin hack: This flag tells the linker that no global symbols
695 // contain code that falls through to other global symbols (e.g. the obvious
696 // implementation of multiple entry points). If this doesn't occur, the
697 // linker can safely perform dead code stripping. Since LLVM never
698 // generates code that does this, it is always safe to set.
699 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
703 //===----------------------------------------------------------------------===//
704 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
706 // The following seem like one-off assembler flags, but they actually need
707 // to appear in the .ARM.attributes section in ELF.
708 // Instead of subclassing the MCELFStreamer, we do the work here.
710 void ARMAsmPrinter::emitAttributes() {
712 emitARMAttributeSection();
714 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
715 bool emitFPU = false;
716 AttributeEmitter *AttrEmitter;
717 if (OutStreamer.hasRawTextSupport()) {
718 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
721 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
722 AttrEmitter = new ObjectAttributeEmitter(O);
725 AttrEmitter->MaybeSwitchVendor("aeabi");
727 std::string CPUString = Subtarget->getCPUString();
729 if (CPUString == "cortex-a8" ||
730 Subtarget->isCortexA8()) {
731 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
732 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
733 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
734 ARMBuildAttrs::ApplicationProfile);
735 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
736 ARMBuildAttrs::Allowed);
737 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
738 ARMBuildAttrs::AllowThumb32);
739 // Fixme: figure out when this is emitted.
740 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
741 // ARMBuildAttrs::AllowWMMXv1);
744 /// ADD additional Else-cases here!
745 } else if (CPUString == "xscale") {
746 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
748 ARMBuildAttrs::Allowed);
749 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
750 ARMBuildAttrs::Allowed);
751 } else if (CPUString == "generic") {
752 // FIXME: Why these defaults?
753 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
754 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
755 ARMBuildAttrs::Allowed);
756 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
757 ARMBuildAttrs::Allowed);
760 if (Subtarget->hasNEON() && emitFPU) {
761 /* NEON is not exactly a VFP architecture, but GAS emit one of
762 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
763 if (Subtarget->hasVFP4())
764 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
767 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
768 /* If emitted for NEON, omit from VFP below, since you can have both
769 * NEON and VFP in build attributes but only one .fpu */
774 if (Subtarget->hasVFP4()) {
775 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
776 ARMBuildAttrs::AllowFPv4A);
778 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
781 } else if (Subtarget->hasVFP3()) {
782 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
783 ARMBuildAttrs::AllowFPv3A);
785 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
788 } else if (Subtarget->hasVFP2()) {
789 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
790 ARMBuildAttrs::AllowFPv2);
792 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
795 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
796 * since NEON can have 1 (allowed) or 2 (MAC operations) */
797 if (Subtarget->hasNEON()) {
798 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
799 ARMBuildAttrs::Allowed);
802 // Signal various FP modes.
803 if (!TM.Options.UnsafeFPMath) {
804 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
805 ARMBuildAttrs::Allowed);
806 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
807 ARMBuildAttrs::Allowed);
810 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
811 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
812 ARMBuildAttrs::Allowed);
814 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
815 ARMBuildAttrs::AllowIEE754);
817 // FIXME: add more flags to ARMBuildAttrs.h
818 // 8-bytes alignment stuff.
819 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
820 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
822 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
823 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
824 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
825 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
827 // FIXME: Should we signal R9 usage?
829 if (Subtarget->hasDivide())
830 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
832 AttrEmitter->Finish();
836 void ARMAsmPrinter::emitARMAttributeSection() {
838 // [ <section-length> "vendor-name"
839 // [ <file-tag> <size> <attribute>*
840 // | <section-tag> <size> <section-number>* 0 <attribute>*
841 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
845 if (OutStreamer.hasRawTextSupport())
848 const ARMElfTargetObjectFile &TLOFELF =
849 static_cast<const ARMElfTargetObjectFile &>
850 (getObjFileLowering());
852 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
855 OutStreamer.EmitIntValue(0x41, 1);
858 //===----------------------------------------------------------------------===//
860 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
861 unsigned LabelId, MCContext &Ctx) {
863 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
864 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
868 static MCSymbolRefExpr::VariantKind
869 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
871 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
872 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
873 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
874 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
875 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
876 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
878 llvm_unreachable("Invalid ARMCPModifier!");
881 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
882 bool isIndirect = Subtarget->isTargetDarwin() &&
883 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
885 return Mang->getSymbol(GV);
887 // FIXME: Remove this when Darwin transition to @GOT like syntax.
888 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
889 MachineModuleInfoMachO &MMIMachO =
890 MMI->getObjFileInfo<MachineModuleInfoMachO>();
891 MachineModuleInfoImpl::StubValueTy &StubSym =
892 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
893 MMIMachO.getGVStubEntry(MCSym);
894 if (StubSym.getPointer() == 0)
895 StubSym = MachineModuleInfoImpl::
896 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
901 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
902 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
904 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
907 if (ACPV->isLSDA()) {
908 SmallString<128> Str;
909 raw_svector_ostream OS(Str);
910 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
911 MCSym = OutContext.GetOrCreateSymbol(OS.str());
912 } else if (ACPV->isBlockAddress()) {
913 const BlockAddress *BA =
914 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
915 MCSym = GetBlockAddressSymbol(BA);
916 } else if (ACPV->isGlobalValue()) {
917 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
918 MCSym = GetARMGVSymbol(GV);
919 } else if (ACPV->isMachineBasicBlock()) {
920 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
921 MCSym = MBB->getSymbol();
923 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
924 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
925 MCSym = GetExternalSymbolSymbol(Sym);
928 // Create an MCSymbol for the reference.
930 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
933 if (ACPV->getPCAdjustment()) {
934 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
938 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
940 MCBinaryExpr::CreateAdd(PCRelExpr,
941 MCConstantExpr::Create(ACPV->getPCAdjustment(),
944 if (ACPV->mustAddCurrentAddress()) {
945 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
946 // label, so just emit a local label end reference that instead.
947 MCSymbol *DotSym = OutContext.CreateTempSymbol();
948 OutStreamer.EmitLabel(DotSym);
949 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
950 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
952 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
954 OutStreamer.EmitValue(Expr, Size);
957 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
958 unsigned Opcode = MI->getOpcode();
960 if (Opcode == ARM::BR_JTadd)
962 else if (Opcode == ARM::BR_JTm)
965 const MachineOperand &MO1 = MI->getOperand(OpNum);
966 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
967 unsigned JTI = MO1.getIndex();
969 // Emit a label for the jump table.
970 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
971 OutStreamer.EmitLabel(JTISymbol);
973 // Mark the jump table as data-in-code.
974 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
976 // Emit each entry of the table.
977 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
978 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
979 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
981 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
982 MachineBasicBlock *MBB = JTBBs[i];
983 // Construct an MCExpr for the entry. We want a value of the form:
984 // (BasicBlockAddr - TableBeginAddr)
986 // For example, a table with entries jumping to basic blocks BB0 and BB1
989 // .word (LBB0 - LJTI_0_0)
990 // .word (LBB1 - LJTI_0_0)
991 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
993 if (TM.getRelocationModel() == Reloc::PIC_)
994 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
997 // If we're generating a table of Thumb addresses in static relocation
998 // model, we need to add one to keep interworking correctly.
999 else if (AFI->isThumbFunction())
1000 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1002 OutStreamer.EmitValue(Expr, 4);
1004 // Mark the end of jump table data-in-code region.
1005 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1008 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1009 unsigned Opcode = MI->getOpcode();
1010 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1011 const MachineOperand &MO1 = MI->getOperand(OpNum);
1012 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1013 unsigned JTI = MO1.getIndex();
1015 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1016 OutStreamer.EmitLabel(JTISymbol);
1018 // Emit each entry of the table.
1019 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1020 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1021 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1022 unsigned OffsetWidth = 4;
1023 if (MI->getOpcode() == ARM::t2TBB_JT) {
1025 // Mark the jump table as data-in-code.
1026 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1027 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1029 // Mark the jump table as data-in-code.
1030 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1033 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1034 MachineBasicBlock *MBB = JTBBs[i];
1035 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1037 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1038 if (OffsetWidth == 4) {
1040 BrInst.setOpcode(ARM::t2B);
1041 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1042 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1043 BrInst.addOperand(MCOperand::CreateReg(0));
1044 OutStreamer.EmitInstruction(BrInst);
1047 // Otherwise it's an offset from the dispatch instruction. Construct an
1048 // MCExpr for the entry. We want a value of the form:
1049 // (BasicBlockAddr - TableBeginAddr) / 2
1051 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1054 // .byte (LBB0 - LJTI_0_0) / 2
1055 // .byte (LBB1 - LJTI_0_0) / 2
1056 const MCExpr *Expr =
1057 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1058 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1060 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1062 OutStreamer.EmitValue(Expr, OffsetWidth);
1064 // Mark the end of jump table data-in-code region. 32-bit offsets use
1065 // actual branch instructions here, so we don't mark those as a data-region
1067 if (OffsetWidth != 4)
1068 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1071 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1073 unsigned NOps = MI->getNumOperands();
1075 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1076 // cast away const; DIetc do not take const operands for some reason.
1077 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1080 // Frame address. Currently handles register +- offset only.
1081 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1082 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1085 printOperand(MI, NOps-2, OS);
1088 static void populateADROperands(MCInst &Inst, unsigned Dest,
1089 const MCSymbol *Label,
1090 unsigned pred, unsigned ccreg,
1092 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1093 Inst.addOperand(MCOperand::CreateReg(Dest));
1094 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1095 // Add predicate operands.
1096 Inst.addOperand(MCOperand::CreateImm(pred));
1097 Inst.addOperand(MCOperand::CreateReg(ccreg));
1100 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1101 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1102 "Only instruction which are involved into frame setup code are allowed");
1104 const MachineFunction &MF = *MI->getParent()->getParent();
1105 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1106 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1108 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1109 unsigned Opc = MI->getOpcode();
1110 unsigned SrcReg, DstReg;
1112 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1113 // Two special cases:
1114 // 1) tPUSH does not have src/dst regs.
1115 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1116 // load. Yes, this is pretty fragile, but for now I don't see better
1118 SrcReg = DstReg = ARM::SP;
1120 SrcReg = MI->getOperand(1).getReg();
1121 DstReg = MI->getOperand(0).getReg();
1124 // Try to figure out the unwinding opcode out of src / dst regs.
1125 if (MI->mayStore()) {
1127 assert(DstReg == ARM::SP &&
1128 "Only stack pointer as a destination reg is supported");
1130 SmallVector<unsigned, 4> RegList;
1131 // Skip src & dst reg, and pred ops.
1132 unsigned StartOp = 2 + 2;
1133 // Use all the operands.
1134 unsigned NumOffset = 0;
1139 llvm_unreachable("Unsupported opcode for unwinding information");
1141 // Special case here: no src & dst reg, but two extra imp ops.
1142 StartOp = 2; NumOffset = 2;
1143 case ARM::STMDB_UPD:
1144 case ARM::t2STMDB_UPD:
1145 case ARM::VSTMDDB_UPD:
1146 assert(SrcReg == ARM::SP &&
1147 "Only stack pointer as a source reg is supported");
1148 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1150 const MachineOperand &MO = MI->getOperand(i);
1151 // Actually, there should never be any impdef stuff here. Skip it
1152 // temporary to workaround PR11902.
1153 if (MO.isImplicit())
1155 RegList.push_back(MO.getReg());
1158 case ARM::STR_PRE_IMM:
1159 case ARM::STR_PRE_REG:
1160 case ARM::t2STR_PRE:
1161 assert(MI->getOperand(2).getReg() == ARM::SP &&
1162 "Only stack pointer as a source reg is supported");
1163 RegList.push_back(SrcReg);
1166 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1168 // Changes of stack / frame pointer.
1169 if (SrcReg == ARM::SP) {
1174 llvm_unreachable("Unsupported opcode for unwinding information");
1180 Offset = -MI->getOperand(2).getImm();
1184 Offset = MI->getOperand(2).getImm();
1187 Offset = MI->getOperand(2).getImm()*4;
1191 Offset = -MI->getOperand(2).getImm()*4;
1193 case ARM::tLDRpci: {
1194 // Grab the constpool index and check, whether it corresponds to
1195 // original or cloned constpool entry.
1196 unsigned CPI = MI->getOperand(1).getIndex();
1197 const MachineConstantPool *MCP = MF.getConstantPool();
1198 if (CPI >= MCP->getConstants().size())
1199 CPI = AFI.getOriginalCPIdx(CPI);
1200 assert(CPI != -1U && "Invalid constpool index");
1202 // Derive the actual offset.
1203 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1204 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1205 // FIXME: Check for user, it should be "add" instruction!
1206 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1211 if (DstReg == FramePtr && FramePtr != ARM::SP)
1212 // Set-up of the frame pointer. Positive values correspond to "add"
1214 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1215 else if (DstReg == ARM::SP) {
1216 // Change of SP by an offset. Positive values correspond to "sub"
1218 OutStreamer.EmitPad(Offset);
1221 llvm_unreachable("Unsupported opcode for unwinding information");
1223 } else if (DstReg == ARM::SP) {
1224 // FIXME: .movsp goes here
1226 llvm_unreachable("Unsupported opcode for unwinding information");
1230 llvm_unreachable("Unsupported opcode for unwinding information");
1235 extern cl::opt<bool> EnableARMEHABI;
1237 // Simple pseudo-instructions have their lowering (with expansion to real
1238 // instructions) auto-generated.
1239 #include "ARMGenMCPseudoLowering.inc"
1241 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1242 // If we just ended a constant pool, mark it as such.
1243 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1244 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1245 InConstantPool = false;
1248 // Emit unwinding stuff for frame-related instructions
1249 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1250 EmitUnwindingInstruction(MI);
1252 // Do any auto-generated pseudo lowerings.
1253 if (emitPseudoExpansionLowering(OutStreamer, MI))
1256 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1257 "Pseudo flag setting opcode should be expanded early");
1259 // Check for manual lowerings.
1260 unsigned Opc = MI->getOpcode();
1262 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1263 case ARM::DBG_VALUE: {
1264 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1265 SmallString<128> TmpStr;
1266 raw_svector_ostream OS(TmpStr);
1267 PrintDebugValueComment(MI, OS);
1268 OutStreamer.EmitRawText(StringRef(OS.str()));
1273 case ARM::tLEApcrel:
1274 case ARM::t2LEApcrel: {
1275 // FIXME: Need to also handle globals and externals
1277 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1278 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1280 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1281 GetCPISymbol(MI->getOperand(1).getIndex()),
1282 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1284 OutStreamer.EmitInstruction(TmpInst);
1287 case ARM::LEApcrelJT:
1288 case ARM::tLEApcrelJT:
1289 case ARM::t2LEApcrelJT: {
1291 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1292 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1294 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1295 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1296 MI->getOperand(2).getImm()),
1297 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1299 OutStreamer.EmitInstruction(TmpInst);
1302 // Darwin call instructions are just normal call instructions with different
1303 // clobber semantics (they clobber R9).
1304 case ARM::BX_CALL: {
1307 TmpInst.setOpcode(ARM::MOVr);
1308 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1309 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1310 // Add predicate operands.
1311 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1312 TmpInst.addOperand(MCOperand::CreateReg(0));
1313 // Add 's' bit operand (always reg0 for this)
1314 TmpInst.addOperand(MCOperand::CreateReg(0));
1315 OutStreamer.EmitInstruction(TmpInst);
1319 TmpInst.setOpcode(ARM::BX);
1320 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1321 OutStreamer.EmitInstruction(TmpInst);
1325 case ARM::tBX_CALL: {
1328 TmpInst.setOpcode(ARM::tMOVr);
1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1330 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1331 // Add predicate operands.
1332 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 OutStreamer.EmitInstruction(TmpInst);
1338 TmpInst.setOpcode(ARM::tBX);
1339 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1340 // Add predicate operands.
1341 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1342 TmpInst.addOperand(MCOperand::CreateReg(0));
1343 OutStreamer.EmitInstruction(TmpInst);
1347 case ARM::BMOVPCRX_CALL: {
1350 TmpInst.setOpcode(ARM::MOVr);
1351 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1352 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1353 // Add predicate operands.
1354 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1355 TmpInst.addOperand(MCOperand::CreateReg(0));
1356 // Add 's' bit operand (always reg0 for this)
1357 TmpInst.addOperand(MCOperand::CreateReg(0));
1358 OutStreamer.EmitInstruction(TmpInst);
1362 TmpInst.setOpcode(ARM::MOVr);
1363 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1364 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1365 // Add predicate operands.
1366 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1367 TmpInst.addOperand(MCOperand::CreateReg(0));
1368 // Add 's' bit operand (always reg0 for this)
1369 TmpInst.addOperand(MCOperand::CreateReg(0));
1370 OutStreamer.EmitInstruction(TmpInst);
1374 case ARM::BMOVPCB_CALL: {
1377 TmpInst.setOpcode(ARM::MOVr);
1378 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1379 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1380 // Add predicate operands.
1381 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 // Add 's' bit operand (always reg0 for this)
1384 TmpInst.addOperand(MCOperand::CreateReg(0));
1385 OutStreamer.EmitInstruction(TmpInst);
1389 TmpInst.setOpcode(ARM::Bcc);
1390 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1391 MCSymbol *GVSym = Mang->getSymbol(GV);
1392 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1393 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1394 // Add predicate operands.
1395 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1396 TmpInst.addOperand(MCOperand::CreateReg(0));
1397 OutStreamer.EmitInstruction(TmpInst);
1401 case ARM::t2BMOVPCB_CALL: {
1404 TmpInst.setOpcode(ARM::tMOVr);
1405 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1406 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1407 // Add predicate operands.
1408 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1409 TmpInst.addOperand(MCOperand::CreateReg(0));
1410 OutStreamer.EmitInstruction(TmpInst);
1414 TmpInst.setOpcode(ARM::t2B);
1415 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1416 MCSymbol *GVSym = Mang->getSymbol(GV);
1417 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1418 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1419 // Add predicate operands.
1420 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1421 TmpInst.addOperand(MCOperand::CreateReg(0));
1422 OutStreamer.EmitInstruction(TmpInst);
1426 case ARM::MOVi16_ga_pcrel:
1427 case ARM::t2MOVi16_ga_pcrel: {
1429 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1430 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1432 unsigned TF = MI->getOperand(1).getTargetFlags();
1433 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1434 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1435 MCSymbol *GVSym = GetARMGVSymbol(GV);
1436 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1438 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1439 getFunctionNumber(),
1440 MI->getOperand(2).getImm(), OutContext);
1441 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1442 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1443 const MCExpr *PCRelExpr =
1444 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1445 MCBinaryExpr::CreateAdd(LabelSymExpr,
1446 MCConstantExpr::Create(PCAdj, OutContext),
1447 OutContext), OutContext), OutContext);
1448 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1450 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1451 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1454 // Add predicate operands.
1455 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1456 TmpInst.addOperand(MCOperand::CreateReg(0));
1457 // Add 's' bit operand (always reg0 for this)
1458 TmpInst.addOperand(MCOperand::CreateReg(0));
1459 OutStreamer.EmitInstruction(TmpInst);
1462 case ARM::MOVTi16_ga_pcrel:
1463 case ARM::t2MOVTi16_ga_pcrel: {
1465 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1466 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1467 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1468 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1470 unsigned TF = MI->getOperand(2).getTargetFlags();
1471 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1472 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1473 MCSymbol *GVSym = GetARMGVSymbol(GV);
1474 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1476 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1477 getFunctionNumber(),
1478 MI->getOperand(3).getImm(), OutContext);
1479 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1480 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1481 const MCExpr *PCRelExpr =
1482 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1483 MCBinaryExpr::CreateAdd(LabelSymExpr,
1484 MCConstantExpr::Create(PCAdj, OutContext),
1485 OutContext), OutContext), OutContext);
1486 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1488 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1489 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1491 // Add predicate operands.
1492 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1493 TmpInst.addOperand(MCOperand::CreateReg(0));
1494 // Add 's' bit operand (always reg0 for this)
1495 TmpInst.addOperand(MCOperand::CreateReg(0));
1496 OutStreamer.EmitInstruction(TmpInst);
1499 case ARM::tPICADD: {
1500 // This is a pseudo op for a label + instruction sequence, which looks like:
1503 // This adds the address of LPC0 to r0.
1506 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1507 getFunctionNumber(), MI->getOperand(2).getImm(),
1510 // Form and emit the add.
1512 AddInst.setOpcode(ARM::tADDhirr);
1513 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1514 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1515 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1516 // Add predicate operands.
1517 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1518 AddInst.addOperand(MCOperand::CreateReg(0));
1519 OutStreamer.EmitInstruction(AddInst);
1523 // This is a pseudo op for a label + instruction sequence, which looks like:
1526 // This adds the address of LPC0 to r0.
1529 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1530 getFunctionNumber(), MI->getOperand(2).getImm(),
1533 // Form and emit the add.
1535 AddInst.setOpcode(ARM::ADDrr);
1536 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1537 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1538 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1539 // Add predicate operands.
1540 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1541 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1542 // Add 's' bit operand (always reg0 for this)
1543 AddInst.addOperand(MCOperand::CreateReg(0));
1544 OutStreamer.EmitInstruction(AddInst);
1554 case ARM::PICLDRSH: {
1555 // This is a pseudo op for a label + instruction sequence, which looks like:
1558 // The LCP0 label is referenced by a constant pool entry in order to get
1559 // a PC-relative address at the ldr instruction.
1562 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1563 getFunctionNumber(), MI->getOperand(2).getImm(),
1566 // Form and emit the load
1568 switch (MI->getOpcode()) {
1570 llvm_unreachable("Unexpected opcode!");
1571 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1572 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1573 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1574 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1575 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1576 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1577 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1578 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1581 LdStInst.setOpcode(Opcode);
1582 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1583 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1584 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1585 LdStInst.addOperand(MCOperand::CreateImm(0));
1586 // Add predicate operands.
1587 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1588 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1589 OutStreamer.EmitInstruction(LdStInst);
1593 case ARM::CONSTPOOL_ENTRY: {
1594 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1595 /// in the function. The first operand is the ID# for this instruction, the
1596 /// second is the index into the MachineConstantPool that this is, the third
1597 /// is the size in bytes of this constant pool entry.
1598 /// The required alignment is specified on the basic block holding this MI.
1599 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1600 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1602 // If this is the first entry of the pool, mark it.
1603 if (!InConstantPool) {
1604 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1605 InConstantPool = true;
1608 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1610 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1611 if (MCPE.isMachineConstantPoolEntry())
1612 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1614 EmitGlobalConstant(MCPE.Val.ConstVal);
1617 case ARM::t2BR_JT: {
1618 // Lower and emit the instruction itself, then the jump table following it.
1620 TmpInst.setOpcode(ARM::tMOVr);
1621 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1622 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1623 // Add predicate operands.
1624 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1625 TmpInst.addOperand(MCOperand::CreateReg(0));
1626 OutStreamer.EmitInstruction(TmpInst);
1627 // Output the data for the jump table itself
1631 case ARM::t2TBB_JT: {
1632 // Lower and emit the instruction itself, then the jump table following it.
1635 TmpInst.setOpcode(ARM::t2TBB);
1636 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1637 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1638 // Add predicate operands.
1639 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1640 TmpInst.addOperand(MCOperand::CreateReg(0));
1641 OutStreamer.EmitInstruction(TmpInst);
1642 // Output the data for the jump table itself
1644 // Make sure the next instruction is 2-byte aligned.
1648 case ARM::t2TBH_JT: {
1649 // Lower and emit the instruction itself, then the jump table following it.
1652 TmpInst.setOpcode(ARM::t2TBH);
1653 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1654 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1655 // Add predicate operands.
1656 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1657 TmpInst.addOperand(MCOperand::CreateReg(0));
1658 OutStreamer.EmitInstruction(TmpInst);
1659 // Output the data for the jump table itself
1665 // Lower and emit the instruction itself, then the jump table following it.
1668 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1669 ARM::MOVr : ARM::tMOVr;
1670 TmpInst.setOpcode(Opc);
1671 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1672 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1673 // Add predicate operands.
1674 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1675 TmpInst.addOperand(MCOperand::CreateReg(0));
1676 // Add 's' bit operand (always reg0 for this)
1677 if (Opc == ARM::MOVr)
1678 TmpInst.addOperand(MCOperand::CreateReg(0));
1679 OutStreamer.EmitInstruction(TmpInst);
1681 // Make sure the Thumb jump table is 4-byte aligned.
1682 if (Opc == ARM::tMOVr)
1685 // Output the data for the jump table itself
1690 // Lower and emit the instruction itself, then the jump table following it.
1693 if (MI->getOperand(1).getReg() == 0) {
1695 TmpInst.setOpcode(ARM::LDRi12);
1696 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1697 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1698 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1700 TmpInst.setOpcode(ARM::LDRrs);
1701 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1702 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1703 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1704 TmpInst.addOperand(MCOperand::CreateImm(0));
1706 // Add predicate operands.
1707 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1708 TmpInst.addOperand(MCOperand::CreateReg(0));
1709 OutStreamer.EmitInstruction(TmpInst);
1711 // Output the data for the jump table itself
1715 case ARM::BR_JTadd: {
1716 // Lower and emit the instruction itself, then the jump table following it.
1717 // add pc, target, idx
1719 TmpInst.setOpcode(ARM::ADDrr);
1720 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1721 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1722 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1723 // Add predicate operands.
1724 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1725 TmpInst.addOperand(MCOperand::CreateReg(0));
1726 // Add 's' bit operand (always reg0 for this)
1727 TmpInst.addOperand(MCOperand::CreateReg(0));
1728 OutStreamer.EmitInstruction(TmpInst);
1730 // Output the data for the jump table itself
1735 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1736 // FIXME: Remove this special case when they do.
1737 if (!Subtarget->isTargetDarwin()) {
1738 //.long 0xe7ffdefe @ trap
1739 uint32_t Val = 0xe7ffdefeUL;
1740 OutStreamer.AddComment("trap");
1741 OutStreamer.EmitIntValue(Val, 4);
1747 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1748 // FIXME: Remove this special case when they do.
1749 if (!Subtarget->isTargetDarwin()) {
1750 //.short 57086 @ trap
1751 uint16_t Val = 0xdefe;
1752 OutStreamer.AddComment("trap");
1753 OutStreamer.EmitIntValue(Val, 2);
1758 case ARM::t2Int_eh_sjlj_setjmp:
1759 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1760 case ARM::tInt_eh_sjlj_setjmp: {
1761 // Two incoming args: GPR:$src, GPR:$val
1764 // str $val, [$src, #4]
1769 unsigned SrcReg = MI->getOperand(0).getReg();
1770 unsigned ValReg = MI->getOperand(1).getReg();
1771 MCSymbol *Label = GetARMSJLJEHLabel();
1774 TmpInst.setOpcode(ARM::tMOVr);
1775 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1776 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1778 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1779 TmpInst.addOperand(MCOperand::CreateReg(0));
1780 OutStreamer.AddComment("eh_setjmp begin");
1781 OutStreamer.EmitInstruction(TmpInst);
1785 TmpInst.setOpcode(ARM::tADDi3);
1786 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1788 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1789 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1790 TmpInst.addOperand(MCOperand::CreateImm(7));
1792 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1793 TmpInst.addOperand(MCOperand::CreateReg(0));
1794 OutStreamer.EmitInstruction(TmpInst);
1798 TmpInst.setOpcode(ARM::tSTRi);
1799 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1800 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1801 // The offset immediate is #4. The operand value is scaled by 4 for the
1802 // tSTR instruction.
1803 TmpInst.addOperand(MCOperand::CreateImm(1));
1805 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1806 TmpInst.addOperand(MCOperand::CreateReg(0));
1807 OutStreamer.EmitInstruction(TmpInst);
1811 TmpInst.setOpcode(ARM::tMOVi8);
1812 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1813 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1814 TmpInst.addOperand(MCOperand::CreateImm(0));
1816 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1817 TmpInst.addOperand(MCOperand::CreateReg(0));
1818 OutStreamer.EmitInstruction(TmpInst);
1821 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1823 TmpInst.setOpcode(ARM::tB);
1824 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1825 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1826 TmpInst.addOperand(MCOperand::CreateReg(0));
1827 OutStreamer.EmitInstruction(TmpInst);
1831 TmpInst.setOpcode(ARM::tMOVi8);
1832 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1833 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1834 TmpInst.addOperand(MCOperand::CreateImm(1));
1836 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1837 TmpInst.addOperand(MCOperand::CreateReg(0));
1838 OutStreamer.AddComment("eh_setjmp end");
1839 OutStreamer.EmitInstruction(TmpInst);
1841 OutStreamer.EmitLabel(Label);
1845 case ARM::Int_eh_sjlj_setjmp_nofp:
1846 case ARM::Int_eh_sjlj_setjmp: {
1847 // Two incoming args: GPR:$src, GPR:$val
1849 // str $val, [$src, #+4]
1853 unsigned SrcReg = MI->getOperand(0).getReg();
1854 unsigned ValReg = MI->getOperand(1).getReg();
1858 TmpInst.setOpcode(ARM::ADDri);
1859 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1860 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1861 TmpInst.addOperand(MCOperand::CreateImm(8));
1863 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1864 TmpInst.addOperand(MCOperand::CreateReg(0));
1865 // 's' bit operand (always reg0 for this).
1866 TmpInst.addOperand(MCOperand::CreateReg(0));
1867 OutStreamer.AddComment("eh_setjmp begin");
1868 OutStreamer.EmitInstruction(TmpInst);
1872 TmpInst.setOpcode(ARM::STRi12);
1873 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1874 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1875 TmpInst.addOperand(MCOperand::CreateImm(4));
1877 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1878 TmpInst.addOperand(MCOperand::CreateReg(0));
1879 OutStreamer.EmitInstruction(TmpInst);
1883 TmpInst.setOpcode(ARM::MOVi);
1884 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1885 TmpInst.addOperand(MCOperand::CreateImm(0));
1887 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1888 TmpInst.addOperand(MCOperand::CreateReg(0));
1889 // 's' bit operand (always reg0 for this).
1890 TmpInst.addOperand(MCOperand::CreateReg(0));
1891 OutStreamer.EmitInstruction(TmpInst);
1895 TmpInst.setOpcode(ARM::ADDri);
1896 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1897 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1898 TmpInst.addOperand(MCOperand::CreateImm(0));
1900 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1901 TmpInst.addOperand(MCOperand::CreateReg(0));
1902 // 's' bit operand (always reg0 for this).
1903 TmpInst.addOperand(MCOperand::CreateReg(0));
1904 OutStreamer.EmitInstruction(TmpInst);
1908 TmpInst.setOpcode(ARM::MOVi);
1909 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1910 TmpInst.addOperand(MCOperand::CreateImm(1));
1912 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1913 TmpInst.addOperand(MCOperand::CreateReg(0));
1914 // 's' bit operand (always reg0 for this).
1915 TmpInst.addOperand(MCOperand::CreateReg(0));
1916 OutStreamer.AddComment("eh_setjmp end");
1917 OutStreamer.EmitInstruction(TmpInst);
1921 case ARM::Int_eh_sjlj_longjmp: {
1922 // ldr sp, [$src, #8]
1923 // ldr $scratch, [$src, #4]
1926 unsigned SrcReg = MI->getOperand(0).getReg();
1927 unsigned ScratchReg = MI->getOperand(1).getReg();
1930 TmpInst.setOpcode(ARM::LDRi12);
1931 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1932 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1933 TmpInst.addOperand(MCOperand::CreateImm(8));
1935 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1936 TmpInst.addOperand(MCOperand::CreateReg(0));
1937 OutStreamer.EmitInstruction(TmpInst);
1941 TmpInst.setOpcode(ARM::LDRi12);
1942 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1943 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1944 TmpInst.addOperand(MCOperand::CreateImm(4));
1946 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1947 TmpInst.addOperand(MCOperand::CreateReg(0));
1948 OutStreamer.EmitInstruction(TmpInst);
1952 TmpInst.setOpcode(ARM::LDRi12);
1953 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1954 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1955 TmpInst.addOperand(MCOperand::CreateImm(0));
1957 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1958 TmpInst.addOperand(MCOperand::CreateReg(0));
1959 OutStreamer.EmitInstruction(TmpInst);
1963 TmpInst.setOpcode(ARM::BX);
1964 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1966 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1967 TmpInst.addOperand(MCOperand::CreateReg(0));
1968 OutStreamer.EmitInstruction(TmpInst);
1972 case ARM::tInt_eh_sjlj_longjmp: {
1973 // ldr $scratch, [$src, #8]
1975 // ldr $scratch, [$src, #4]
1978 unsigned SrcReg = MI->getOperand(0).getReg();
1979 unsigned ScratchReg = MI->getOperand(1).getReg();
1982 TmpInst.setOpcode(ARM::tLDRi);
1983 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1984 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1985 // The offset immediate is #8. The operand value is scaled by 4 for the
1986 // tLDR instruction.
1987 TmpInst.addOperand(MCOperand::CreateImm(2));
1989 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1990 TmpInst.addOperand(MCOperand::CreateReg(0));
1991 OutStreamer.EmitInstruction(TmpInst);
1995 TmpInst.setOpcode(ARM::tMOVr);
1996 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1997 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1999 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2000 TmpInst.addOperand(MCOperand::CreateReg(0));
2001 OutStreamer.EmitInstruction(TmpInst);
2005 TmpInst.setOpcode(ARM::tLDRi);
2006 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2007 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2008 TmpInst.addOperand(MCOperand::CreateImm(1));
2010 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2011 TmpInst.addOperand(MCOperand::CreateReg(0));
2012 OutStreamer.EmitInstruction(TmpInst);
2016 TmpInst.setOpcode(ARM::tLDRi);
2017 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2018 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2019 TmpInst.addOperand(MCOperand::CreateImm(0));
2021 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2022 TmpInst.addOperand(MCOperand::CreateReg(0));
2023 OutStreamer.EmitInstruction(TmpInst);
2027 TmpInst.setOpcode(ARM::tBX);
2028 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2030 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2031 TmpInst.addOperand(MCOperand::CreateReg(0));
2032 OutStreamer.EmitInstruction(TmpInst);
2039 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2041 OutStreamer.EmitInstruction(TmpInst);
2044 //===----------------------------------------------------------------------===//
2045 // Target Registry Stuff
2046 //===----------------------------------------------------------------------===//
2048 // Force static initialization.
2049 extern "C" void LLVMInitializeARMAsmPrinter() {
2050 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2051 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);