1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 void ARMAsmPrinter::EmitFunctionEntryLabel() {
176 if (AFI->isThumbFunction()) {
177 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
178 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
181 OutStreamer.EmitLabel(CurrentFnSym);
184 /// runOnMachineFunction - This uses the EmitInstruction()
185 /// method to print assembly for each instruction.
187 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
188 AFI = MF.getInfo<ARMFunctionInfo>();
189 MCP = MF.getConstantPool();
191 return AsmPrinter::runOnMachineFunction(MF);
194 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
195 raw_ostream &O, const char *Modifier) {
196 const MachineOperand &MO = MI->getOperand(OpNum);
197 unsigned TF = MO.getTargetFlags();
199 switch (MO.getType()) {
201 assert(0 && "<unknown operand type>");
202 case MachineOperand::MO_Register: {
203 unsigned Reg = MO.getReg();
204 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
205 assert(!MO.getSubReg() && "Subregs should be eliminated!");
206 O << ARMInstPrinter::getRegisterName(Reg);
209 case MachineOperand::MO_Immediate: {
210 int64_t Imm = MO.getImm();
212 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
213 (TF == ARMII::MO_LO16))
215 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
216 (TF == ARMII::MO_HI16))
221 case MachineOperand::MO_MachineBasicBlock:
222 O << *MO.getMBB()->getSymbol();
224 case MachineOperand::MO_GlobalAddress: {
225 const GlobalValue *GV = MO.getGlobal();
226 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
227 (TF & ARMII::MO_LO16))
229 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
230 (TF & ARMII::MO_HI16))
232 O << *Mang->getSymbol(GV);
234 printOffset(MO.getOffset(), O);
235 if (TF == ARMII::MO_PLT)
239 case MachineOperand::MO_ExternalSymbol: {
240 O << *GetExternalSymbolSymbol(MO.getSymbolName());
241 if (TF == ARMII::MO_PLT)
245 case MachineOperand::MO_ConstantPoolIndex:
246 O << *GetCPISymbol(MO.getIndex());
248 case MachineOperand::MO_JumpTableIndex:
249 O << *GetJTISymbol(MO.getIndex());
254 //===--------------------------------------------------------------------===//
256 MCSymbol *ARMAsmPrinter::
257 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
258 const MachineBasicBlock *MBB) const {
259 SmallString<60> Name;
260 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
261 << getFunctionNumber() << '_' << uid << '_' << uid2
262 << "_set_" << MBB->getNumber();
263 return OutContext.GetOrCreateSymbol(Name.str());
266 MCSymbol *ARMAsmPrinter::
267 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
268 SmallString<60> Name;
269 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
270 << getFunctionNumber() << '_' << uid << '_' << uid2;
271 return OutContext.GetOrCreateSymbol(Name.str());
275 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
276 SmallString<60> Name;
277 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
278 << getFunctionNumber();
279 return OutContext.GetOrCreateSymbol(Name.str());
282 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
283 unsigned AsmVariant, const char *ExtraCode,
285 // Does this asm operand have a single letter operand modifier?
286 if (ExtraCode && ExtraCode[0]) {
287 if (ExtraCode[1] != 0) return true; // Unknown modifier.
289 switch (ExtraCode[0]) {
290 default: return true; // Unknown modifier.
291 case 'a': // Print as a memory address.
292 if (MI->getOperand(OpNum).isReg()) {
294 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
299 case 'c': // Don't print "#" before an immediate operand.
300 if (!MI->getOperand(OpNum).isImm())
302 O << MI->getOperand(OpNum).getImm();
304 case 'P': // Print a VFP double precision register.
305 case 'q': // Print a NEON quad precision register.
306 printOperand(MI, OpNum, O);
311 // These modifiers are not yet supported.
316 printOperand(MI, OpNum, O);
320 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
321 unsigned OpNum, unsigned AsmVariant,
322 const char *ExtraCode,
324 if (ExtraCode && ExtraCode[0])
325 return true; // Unknown modifier.
327 const MachineOperand &MO = MI->getOperand(OpNum);
328 assert(MO.isReg() && "unexpected inline asm memory operand");
329 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
333 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
334 if (Subtarget->isTargetDarwin()) {
335 Reloc::Model RelocM = TM.getRelocationModel();
336 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
337 // Declare all the text sections up front (before the DWARF sections
338 // emitted by AsmPrinter::doInitialization) so the assembler will keep
339 // them together at the beginning of the object file. This helps
340 // avoid out-of-range branches that are due a fundamental limitation of
341 // the way symbol offsets are encoded with the current Darwin ARM
343 const TargetLoweringObjectFileMachO &TLOFMacho =
344 static_cast<const TargetLoweringObjectFileMachO &>(
345 getObjFileLowering());
346 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
347 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
348 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
349 if (RelocM == Reloc::DynamicNoPIC) {
350 const MCSection *sect =
351 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
352 MCSectionMachO::S_SYMBOL_STUBS,
353 12, SectionKind::getText());
354 OutStreamer.SwitchSection(sect);
356 const MCSection *sect =
357 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
358 MCSectionMachO::S_SYMBOL_STUBS,
359 16, SectionKind::getText());
360 OutStreamer.SwitchSection(sect);
362 const MCSection *StaticInitSect =
363 OutContext.getMachOSection("__TEXT", "__StaticInit",
364 MCSectionMachO::S_REGULAR |
365 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
366 SectionKind::getText());
367 OutStreamer.SwitchSection(StaticInitSect);
371 // Use unified assembler syntax.
372 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
374 // Emit ARM Build Attributes
375 if (Subtarget->isTargetELF()) {
382 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
383 if (Subtarget->isTargetDarwin()) {
384 // All darwin targets use mach-o.
385 const TargetLoweringObjectFileMachO &TLOFMacho =
386 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
387 MachineModuleInfoMachO &MMIMacho =
388 MMI->getObjFileInfo<MachineModuleInfoMachO>();
390 // Output non-lazy-pointers for external and common global variables.
391 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
393 if (!Stubs.empty()) {
394 // Switch with ".non_lazy_symbol_pointer" directive.
395 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
397 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
399 OutStreamer.EmitLabel(Stubs[i].first);
400 // .indirect_symbol _foo
401 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
402 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
405 // External to current translation unit.
406 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
408 // Internal to current translation unit.
410 // When we place the LSDA into the TEXT section, the type info
411 // pointers need to be indirect and pc-rel. We accomplish this by
412 // using NLPs; however, sometimes the types are local to the file.
413 // We need to fill in the value for the NLP in those cases.
414 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
416 4/*size*/, 0/*addrspace*/);
420 OutStreamer.AddBlankLine();
423 Stubs = MMIMacho.GetHiddenGVStubList();
424 if (!Stubs.empty()) {
425 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
427 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
429 OutStreamer.EmitLabel(Stubs[i].first);
431 OutStreamer.EmitValue(MCSymbolRefExpr::
432 Create(Stubs[i].second.getPointer(),
434 4/*size*/, 0/*addrspace*/);
438 OutStreamer.AddBlankLine();
441 // Funny Darwin hack: This flag tells the linker that no global symbols
442 // contain code that falls through to other global symbols (e.g. the obvious
443 // implementation of multiple entry points). If this doesn't occur, the
444 // linker can safely perform dead code stripping. Since LLVM never
445 // generates code that does this, it is always safe to set.
446 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
450 //===----------------------------------------------------------------------===//
451 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
453 // The following seem like one-off assembler flags, but they actually need
454 // to appear in the .ARM.attributes section in ELF.
455 // Instead of subclassing the MCELFStreamer, we do the work here.
457 void ARMAsmPrinter::emitAttributes() {
459 emitARMAttributeSection();
461 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
462 bool emitFPU = false;
463 AttributeEmitter *AttrEmitter;
464 if (OutStreamer.hasRawTextSupport()) {
465 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
468 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
469 AttrEmitter = new ObjectAttributeEmitter(O);
472 AttrEmitter->MaybeSwitchVendor("aeabi");
474 std::string CPUString = Subtarget->getCPUString();
476 if (CPUString == "cortex-a8" ||
477 Subtarget->isCortexA8()) {
478 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
479 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
480 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
481 ARMBuildAttrs::ApplicationProfile);
482 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
483 ARMBuildAttrs::Allowed);
484 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
485 ARMBuildAttrs::AllowThumb32);
486 // Fixme: figure out when this is emitted.
487 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
488 // ARMBuildAttrs::AllowWMMXv1);
491 /// ADD additional Else-cases here!
492 } else if (CPUString == "generic") {
493 // FIXME: Why these defaults?
494 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
495 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
496 ARMBuildAttrs::Allowed);
497 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
498 ARMBuildAttrs::Allowed);
501 if (Subtarget->hasNEON() && emitFPU) {
502 /* NEON is not exactly a VFP architecture, but GAS emit one of
503 * neon/vfpv3/vfpv2 for .fpu parameters */
504 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
505 /* If emitted for NEON, omit from VFP below, since you can have both
506 * NEON and VFP in build attributes but only one .fpu */
511 if (Subtarget->hasVFP3()) {
512 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
513 ARMBuildAttrs::AllowFPv3A);
515 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
518 } else if (Subtarget->hasVFP2()) {
519 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
520 ARMBuildAttrs::AllowFPv2);
522 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
525 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
526 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
527 if (Subtarget->hasNEON()) {
528 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
529 ARMBuildAttrs::Allowed);
532 // Signal various FP modes.
534 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
535 ARMBuildAttrs::Allowed);
536 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
537 ARMBuildAttrs::Allowed);
540 if (NoInfsFPMath && NoNaNsFPMath)
541 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
542 ARMBuildAttrs::Allowed);
544 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
545 ARMBuildAttrs::AllowIEE754);
547 // FIXME: add more flags to ARMBuildAttrs.h
548 // 8-bytes alignment stuff.
549 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
550 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
552 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
553 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
554 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
555 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
557 // FIXME: Should we signal R9 usage?
559 if (Subtarget->hasDivide())
560 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
562 AttrEmitter->Finish();
566 void ARMAsmPrinter::emitARMAttributeSection() {
568 // [ <section-length> "vendor-name"
569 // [ <file-tag> <size> <attribute>*
570 // | <section-tag> <size> <section-number>* 0 <attribute>*
571 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
575 if (OutStreamer.hasRawTextSupport())
578 const ARMElfTargetObjectFile &TLOFELF =
579 static_cast<const ARMElfTargetObjectFile &>
580 (getObjFileLowering());
582 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
585 OutStreamer.EmitIntValue(0x41, 1);
588 //===----------------------------------------------------------------------===//
590 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
591 unsigned LabelId, MCContext &Ctx) {
593 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
594 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
598 static MCSymbolRefExpr::VariantKind
599 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
601 default: llvm_unreachable("Unknown modifier!");
602 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
603 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
604 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
605 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
606 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
607 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
609 return MCSymbolRefExpr::VK_None;
612 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
613 bool isIndirect = Subtarget->isTargetDarwin() &&
614 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
616 return Mang->getSymbol(GV);
618 // FIXME: Remove this when Darwin transition to @GOT like syntax.
619 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
620 MachineModuleInfoMachO &MMIMachO =
621 MMI->getObjFileInfo<MachineModuleInfoMachO>();
622 MachineModuleInfoImpl::StubValueTy &StubSym =
623 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
624 MMIMachO.getGVStubEntry(MCSym);
625 if (StubSym.getPointer() == 0)
626 StubSym = MachineModuleInfoImpl::
627 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
632 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
633 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
635 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
638 if (ACPV->isLSDA()) {
639 SmallString<128> Str;
640 raw_svector_ostream OS(Str);
641 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
642 MCSym = OutContext.GetOrCreateSymbol(OS.str());
643 } else if (ACPV->isBlockAddress()) {
644 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
645 } else if (ACPV->isGlobalValue()) {
646 const GlobalValue *GV = ACPV->getGV();
647 MCSym = GetARMGVSymbol(GV);
649 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
650 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
653 // Create an MCSymbol for the reference.
655 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
658 if (ACPV->getPCAdjustment()) {
659 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
663 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
665 MCBinaryExpr::CreateAdd(PCRelExpr,
666 MCConstantExpr::Create(ACPV->getPCAdjustment(),
669 if (ACPV->mustAddCurrentAddress()) {
670 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
671 // label, so just emit a local label end reference that instead.
672 MCSymbol *DotSym = OutContext.CreateTempSymbol();
673 OutStreamer.EmitLabel(DotSym);
674 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
675 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
677 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
679 OutStreamer.EmitValue(Expr, Size);
682 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
683 unsigned Opcode = MI->getOpcode();
685 if (Opcode == ARM::BR_JTadd)
687 else if (Opcode == ARM::BR_JTm)
690 const MachineOperand &MO1 = MI->getOperand(OpNum);
691 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
692 unsigned JTI = MO1.getIndex();
694 // Emit a label for the jump table.
695 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
696 OutStreamer.EmitLabel(JTISymbol);
698 // Emit each entry of the table.
699 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
700 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
701 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
703 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
704 MachineBasicBlock *MBB = JTBBs[i];
705 // Construct an MCExpr for the entry. We want a value of the form:
706 // (BasicBlockAddr - TableBeginAddr)
708 // For example, a table with entries jumping to basic blocks BB0 and BB1
711 // .word (LBB0 - LJTI_0_0)
712 // .word (LBB1 - LJTI_0_0)
713 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
715 if (TM.getRelocationModel() == Reloc::PIC_)
716 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
719 OutStreamer.EmitValue(Expr, 4);
723 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
724 unsigned Opcode = MI->getOpcode();
725 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
726 const MachineOperand &MO1 = MI->getOperand(OpNum);
727 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
728 unsigned JTI = MO1.getIndex();
730 // Emit a label for the jump table.
731 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
732 OutStreamer.EmitLabel(JTISymbol);
734 // Emit each entry of the table.
735 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
736 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
737 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
738 unsigned OffsetWidth = 4;
739 if (MI->getOpcode() == ARM::t2TBB_JT)
741 else if (MI->getOpcode() == ARM::t2TBH_JT)
744 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
745 MachineBasicBlock *MBB = JTBBs[i];
746 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
748 // If this isn't a TBB or TBH, the entries are direct branch instructions.
749 if (OffsetWidth == 4) {
751 BrInst.setOpcode(ARM::t2B);
752 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
753 OutStreamer.EmitInstruction(BrInst);
756 // Otherwise it's an offset from the dispatch instruction. Construct an
757 // MCExpr for the entry. We want a value of the form:
758 // (BasicBlockAddr - TableBeginAddr) / 2
760 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
763 // .byte (LBB0 - LJTI_0_0) / 2
764 // .byte (LBB1 - LJTI_0_0) / 2
766 MCBinaryExpr::CreateSub(MBBSymbolExpr,
767 MCSymbolRefExpr::Create(JTISymbol, OutContext),
769 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
771 OutStreamer.EmitValue(Expr, OffsetWidth);
775 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
777 unsigned NOps = MI->getNumOperands();
779 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
780 // cast away const; DIetc do not take const operands for some reason.
781 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
784 // Frame address. Currently handles register +- offset only.
785 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
786 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
789 printOperand(MI, NOps-2, OS);
792 static void populateADROperands(MCInst &Inst, unsigned Dest,
793 const MCSymbol *Label,
794 unsigned pred, unsigned ccreg,
796 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
797 Inst.addOperand(MCOperand::CreateReg(Dest));
798 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
799 // Add predicate operands.
800 Inst.addOperand(MCOperand::CreateImm(pred));
801 Inst.addOperand(MCOperand::CreateReg(ccreg));
804 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
808 // Emit the instruction as usual, just patch the opcode.
809 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
810 TmpInst.setOpcode(Opcode);
811 OutStreamer.EmitInstruction(TmpInst);
814 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
815 assert(MI->getFlag(MachineInstr::FrameSetup) &&
816 "Only instruction which are involved into frame setup code are allowed");
818 const MachineFunction &MF = *MI->getParent()->getParent();
819 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
820 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
822 unsigned FramePtr = RegInfo->getFrameRegister(MF);
823 unsigned Opc = MI->getOpcode();
824 unsigned SrcReg, DstReg;
826 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
827 // Two special cases:
828 // 1) tPUSH does not have src/dst regs.
829 // 2) for Thumb1 code we sometimes materialize the constant via constpool
830 // load. Yes, this is pretty fragile, but for now I don't see better
832 SrcReg = DstReg = ARM::SP;
834 SrcReg = MI->getOperand(1).getReg();
835 DstReg = MI->getOperand(0).getReg();
838 // Try to figure out the unwinding opcode out of src / dst regs.
839 if (MI->getDesc().mayStore()) {
841 assert(DstReg == ARM::SP &&
842 "Only stack pointer as a destination reg is supported");
844 SmallVector<unsigned, 4> RegList;
845 // Skip src & dst reg, and pred ops.
846 unsigned StartOp = 2 + 2;
847 // Use all the operands.
848 unsigned NumOffset = 0;
853 assert(0 && "Unsupported opcode for unwinding information");
855 // Special case here: no src & dst reg, but two extra imp ops.
856 StartOp = 2; NumOffset = 2;
858 case ARM::t2STMDB_UPD:
859 case ARM::VSTMDDB_UPD:
860 assert(SrcReg == ARM::SP &&
861 "Only stack pointer as a source reg is supported");
862 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
864 RegList.push_back(MI->getOperand(i).getReg());
867 assert(MI->getOperand(2).getReg() == ARM::SP &&
868 "Only stack pointer as a source reg is supported");
869 RegList.push_back(SrcReg);
872 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
874 // Changes of stack / frame pointer.
875 if (SrcReg == ARM::SP) {
880 assert(0 && "Unsupported opcode for unwinding information");
882 case ARM::tMOVgpr2gpr:
883 case ARM::tMOVgpr2tgpr:
887 Offset = -MI->getOperand(2).getImm();
891 Offset = MI->getOperand(2).getImm();
894 Offset = MI->getOperand(2).getImm()*4;
898 Offset = -MI->getOperand(2).getImm()*4;
901 // Grab the constpool index and check, whether it corresponds to
902 // original or cloned constpool entry.
903 unsigned CPI = MI->getOperand(1).getIndex();
904 const MachineConstantPool *MCP = MF.getConstantPool();
905 if (CPI >= MCP->getConstants().size())
906 CPI = AFI.getOriginalCPIdx(CPI);
907 assert(CPI != -1U && "Invalid constpool index");
909 // Derive the actual offset.
910 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
911 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
912 // FIXME: Check for user, it should be "add" instruction!
913 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
918 if (DstReg == FramePtr && FramePtr != ARM::SP)
919 // Set-up of the frame pointer. Positive values correspond to "add"
921 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
922 else if (DstReg == ARM::SP) {
923 // Change of SP by an offset. Positive values correspond to "sub"
925 OutStreamer.EmitPad(Offset);
928 assert(0 && "Unsupported opcode for unwinding information");
930 } else if (DstReg == ARM::SP) {
931 // FIXME: .movsp goes here
933 assert(0 && "Unsupported opcode for unwinding information");
937 assert(0 && "Unsupported opcode for unwinding information");
942 extern cl::opt<bool> EnableARMEHABI;
944 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
945 unsigned Opc = MI->getOpcode();
949 // B is just a Bcc with an 'always' predicate.
951 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
952 TmpInst.setOpcode(ARM::Bcc);
953 // Add predicate operands.
954 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
955 TmpInst.addOperand(MCOperand::CreateReg(0));
956 OutStreamer.EmitInstruction(TmpInst);
959 case ARM::LDMIA_RET: {
960 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
961 // such has additional code-gen properties and scheduling information.
962 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
964 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
965 TmpInst.setOpcode(ARM::LDMIA_UPD);
966 OutStreamer.EmitInstruction(TmpInst);
970 case ARM::t2ADDrSPi12:
972 case ARM::t2SUBrSPi12:
973 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
974 "Unexpected source register!");
977 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
978 case ARM::DBG_VALUE: {
979 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
980 SmallString<128> TmpStr;
981 raw_svector_ostream OS(TmpStr);
982 PrintDebugValueComment(MI, OS);
983 OutStreamer.EmitRawText(StringRef(OS.str()));
989 TmpInst.setOpcode(ARM::tBL);
990 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
991 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
992 OutStreamer.EmitInstruction(TmpInst);
997 case ARM::t2LEApcrel: {
998 // FIXME: Need to also handle globals and externals
1000 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1001 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1003 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1004 GetCPISymbol(MI->getOperand(1).getIndex()),
1005 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1007 OutStreamer.EmitInstruction(TmpInst);
1010 case ARM::LEApcrelJT:
1011 case ARM::tLEApcrelJT:
1012 case ARM::t2LEApcrelJT: {
1014 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1015 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1017 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1018 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1019 MI->getOperand(2).getImm()),
1020 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1022 OutStreamer.EmitInstruction(TmpInst);
1025 case ARM::MOVPCRX: {
1027 TmpInst.setOpcode(ARM::MOVr);
1028 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1029 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1030 // Add predicate operands.
1031 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1032 TmpInst.addOperand(MCOperand::CreateReg(0));
1033 // Add 's' bit operand (always reg0 for this)
1034 TmpInst.addOperand(MCOperand::CreateReg(0));
1035 OutStreamer.EmitInstruction(TmpInst);
1038 // Darwin call instructions are just normal call instructions with different
1039 // clobber semantics (they clobber R9).
1041 case ARM::BLr9_pred:
1043 case ARM::BLXr9_pred: {
1047 case ARM::BLr9: newOpc = ARM::BL; break;
1048 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1049 case ARM::BLXr9: newOpc = ARM::BLX; break;
1050 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1053 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1054 TmpInst.setOpcode(newOpc);
1055 OutStreamer.EmitInstruction(TmpInst);
1058 case ARM::BXr9_CALL:
1059 case ARM::BX_CALL: {
1062 TmpInst.setOpcode(ARM::MOVr);
1063 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1064 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1065 // Add predicate operands.
1066 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1067 TmpInst.addOperand(MCOperand::CreateReg(0));
1068 // Add 's' bit operand (always reg0 for this)
1069 TmpInst.addOperand(MCOperand::CreateReg(0));
1070 OutStreamer.EmitInstruction(TmpInst);
1074 TmpInst.setOpcode(ARM::BX);
1075 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1076 OutStreamer.EmitInstruction(TmpInst);
1080 case ARM::BMOVPCRXr9_CALL:
1081 case ARM::BMOVPCRX_CALL: {
1084 TmpInst.setOpcode(ARM::MOVr);
1085 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1086 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1087 // Add predicate operands.
1088 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1089 TmpInst.addOperand(MCOperand::CreateReg(0));
1090 // Add 's' bit operand (always reg0 for this)
1091 TmpInst.addOperand(MCOperand::CreateReg(0));
1092 OutStreamer.EmitInstruction(TmpInst);
1096 TmpInst.setOpcode(ARM::MOVr);
1097 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1098 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1099 // Add predicate operands.
1100 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1101 TmpInst.addOperand(MCOperand::CreateReg(0));
1102 // Add 's' bit operand (always reg0 for this)
1103 TmpInst.addOperand(MCOperand::CreateReg(0));
1104 OutStreamer.EmitInstruction(TmpInst);
1108 case ARM::MOVi16_ga_pcrel:
1109 case ARM::t2MOVi16_ga_pcrel: {
1111 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1112 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1114 unsigned TF = MI->getOperand(1).getTargetFlags();
1115 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1116 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1117 MCSymbol *GVSym = GetARMGVSymbol(GV);
1118 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1120 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1121 getFunctionNumber(),
1122 MI->getOperand(2).getImm(), OutContext);
1123 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1124 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1125 const MCExpr *PCRelExpr =
1126 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1127 MCBinaryExpr::CreateAdd(LabelSymExpr,
1128 MCConstantExpr::Create(PCAdj, OutContext),
1129 OutContext), OutContext), OutContext);
1130 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1132 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1133 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1136 // Add predicate operands.
1137 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1138 TmpInst.addOperand(MCOperand::CreateReg(0));
1139 // Add 's' bit operand (always reg0 for this)
1140 TmpInst.addOperand(MCOperand::CreateReg(0));
1141 OutStreamer.EmitInstruction(TmpInst);
1144 case ARM::MOVTi16_ga_pcrel:
1145 case ARM::t2MOVTi16_ga_pcrel: {
1147 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1148 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1149 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1150 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1152 unsigned TF = MI->getOperand(2).getTargetFlags();
1153 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1154 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1155 MCSymbol *GVSym = GetARMGVSymbol(GV);
1156 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1158 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1159 getFunctionNumber(),
1160 MI->getOperand(3).getImm(), OutContext);
1161 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1162 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1163 const MCExpr *PCRelExpr =
1164 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1165 MCBinaryExpr::CreateAdd(LabelSymExpr,
1166 MCConstantExpr::Create(PCAdj, OutContext),
1167 OutContext), OutContext), OutContext);
1168 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1170 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1171 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1173 // Add predicate operands.
1174 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1175 TmpInst.addOperand(MCOperand::CreateReg(0));
1176 // Add 's' bit operand (always reg0 for this)
1177 TmpInst.addOperand(MCOperand::CreateReg(0));
1178 OutStreamer.EmitInstruction(TmpInst);
1181 case ARM::tPICADD: {
1182 // This is a pseudo op for a label + instruction sequence, which looks like:
1185 // This adds the address of LPC0 to r0.
1188 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1189 getFunctionNumber(), MI->getOperand(2).getImm(),
1192 // Form and emit the add.
1194 AddInst.setOpcode(ARM::tADDhirr);
1195 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1196 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1197 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1198 // Add predicate operands.
1199 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1200 AddInst.addOperand(MCOperand::CreateReg(0));
1201 OutStreamer.EmitInstruction(AddInst);
1205 // This is a pseudo op for a label + instruction sequence, which looks like:
1208 // This adds the address of LPC0 to r0.
1211 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1212 getFunctionNumber(), MI->getOperand(2).getImm(),
1215 // Form and emit the add.
1217 AddInst.setOpcode(ARM::ADDrr);
1218 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1219 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1220 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1221 // Add predicate operands.
1222 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1223 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1224 // Add 's' bit operand (always reg0 for this)
1225 AddInst.addOperand(MCOperand::CreateReg(0));
1226 OutStreamer.EmitInstruction(AddInst);
1236 case ARM::PICLDRSH: {
1237 // This is a pseudo op for a label + instruction sequence, which looks like:
1240 // The LCP0 label is referenced by a constant pool entry in order to get
1241 // a PC-relative address at the ldr instruction.
1244 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1245 getFunctionNumber(), MI->getOperand(2).getImm(),
1248 // Form and emit the load
1250 switch (MI->getOpcode()) {
1252 llvm_unreachable("Unexpected opcode!");
1253 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1254 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1255 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1256 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1257 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1258 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1259 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1260 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1263 LdStInst.setOpcode(Opcode);
1264 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1265 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1266 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1267 LdStInst.addOperand(MCOperand::CreateImm(0));
1268 // Add predicate operands.
1269 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1270 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1271 OutStreamer.EmitInstruction(LdStInst);
1275 case ARM::CONSTPOOL_ENTRY: {
1276 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1277 /// in the function. The first operand is the ID# for this instruction, the
1278 /// second is the index into the MachineConstantPool that this is, the third
1279 /// is the size in bytes of this constant pool entry.
1280 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1281 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1284 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1286 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1287 if (MCPE.isMachineConstantPoolEntry())
1288 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1290 EmitGlobalConstant(MCPE.Val.ConstVal);
1294 case ARM::t2BR_JT: {
1295 // Lower and emit the instruction itself, then the jump table following it.
1297 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1298 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1299 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1300 // Add predicate operands.
1301 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1302 TmpInst.addOperand(MCOperand::CreateReg(0));
1303 OutStreamer.EmitInstruction(TmpInst);
1304 // Output the data for the jump table itself
1308 case ARM::t2TBB_JT: {
1309 // Lower and emit the instruction itself, then the jump table following it.
1312 TmpInst.setOpcode(ARM::t2TBB);
1313 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1314 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1315 // Add predicate operands.
1316 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
1318 OutStreamer.EmitInstruction(TmpInst);
1319 // Output the data for the jump table itself
1321 // Make sure the next instruction is 2-byte aligned.
1325 case ARM::t2TBH_JT: {
1326 // Lower and emit the instruction itself, then the jump table following it.
1329 TmpInst.setOpcode(ARM::t2TBH);
1330 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1331 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1332 // Add predicate operands.
1333 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1334 TmpInst.addOperand(MCOperand::CreateReg(0));
1335 OutStreamer.EmitInstruction(TmpInst);
1336 // Output the data for the jump table itself
1342 // Lower and emit the instruction itself, then the jump table following it.
1345 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1346 ARM::MOVr : ARM::tMOVgpr2gpr;
1347 TmpInst.setOpcode(Opc);
1348 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1349 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1350 // Add predicate operands.
1351 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1352 TmpInst.addOperand(MCOperand::CreateReg(0));
1353 // Add 's' bit operand (always reg0 for this)
1354 if (Opc == ARM::MOVr)
1355 TmpInst.addOperand(MCOperand::CreateReg(0));
1356 OutStreamer.EmitInstruction(TmpInst);
1358 // Make sure the Thumb jump table is 4-byte aligned.
1359 if (Opc == ARM::tMOVgpr2gpr)
1362 // Output the data for the jump table itself
1367 // Lower and emit the instruction itself, then the jump table following it.
1370 if (MI->getOperand(1).getReg() == 0) {
1372 TmpInst.setOpcode(ARM::LDRi12);
1373 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1374 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1375 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1377 TmpInst.setOpcode(ARM::LDRrs);
1378 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1379 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1380 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1381 TmpInst.addOperand(MCOperand::CreateImm(0));
1383 // Add predicate operands.
1384 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1385 TmpInst.addOperand(MCOperand::CreateReg(0));
1386 OutStreamer.EmitInstruction(TmpInst);
1388 // Output the data for the jump table itself
1392 case ARM::BR_JTadd: {
1393 // Lower and emit the instruction itself, then the jump table following it.
1394 // add pc, target, idx
1396 TmpInst.setOpcode(ARM::ADDrr);
1397 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1398 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1399 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1400 // Add predicate operands.
1401 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1402 TmpInst.addOperand(MCOperand::CreateReg(0));
1403 // Add 's' bit operand (always reg0 for this)
1404 TmpInst.addOperand(MCOperand::CreateReg(0));
1405 OutStreamer.EmitInstruction(TmpInst);
1407 // Output the data for the jump table itself
1412 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1413 // FIXME: Remove this special case when they do.
1414 if (!Subtarget->isTargetDarwin()) {
1415 //.long 0xe7ffdefe @ trap
1416 uint32_t Val = 0xe7ffdefeUL;
1417 OutStreamer.AddComment("trap");
1418 OutStreamer.EmitIntValue(Val, 4);
1424 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1425 // FIXME: Remove this special case when they do.
1426 if (!Subtarget->isTargetDarwin()) {
1427 //.short 57086 @ trap
1428 uint16_t Val = 0xdefe;
1429 OutStreamer.AddComment("trap");
1430 OutStreamer.EmitIntValue(Val, 2);
1435 case ARM::t2Int_eh_sjlj_setjmp:
1436 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1437 case ARM::tInt_eh_sjlj_setjmp: {
1438 // Two incoming args: GPR:$src, GPR:$val
1441 // str $val, [$src, #4]
1446 unsigned SrcReg = MI->getOperand(0).getReg();
1447 unsigned ValReg = MI->getOperand(1).getReg();
1448 MCSymbol *Label = GetARMSJLJEHLabel();
1451 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1452 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1453 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1455 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1456 OutStreamer.AddComment("eh_setjmp begin");
1457 OutStreamer.EmitInstruction(TmpInst);
1461 TmpInst.setOpcode(ARM::tADDi3);
1462 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1464 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1465 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1466 TmpInst.addOperand(MCOperand::CreateImm(7));
1468 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1469 TmpInst.addOperand(MCOperand::CreateReg(0));
1470 OutStreamer.EmitInstruction(TmpInst);
1474 TmpInst.setOpcode(ARM::tSTRi);
1475 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1476 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1477 // The offset immediate is #4. The operand value is scaled by 4 for the
1478 // tSTR instruction.
1479 TmpInst.addOperand(MCOperand::CreateImm(1));
1481 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1482 TmpInst.addOperand(MCOperand::CreateReg(0));
1483 OutStreamer.EmitInstruction(TmpInst);
1487 TmpInst.setOpcode(ARM::tMOVi8);
1488 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1489 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1490 TmpInst.addOperand(MCOperand::CreateImm(0));
1492 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1493 TmpInst.addOperand(MCOperand::CreateReg(0));
1494 OutStreamer.EmitInstruction(TmpInst);
1497 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1499 TmpInst.setOpcode(ARM::tB);
1500 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1501 OutStreamer.EmitInstruction(TmpInst);
1505 TmpInst.setOpcode(ARM::tMOVi8);
1506 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1507 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1508 TmpInst.addOperand(MCOperand::CreateImm(1));
1510 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1511 TmpInst.addOperand(MCOperand::CreateReg(0));
1512 OutStreamer.AddComment("eh_setjmp end");
1513 OutStreamer.EmitInstruction(TmpInst);
1515 OutStreamer.EmitLabel(Label);
1519 case ARM::Int_eh_sjlj_setjmp_nofp:
1520 case ARM::Int_eh_sjlj_setjmp: {
1521 // Two incoming args: GPR:$src, GPR:$val
1523 // str $val, [$src, #+4]
1527 unsigned SrcReg = MI->getOperand(0).getReg();
1528 unsigned ValReg = MI->getOperand(1).getReg();
1532 TmpInst.setOpcode(ARM::ADDri);
1533 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1534 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1535 TmpInst.addOperand(MCOperand::CreateImm(8));
1537 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1538 TmpInst.addOperand(MCOperand::CreateReg(0));
1539 // 's' bit operand (always reg0 for this).
1540 TmpInst.addOperand(MCOperand::CreateReg(0));
1541 OutStreamer.AddComment("eh_setjmp begin");
1542 OutStreamer.EmitInstruction(TmpInst);
1546 TmpInst.setOpcode(ARM::STRi12);
1547 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1548 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1549 TmpInst.addOperand(MCOperand::CreateImm(4));
1551 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1552 TmpInst.addOperand(MCOperand::CreateReg(0));
1553 OutStreamer.EmitInstruction(TmpInst);
1557 TmpInst.setOpcode(ARM::MOVi);
1558 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1559 TmpInst.addOperand(MCOperand::CreateImm(0));
1561 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1562 TmpInst.addOperand(MCOperand::CreateReg(0));
1563 // 's' bit operand (always reg0 for this).
1564 TmpInst.addOperand(MCOperand::CreateReg(0));
1565 OutStreamer.EmitInstruction(TmpInst);
1569 TmpInst.setOpcode(ARM::ADDri);
1570 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1571 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1572 TmpInst.addOperand(MCOperand::CreateImm(0));
1574 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1575 TmpInst.addOperand(MCOperand::CreateReg(0));
1576 // 's' bit operand (always reg0 for this).
1577 TmpInst.addOperand(MCOperand::CreateReg(0));
1578 OutStreamer.EmitInstruction(TmpInst);
1582 TmpInst.setOpcode(ARM::MOVi);
1583 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1584 TmpInst.addOperand(MCOperand::CreateImm(1));
1586 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1587 TmpInst.addOperand(MCOperand::CreateReg(0));
1588 // 's' bit operand (always reg0 for this).
1589 TmpInst.addOperand(MCOperand::CreateReg(0));
1590 OutStreamer.AddComment("eh_setjmp end");
1591 OutStreamer.EmitInstruction(TmpInst);
1595 case ARM::Int_eh_sjlj_longjmp: {
1596 // ldr sp, [$src, #8]
1597 // ldr $scratch, [$src, #4]
1600 unsigned SrcReg = MI->getOperand(0).getReg();
1601 unsigned ScratchReg = MI->getOperand(1).getReg();
1604 TmpInst.setOpcode(ARM::LDRi12);
1605 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1606 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1607 TmpInst.addOperand(MCOperand::CreateImm(8));
1609 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1610 TmpInst.addOperand(MCOperand::CreateReg(0));
1611 OutStreamer.EmitInstruction(TmpInst);
1615 TmpInst.setOpcode(ARM::LDRi12);
1616 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1617 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1618 TmpInst.addOperand(MCOperand::CreateImm(4));
1620 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1621 TmpInst.addOperand(MCOperand::CreateReg(0));
1622 OutStreamer.EmitInstruction(TmpInst);
1626 TmpInst.setOpcode(ARM::LDRi12);
1627 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1628 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1629 TmpInst.addOperand(MCOperand::CreateImm(0));
1631 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1632 TmpInst.addOperand(MCOperand::CreateReg(0));
1633 OutStreamer.EmitInstruction(TmpInst);
1637 TmpInst.setOpcode(ARM::BX);
1638 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1640 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1641 TmpInst.addOperand(MCOperand::CreateReg(0));
1642 OutStreamer.EmitInstruction(TmpInst);
1646 case ARM::tInt_eh_sjlj_longjmp: {
1647 // ldr $scratch, [$src, #8]
1649 // ldr $scratch, [$src, #4]
1652 unsigned SrcReg = MI->getOperand(0).getReg();
1653 unsigned ScratchReg = MI->getOperand(1).getReg();
1656 TmpInst.setOpcode(ARM::tLDRi);
1657 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1658 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1659 // The offset immediate is #8. The operand value is scaled by 4 for the
1660 // tLDR instruction.
1661 TmpInst.addOperand(MCOperand::CreateImm(2));
1663 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1664 TmpInst.addOperand(MCOperand::CreateReg(0));
1665 OutStreamer.EmitInstruction(TmpInst);
1669 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1670 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1671 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1673 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1674 TmpInst.addOperand(MCOperand::CreateReg(0));
1675 OutStreamer.EmitInstruction(TmpInst);
1679 TmpInst.setOpcode(ARM::tLDRi);
1680 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1681 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1682 TmpInst.addOperand(MCOperand::CreateImm(1));
1684 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1685 TmpInst.addOperand(MCOperand::CreateReg(0));
1686 OutStreamer.EmitInstruction(TmpInst);
1690 TmpInst.setOpcode(ARM::tLDRr);
1691 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1692 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1693 TmpInst.addOperand(MCOperand::CreateReg(0));
1695 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1696 TmpInst.addOperand(MCOperand::CreateReg(0));
1697 OutStreamer.EmitInstruction(TmpInst);
1701 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1702 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1704 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1705 TmpInst.addOperand(MCOperand::CreateReg(0));
1706 OutStreamer.EmitInstruction(TmpInst);
1710 // Tail jump branches are really just branch instructions with additional
1711 // code-gen attributes. Convert them to the canonical form here.
1713 case ARM::TAILJMPdND: {
1714 MCInst TmpInst, TmpInst2;
1715 // Lower the instruction as-is to get the operands properly converted.
1716 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1717 TmpInst.setOpcode(ARM::Bcc);
1718 TmpInst.addOperand(TmpInst2.getOperand(0));
1719 // Add predicate operands.
1720 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1721 TmpInst.addOperand(MCOperand::CreateReg(0));
1722 OutStreamer.AddComment("TAILCALL");
1723 OutStreamer.EmitInstruction(TmpInst);
1726 case ARM::tTAILJMPd:
1727 case ARM::tTAILJMPdND: {
1728 MCInst TmpInst, TmpInst2;
1729 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1730 TmpInst.setOpcode(ARM::tB);
1731 TmpInst.addOperand(TmpInst2.getOperand(0));
1732 OutStreamer.AddComment("TAILCALL");
1733 OutStreamer.EmitInstruction(TmpInst);
1736 case ARM::TAILJMPrND:
1737 case ARM::tTAILJMPrND:
1739 case ARM::tTAILJMPr: {
1740 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1741 ? ARM::BX : ARM::tBX;
1743 TmpInst.setOpcode(newOpc);
1744 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1746 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1747 TmpInst.addOperand(MCOperand::CreateReg(0));
1748 OutStreamer.AddComment("TAILCALL");
1749 OutStreamer.EmitInstruction(TmpInst);
1753 // These are the pseudos created to comply with stricter operand restrictions
1754 // on ARMv5. Lower them now to "normal" instructions, since all the
1755 // restrictions are already satisfied.
1757 EmitPatchedInstruction(MI, ARM::MUL);
1760 EmitPatchedInstruction(MI, ARM::MLA);
1763 EmitPatchedInstruction(MI, ARM::SMULL);
1766 EmitPatchedInstruction(MI, ARM::UMULL);
1769 EmitPatchedInstruction(MI, ARM::SMLAL);
1772 EmitPatchedInstruction(MI, ARM::UMLAL);
1775 EmitPatchedInstruction(MI, ARM::UMAAL);
1780 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1782 // Emit unwinding stuff for frame-related instructions
1783 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1784 EmitUnwindingInstruction(MI);
1786 OutStreamer.EmitInstruction(TmpInst);
1789 //===----------------------------------------------------------------------===//
1790 // Target Registry Stuff
1791 //===----------------------------------------------------------------------===//
1793 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1795 unsigned SyntaxVariant,
1796 const MCAsmInfo &MAI) {
1797 if (SyntaxVariant == 0)
1798 return new ARMInstPrinter(TM, MAI);
1802 // Force static initialization.
1803 extern "C" void LLVMInitializeARMAsmPrinter() {
1804 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1805 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1807 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1808 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);