1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 // This structure holds all attributes, accounting for
104 // their string/numeric value, so we can later emmit them
105 // in declaration order, keeping all in the same vector
106 struct AttributeItemType {
114 StringRef StringValue;
117 MCObjectStreamer &Streamer;
118 StringRef CurrentVendor;
119 SmallVector<AttributeItemType, 64> Contents;
121 // Account for the ULEB/String size of each item,
122 // not just the number of items
124 // FIXME: this should be in a more generic place, but
125 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
126 size_t getULEBSize(int Value) {
130 Size += sizeof(int8_t); // Is this really necessary?
136 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
137 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
139 void MaybeSwitchVendor(StringRef Vendor) {
140 assert(!Vendor.empty() && "Vendor cannot be empty.");
142 if (CurrentVendor.empty())
143 CurrentVendor = Vendor;
144 else if (CurrentVendor == Vendor)
149 CurrentVendor = Vendor;
151 assert(Contents.size() == 0);
154 void EmitAttribute(unsigned Attribute, unsigned Value) {
155 AttributeItemType attr = {
156 AttributeItemType::NumericAttribute,
161 ContentsSize += getULEBSize(Attribute);
162 ContentsSize += getULEBSize(Value);
163 Contents.push_back(attr);
166 void EmitTextAttribute(unsigned Attribute, StringRef String) {
167 AttributeItemType attr = {
168 AttributeItemType::TextAttribute,
173 ContentsSize += getULEBSize(Attribute);
175 ContentsSize += String.size()+1;
177 Contents.push_back(attr);
181 // Vendor size + Vendor name + '\0'
182 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
185 const size_t TagHeaderSize = 1 + 4;
187 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
188 Streamer.EmitBytes(CurrentVendor, 0);
189 Streamer.EmitIntValue(0, 1); // '\0'
191 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
192 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
194 // Size should have been accounted for already, now
195 // emit each field as its type (ULEB or String)
196 for (unsigned int i=0; i<Contents.size(); ++i) {
197 AttributeItemType item = Contents[i];
198 Streamer.EmitULEB128IntValue(item.Tag, 0);
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue, 0);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(UppercaseString(item.StringValue), 0);
205 Streamer.EmitIntValue(0, 1); // '\0'
208 assert(0 && "Invalid attribute type");
216 } // end of anonymous namespace
218 MachineLocation ARMAsmPrinter::
219 getDebugValueLocation(const MachineInstr *MI) const {
220 MachineLocation Location;
221 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
222 // Frame address. Currently handles register +- offset only.
223 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
224 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
226 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
231 /// EmitDwarfRegOp - Emit dwarf register operation.
232 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
233 const TargetRegisterInfo *RI = TM.getRegisterInfo();
234 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
235 AsmPrinter::EmitDwarfRegOp(MLoc);
237 unsigned Reg = MLoc.getReg();
238 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
239 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
240 // S registers are described as bit-pieces of a register
241 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
242 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
248 OutStreamer.AddComment("DW_OP_regx for S register");
249 EmitInt8(dwarf::DW_OP_regx);
251 OutStreamer.AddComment(Twine(SReg));
255 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
261 EmitInt8(dwarf::DW_OP_bit_piece);
265 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
266 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
267 // Q registers Q0-Q15 are described by composing two D registers together.
268 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
270 unsigned QReg = Reg - ARM::Q0;
271 unsigned D1 = 256 + 2 * QReg;
272 unsigned D2 = D1 + 1;
274 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
275 EmitInt8(dwarf::DW_OP_regx);
277 OutStreamer.AddComment("DW_OP_piece 8");
278 EmitInt8(dwarf::DW_OP_piece);
281 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
282 EmitInt8(dwarf::DW_OP_regx);
284 OutStreamer.AddComment("DW_OP_piece 8");
285 EmitInt8(dwarf::DW_OP_piece);
291 void ARMAsmPrinter::EmitFunctionEntryLabel() {
292 if (AFI->isThumbFunction()) {
293 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
294 OutStreamer.EmitThumbFunc(CurrentFnSym);
297 OutStreamer.EmitLabel(CurrentFnSym);
300 /// runOnMachineFunction - This uses the EmitInstruction()
301 /// method to print assembly for each instruction.
303 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
304 AFI = MF.getInfo<ARMFunctionInfo>();
305 MCP = MF.getConstantPool();
307 return AsmPrinter::runOnMachineFunction(MF);
310 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
311 raw_ostream &O, const char *Modifier) {
312 const MachineOperand &MO = MI->getOperand(OpNum);
313 unsigned TF = MO.getTargetFlags();
315 switch (MO.getType()) {
317 assert(0 && "<unknown operand type>");
318 case MachineOperand::MO_Register: {
319 unsigned Reg = MO.getReg();
320 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
321 assert(!MO.getSubReg() && "Subregs should be eliminated!");
322 O << ARMInstPrinter::getRegisterName(Reg);
325 case MachineOperand::MO_Immediate: {
326 int64_t Imm = MO.getImm();
328 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
329 (TF == ARMII::MO_LO16))
331 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
332 (TF == ARMII::MO_HI16))
337 case MachineOperand::MO_MachineBasicBlock:
338 O << *MO.getMBB()->getSymbol();
340 case MachineOperand::MO_GlobalAddress: {
341 const GlobalValue *GV = MO.getGlobal();
342 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
343 (TF & ARMII::MO_LO16))
345 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
346 (TF & ARMII::MO_HI16))
348 O << *Mang->getSymbol(GV);
350 printOffset(MO.getOffset(), O);
351 if (TF == ARMII::MO_PLT)
355 case MachineOperand::MO_ExternalSymbol: {
356 O << *GetExternalSymbolSymbol(MO.getSymbolName());
357 if (TF == ARMII::MO_PLT)
361 case MachineOperand::MO_ConstantPoolIndex:
362 O << *GetCPISymbol(MO.getIndex());
364 case MachineOperand::MO_JumpTableIndex:
365 O << *GetJTISymbol(MO.getIndex());
370 //===--------------------------------------------------------------------===//
372 MCSymbol *ARMAsmPrinter::
373 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
374 const MachineBasicBlock *MBB) const {
375 SmallString<60> Name;
376 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
377 << getFunctionNumber() << '_' << uid << '_' << uid2
378 << "_set_" << MBB->getNumber();
379 return OutContext.GetOrCreateSymbol(Name.str());
382 MCSymbol *ARMAsmPrinter::
383 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
384 SmallString<60> Name;
385 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
386 << getFunctionNumber() << '_' << uid << '_' << uid2;
387 return OutContext.GetOrCreateSymbol(Name.str());
391 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
392 SmallString<60> Name;
393 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
394 << getFunctionNumber();
395 return OutContext.GetOrCreateSymbol(Name.str());
398 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
399 unsigned AsmVariant, const char *ExtraCode,
401 // Does this asm operand have a single letter operand modifier?
402 if (ExtraCode && ExtraCode[0]) {
403 if (ExtraCode[1] != 0) return true; // Unknown modifier.
405 switch (ExtraCode[0]) {
406 default: return true; // Unknown modifier.
407 case 'a': // Print as a memory address.
408 if (MI->getOperand(OpNum).isReg()) {
410 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
415 case 'c': // Don't print "#" before an immediate operand.
416 if (!MI->getOperand(OpNum).isImm())
418 O << MI->getOperand(OpNum).getImm();
420 case 'P': // Print a VFP double precision register.
421 case 'q': // Print a NEON quad precision register.
422 printOperand(MI, OpNum, O);
424 case 'y': // Print a VFP single precision register as indexed double.
425 // This uses the ordering of the alias table to get the first 'd' register
426 // that overlaps the 's' register. Also, s0 is an odd register, hence the
427 // odd modulus check below.
428 if (MI->getOperand(OpNum).isReg()) {
429 unsigned Reg = MI->getOperand(OpNum).getReg();
430 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
431 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
432 (((Reg % 2) == 1) ? "[0]" : "[1]");
436 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
437 if (!MI->getOperand(OpNum).isImm())
439 O << ~(MI->getOperand(OpNum).getImm());
441 case 'L': // The low 16 bits of an immediate constant.
442 if (!MI->getOperand(OpNum).isImm())
444 O << (MI->getOperand(OpNum).getImm() & 0xffff);
446 case 'M': { // A register range suitable for LDM/STM.
447 if (!MI->getOperand(OpNum).isReg())
449 const MachineOperand &MO = MI->getOperand(OpNum);
450 unsigned RegBegin = MO.getReg();
451 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
452 // already got the operands in registers that are operands to the
453 // inline asm statement.
455 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
457 // FIXME: The register allocator not only may not have given us the
458 // registers in sequence, but may not be in ascending registers. This
459 // will require changes in the register allocator that'll need to be
460 // propagated down here if the operands change.
461 unsigned RegOps = OpNum + 1;
462 while (MI->getOperand(RegOps).isReg()) {
464 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
472 // These modifiers are not yet supported.
473 case 'p': // The high single-precision register of a VFP double-precision
475 case 'e': // The low doubleword register of a NEON quad register.
476 case 'f': // The high doubleword register of a NEON quad register.
477 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
478 case 'Q': // The least significant register of a pair.
479 case 'R': // The most significant register of a pair.
480 case 'H': // The highest-numbered register of a pair.
485 printOperand(MI, OpNum, O);
489 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
490 unsigned OpNum, unsigned AsmVariant,
491 const char *ExtraCode,
493 // Does this asm operand have a single letter operand modifier?
494 if (ExtraCode && ExtraCode[0]) {
495 if (ExtraCode[1] != 0) return true; // Unknown modifier.
497 switch (ExtraCode[0]) {
498 case 'A': // A memory operand for a VLD1/VST1 instruction.
499 default: return true; // Unknown modifier.
500 case 'm': // The base register of a memory operand.
501 if (!MI->getOperand(OpNum).isReg())
503 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
508 const MachineOperand &MO = MI->getOperand(OpNum);
509 assert(MO.isReg() && "unexpected inline asm memory operand");
510 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
514 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
515 if (Subtarget->isTargetDarwin()) {
516 Reloc::Model RelocM = TM.getRelocationModel();
517 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
518 // Declare all the text sections up front (before the DWARF sections
519 // emitted by AsmPrinter::doInitialization) so the assembler will keep
520 // them together at the beginning of the object file. This helps
521 // avoid out-of-range branches that are due a fundamental limitation of
522 // the way symbol offsets are encoded with the current Darwin ARM
524 const TargetLoweringObjectFileMachO &TLOFMacho =
525 static_cast<const TargetLoweringObjectFileMachO &>(
526 getObjFileLowering());
527 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
528 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
529 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
530 if (RelocM == Reloc::DynamicNoPIC) {
531 const MCSection *sect =
532 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
533 MCSectionMachO::S_SYMBOL_STUBS,
534 12, SectionKind::getText());
535 OutStreamer.SwitchSection(sect);
537 const MCSection *sect =
538 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
539 MCSectionMachO::S_SYMBOL_STUBS,
540 16, SectionKind::getText());
541 OutStreamer.SwitchSection(sect);
543 const MCSection *StaticInitSect =
544 OutContext.getMachOSection("__TEXT", "__StaticInit",
545 MCSectionMachO::S_REGULAR |
546 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
547 SectionKind::getText());
548 OutStreamer.SwitchSection(StaticInitSect);
552 // Use unified assembler syntax.
553 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
555 // Emit ARM Build Attributes
556 if (Subtarget->isTargetELF()) {
563 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
564 if (Subtarget->isTargetDarwin()) {
565 // All darwin targets use mach-o.
566 const TargetLoweringObjectFileMachO &TLOFMacho =
567 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
568 MachineModuleInfoMachO &MMIMacho =
569 MMI->getObjFileInfo<MachineModuleInfoMachO>();
571 // Output non-lazy-pointers for external and common global variables.
572 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
574 if (!Stubs.empty()) {
575 // Switch with ".non_lazy_symbol_pointer" directive.
576 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
578 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
580 OutStreamer.EmitLabel(Stubs[i].first);
581 // .indirect_symbol _foo
582 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
583 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
586 // External to current translation unit.
587 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
589 // Internal to current translation unit.
591 // When we place the LSDA into the TEXT section, the type info
592 // pointers need to be indirect and pc-rel. We accomplish this by
593 // using NLPs; however, sometimes the types are local to the file.
594 // We need to fill in the value for the NLP in those cases.
595 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
597 4/*size*/, 0/*addrspace*/);
601 OutStreamer.AddBlankLine();
604 Stubs = MMIMacho.GetHiddenGVStubList();
605 if (!Stubs.empty()) {
606 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
608 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
610 OutStreamer.EmitLabel(Stubs[i].first);
612 OutStreamer.EmitValue(MCSymbolRefExpr::
613 Create(Stubs[i].second.getPointer(),
615 4/*size*/, 0/*addrspace*/);
619 OutStreamer.AddBlankLine();
622 // Funny Darwin hack: This flag tells the linker that no global symbols
623 // contain code that falls through to other global symbols (e.g. the obvious
624 // implementation of multiple entry points). If this doesn't occur, the
625 // linker can safely perform dead code stripping. Since LLVM never
626 // generates code that does this, it is always safe to set.
627 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
631 //===----------------------------------------------------------------------===//
632 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
634 // The following seem like one-off assembler flags, but they actually need
635 // to appear in the .ARM.attributes section in ELF.
636 // Instead of subclassing the MCELFStreamer, we do the work here.
638 void ARMAsmPrinter::emitAttributes() {
640 emitARMAttributeSection();
642 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
643 bool emitFPU = false;
644 AttributeEmitter *AttrEmitter;
645 if (OutStreamer.hasRawTextSupport()) {
646 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
649 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
650 AttrEmitter = new ObjectAttributeEmitter(O);
653 AttrEmitter->MaybeSwitchVendor("aeabi");
655 std::string CPUString = Subtarget->getCPUString();
657 if (CPUString == "cortex-a8" ||
658 Subtarget->isCortexA8()) {
659 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
660 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
661 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
662 ARMBuildAttrs::ApplicationProfile);
663 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
664 ARMBuildAttrs::Allowed);
665 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
666 ARMBuildAttrs::AllowThumb32);
667 // Fixme: figure out when this is emitted.
668 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
669 // ARMBuildAttrs::AllowWMMXv1);
672 /// ADD additional Else-cases here!
673 } else if (CPUString == "xscale") {
674 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
675 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
676 ARMBuildAttrs::Allowed);
677 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
678 ARMBuildAttrs::Allowed);
679 } else if (CPUString == "generic") {
680 // FIXME: Why these defaults?
681 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
682 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
683 ARMBuildAttrs::Allowed);
684 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
685 ARMBuildAttrs::Allowed);
688 if (Subtarget->hasNEON() && emitFPU) {
689 /* NEON is not exactly a VFP architecture, but GAS emit one of
690 * neon/vfpv3/vfpv2 for .fpu parameters */
691 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
692 /* If emitted for NEON, omit from VFP below, since you can have both
693 * NEON and VFP in build attributes but only one .fpu */
698 if (Subtarget->hasVFP3()) {
699 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
700 ARMBuildAttrs::AllowFPv3A);
702 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
705 } else if (Subtarget->hasVFP2()) {
706 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
707 ARMBuildAttrs::AllowFPv2);
709 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
712 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
713 * since NEON can have 1 (allowed) or 2 (MAC operations) */
714 if (Subtarget->hasNEON()) {
715 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
716 ARMBuildAttrs::Allowed);
719 // Signal various FP modes.
721 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
722 ARMBuildAttrs::Allowed);
723 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
724 ARMBuildAttrs::Allowed);
727 if (NoInfsFPMath && NoNaNsFPMath)
728 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
729 ARMBuildAttrs::Allowed);
731 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
732 ARMBuildAttrs::AllowIEE754);
734 // FIXME: add more flags to ARMBuildAttrs.h
735 // 8-bytes alignment stuff.
736 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
737 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
739 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
740 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
741 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
742 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
744 // FIXME: Should we signal R9 usage?
746 if (Subtarget->hasDivide())
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
749 AttrEmitter->Finish();
753 void ARMAsmPrinter::emitARMAttributeSection() {
755 // [ <section-length> "vendor-name"
756 // [ <file-tag> <size> <attribute>*
757 // | <section-tag> <size> <section-number>* 0 <attribute>*
758 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
762 if (OutStreamer.hasRawTextSupport())
765 const ARMElfTargetObjectFile &TLOFELF =
766 static_cast<const ARMElfTargetObjectFile &>
767 (getObjFileLowering());
769 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
772 OutStreamer.EmitIntValue(0x41, 1);
775 //===----------------------------------------------------------------------===//
777 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
778 unsigned LabelId, MCContext &Ctx) {
780 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
781 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
785 static MCSymbolRefExpr::VariantKind
786 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
788 default: llvm_unreachable("Unknown modifier!");
789 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
790 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
791 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
792 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
793 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
794 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
796 return MCSymbolRefExpr::VK_None;
799 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
800 bool isIndirect = Subtarget->isTargetDarwin() &&
801 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
803 return Mang->getSymbol(GV);
805 // FIXME: Remove this when Darwin transition to @GOT like syntax.
806 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
807 MachineModuleInfoMachO &MMIMachO =
808 MMI->getObjFileInfo<MachineModuleInfoMachO>();
809 MachineModuleInfoImpl::StubValueTy &StubSym =
810 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
811 MMIMachO.getGVStubEntry(MCSym);
812 if (StubSym.getPointer() == 0)
813 StubSym = MachineModuleInfoImpl::
814 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
819 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
820 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
822 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
825 if (ACPV->isLSDA()) {
826 SmallString<128> Str;
827 raw_svector_ostream OS(Str);
828 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
829 MCSym = OutContext.GetOrCreateSymbol(OS.str());
830 } else if (ACPV->isBlockAddress()) {
831 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
832 } else if (ACPV->isGlobalValue()) {
833 const GlobalValue *GV = ACPV->getGV();
834 MCSym = GetARMGVSymbol(GV);
836 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
837 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
840 // Create an MCSymbol for the reference.
842 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
845 if (ACPV->getPCAdjustment()) {
846 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
850 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
852 MCBinaryExpr::CreateAdd(PCRelExpr,
853 MCConstantExpr::Create(ACPV->getPCAdjustment(),
856 if (ACPV->mustAddCurrentAddress()) {
857 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
858 // label, so just emit a local label end reference that instead.
859 MCSymbol *DotSym = OutContext.CreateTempSymbol();
860 OutStreamer.EmitLabel(DotSym);
861 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
862 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
864 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
866 OutStreamer.EmitValue(Expr, Size);
869 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
870 unsigned Opcode = MI->getOpcode();
872 if (Opcode == ARM::BR_JTadd)
874 else if (Opcode == ARM::BR_JTm)
877 const MachineOperand &MO1 = MI->getOperand(OpNum);
878 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
879 unsigned JTI = MO1.getIndex();
881 // Emit a label for the jump table.
882 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
883 OutStreamer.EmitLabel(JTISymbol);
885 // Emit each entry of the table.
886 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
887 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
888 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
890 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
891 MachineBasicBlock *MBB = JTBBs[i];
892 // Construct an MCExpr for the entry. We want a value of the form:
893 // (BasicBlockAddr - TableBeginAddr)
895 // For example, a table with entries jumping to basic blocks BB0 and BB1
898 // .word (LBB0 - LJTI_0_0)
899 // .word (LBB1 - LJTI_0_0)
900 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
902 if (TM.getRelocationModel() == Reloc::PIC_)
903 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
906 OutStreamer.EmitValue(Expr, 4);
910 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
911 unsigned Opcode = MI->getOpcode();
912 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
913 const MachineOperand &MO1 = MI->getOperand(OpNum);
914 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
915 unsigned JTI = MO1.getIndex();
917 // Emit a label for the jump table.
918 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
919 OutStreamer.EmitLabel(JTISymbol);
921 // Emit each entry of the table.
922 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
923 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
924 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
925 unsigned OffsetWidth = 4;
926 if (MI->getOpcode() == ARM::t2TBB_JT)
928 else if (MI->getOpcode() == ARM::t2TBH_JT)
931 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
932 MachineBasicBlock *MBB = JTBBs[i];
933 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
935 // If this isn't a TBB or TBH, the entries are direct branch instructions.
936 if (OffsetWidth == 4) {
938 BrInst.setOpcode(ARM::t2B);
939 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
940 OutStreamer.EmitInstruction(BrInst);
943 // Otherwise it's an offset from the dispatch instruction. Construct an
944 // MCExpr for the entry. We want a value of the form:
945 // (BasicBlockAddr - TableBeginAddr) / 2
947 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
950 // .byte (LBB0 - LJTI_0_0) / 2
951 // .byte (LBB1 - LJTI_0_0) / 2
953 MCBinaryExpr::CreateSub(MBBSymbolExpr,
954 MCSymbolRefExpr::Create(JTISymbol, OutContext),
956 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
958 OutStreamer.EmitValue(Expr, OffsetWidth);
962 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
964 unsigned NOps = MI->getNumOperands();
966 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
967 // cast away const; DIetc do not take const operands for some reason.
968 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
971 // Frame address. Currently handles register +- offset only.
972 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
973 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
976 printOperand(MI, NOps-2, OS);
979 static void populateADROperands(MCInst &Inst, unsigned Dest,
980 const MCSymbol *Label,
981 unsigned pred, unsigned ccreg,
983 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
984 Inst.addOperand(MCOperand::CreateReg(Dest));
985 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
986 // Add predicate operands.
987 Inst.addOperand(MCOperand::CreateImm(pred));
988 Inst.addOperand(MCOperand::CreateReg(ccreg));
991 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
995 // Emit the instruction as usual, just patch the opcode.
996 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
997 TmpInst.setOpcode(Opcode);
998 OutStreamer.EmitInstruction(TmpInst);
1001 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1002 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1003 "Only instruction which are involved into frame setup code are allowed");
1005 const MachineFunction &MF = *MI->getParent()->getParent();
1006 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1007 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1009 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1010 unsigned Opc = MI->getOpcode();
1011 unsigned SrcReg, DstReg;
1013 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1014 // Two special cases:
1015 // 1) tPUSH does not have src/dst regs.
1016 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1017 // load. Yes, this is pretty fragile, but for now I don't see better
1019 SrcReg = DstReg = ARM::SP;
1021 SrcReg = MI->getOperand(1).getReg();
1022 DstReg = MI->getOperand(0).getReg();
1025 // Try to figure out the unwinding opcode out of src / dst regs.
1026 if (MI->getDesc().mayStore()) {
1028 assert(DstReg == ARM::SP &&
1029 "Only stack pointer as a destination reg is supported");
1031 SmallVector<unsigned, 4> RegList;
1032 // Skip src & dst reg, and pred ops.
1033 unsigned StartOp = 2 + 2;
1034 // Use all the operands.
1035 unsigned NumOffset = 0;
1040 assert(0 && "Unsupported opcode for unwinding information");
1042 // Special case here: no src & dst reg, but two extra imp ops.
1043 StartOp = 2; NumOffset = 2;
1044 case ARM::STMDB_UPD:
1045 case ARM::t2STMDB_UPD:
1046 case ARM::VSTMDDB_UPD:
1047 assert(SrcReg == ARM::SP &&
1048 "Only stack pointer as a source reg is supported");
1049 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1051 RegList.push_back(MI->getOperand(i).getReg());
1053 case ARM::STR_PRE_IMM:
1054 case ARM::STR_PRE_REG:
1055 assert(MI->getOperand(2).getReg() == ARM::SP &&
1056 "Only stack pointer as a source reg is supported");
1057 RegList.push_back(SrcReg);
1060 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1062 // Changes of stack / frame pointer.
1063 if (SrcReg == ARM::SP) {
1068 assert(0 && "Unsupported opcode for unwinding information");
1073 Offset = -MI->getOperand(2).getImm();
1076 Offset = MI->getOperand(2).getImm();
1079 Offset = MI->getOperand(2).getImm()*4;
1083 Offset = -MI->getOperand(2).getImm()*4;
1085 case ARM::tLDRpci: {
1086 // Grab the constpool index and check, whether it corresponds to
1087 // original or cloned constpool entry.
1088 unsigned CPI = MI->getOperand(1).getIndex();
1089 const MachineConstantPool *MCP = MF.getConstantPool();
1090 if (CPI >= MCP->getConstants().size())
1091 CPI = AFI.getOriginalCPIdx(CPI);
1092 assert(CPI != -1U && "Invalid constpool index");
1094 // Derive the actual offset.
1095 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1096 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1097 // FIXME: Check for user, it should be "add" instruction!
1098 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1103 if (DstReg == FramePtr && FramePtr != ARM::SP)
1104 // Set-up of the frame pointer. Positive values correspond to "add"
1106 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1107 else if (DstReg == ARM::SP) {
1108 // Change of SP by an offset. Positive values correspond to "sub"
1110 OutStreamer.EmitPad(Offset);
1113 assert(0 && "Unsupported opcode for unwinding information");
1115 } else if (DstReg == ARM::SP) {
1116 // FIXME: .movsp goes here
1118 assert(0 && "Unsupported opcode for unwinding information");
1122 assert(0 && "Unsupported opcode for unwinding information");
1127 extern cl::opt<bool> EnableARMEHABI;
1129 // Simple pseudo-instructions have their lowering (with expansion to real
1130 // instructions) auto-generated.
1131 #include "ARMGenMCPseudoLowering.inc"
1133 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1134 // Do any auto-generated pseudo lowerings.
1135 if (emitPseudoExpansionLowering(OutStreamer, MI))
1138 // Check for manual lowerings.
1139 unsigned Opc = MI->getOpcode();
1141 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1142 case ARM::DBG_VALUE: {
1143 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1144 SmallString<128> TmpStr;
1145 raw_svector_ostream OS(TmpStr);
1146 PrintDebugValueComment(MI, OS);
1147 OutStreamer.EmitRawText(StringRef(OS.str()));
1152 case ARM::tLEApcrel:
1153 case ARM::t2LEApcrel: {
1154 // FIXME: Need to also handle globals and externals
1156 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1157 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1159 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1160 GetCPISymbol(MI->getOperand(1).getIndex()),
1161 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1163 OutStreamer.EmitInstruction(TmpInst);
1166 case ARM::LEApcrelJT:
1167 case ARM::tLEApcrelJT:
1168 case ARM::t2LEApcrelJT: {
1170 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1171 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1173 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1174 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1175 MI->getOperand(2).getImm()),
1176 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1178 OutStreamer.EmitInstruction(TmpInst);
1181 // Darwin call instructions are just normal call instructions with different
1182 // clobber semantics (they clobber R9).
1183 case ARM::BXr9_CALL:
1184 case ARM::BX_CALL: {
1187 TmpInst.setOpcode(ARM::MOVr);
1188 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1189 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1190 // Add predicate operands.
1191 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1192 TmpInst.addOperand(MCOperand::CreateReg(0));
1193 // Add 's' bit operand (always reg0 for this)
1194 TmpInst.addOperand(MCOperand::CreateReg(0));
1195 OutStreamer.EmitInstruction(TmpInst);
1199 TmpInst.setOpcode(ARM::BX);
1200 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1201 OutStreamer.EmitInstruction(TmpInst);
1205 case ARM::tBXr9_CALL:
1206 case ARM::tBX_CALL: {
1209 TmpInst.setOpcode(ARM::tMOVr);
1210 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1211 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1212 // Add predicate operands.
1213 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1214 TmpInst.addOperand(MCOperand::CreateReg(0));
1215 OutStreamer.EmitInstruction(TmpInst);
1219 TmpInst.setOpcode(ARM::tBX);
1220 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1221 // Add predicate operands.
1222 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1223 TmpInst.addOperand(MCOperand::CreateReg(0));
1224 OutStreamer.EmitInstruction(TmpInst);
1228 case ARM::BMOVPCRXr9_CALL:
1229 case ARM::BMOVPCRX_CALL: {
1232 TmpInst.setOpcode(ARM::MOVr);
1233 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1234 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1235 // Add predicate operands.
1236 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
1238 // Add 's' bit operand (always reg0 for this)
1239 TmpInst.addOperand(MCOperand::CreateReg(0));
1240 OutStreamer.EmitInstruction(TmpInst);
1244 TmpInst.setOpcode(ARM::MOVr);
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1246 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1247 // Add predicate operands.
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 // Add 's' bit operand (always reg0 for this)
1251 TmpInst.addOperand(MCOperand::CreateReg(0));
1252 OutStreamer.EmitInstruction(TmpInst);
1256 case ARM::MOVi16_ga_pcrel:
1257 case ARM::t2MOVi16_ga_pcrel: {
1259 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1260 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1262 unsigned TF = MI->getOperand(1).getTargetFlags();
1263 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1264 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1265 MCSymbol *GVSym = GetARMGVSymbol(GV);
1266 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1268 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1269 getFunctionNumber(),
1270 MI->getOperand(2).getImm(), OutContext);
1271 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1272 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1273 const MCExpr *PCRelExpr =
1274 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1275 MCBinaryExpr::CreateAdd(LabelSymExpr,
1276 MCConstantExpr::Create(PCAdj, OutContext),
1277 OutContext), OutContext), OutContext);
1278 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1280 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1281 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1284 // Add predicate operands.
1285 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1286 TmpInst.addOperand(MCOperand::CreateReg(0));
1287 // Add 's' bit operand (always reg0 for this)
1288 TmpInst.addOperand(MCOperand::CreateReg(0));
1289 OutStreamer.EmitInstruction(TmpInst);
1292 case ARM::MOVTi16_ga_pcrel:
1293 case ARM::t2MOVTi16_ga_pcrel: {
1295 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1296 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1297 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1298 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1300 unsigned TF = MI->getOperand(2).getTargetFlags();
1301 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1302 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1303 MCSymbol *GVSym = GetARMGVSymbol(GV);
1304 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1306 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1307 getFunctionNumber(),
1308 MI->getOperand(3).getImm(), OutContext);
1309 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1310 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1311 const MCExpr *PCRelExpr =
1312 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1313 MCBinaryExpr::CreateAdd(LabelSymExpr,
1314 MCConstantExpr::Create(PCAdj, OutContext),
1315 OutContext), OutContext), OutContext);
1316 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1318 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1319 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1321 // Add predicate operands.
1322 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1323 TmpInst.addOperand(MCOperand::CreateReg(0));
1324 // Add 's' bit operand (always reg0 for this)
1325 TmpInst.addOperand(MCOperand::CreateReg(0));
1326 OutStreamer.EmitInstruction(TmpInst);
1329 case ARM::tPICADD: {
1330 // This is a pseudo op for a label + instruction sequence, which looks like:
1333 // This adds the address of LPC0 to r0.
1336 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1337 getFunctionNumber(), MI->getOperand(2).getImm(),
1340 // Form and emit the add.
1342 AddInst.setOpcode(ARM::tADDhirr);
1343 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1344 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1345 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1346 // Add predicate operands.
1347 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1348 AddInst.addOperand(MCOperand::CreateReg(0));
1349 OutStreamer.EmitInstruction(AddInst);
1353 // This is a pseudo op for a label + instruction sequence, which looks like:
1356 // This adds the address of LPC0 to r0.
1359 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1360 getFunctionNumber(), MI->getOperand(2).getImm(),
1363 // Form and emit the add.
1365 AddInst.setOpcode(ARM::ADDrr);
1366 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1367 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1368 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1369 // Add predicate operands.
1370 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1371 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1372 // Add 's' bit operand (always reg0 for this)
1373 AddInst.addOperand(MCOperand::CreateReg(0));
1374 OutStreamer.EmitInstruction(AddInst);
1384 case ARM::PICLDRSH: {
1385 // This is a pseudo op for a label + instruction sequence, which looks like:
1388 // The LCP0 label is referenced by a constant pool entry in order to get
1389 // a PC-relative address at the ldr instruction.
1392 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1393 getFunctionNumber(), MI->getOperand(2).getImm(),
1396 // Form and emit the load
1398 switch (MI->getOpcode()) {
1400 llvm_unreachable("Unexpected opcode!");
1401 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1402 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1403 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1404 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1405 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1406 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1407 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1408 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1411 LdStInst.setOpcode(Opcode);
1412 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1413 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1414 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1415 LdStInst.addOperand(MCOperand::CreateImm(0));
1416 // Add predicate operands.
1417 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1418 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1419 OutStreamer.EmitInstruction(LdStInst);
1423 case ARM::CONSTPOOL_ENTRY: {
1424 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1425 /// in the function. The first operand is the ID# for this instruction, the
1426 /// second is the index into the MachineConstantPool that this is, the third
1427 /// is the size in bytes of this constant pool entry.
1428 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1429 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1432 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1434 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1435 if (MCPE.isMachineConstantPoolEntry())
1436 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1438 EmitGlobalConstant(MCPE.Val.ConstVal);
1442 case ARM::t2BR_JT: {
1443 // Lower and emit the instruction itself, then the jump table following it.
1445 TmpInst.setOpcode(ARM::tMOVr);
1446 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1447 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1448 // Add predicate operands.
1449 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1450 TmpInst.addOperand(MCOperand::CreateReg(0));
1451 OutStreamer.EmitInstruction(TmpInst);
1452 // Output the data for the jump table itself
1456 case ARM::t2TBB_JT: {
1457 // Lower and emit the instruction itself, then the jump table following it.
1460 TmpInst.setOpcode(ARM::t2TBB);
1461 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1462 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1463 // Add predicate operands.
1464 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1465 TmpInst.addOperand(MCOperand::CreateReg(0));
1466 OutStreamer.EmitInstruction(TmpInst);
1467 // Output the data for the jump table itself
1469 // Make sure the next instruction is 2-byte aligned.
1473 case ARM::t2TBH_JT: {
1474 // Lower and emit the instruction itself, then the jump table following it.
1477 TmpInst.setOpcode(ARM::t2TBH);
1478 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1479 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1480 // Add predicate operands.
1481 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1482 TmpInst.addOperand(MCOperand::CreateReg(0));
1483 OutStreamer.EmitInstruction(TmpInst);
1484 // Output the data for the jump table itself
1490 // Lower and emit the instruction itself, then the jump table following it.
1493 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1494 ARM::MOVr : ARM::tMOVr;
1495 TmpInst.setOpcode(Opc);
1496 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1497 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1498 // Add predicate operands.
1499 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1500 TmpInst.addOperand(MCOperand::CreateReg(0));
1501 // Add 's' bit operand (always reg0 for this)
1502 if (Opc == ARM::MOVr)
1503 TmpInst.addOperand(MCOperand::CreateReg(0));
1504 OutStreamer.EmitInstruction(TmpInst);
1506 // Make sure the Thumb jump table is 4-byte aligned.
1507 if (Opc == ARM::tMOVr)
1510 // Output the data for the jump table itself
1515 // Lower and emit the instruction itself, then the jump table following it.
1518 if (MI->getOperand(1).getReg() == 0) {
1520 TmpInst.setOpcode(ARM::LDRi12);
1521 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1522 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1523 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1525 TmpInst.setOpcode(ARM::LDRrs);
1526 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1527 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1528 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1529 TmpInst.addOperand(MCOperand::CreateImm(0));
1531 // Add predicate operands.
1532 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1533 TmpInst.addOperand(MCOperand::CreateReg(0));
1534 OutStreamer.EmitInstruction(TmpInst);
1536 // Output the data for the jump table itself
1540 case ARM::BR_JTadd: {
1541 // Lower and emit the instruction itself, then the jump table following it.
1542 // add pc, target, idx
1544 TmpInst.setOpcode(ARM::ADDrr);
1545 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1546 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1547 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1548 // Add predicate operands.
1549 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1550 TmpInst.addOperand(MCOperand::CreateReg(0));
1551 // Add 's' bit operand (always reg0 for this)
1552 TmpInst.addOperand(MCOperand::CreateReg(0));
1553 OutStreamer.EmitInstruction(TmpInst);
1555 // Output the data for the jump table itself
1560 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1561 // FIXME: Remove this special case when they do.
1562 if (!Subtarget->isTargetDarwin()) {
1563 //.long 0xe7ffdefe @ trap
1564 uint32_t Val = 0xe7ffdefeUL;
1565 OutStreamer.AddComment("trap");
1566 OutStreamer.EmitIntValue(Val, 4);
1572 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1573 // FIXME: Remove this special case when they do.
1574 if (!Subtarget->isTargetDarwin()) {
1575 //.short 57086 @ trap
1576 uint16_t Val = 0xdefe;
1577 OutStreamer.AddComment("trap");
1578 OutStreamer.EmitIntValue(Val, 2);
1583 case ARM::t2Int_eh_sjlj_setjmp:
1584 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1585 case ARM::tInt_eh_sjlj_setjmp: {
1586 // Two incoming args: GPR:$src, GPR:$val
1589 // str $val, [$src, #4]
1594 unsigned SrcReg = MI->getOperand(0).getReg();
1595 unsigned ValReg = MI->getOperand(1).getReg();
1596 MCSymbol *Label = GetARMSJLJEHLabel();
1599 TmpInst.setOpcode(ARM::tMOVr);
1600 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1601 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1603 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1604 TmpInst.addOperand(MCOperand::CreateReg(0));
1605 OutStreamer.AddComment("eh_setjmp begin");
1606 OutStreamer.EmitInstruction(TmpInst);
1610 TmpInst.setOpcode(ARM::tADDi3);
1611 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1613 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1614 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1615 TmpInst.addOperand(MCOperand::CreateImm(7));
1617 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1618 TmpInst.addOperand(MCOperand::CreateReg(0));
1619 OutStreamer.EmitInstruction(TmpInst);
1623 TmpInst.setOpcode(ARM::tSTRi);
1624 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1625 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1626 // The offset immediate is #4. The operand value is scaled by 4 for the
1627 // tSTR instruction.
1628 TmpInst.addOperand(MCOperand::CreateImm(1));
1630 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1631 TmpInst.addOperand(MCOperand::CreateReg(0));
1632 OutStreamer.EmitInstruction(TmpInst);
1636 TmpInst.setOpcode(ARM::tMOVi8);
1637 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1638 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1639 TmpInst.addOperand(MCOperand::CreateImm(0));
1641 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1642 TmpInst.addOperand(MCOperand::CreateReg(0));
1643 OutStreamer.EmitInstruction(TmpInst);
1646 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1648 TmpInst.setOpcode(ARM::tB);
1649 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1650 OutStreamer.EmitInstruction(TmpInst);
1654 TmpInst.setOpcode(ARM::tMOVi8);
1655 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1656 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1657 TmpInst.addOperand(MCOperand::CreateImm(1));
1659 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1660 TmpInst.addOperand(MCOperand::CreateReg(0));
1661 OutStreamer.AddComment("eh_setjmp end");
1662 OutStreamer.EmitInstruction(TmpInst);
1664 OutStreamer.EmitLabel(Label);
1668 case ARM::Int_eh_sjlj_setjmp_nofp:
1669 case ARM::Int_eh_sjlj_setjmp: {
1670 // Two incoming args: GPR:$src, GPR:$val
1672 // str $val, [$src, #+4]
1676 unsigned SrcReg = MI->getOperand(0).getReg();
1677 unsigned ValReg = MI->getOperand(1).getReg();
1681 TmpInst.setOpcode(ARM::ADDri);
1682 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1683 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1684 TmpInst.addOperand(MCOperand::CreateImm(8));
1686 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1687 TmpInst.addOperand(MCOperand::CreateReg(0));
1688 // 's' bit operand (always reg0 for this).
1689 TmpInst.addOperand(MCOperand::CreateReg(0));
1690 OutStreamer.AddComment("eh_setjmp begin");
1691 OutStreamer.EmitInstruction(TmpInst);
1695 TmpInst.setOpcode(ARM::STRi12);
1696 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1697 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1698 TmpInst.addOperand(MCOperand::CreateImm(4));
1700 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1701 TmpInst.addOperand(MCOperand::CreateReg(0));
1702 OutStreamer.EmitInstruction(TmpInst);
1706 TmpInst.setOpcode(ARM::MOVi);
1707 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1708 TmpInst.addOperand(MCOperand::CreateImm(0));
1710 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1711 TmpInst.addOperand(MCOperand::CreateReg(0));
1712 // 's' bit operand (always reg0 for this).
1713 TmpInst.addOperand(MCOperand::CreateReg(0));
1714 OutStreamer.EmitInstruction(TmpInst);
1718 TmpInst.setOpcode(ARM::ADDri);
1719 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1720 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1721 TmpInst.addOperand(MCOperand::CreateImm(0));
1723 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1724 TmpInst.addOperand(MCOperand::CreateReg(0));
1725 // 's' bit operand (always reg0 for this).
1726 TmpInst.addOperand(MCOperand::CreateReg(0));
1727 OutStreamer.EmitInstruction(TmpInst);
1731 TmpInst.setOpcode(ARM::MOVi);
1732 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1733 TmpInst.addOperand(MCOperand::CreateImm(1));
1735 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1736 TmpInst.addOperand(MCOperand::CreateReg(0));
1737 // 's' bit operand (always reg0 for this).
1738 TmpInst.addOperand(MCOperand::CreateReg(0));
1739 OutStreamer.AddComment("eh_setjmp end");
1740 OutStreamer.EmitInstruction(TmpInst);
1744 case ARM::Int_eh_sjlj_longjmp: {
1745 // ldr sp, [$src, #8]
1746 // ldr $scratch, [$src, #4]
1749 unsigned SrcReg = MI->getOperand(0).getReg();
1750 unsigned ScratchReg = MI->getOperand(1).getReg();
1753 TmpInst.setOpcode(ARM::LDRi12);
1754 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1755 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1756 TmpInst.addOperand(MCOperand::CreateImm(8));
1758 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1759 TmpInst.addOperand(MCOperand::CreateReg(0));
1760 OutStreamer.EmitInstruction(TmpInst);
1764 TmpInst.setOpcode(ARM::LDRi12);
1765 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1766 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1767 TmpInst.addOperand(MCOperand::CreateImm(4));
1769 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1770 TmpInst.addOperand(MCOperand::CreateReg(0));
1771 OutStreamer.EmitInstruction(TmpInst);
1775 TmpInst.setOpcode(ARM::LDRi12);
1776 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1777 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1778 TmpInst.addOperand(MCOperand::CreateImm(0));
1780 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1781 TmpInst.addOperand(MCOperand::CreateReg(0));
1782 OutStreamer.EmitInstruction(TmpInst);
1786 TmpInst.setOpcode(ARM::BX);
1787 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1789 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1790 TmpInst.addOperand(MCOperand::CreateReg(0));
1791 OutStreamer.EmitInstruction(TmpInst);
1795 case ARM::tInt_eh_sjlj_longjmp: {
1796 // ldr $scratch, [$src, #8]
1798 // ldr $scratch, [$src, #4]
1801 unsigned SrcReg = MI->getOperand(0).getReg();
1802 unsigned ScratchReg = MI->getOperand(1).getReg();
1805 TmpInst.setOpcode(ARM::tLDRi);
1806 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1807 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1808 // The offset immediate is #8. The operand value is scaled by 4 for the
1809 // tLDR instruction.
1810 TmpInst.addOperand(MCOperand::CreateImm(2));
1812 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1813 TmpInst.addOperand(MCOperand::CreateReg(0));
1814 OutStreamer.EmitInstruction(TmpInst);
1818 TmpInst.setOpcode(ARM::tMOVr);
1819 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1820 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1822 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1823 TmpInst.addOperand(MCOperand::CreateReg(0));
1824 OutStreamer.EmitInstruction(TmpInst);
1828 TmpInst.setOpcode(ARM::tLDRi);
1829 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1830 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1831 TmpInst.addOperand(MCOperand::CreateImm(1));
1833 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1834 TmpInst.addOperand(MCOperand::CreateReg(0));
1835 OutStreamer.EmitInstruction(TmpInst);
1839 TmpInst.setOpcode(ARM::tLDRr);
1840 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1841 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1842 TmpInst.addOperand(MCOperand::CreateReg(0));
1844 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1845 TmpInst.addOperand(MCOperand::CreateReg(0));
1846 OutStreamer.EmitInstruction(TmpInst);
1850 TmpInst.setOpcode(ARM::tBX);
1851 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1853 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1854 TmpInst.addOperand(MCOperand::CreateReg(0));
1855 OutStreamer.EmitInstruction(TmpInst);
1862 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1864 // Emit unwinding stuff for frame-related instructions
1865 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1866 EmitUnwindingInstruction(MI);
1868 OutStreamer.EmitInstruction(TmpInst);
1871 //===----------------------------------------------------------------------===//
1872 // Target Registry Stuff
1873 //===----------------------------------------------------------------------===//
1875 // Force static initialization.
1876 extern "C" void LLVMInitializeARMAsmPrinter() {
1877 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1878 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);