1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionBodyEnd() {
287 // Make sure to terminate any constant pools that were at the end
291 InConstantPool = false;
292 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296 if (AFI->isThumbFunction()) {
297 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
298 OutStreamer.EmitThumbFunc(CurrentFnSym);
301 OutStreamer.EmitLabel(CurrentFnSym);
304 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306 assert(Size && "C++ constructor pointer had zero size!");
308 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
309 assert(GV && "C++ constructor pointer was not a GlobalValue!");
311 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312 (Subtarget->isTargetDarwin()
313 ? MCSymbolRefExpr::VK_None
314 : MCSymbolRefExpr::VK_ARM_TARGET1),
317 OutStreamer.EmitValue(E, Size);
320 /// runOnMachineFunction - This uses the EmitInstruction()
321 /// method to print assembly for each instruction.
323 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
324 AFI = MF.getInfo<ARMFunctionInfo>();
325 MCP = MF.getConstantPool();
327 return AsmPrinter::runOnMachineFunction(MF);
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
331 raw_ostream &O, const char *Modifier) {
332 const MachineOperand &MO = MI->getOperand(OpNum);
333 unsigned TF = MO.getTargetFlags();
335 switch (MO.getType()) {
336 default: llvm_unreachable("<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 assert(!MO.getSubReg() && "Subregs should be eliminated!");
341 O << ARMInstPrinter::getRegisterName(Reg);
344 case MachineOperand::MO_Immediate: {
345 int64_t Imm = MO.getImm();
347 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
348 (TF == ARMII::MO_LO16))
350 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
351 (TF == ARMII::MO_HI16))
356 case MachineOperand::MO_MachineBasicBlock:
357 O << *MO.getMBB()->getSymbol();
359 case MachineOperand::MO_GlobalAddress: {
360 const GlobalValue *GV = MO.getGlobal();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
367 O << *Mang->getSymbol(GV);
369 printOffset(MO.getOffset(), O);
370 if (TF == ARMII::MO_PLT)
374 case MachineOperand::MO_ExternalSymbol: {
375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
376 if (TF == ARMII::MO_PLT)
380 case MachineOperand::MO_ConstantPoolIndex:
381 O << *GetCPISymbol(MO.getIndex());
383 case MachineOperand::MO_JumpTableIndex:
384 O << *GetJTISymbol(MO.getIndex());
389 //===--------------------------------------------------------------------===//
391 MCSymbol *ARMAsmPrinter::
392 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393 const MachineBasicBlock *MBB) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
396 << getFunctionNumber() << '_' << uid << '_' << uid2
397 << "_set_" << MBB->getNumber();
398 return OutContext.GetOrCreateSymbol(Name.str());
401 MCSymbol *ARMAsmPrinter::
402 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403 SmallString<60> Name;
404 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
405 << getFunctionNumber() << '_' << uid << '_' << uid2;
406 return OutContext.GetOrCreateSymbol(Name.str());
410 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411 SmallString<60> Name;
412 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413 << getFunctionNumber();
414 return OutContext.GetOrCreateSymbol(Name.str());
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
418 unsigned AsmVariant, const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 default: return true; // Unknown modifier.
426 case 'a': // Print as a memory address.
427 if (MI->getOperand(OpNum).isReg()) {
429 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
434 case 'c': // Don't print "#" before an immediate operand.
435 if (!MI->getOperand(OpNum).isImm())
437 O << MI->getOperand(OpNum).getImm();
439 case 'P': // Print a VFP double precision register.
440 case 'q': // Print a NEON quad precision register.
441 printOperand(MI, OpNum, O);
443 case 'y': // Print a VFP single precision register as indexed double.
444 if (MI->getOperand(OpNum).isReg()) {
445 unsigned Reg = MI->getOperand(OpNum).getReg();
446 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
447 // Find the 'd' register that has this 's' register as a sub-register,
448 // and determine the lane number.
449 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
450 if (!ARM::DPRRegClass.contains(*SR))
452 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
453 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
458 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
459 if (!MI->getOperand(OpNum).isImm())
461 O << ~(MI->getOperand(OpNum).getImm());
463 case 'L': // The low 16 bits of an immediate constant.
464 if (!MI->getOperand(OpNum).isImm())
466 O << (MI->getOperand(OpNum).getImm() & 0xffff);
468 case 'M': { // A register range suitable for LDM/STM.
469 if (!MI->getOperand(OpNum).isReg())
471 const MachineOperand &MO = MI->getOperand(OpNum);
472 unsigned RegBegin = MO.getReg();
473 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
474 // already got the operands in registers that are operands to the
475 // inline asm statement.
477 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
479 // FIXME: The register allocator not only may not have given us the
480 // registers in sequence, but may not be in ascending registers. This
481 // will require changes in the register allocator that'll need to be
482 // propagated down here if the operands change.
483 unsigned RegOps = OpNum + 1;
484 while (MI->getOperand(RegOps).isReg()) {
486 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
494 case 'R': // The most significant register of a pair.
495 case 'Q': { // The least significant register of a pair.
498 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
499 if (!FlagsOP.isImm())
501 unsigned Flags = FlagsOP.getImm();
502 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
505 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
506 if (RegOp >= MI->getNumOperands())
508 const MachineOperand &MO = MI->getOperand(RegOp);
511 unsigned Reg = MO.getReg();
512 O << ARMInstPrinter::getRegisterName(Reg);
516 case 'e': // The low doubleword register of a NEON quad register.
517 case 'f': { // The high doubleword register of a NEON quad register.
518 if (!MI->getOperand(OpNum).isReg())
520 unsigned Reg = MI->getOperand(OpNum).getReg();
521 if (!ARM::QPRRegClass.contains(Reg))
523 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
524 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
525 ARM::dsub_0 : ARM::dsub_1);
526 O << ARMInstPrinter::getRegisterName(SubReg);
530 // These modifiers are not yet supported.
531 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
532 case 'H': // The highest-numbered register of a pair.
537 printOperand(MI, OpNum, O);
541 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
542 unsigned OpNum, unsigned AsmVariant,
543 const char *ExtraCode,
545 // Does this asm operand have a single letter operand modifier?
546 if (ExtraCode && ExtraCode[0]) {
547 if (ExtraCode[1] != 0) return true; // Unknown modifier.
549 switch (ExtraCode[0]) {
550 case 'A': // A memory operand for a VLD1/VST1 instruction.
551 default: return true; // Unknown modifier.
552 case 'm': // The base register of a memory operand.
553 if (!MI->getOperand(OpNum).isReg())
555 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
560 const MachineOperand &MO = MI->getOperand(OpNum);
561 assert(MO.isReg() && "unexpected inline asm memory operand");
562 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
566 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
567 if (Subtarget->isTargetDarwin()) {
568 Reloc::Model RelocM = TM.getRelocationModel();
569 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
570 // Declare all the text sections up front (before the DWARF sections
571 // emitted by AsmPrinter::doInitialization) so the assembler will keep
572 // them together at the beginning of the object file. This helps
573 // avoid out-of-range branches that are due a fundamental limitation of
574 // the way symbol offsets are encoded with the current Darwin ARM
576 const TargetLoweringObjectFileMachO &TLOFMacho =
577 static_cast<const TargetLoweringObjectFileMachO &>(
578 getObjFileLowering());
579 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
580 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
581 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
582 if (RelocM == Reloc::DynamicNoPIC) {
583 const MCSection *sect =
584 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
585 MCSectionMachO::S_SYMBOL_STUBS,
586 12, SectionKind::getText());
587 OutStreamer.SwitchSection(sect);
589 const MCSection *sect =
590 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
591 MCSectionMachO::S_SYMBOL_STUBS,
592 16, SectionKind::getText());
593 OutStreamer.SwitchSection(sect);
595 const MCSection *StaticInitSect =
596 OutContext.getMachOSection("__TEXT", "__StaticInit",
597 MCSectionMachO::S_REGULAR |
598 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
599 SectionKind::getText());
600 OutStreamer.SwitchSection(StaticInitSect);
604 // Use unified assembler syntax.
605 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
607 // Emit ARM Build Attributes
608 if (Subtarget->isTargetELF())
613 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
614 if (Subtarget->isTargetDarwin()) {
615 // All darwin targets use mach-o.
616 const TargetLoweringObjectFileMachO &TLOFMacho =
617 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
618 MachineModuleInfoMachO &MMIMacho =
619 MMI->getObjFileInfo<MachineModuleInfoMachO>();
621 // Output non-lazy-pointers for external and common global variables.
622 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
624 if (!Stubs.empty()) {
625 // Switch with ".non_lazy_symbol_pointer" directive.
626 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
628 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
630 OutStreamer.EmitLabel(Stubs[i].first);
631 // .indirect_symbol _foo
632 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
633 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
636 // External to current translation unit.
637 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
639 // Internal to current translation unit.
641 // When we place the LSDA into the TEXT section, the type info
642 // pointers need to be indirect and pc-rel. We accomplish this by
643 // using NLPs; however, sometimes the types are local to the file.
644 // We need to fill in the value for the NLP in those cases.
645 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
647 4/*size*/, 0/*addrspace*/);
651 OutStreamer.AddBlankLine();
654 Stubs = MMIMacho.GetHiddenGVStubList();
655 if (!Stubs.empty()) {
656 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
658 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
660 OutStreamer.EmitLabel(Stubs[i].first);
662 OutStreamer.EmitValue(MCSymbolRefExpr::
663 Create(Stubs[i].second.getPointer(),
665 4/*size*/, 0/*addrspace*/);
669 OutStreamer.AddBlankLine();
672 // Funny Darwin hack: This flag tells the linker that no global symbols
673 // contain code that falls through to other global symbols (e.g. the obvious
674 // implementation of multiple entry points). If this doesn't occur, the
675 // linker can safely perform dead code stripping. Since LLVM never
676 // generates code that does this, it is always safe to set.
677 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
681 //===----------------------------------------------------------------------===//
682 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
684 // The following seem like one-off assembler flags, but they actually need
685 // to appear in the .ARM.attributes section in ELF.
686 // Instead of subclassing the MCELFStreamer, we do the work here.
688 void ARMAsmPrinter::emitAttributes() {
690 emitARMAttributeSection();
692 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
693 bool emitFPU = false;
694 AttributeEmitter *AttrEmitter;
695 if (OutStreamer.hasRawTextSupport()) {
696 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
699 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
700 AttrEmitter = new ObjectAttributeEmitter(O);
703 AttrEmitter->MaybeSwitchVendor("aeabi");
705 std::string CPUString = Subtarget->getCPUString();
707 if (CPUString == "cortex-a8" ||
708 Subtarget->isCortexA8()) {
709 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
710 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
711 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
712 ARMBuildAttrs::ApplicationProfile);
713 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
714 ARMBuildAttrs::Allowed);
715 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
716 ARMBuildAttrs::AllowThumb32);
717 // Fixme: figure out when this is emitted.
718 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
719 // ARMBuildAttrs::AllowWMMXv1);
722 /// ADD additional Else-cases here!
723 } else if (CPUString == "xscale") {
724 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
725 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
726 ARMBuildAttrs::Allowed);
727 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
728 ARMBuildAttrs::Allowed);
729 } else if (CPUString == "generic") {
730 // FIXME: Why these defaults?
731 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
732 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
733 ARMBuildAttrs::Allowed);
734 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
735 ARMBuildAttrs::Allowed);
738 if (Subtarget->hasNEON() && emitFPU) {
739 /* NEON is not exactly a VFP architecture, but GAS emit one of
740 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
741 if (Subtarget->hasVFP4())
742 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
745 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
746 /* If emitted for NEON, omit from VFP below, since you can have both
747 * NEON and VFP in build attributes but only one .fpu */
752 if (Subtarget->hasVFP4()) {
753 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
754 ARMBuildAttrs::AllowFPv4A);
756 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
759 } else if (Subtarget->hasVFP3()) {
760 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
761 ARMBuildAttrs::AllowFPv3A);
763 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
766 } else if (Subtarget->hasVFP2()) {
767 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
768 ARMBuildAttrs::AllowFPv2);
770 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
773 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
774 * since NEON can have 1 (allowed) or 2 (MAC operations) */
775 if (Subtarget->hasNEON()) {
776 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
777 ARMBuildAttrs::Allowed);
780 // Signal various FP modes.
781 if (!TM.Options.UnsafeFPMath) {
782 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
783 ARMBuildAttrs::Allowed);
784 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
785 ARMBuildAttrs::Allowed);
788 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
789 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
790 ARMBuildAttrs::Allowed);
792 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
793 ARMBuildAttrs::AllowIEE754);
795 // FIXME: add more flags to ARMBuildAttrs.h
796 // 8-bytes alignment stuff.
797 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
798 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
800 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
801 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
802 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
803 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
805 // FIXME: Should we signal R9 usage?
807 if (Subtarget->hasDivide())
808 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
810 AttrEmitter->Finish();
814 void ARMAsmPrinter::emitARMAttributeSection() {
816 // [ <section-length> "vendor-name"
817 // [ <file-tag> <size> <attribute>*
818 // | <section-tag> <size> <section-number>* 0 <attribute>*
819 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
823 if (OutStreamer.hasRawTextSupport())
826 const ARMElfTargetObjectFile &TLOFELF =
827 static_cast<const ARMElfTargetObjectFile &>
828 (getObjFileLowering());
830 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
833 OutStreamer.EmitIntValue(0x41, 1);
836 //===----------------------------------------------------------------------===//
838 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
839 unsigned LabelId, MCContext &Ctx) {
841 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
842 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
846 static MCSymbolRefExpr::VariantKind
847 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
849 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
850 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
851 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
852 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
853 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
854 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
856 llvm_unreachable("Invalid ARMCPModifier!");
859 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
860 bool isIndirect = Subtarget->isTargetDarwin() &&
861 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
863 return Mang->getSymbol(GV);
865 // FIXME: Remove this when Darwin transition to @GOT like syntax.
866 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
867 MachineModuleInfoMachO &MMIMachO =
868 MMI->getObjFileInfo<MachineModuleInfoMachO>();
869 MachineModuleInfoImpl::StubValueTy &StubSym =
870 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
871 MMIMachO.getGVStubEntry(MCSym);
872 if (StubSym.getPointer() == 0)
873 StubSym = MachineModuleInfoImpl::
874 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
879 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
880 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
882 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
885 if (ACPV->isLSDA()) {
886 SmallString<128> Str;
887 raw_svector_ostream OS(Str);
888 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
889 MCSym = OutContext.GetOrCreateSymbol(OS.str());
890 } else if (ACPV->isBlockAddress()) {
891 const BlockAddress *BA =
892 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
893 MCSym = GetBlockAddressSymbol(BA);
894 } else if (ACPV->isGlobalValue()) {
895 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
896 MCSym = GetARMGVSymbol(GV);
897 } else if (ACPV->isMachineBasicBlock()) {
898 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
899 MCSym = MBB->getSymbol();
901 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
902 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
903 MCSym = GetExternalSymbolSymbol(Sym);
906 // Create an MCSymbol for the reference.
908 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
911 if (ACPV->getPCAdjustment()) {
912 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
916 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
918 MCBinaryExpr::CreateAdd(PCRelExpr,
919 MCConstantExpr::Create(ACPV->getPCAdjustment(),
922 if (ACPV->mustAddCurrentAddress()) {
923 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
924 // label, so just emit a local label end reference that instead.
925 MCSymbol *DotSym = OutContext.CreateTempSymbol();
926 OutStreamer.EmitLabel(DotSym);
927 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
928 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
930 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
932 OutStreamer.EmitValue(Expr, Size);
935 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
936 unsigned Opcode = MI->getOpcode();
938 if (Opcode == ARM::BR_JTadd)
940 else if (Opcode == ARM::BR_JTm)
943 const MachineOperand &MO1 = MI->getOperand(OpNum);
944 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
945 unsigned JTI = MO1.getIndex();
947 // Emit a label for the jump table.
948 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
949 OutStreamer.EmitLabel(JTISymbol);
951 // Mark the jump table as data-in-code.
952 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
954 // Emit each entry of the table.
955 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
956 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
957 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
959 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
960 MachineBasicBlock *MBB = JTBBs[i];
961 // Construct an MCExpr for the entry. We want a value of the form:
962 // (BasicBlockAddr - TableBeginAddr)
964 // For example, a table with entries jumping to basic blocks BB0 and BB1
967 // .word (LBB0 - LJTI_0_0)
968 // .word (LBB1 - LJTI_0_0)
969 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
971 if (TM.getRelocationModel() == Reloc::PIC_)
972 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
975 // If we're generating a table of Thumb addresses in static relocation
976 // model, we need to add one to keep interworking correctly.
977 else if (AFI->isThumbFunction())
978 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
980 OutStreamer.EmitValue(Expr, 4);
982 // Mark the end of jump table data-in-code region.
983 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
986 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
987 unsigned Opcode = MI->getOpcode();
988 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
989 const MachineOperand &MO1 = MI->getOperand(OpNum);
990 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
991 unsigned JTI = MO1.getIndex();
993 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
994 OutStreamer.EmitLabel(JTISymbol);
996 // Emit each entry of the table.
997 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
998 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
999 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1000 unsigned OffsetWidth = 4;
1001 if (MI->getOpcode() == ARM::t2TBB_JT) {
1003 // Mark the jump table as data-in-code.
1004 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1005 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1007 // Mark the jump table as data-in-code.
1008 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1011 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1012 MachineBasicBlock *MBB = JTBBs[i];
1013 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1015 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1016 if (OffsetWidth == 4) {
1018 BrInst.setOpcode(ARM::t2B);
1019 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1020 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1021 BrInst.addOperand(MCOperand::CreateReg(0));
1022 OutStreamer.EmitInstruction(BrInst);
1025 // Otherwise it's an offset from the dispatch instruction. Construct an
1026 // MCExpr for the entry. We want a value of the form:
1027 // (BasicBlockAddr - TableBeginAddr) / 2
1029 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1032 // .byte (LBB0 - LJTI_0_0) / 2
1033 // .byte (LBB1 - LJTI_0_0) / 2
1034 const MCExpr *Expr =
1035 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1036 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1038 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1040 OutStreamer.EmitValue(Expr, OffsetWidth);
1042 // Mark the end of jump table data-in-code region. 32-bit offsets use
1043 // actual branch instructions here, so we don't mark those as a data-region
1045 if (OffsetWidth != 4)
1046 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1049 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1051 unsigned NOps = MI->getNumOperands();
1053 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1054 // cast away const; DIetc do not take const operands for some reason.
1055 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1058 // Frame address. Currently handles register +- offset only.
1059 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1060 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1063 printOperand(MI, NOps-2, OS);
1066 static void populateADROperands(MCInst &Inst, unsigned Dest,
1067 const MCSymbol *Label,
1068 unsigned pred, unsigned ccreg,
1070 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1071 Inst.addOperand(MCOperand::CreateReg(Dest));
1072 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1073 // Add predicate operands.
1074 Inst.addOperand(MCOperand::CreateImm(pred));
1075 Inst.addOperand(MCOperand::CreateReg(ccreg));
1078 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1082 // Emit the instruction as usual, just patch the opcode.
1083 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1084 TmpInst.setOpcode(Opcode);
1085 OutStreamer.EmitInstruction(TmpInst);
1088 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1089 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1090 "Only instruction which are involved into frame setup code are allowed");
1092 const MachineFunction &MF = *MI->getParent()->getParent();
1093 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1094 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1096 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1097 unsigned Opc = MI->getOpcode();
1098 unsigned SrcReg, DstReg;
1100 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1101 // Two special cases:
1102 // 1) tPUSH does not have src/dst regs.
1103 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1104 // load. Yes, this is pretty fragile, but for now I don't see better
1106 SrcReg = DstReg = ARM::SP;
1108 SrcReg = MI->getOperand(1).getReg();
1109 DstReg = MI->getOperand(0).getReg();
1112 // Try to figure out the unwinding opcode out of src / dst regs.
1113 if (MI->mayStore()) {
1115 assert(DstReg == ARM::SP &&
1116 "Only stack pointer as a destination reg is supported");
1118 SmallVector<unsigned, 4> RegList;
1119 // Skip src & dst reg, and pred ops.
1120 unsigned StartOp = 2 + 2;
1121 // Use all the operands.
1122 unsigned NumOffset = 0;
1127 llvm_unreachable("Unsupported opcode for unwinding information");
1129 // Special case here: no src & dst reg, but two extra imp ops.
1130 StartOp = 2; NumOffset = 2;
1131 case ARM::STMDB_UPD:
1132 case ARM::t2STMDB_UPD:
1133 case ARM::VSTMDDB_UPD:
1134 assert(SrcReg == ARM::SP &&
1135 "Only stack pointer as a source reg is supported");
1136 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1138 RegList.push_back(MI->getOperand(i).getReg());
1140 case ARM::STR_PRE_IMM:
1141 case ARM::STR_PRE_REG:
1142 case ARM::t2STR_PRE:
1143 assert(MI->getOperand(2).getReg() == ARM::SP &&
1144 "Only stack pointer as a source reg is supported");
1145 RegList.push_back(SrcReg);
1148 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1150 // Changes of stack / frame pointer.
1151 if (SrcReg == ARM::SP) {
1156 llvm_unreachable("Unsupported opcode for unwinding information");
1162 Offset = -MI->getOperand(2).getImm();
1166 Offset = MI->getOperand(2).getImm();
1169 Offset = MI->getOperand(2).getImm()*4;
1173 Offset = -MI->getOperand(2).getImm()*4;
1175 case ARM::tLDRpci: {
1176 // Grab the constpool index and check, whether it corresponds to
1177 // original or cloned constpool entry.
1178 unsigned CPI = MI->getOperand(1).getIndex();
1179 const MachineConstantPool *MCP = MF.getConstantPool();
1180 if (CPI >= MCP->getConstants().size())
1181 CPI = AFI.getOriginalCPIdx(CPI);
1182 assert(CPI != -1U && "Invalid constpool index");
1184 // Derive the actual offset.
1185 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1186 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1187 // FIXME: Check for user, it should be "add" instruction!
1188 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1193 if (DstReg == FramePtr && FramePtr != ARM::SP)
1194 // Set-up of the frame pointer. Positive values correspond to "add"
1196 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1197 else if (DstReg == ARM::SP) {
1198 // Change of SP by an offset. Positive values correspond to "sub"
1200 OutStreamer.EmitPad(Offset);
1203 llvm_unreachable("Unsupported opcode for unwinding information");
1205 } else if (DstReg == ARM::SP) {
1206 // FIXME: .movsp goes here
1208 llvm_unreachable("Unsupported opcode for unwinding information");
1212 llvm_unreachable("Unsupported opcode for unwinding information");
1217 extern cl::opt<bool> EnableARMEHABI;
1219 // Simple pseudo-instructions have their lowering (with expansion to real
1220 // instructions) auto-generated.
1221 #include "ARMGenMCPseudoLowering.inc"
1223 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1224 // If we just ended a constant pool, mark it as such.
1225 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1226 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1227 InConstantPool = false;
1230 // Emit unwinding stuff for frame-related instructions
1231 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1232 EmitUnwindingInstruction(MI);
1234 // Do any auto-generated pseudo lowerings.
1235 if (emitPseudoExpansionLowering(OutStreamer, MI))
1238 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1239 "Pseudo flag setting opcode should be expanded early");
1241 // Check for manual lowerings.
1242 unsigned Opc = MI->getOpcode();
1244 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1245 case ARM::DBG_VALUE: {
1246 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1247 SmallString<128> TmpStr;
1248 raw_svector_ostream OS(TmpStr);
1249 PrintDebugValueComment(MI, OS);
1250 OutStreamer.EmitRawText(StringRef(OS.str()));
1255 case ARM::tLEApcrel:
1256 case ARM::t2LEApcrel: {
1257 // FIXME: Need to also handle globals and externals
1259 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1260 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1262 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1263 GetCPISymbol(MI->getOperand(1).getIndex()),
1264 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1266 OutStreamer.EmitInstruction(TmpInst);
1269 case ARM::LEApcrelJT:
1270 case ARM::tLEApcrelJT:
1271 case ARM::t2LEApcrelJT: {
1273 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1274 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1276 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1277 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1278 MI->getOperand(2).getImm()),
1279 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1281 OutStreamer.EmitInstruction(TmpInst);
1284 // Darwin call instructions are just normal call instructions with different
1285 // clobber semantics (they clobber R9).
1286 case ARM::BX_CALL: {
1289 TmpInst.setOpcode(ARM::MOVr);
1290 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1291 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1292 // Add predicate operands.
1293 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1294 TmpInst.addOperand(MCOperand::CreateReg(0));
1295 // Add 's' bit operand (always reg0 for this)
1296 TmpInst.addOperand(MCOperand::CreateReg(0));
1297 OutStreamer.EmitInstruction(TmpInst);
1301 TmpInst.setOpcode(ARM::BX);
1302 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1303 OutStreamer.EmitInstruction(TmpInst);
1307 case ARM::tBX_CALL: {
1310 TmpInst.setOpcode(ARM::tMOVr);
1311 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1312 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1313 // Add predicate operands.
1314 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1315 TmpInst.addOperand(MCOperand::CreateReg(0));
1316 OutStreamer.EmitInstruction(TmpInst);
1320 TmpInst.setOpcode(ARM::tBX);
1321 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1322 // Add predicate operands.
1323 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1324 TmpInst.addOperand(MCOperand::CreateReg(0));
1325 OutStreamer.EmitInstruction(TmpInst);
1329 case ARM::BMOVPCRX_CALL: {
1332 TmpInst.setOpcode(ARM::MOVr);
1333 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1334 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1335 // Add predicate operands.
1336 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1337 TmpInst.addOperand(MCOperand::CreateReg(0));
1338 // Add 's' bit operand (always reg0 for this)
1339 TmpInst.addOperand(MCOperand::CreateReg(0));
1340 OutStreamer.EmitInstruction(TmpInst);
1344 TmpInst.setOpcode(ARM::MOVr);
1345 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1346 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1347 // Add predicate operands.
1348 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1349 TmpInst.addOperand(MCOperand::CreateReg(0));
1350 // Add 's' bit operand (always reg0 for this)
1351 TmpInst.addOperand(MCOperand::CreateReg(0));
1352 OutStreamer.EmitInstruction(TmpInst);
1356 case ARM::BMOVPCB_CALL: {
1359 TmpInst.setOpcode(ARM::MOVr);
1360 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1361 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1362 // Add predicate operands.
1363 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1364 TmpInst.addOperand(MCOperand::CreateReg(0));
1365 // Add 's' bit operand (always reg0 for this)
1366 TmpInst.addOperand(MCOperand::CreateReg(0));
1367 OutStreamer.EmitInstruction(TmpInst);
1371 TmpInst.setOpcode(ARM::Bcc);
1372 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1373 MCSymbol *GVSym = Mang->getSymbol(GV);
1374 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1375 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1376 // Add predicate operands.
1377 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1378 TmpInst.addOperand(MCOperand::CreateReg(0));
1379 OutStreamer.EmitInstruction(TmpInst);
1383 case ARM::t2BMOVPCB_CALL: {
1386 TmpInst.setOpcode(ARM::tMOVr);
1387 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1388 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1389 // Add predicate operands.
1390 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1391 TmpInst.addOperand(MCOperand::CreateReg(0));
1392 OutStreamer.EmitInstruction(TmpInst);
1396 TmpInst.setOpcode(ARM::t2B);
1397 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1398 MCSymbol *GVSym = Mang->getSymbol(GV);
1399 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1400 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1401 // Add predicate operands.
1402 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1403 TmpInst.addOperand(MCOperand::CreateReg(0));
1404 OutStreamer.EmitInstruction(TmpInst);
1408 case ARM::MOVi16_ga_pcrel:
1409 case ARM::t2MOVi16_ga_pcrel: {
1411 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1412 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1414 unsigned TF = MI->getOperand(1).getTargetFlags();
1415 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1416 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1417 MCSymbol *GVSym = GetARMGVSymbol(GV);
1418 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1420 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1421 getFunctionNumber(),
1422 MI->getOperand(2).getImm(), OutContext);
1423 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1424 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1425 const MCExpr *PCRelExpr =
1426 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1427 MCBinaryExpr::CreateAdd(LabelSymExpr,
1428 MCConstantExpr::Create(PCAdj, OutContext),
1429 OutContext), OutContext), OutContext);
1430 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1432 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1433 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1436 // Add predicate operands.
1437 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1438 TmpInst.addOperand(MCOperand::CreateReg(0));
1439 // Add 's' bit operand (always reg0 for this)
1440 TmpInst.addOperand(MCOperand::CreateReg(0));
1441 OutStreamer.EmitInstruction(TmpInst);
1444 case ARM::MOVTi16_ga_pcrel:
1445 case ARM::t2MOVTi16_ga_pcrel: {
1447 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1448 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1449 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1450 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1452 unsigned TF = MI->getOperand(2).getTargetFlags();
1453 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1454 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1455 MCSymbol *GVSym = GetARMGVSymbol(GV);
1456 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1458 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1459 getFunctionNumber(),
1460 MI->getOperand(3).getImm(), OutContext);
1461 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1462 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1463 const MCExpr *PCRelExpr =
1464 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1465 MCBinaryExpr::CreateAdd(LabelSymExpr,
1466 MCConstantExpr::Create(PCAdj, OutContext),
1467 OutContext), OutContext), OutContext);
1468 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1470 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1471 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1473 // Add predicate operands.
1474 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1475 TmpInst.addOperand(MCOperand::CreateReg(0));
1476 // Add 's' bit operand (always reg0 for this)
1477 TmpInst.addOperand(MCOperand::CreateReg(0));
1478 OutStreamer.EmitInstruction(TmpInst);
1481 case ARM::tPICADD: {
1482 // This is a pseudo op for a label + instruction sequence, which looks like:
1485 // This adds the address of LPC0 to r0.
1488 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1489 getFunctionNumber(), MI->getOperand(2).getImm(),
1492 // Form and emit the add.
1494 AddInst.setOpcode(ARM::tADDhirr);
1495 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1496 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1497 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1498 // Add predicate operands.
1499 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1500 AddInst.addOperand(MCOperand::CreateReg(0));
1501 OutStreamer.EmitInstruction(AddInst);
1505 // This is a pseudo op for a label + instruction sequence, which looks like:
1508 // This adds the address of LPC0 to r0.
1511 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1512 getFunctionNumber(), MI->getOperand(2).getImm(),
1515 // Form and emit the add.
1517 AddInst.setOpcode(ARM::ADDrr);
1518 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1519 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1520 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1521 // Add predicate operands.
1522 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1523 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1524 // Add 's' bit operand (always reg0 for this)
1525 AddInst.addOperand(MCOperand::CreateReg(0));
1526 OutStreamer.EmitInstruction(AddInst);
1536 case ARM::PICLDRSH: {
1537 // This is a pseudo op for a label + instruction sequence, which looks like:
1540 // The LCP0 label is referenced by a constant pool entry in order to get
1541 // a PC-relative address at the ldr instruction.
1544 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1545 getFunctionNumber(), MI->getOperand(2).getImm(),
1548 // Form and emit the load
1550 switch (MI->getOpcode()) {
1552 llvm_unreachable("Unexpected opcode!");
1553 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1554 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1555 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1556 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1557 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1558 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1559 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1560 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1563 LdStInst.setOpcode(Opcode);
1564 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1565 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1566 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1567 LdStInst.addOperand(MCOperand::CreateImm(0));
1568 // Add predicate operands.
1569 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1570 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1571 OutStreamer.EmitInstruction(LdStInst);
1575 case ARM::CONSTPOOL_ENTRY: {
1576 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1577 /// in the function. The first operand is the ID# for this instruction, the
1578 /// second is the index into the MachineConstantPool that this is, the third
1579 /// is the size in bytes of this constant pool entry.
1580 /// The required alignment is specified on the basic block holding this MI.
1581 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1582 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1584 // If this is the first entry of the pool, mark it.
1585 if (!InConstantPool) {
1586 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1587 InConstantPool = true;
1590 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1592 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1593 if (MCPE.isMachineConstantPoolEntry())
1594 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1596 EmitGlobalConstant(MCPE.Val.ConstVal);
1599 case ARM::t2BR_JT: {
1600 // Lower and emit the instruction itself, then the jump table following it.
1602 TmpInst.setOpcode(ARM::tMOVr);
1603 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1604 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1605 // Add predicate operands.
1606 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1607 TmpInst.addOperand(MCOperand::CreateReg(0));
1608 OutStreamer.EmitInstruction(TmpInst);
1609 // Output the data for the jump table itself
1613 case ARM::t2TBB_JT: {
1614 // Lower and emit the instruction itself, then the jump table following it.
1617 TmpInst.setOpcode(ARM::t2TBB);
1618 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1619 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1620 // Add predicate operands.
1621 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1622 TmpInst.addOperand(MCOperand::CreateReg(0));
1623 OutStreamer.EmitInstruction(TmpInst);
1624 // Output the data for the jump table itself
1626 // Make sure the next instruction is 2-byte aligned.
1630 case ARM::t2TBH_JT: {
1631 // Lower and emit the instruction itself, then the jump table following it.
1634 TmpInst.setOpcode(ARM::t2TBH);
1635 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1636 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1637 // Add predicate operands.
1638 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1639 TmpInst.addOperand(MCOperand::CreateReg(0));
1640 OutStreamer.EmitInstruction(TmpInst);
1641 // Output the data for the jump table itself
1647 // Lower and emit the instruction itself, then the jump table following it.
1650 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1651 ARM::MOVr : ARM::tMOVr;
1652 TmpInst.setOpcode(Opc);
1653 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1654 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1655 // Add predicate operands.
1656 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1657 TmpInst.addOperand(MCOperand::CreateReg(0));
1658 // Add 's' bit operand (always reg0 for this)
1659 if (Opc == ARM::MOVr)
1660 TmpInst.addOperand(MCOperand::CreateReg(0));
1661 OutStreamer.EmitInstruction(TmpInst);
1663 // Make sure the Thumb jump table is 4-byte aligned.
1664 if (Opc == ARM::tMOVr)
1667 // Output the data for the jump table itself
1672 // Lower and emit the instruction itself, then the jump table following it.
1675 if (MI->getOperand(1).getReg() == 0) {
1677 TmpInst.setOpcode(ARM::LDRi12);
1678 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1679 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1680 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1682 TmpInst.setOpcode(ARM::LDRrs);
1683 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1684 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1685 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1686 TmpInst.addOperand(MCOperand::CreateImm(0));
1688 // Add predicate operands.
1689 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1690 TmpInst.addOperand(MCOperand::CreateReg(0));
1691 OutStreamer.EmitInstruction(TmpInst);
1693 // Output the data for the jump table itself
1697 case ARM::BR_JTadd: {
1698 // Lower and emit the instruction itself, then the jump table following it.
1699 // add pc, target, idx
1701 TmpInst.setOpcode(ARM::ADDrr);
1702 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1703 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1704 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1705 // Add predicate operands.
1706 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1707 TmpInst.addOperand(MCOperand::CreateReg(0));
1708 // Add 's' bit operand (always reg0 for this)
1709 TmpInst.addOperand(MCOperand::CreateReg(0));
1710 OutStreamer.EmitInstruction(TmpInst);
1712 // Output the data for the jump table itself
1717 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1718 // FIXME: Remove this special case when they do.
1719 if (!Subtarget->isTargetDarwin()) {
1720 //.long 0xe7ffdefe @ trap
1721 uint32_t Val = 0xe7ffdefeUL;
1722 OutStreamer.AddComment("trap");
1723 OutStreamer.EmitIntValue(Val, 4);
1729 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1730 // FIXME: Remove this special case when they do.
1731 if (!Subtarget->isTargetDarwin()) {
1732 //.short 57086 @ trap
1733 uint16_t Val = 0xdefe;
1734 OutStreamer.AddComment("trap");
1735 OutStreamer.EmitIntValue(Val, 2);
1740 case ARM::t2Int_eh_sjlj_setjmp:
1741 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1742 case ARM::tInt_eh_sjlj_setjmp: {
1743 // Two incoming args: GPR:$src, GPR:$val
1746 // str $val, [$src, #4]
1751 unsigned SrcReg = MI->getOperand(0).getReg();
1752 unsigned ValReg = MI->getOperand(1).getReg();
1753 MCSymbol *Label = GetARMSJLJEHLabel();
1756 TmpInst.setOpcode(ARM::tMOVr);
1757 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1758 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1760 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1761 TmpInst.addOperand(MCOperand::CreateReg(0));
1762 OutStreamer.AddComment("eh_setjmp begin");
1763 OutStreamer.EmitInstruction(TmpInst);
1767 TmpInst.setOpcode(ARM::tADDi3);
1768 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1770 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1771 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1772 TmpInst.addOperand(MCOperand::CreateImm(7));
1774 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1775 TmpInst.addOperand(MCOperand::CreateReg(0));
1776 OutStreamer.EmitInstruction(TmpInst);
1780 TmpInst.setOpcode(ARM::tSTRi);
1781 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1782 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1783 // The offset immediate is #4. The operand value is scaled by 4 for the
1784 // tSTR instruction.
1785 TmpInst.addOperand(MCOperand::CreateImm(1));
1787 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1788 TmpInst.addOperand(MCOperand::CreateReg(0));
1789 OutStreamer.EmitInstruction(TmpInst);
1793 TmpInst.setOpcode(ARM::tMOVi8);
1794 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1795 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1796 TmpInst.addOperand(MCOperand::CreateImm(0));
1798 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1799 TmpInst.addOperand(MCOperand::CreateReg(0));
1800 OutStreamer.EmitInstruction(TmpInst);
1803 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1805 TmpInst.setOpcode(ARM::tB);
1806 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1807 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1808 TmpInst.addOperand(MCOperand::CreateReg(0));
1809 OutStreamer.EmitInstruction(TmpInst);
1813 TmpInst.setOpcode(ARM::tMOVi8);
1814 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1815 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1816 TmpInst.addOperand(MCOperand::CreateImm(1));
1818 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1819 TmpInst.addOperand(MCOperand::CreateReg(0));
1820 OutStreamer.AddComment("eh_setjmp end");
1821 OutStreamer.EmitInstruction(TmpInst);
1823 OutStreamer.EmitLabel(Label);
1827 case ARM::Int_eh_sjlj_setjmp_nofp:
1828 case ARM::Int_eh_sjlj_setjmp: {
1829 // Two incoming args: GPR:$src, GPR:$val
1831 // str $val, [$src, #+4]
1835 unsigned SrcReg = MI->getOperand(0).getReg();
1836 unsigned ValReg = MI->getOperand(1).getReg();
1840 TmpInst.setOpcode(ARM::ADDri);
1841 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1842 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1843 TmpInst.addOperand(MCOperand::CreateImm(8));
1845 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1846 TmpInst.addOperand(MCOperand::CreateReg(0));
1847 // 's' bit operand (always reg0 for this).
1848 TmpInst.addOperand(MCOperand::CreateReg(0));
1849 OutStreamer.AddComment("eh_setjmp begin");
1850 OutStreamer.EmitInstruction(TmpInst);
1854 TmpInst.setOpcode(ARM::STRi12);
1855 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1856 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1857 TmpInst.addOperand(MCOperand::CreateImm(4));
1859 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1860 TmpInst.addOperand(MCOperand::CreateReg(0));
1861 OutStreamer.EmitInstruction(TmpInst);
1865 TmpInst.setOpcode(ARM::MOVi);
1866 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1867 TmpInst.addOperand(MCOperand::CreateImm(0));
1869 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1870 TmpInst.addOperand(MCOperand::CreateReg(0));
1871 // 's' bit operand (always reg0 for this).
1872 TmpInst.addOperand(MCOperand::CreateReg(0));
1873 OutStreamer.EmitInstruction(TmpInst);
1877 TmpInst.setOpcode(ARM::ADDri);
1878 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1879 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1880 TmpInst.addOperand(MCOperand::CreateImm(0));
1882 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1883 TmpInst.addOperand(MCOperand::CreateReg(0));
1884 // 's' bit operand (always reg0 for this).
1885 TmpInst.addOperand(MCOperand::CreateReg(0));
1886 OutStreamer.EmitInstruction(TmpInst);
1890 TmpInst.setOpcode(ARM::MOVi);
1891 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1892 TmpInst.addOperand(MCOperand::CreateImm(1));
1894 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1895 TmpInst.addOperand(MCOperand::CreateReg(0));
1896 // 's' bit operand (always reg0 for this).
1897 TmpInst.addOperand(MCOperand::CreateReg(0));
1898 OutStreamer.AddComment("eh_setjmp end");
1899 OutStreamer.EmitInstruction(TmpInst);
1903 case ARM::Int_eh_sjlj_longjmp: {
1904 // ldr sp, [$src, #8]
1905 // ldr $scratch, [$src, #4]
1908 unsigned SrcReg = MI->getOperand(0).getReg();
1909 unsigned ScratchReg = MI->getOperand(1).getReg();
1912 TmpInst.setOpcode(ARM::LDRi12);
1913 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1914 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1915 TmpInst.addOperand(MCOperand::CreateImm(8));
1917 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1918 TmpInst.addOperand(MCOperand::CreateReg(0));
1919 OutStreamer.EmitInstruction(TmpInst);
1923 TmpInst.setOpcode(ARM::LDRi12);
1924 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1925 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1926 TmpInst.addOperand(MCOperand::CreateImm(4));
1928 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1929 TmpInst.addOperand(MCOperand::CreateReg(0));
1930 OutStreamer.EmitInstruction(TmpInst);
1934 TmpInst.setOpcode(ARM::LDRi12);
1935 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1936 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1937 TmpInst.addOperand(MCOperand::CreateImm(0));
1939 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1940 TmpInst.addOperand(MCOperand::CreateReg(0));
1941 OutStreamer.EmitInstruction(TmpInst);
1945 TmpInst.setOpcode(ARM::BX);
1946 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1948 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1949 TmpInst.addOperand(MCOperand::CreateReg(0));
1950 OutStreamer.EmitInstruction(TmpInst);
1954 case ARM::tInt_eh_sjlj_longjmp: {
1955 // ldr $scratch, [$src, #8]
1957 // ldr $scratch, [$src, #4]
1960 unsigned SrcReg = MI->getOperand(0).getReg();
1961 unsigned ScratchReg = MI->getOperand(1).getReg();
1964 TmpInst.setOpcode(ARM::tLDRi);
1965 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1966 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1967 // The offset immediate is #8. The operand value is scaled by 4 for the
1968 // tLDR instruction.
1969 TmpInst.addOperand(MCOperand::CreateImm(2));
1971 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1972 TmpInst.addOperand(MCOperand::CreateReg(0));
1973 OutStreamer.EmitInstruction(TmpInst);
1977 TmpInst.setOpcode(ARM::tMOVr);
1978 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1979 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1981 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1982 TmpInst.addOperand(MCOperand::CreateReg(0));
1983 OutStreamer.EmitInstruction(TmpInst);
1987 TmpInst.setOpcode(ARM::tLDRi);
1988 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1989 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1990 TmpInst.addOperand(MCOperand::CreateImm(1));
1992 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1993 TmpInst.addOperand(MCOperand::CreateReg(0));
1994 OutStreamer.EmitInstruction(TmpInst);
1998 TmpInst.setOpcode(ARM::tLDRi);
1999 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2000 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2001 TmpInst.addOperand(MCOperand::CreateImm(0));
2003 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2004 TmpInst.addOperand(MCOperand::CreateReg(0));
2005 OutStreamer.EmitInstruction(TmpInst);
2009 TmpInst.setOpcode(ARM::tBX);
2010 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2012 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2013 TmpInst.addOperand(MCOperand::CreateReg(0));
2014 OutStreamer.EmitInstruction(TmpInst);
2021 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2023 OutStreamer.EmitInstruction(TmpInst);
2026 //===----------------------------------------------------------------------===//
2027 // Target Registry Stuff
2028 //===----------------------------------------------------------------------===//
2030 // Force static initialization.
2031 extern "C" void LLVMInitializeARMAsmPrinter() {
2032 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2033 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);