1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
57 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
58 cl::desc("enable experimental asmprinter gunk in the arm backend"));
70 class ARMAsmPrinter : public AsmPrinter {
72 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
73 /// make the right decision when printing asm code for different targets.
74 const ARMSubtarget *Subtarget;
76 /// AFI - Keep a pointer to ARMFunctionInfo for the current
80 /// MCP - Keep a pointer to constantpool entries of the current
82 const MachineConstantPool *MCP;
85 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
86 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
87 Subtarget = &TM.getSubtarget<ARMSubtarget>();
90 virtual const char *getPassName() const {
91 return "ARM Assembly Printer";
94 void printInstructionThroughMCStreamer(const MachineInstr *MI);
97 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
98 const char *Modifier = 0);
99 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
100 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
102 void printSORegOperand(const MachineInstr *MI, int OpNum,
104 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
106 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
108 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
110 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
112 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
113 const char *Modifier = 0);
114 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
115 const char *Modifier = 0);
116 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
118 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
120 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
122 const char *Modifier = 0);
123 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
125 void printMemBOption(const MachineInstr *MI, int OpNum,
127 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
130 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
132 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
133 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
135 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
138 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
140 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
142 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
147 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
148 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
150 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
152 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
154 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
156 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
158 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
161 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
163 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
165 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
167 void printPredicateOperand(const MachineInstr *MI, int OpNum,
169 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
171 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
173 void printPCLabel(const MachineInstr *MI, int OpNum,
175 void printRegisterList(const MachineInstr *MI, int OpNum,
177 void printCPInstOperand(const MachineInstr *MI, int OpNum,
179 const char *Modifier);
180 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
182 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
184 void printTBAddrMode(const MachineInstr *MI, int OpNum,
186 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
188 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
190 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
192 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
195 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
196 unsigned AsmVariant, const char *ExtraCode,
198 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
200 const char *ExtraCode, raw_ostream &O);
202 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
203 static const char *getRegisterName(unsigned RegNo);
205 virtual void EmitInstruction(const MachineInstr *MI);
206 bool runOnMachineFunction(MachineFunction &F);
208 virtual void EmitConstantPool() {} // we emit constant pools customly!
209 virtual void EmitFunctionEntryLabel();
210 void EmitStartOfAsmFile(Module &M);
211 void EmitEndOfAsmFile(Module &M);
213 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 virtual unsigned getISAEncoding() {
226 // ARM/Darwin adds ISA to the DWARF info for each function.
227 if (!Subtarget->isTargetDarwin())
229 return Subtarget->isThumb() ?
230 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
233 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
234 const MachineBasicBlock *MBB) const;
235 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
237 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
239 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
240 SmallString<128> Str;
241 raw_svector_ostream OS(Str);
242 EmitMachineConstantPoolValue(MCPV, OS);
243 OutStreamer.EmitRawText(OS.str());
246 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
248 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
249 case 1: O << MAI->getData8bitsDirective(0); break;
250 case 2: O << MAI->getData16bitsDirective(0); break;
251 case 4: O << MAI->getData32bitsDirective(0); break;
252 default: assert(0 && "Unknown CPV size");
255 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
257 if (ACPV->isLSDA()) {
258 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
259 } else if (ACPV->isBlockAddress()) {
260 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
261 } else if (ACPV->isGlobalValue()) {
262 const GlobalValue *GV = ACPV->getGV();
263 bool isIndirect = Subtarget->isTargetDarwin() &&
264 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
266 O << *Mang->getSymbol(GV);
268 // FIXME: Remove this when Darwin transition to @GOT like syntax.
269 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
272 MachineModuleInfoMachO &MMIMachO =
273 MMI->getObjFileInfo<MachineModuleInfoMachO>();
274 MachineModuleInfoImpl::StubValueTy &StubSym =
275 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
276 MMIMachO.getGVStubEntry(Sym);
277 if (StubSym.getPointer() == 0)
278 StubSym = MachineModuleInfoImpl::
279 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
282 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
283 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
286 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
287 if (ACPV->getPCAdjustment() != 0) {
288 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
289 << getFunctionNumber() << "_" << ACPV->getLabelId()
290 << "+" << (unsigned)ACPV->getPCAdjustment();
291 if (ACPV->mustAddCurrentAddress())
297 } // end of anonymous namespace
299 #include "ARMGenAsmWriter.inc"
301 void ARMAsmPrinter::EmitFunctionEntryLabel() {
302 if (AFI->isThumbFunction()) {
303 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
304 if (!Subtarget->isTargetDarwin())
305 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
307 // This needs to emit to a temporary string to get properly quoted
308 // MCSymbols when they have spaces in them.
309 SmallString<128> Tmp;
310 raw_svector_ostream OS(Tmp);
311 OS << "\t.thumb_func\t" << *CurrentFnSym;
312 OutStreamer.EmitRawText(OS.str());
316 OutStreamer.EmitLabel(CurrentFnSym);
319 /// runOnMachineFunction - This uses the printInstruction()
320 /// method to print assembly for each instruction.
322 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
323 AFI = MF.getInfo<ARMFunctionInfo>();
324 MCP = MF.getConstantPool();
326 return AsmPrinter::runOnMachineFunction(MF);
329 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
330 raw_ostream &O, const char *Modifier) {
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 unsigned TF = MO.getTargetFlags();
334 switch (MO.getType()) {
336 assert(0 && "<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
341 unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
342 unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
344 << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi)
346 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
347 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
349 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
350 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
351 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
353 assert(!MO.getSubReg() && "Subregs should be eliminated!");
354 O << getRegisterName(Reg);
358 case MachineOperand::MO_Immediate: {
359 int64_t Imm = MO.getImm();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
370 case MachineOperand::MO_MachineBasicBlock:
371 O << *MO.getMBB()->getSymbol();
373 case MachineOperand::MO_GlobalAddress: {
374 bool isCallOp = Modifier && !strcmp(Modifier, "call");
375 const GlobalValue *GV = MO.getGlobal();
377 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
378 (TF & ARMII::MO_LO16))
380 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
381 (TF & ARMII::MO_HI16))
383 O << *Mang->getSymbol(GV);
385 printOffset(MO.getOffset(), O);
387 if (isCallOp && Subtarget->isTargetELF() &&
388 TM.getRelocationModel() == Reloc::PIC_)
392 case MachineOperand::MO_ExternalSymbol: {
393 bool isCallOp = Modifier && !strcmp(Modifier, "call");
394 O << *GetExternalSymbolSymbol(MO.getSymbolName());
396 if (isCallOp && Subtarget->isTargetELF() &&
397 TM.getRelocationModel() == Reloc::PIC_)
401 case MachineOperand::MO_ConstantPoolIndex:
402 O << *GetCPISymbol(MO.getIndex());
404 case MachineOperand::MO_JumpTableIndex:
405 O << *GetJTISymbol(MO.getIndex());
410 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
411 const MCAsmInfo *MAI) {
412 // Break it up into two parts that make up a shifter immediate.
413 V = ARM_AM::getSOImmVal(V);
414 assert(V != -1 && "Not a valid so_imm value!");
416 unsigned Imm = ARM_AM::getSOImmValImm(V);
417 unsigned Rot = ARM_AM::getSOImmValRot(V);
419 // Print low-level immediate formation info, per
420 // A5.1.3: "Data-processing operands - Immediate".
422 O << "#" << Imm << ", " << Rot;
423 // Pretty printed version.
425 O << "\t" << MAI->getCommentString() << ' ';
426 O << (int)ARM_AM::rotr32(Imm, Rot);
433 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
434 /// immediate in bits 0-7.
435 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
437 const MachineOperand &MO = MI->getOperand(OpNum);
438 assert(MO.isImm() && "Not a valid so_imm value!");
439 printSOImm(O, MO.getImm(), isVerbose(), MAI);
442 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
443 /// followed by an 'orr' to materialize.
444 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
446 const MachineOperand &MO = MI->getOperand(OpNum);
447 assert(MO.isImm() && "Not a valid so_imm value!");
448 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
449 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
450 printSOImm(O, V1, isVerbose(), MAI);
452 printPredicateOperand(MI, 2, O);
454 printOperand(MI, 0, O);
456 printOperand(MI, 0, O);
458 printSOImm(O, V2, isVerbose(), MAI);
461 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
462 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
464 // REG REG 0,SH_OPC - e.g. R5, ROR R3
465 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
466 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
468 const MachineOperand &MO1 = MI->getOperand(Op);
469 const MachineOperand &MO2 = MI->getOperand(Op+1);
470 const MachineOperand &MO3 = MI->getOperand(Op+2);
472 O << getRegisterName(MO1.getReg());
474 // Print the shift opc.
475 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
476 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
478 O << ' ' << getRegisterName(MO2.getReg());
479 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
480 } else if (ShOpc != ARM_AM::rrx) {
481 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
485 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
487 const MachineOperand &MO1 = MI->getOperand(Op);
488 const MachineOperand &MO2 = MI->getOperand(Op+1);
489 const MachineOperand &MO3 = MI->getOperand(Op+2);
491 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
492 printOperand(MI, Op, O);
496 O << "[" << getRegisterName(MO1.getReg());
499 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
501 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
502 << ARM_AM::getAM2Offset(MO3.getImm());
508 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
509 << getRegisterName(MO2.getReg());
511 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
513 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
518 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
520 const MachineOperand &MO1 = MI->getOperand(Op);
521 const MachineOperand &MO2 = MI->getOperand(Op+1);
524 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
526 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
531 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
532 << getRegisterName(MO1.getReg());
534 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
536 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
540 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
542 const MachineOperand &MO1 = MI->getOperand(Op);
543 const MachineOperand &MO2 = MI->getOperand(Op+1);
544 const MachineOperand &MO3 = MI->getOperand(Op+2);
546 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
547 O << "[" << getRegisterName(MO1.getReg());
551 << (char)ARM_AM::getAM3Op(MO3.getImm())
552 << getRegisterName(MO2.getReg())
557 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
559 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
564 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
566 const MachineOperand &MO1 = MI->getOperand(Op);
567 const MachineOperand &MO2 = MI->getOperand(Op+1);
570 O << (char)ARM_AM::getAM3Op(MO2.getImm())
571 << getRegisterName(MO1.getReg());
575 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
577 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
581 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
583 const char *Modifier) {
584 const MachineOperand &MO2 = MI->getOperand(Op+1);
585 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
586 if (Modifier && strcmp(Modifier, "submode") == 0) {
587 O << ARM_AM::getAMSubModeStr(Mode);
588 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
589 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
590 if (Mode == ARM_AM::ia)
593 printOperand(MI, Op, O);
597 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
599 const char *Modifier) {
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
604 printOperand(MI, Op, O);
608 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
610 O << "[" << getRegisterName(MO1.getReg());
612 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
614 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
620 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
622 const MachineOperand &MO1 = MI->getOperand(Op);
623 const MachineOperand &MO2 = MI->getOperand(Op+1);
625 O << "[" << getRegisterName(MO1.getReg());
627 // FIXME: Both darwin as and GNU as violate ARM docs here.
628 O << ", :" << (MO2.getImm() << 3);
633 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
635 const MachineOperand &MO = MI->getOperand(Op);
636 if (MO.getReg() == 0)
639 O << ", " << getRegisterName(MO.getReg());
642 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
644 const char *Modifier) {
645 if (Modifier && strcmp(Modifier, "label") == 0) {
646 printPCLabel(MI, Op+1, O);
650 const MachineOperand &MO1 = MI->getOperand(Op);
651 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
652 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
656 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
658 const MachineOperand &MO = MI->getOperand(Op);
659 uint32_t v = ~MO.getImm();
660 int32_t lsb = CountTrailingZeros_32(v);
661 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
662 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
663 O << "#" << lsb << ", #" << width;
667 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
669 unsigned val = MI->getOperand(OpNum).getImm();
670 O << ARM_MB::MemBOptToString(val);
673 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
675 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
676 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
678 case ARM_AM::no_shift:
687 assert(0 && "unexpected shift opcode for shift immediate operand");
689 O << ARM_AM::getSORegOffset(ShiftOp);
692 //===--------------------------------------------------------------------===//
694 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
696 O << "#" << MI->getOperand(Op).getImm() * 4;
700 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
702 // (3 - the number of trailing zeros) is the number of then / else.
703 unsigned Mask = MI->getOperand(Op).getImm();
704 unsigned CondBit0 = Mask >> 4 & 1;
705 unsigned NumTZ = CountTrailingZeros_32(Mask);
706 assert(NumTZ <= 3 && "Invalid IT mask!");
707 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
708 bool T = ((Mask >> Pos) & 1) == CondBit0;
717 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
719 const MachineOperand &MO1 = MI->getOperand(Op);
720 const MachineOperand &MO2 = MI->getOperand(Op+1);
721 O << "[" << getRegisterName(MO1.getReg());
722 O << ", " << getRegisterName(MO2.getReg()) << "]";
726 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
729 const MachineOperand &MO1 = MI->getOperand(Op);
730 const MachineOperand &MO2 = MI->getOperand(Op+1);
731 const MachineOperand &MO3 = MI->getOperand(Op+2);
733 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
734 printOperand(MI, Op, O);
738 O << "[" << getRegisterName(MO1.getReg());
740 O << ", " << getRegisterName(MO3.getReg());
741 else if (unsigned ImmOffs = MO2.getImm())
742 O << ", #" << ImmOffs * Scale;
747 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
749 printThumbAddrModeRI5Operand(MI, Op, O, 1);
752 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
754 printThumbAddrModeRI5Operand(MI, Op, O, 2);
757 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
759 printThumbAddrModeRI5Operand(MI, Op, O, 4);
762 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
764 const MachineOperand &MO1 = MI->getOperand(Op);
765 const MachineOperand &MO2 = MI->getOperand(Op+1);
766 O << "[" << getRegisterName(MO1.getReg());
767 if (unsigned ImmOffs = MO2.getImm())
768 O << ", #" << ImmOffs*4;
772 //===--------------------------------------------------------------------===//
774 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
775 // register with shift forms.
777 // REG IMM, SH_OPC - e.g. R5, LSL #3
778 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
780 const MachineOperand &MO1 = MI->getOperand(OpNum);
781 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
783 unsigned Reg = MO1.getReg();
784 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
785 O << getRegisterName(Reg);
787 // Print the shift opc.
788 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
789 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
790 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
791 if (ShOpc != ARM_AM::rrx)
792 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
795 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
798 const MachineOperand &MO1 = MI->getOperand(OpNum);
799 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
801 O << "[" << getRegisterName(MO1.getReg());
803 unsigned OffImm = MO2.getImm();
804 if (OffImm) // Don't print +0.
805 O << ", #" << OffImm;
809 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
812 const MachineOperand &MO1 = MI->getOperand(OpNum);
813 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
815 O << "[" << getRegisterName(MO1.getReg());
817 int32_t OffImm = (int32_t)MO2.getImm();
820 O << ", #-" << -OffImm;
822 O << ", #" << OffImm;
826 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
829 const MachineOperand &MO1 = MI->getOperand(OpNum);
830 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
832 O << "[" << getRegisterName(MO1.getReg());
834 int32_t OffImm = (int32_t)MO2.getImm() / 4;
837 O << ", #-" << -OffImm * 4;
839 O << ", #" << OffImm * 4;
843 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
846 const MachineOperand &MO1 = MI->getOperand(OpNum);
847 int32_t OffImm = (int32_t)MO1.getImm();
850 O << "#-" << -OffImm;
855 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
858 const MachineOperand &MO1 = MI->getOperand(OpNum);
859 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
860 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
862 O << "[" << getRegisterName(MO1.getReg());
864 assert(MO2.getReg() && "Invalid so_reg load / store address!");
865 O << ", " << getRegisterName(MO2.getReg());
867 unsigned ShAmt = MO3.getImm();
869 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
870 O << ", lsl #" << ShAmt;
876 //===--------------------------------------------------------------------===//
878 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
880 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
882 O << ARMCondCodeToString(CC);
885 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
888 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
889 O << ARMCondCodeToString(CC);
892 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
894 unsigned Reg = MI->getOperand(OpNum).getReg();
896 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
901 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
903 int Id = (int)MI->getOperand(OpNum).getImm();
904 O << MAI->getPrivateGlobalPrefix()
905 << "PC" << getFunctionNumber() << "_" << Id;
908 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
911 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
912 if (MI->getOperand(i).isImplicit())
914 if ((int)i != OpNum) O << ", ";
915 printOperand(MI, i, O);
920 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
921 raw_ostream &O, const char *Modifier) {
922 assert(Modifier && "This operand only works with a modifier!");
923 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
925 if (!strcmp(Modifier, "label")) {
926 unsigned ID = MI->getOperand(OpNum).getImm();
927 OutStreamer.EmitLabel(GetCPISymbol(ID));
929 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
930 unsigned CPI = MI->getOperand(OpNum).getIndex();
932 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
934 if (MCPE.isMachineConstantPoolEntry()) {
935 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
937 EmitGlobalConstant(MCPE.Val.ConstVal);
942 MCSymbol *ARMAsmPrinter::
943 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
944 const MachineBasicBlock *MBB) const {
945 SmallString<60> Name;
946 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
947 << getFunctionNumber() << '_' << uid << '_' << uid2
948 << "_set_" << MBB->getNumber();
949 return OutContext.GetOrCreateSymbol(Name.str());
952 MCSymbol *ARMAsmPrinter::
953 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
954 SmallString<60> Name;
955 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
956 << getFunctionNumber() << '_' << uid << '_' << uid2;
957 return OutContext.GetOrCreateSymbol(Name.str());
960 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
962 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
964 const MachineOperand &MO1 = MI->getOperand(OpNum);
965 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
967 unsigned JTI = MO1.getIndex();
968 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
969 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
971 O << "\n" << *JTISymbol << ":\n";
973 const char *JTEntryDirective = MAI->getData32bitsDirective();
975 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
976 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
977 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
978 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
979 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
980 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
981 MachineBasicBlock *MBB = JTBBs[i];
982 bool isNew = JTSets.insert(MBB);
984 if (UseSet && isNew) {
986 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
987 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
990 O << JTEntryDirective << ' ';
992 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
993 else if (TM.getRelocationModel() == Reloc::PIC_)
994 O << *MBB->getSymbol() << '-' << *JTISymbol;
996 O << *MBB->getSymbol();
1003 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
1005 const MachineOperand &MO1 = MI->getOperand(OpNum);
1006 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1007 unsigned JTI = MO1.getIndex();
1009 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1011 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
1013 O << "\n" << *JTISymbol << ":\n";
1015 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1016 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1017 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1018 bool ByteOffset = false, HalfWordOffset = false;
1019 if (MI->getOpcode() == ARM::t2TBB)
1021 else if (MI->getOpcode() == ARM::t2TBH)
1022 HalfWordOffset = true;
1024 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1025 MachineBasicBlock *MBB = JTBBs[i];
1027 O << MAI->getData8bitsDirective();
1028 else if (HalfWordOffset)
1029 O << MAI->getData16bitsDirective();
1031 if (ByteOffset || HalfWordOffset)
1032 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1034 O << "\tb.w " << *MBB->getSymbol();
1041 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1043 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1044 if (MI->getOpcode() == ARM::t2TBH)
1049 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1051 O << MI->getOperand(OpNum).getImm();
1054 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1056 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1057 O << '#' << FP->getValueAPF().convertToFloat();
1059 O << "\t\t" << MAI->getCommentString() << ' ';
1060 WriteAsOperand(O, FP, /*PrintType=*/false);
1064 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1066 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1067 O << '#' << FP->getValueAPF().convertToDouble();
1069 O << "\t\t" << MAI->getCommentString() << ' ';
1070 WriteAsOperand(O, FP, /*PrintType=*/false);
1074 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1076 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1078 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1079 O << "#0x" << utohexstr(Val);
1082 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1083 unsigned AsmVariant, const char *ExtraCode,
1085 // Does this asm operand have a single letter operand modifier?
1086 if (ExtraCode && ExtraCode[0]) {
1087 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1089 switch (ExtraCode[0]) {
1090 default: return true; // Unknown modifier.
1091 case 'a': // Print as a memory address.
1092 if (MI->getOperand(OpNum).isReg()) {
1093 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1097 case 'c': // Don't print "#" before an immediate operand.
1098 if (!MI->getOperand(OpNum).isImm())
1100 printNoHashImmediate(MI, OpNum, O);
1102 case 'P': // Print a VFP double precision register.
1103 case 'q': // Print a NEON quad precision register.
1104 printOperand(MI, OpNum, O);
1109 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1114 printOperand(MI, OpNum, O);
1118 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1119 unsigned OpNum, unsigned AsmVariant,
1120 const char *ExtraCode,
1122 if (ExtraCode && ExtraCode[0])
1123 return true; // Unknown modifier.
1125 const MachineOperand &MO = MI->getOperand(OpNum);
1126 assert(MO.isReg() && "unexpected inline asm memory operand");
1127 O << "[" << getRegisterName(MO.getReg()) << "]";
1131 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1133 printInstructionThroughMCStreamer(MI);
1137 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1140 SmallString<128> Str;
1141 raw_svector_ostream OS(Str);
1142 if (MI->getOpcode() == ARM::DBG_VALUE) {
1143 unsigned NOps = MI->getNumOperands();
1145 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1146 // cast away const; DIetc do not take const operands for some reason.
1147 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1150 // Frame address. Currently handles register +- offset only.
1151 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1152 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1155 printOperand(MI, NOps-2, OS);
1156 OutStreamer.EmitRawText(OS.str());
1160 printInstruction(MI, OS);
1161 OutStreamer.EmitRawText(OS.str());
1163 // Make sure the instruction that follows TBB is 2-byte aligned.
1164 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1165 if (MI->getOpcode() == ARM::t2TBB)
1169 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1170 if (Subtarget->isTargetDarwin()) {
1171 Reloc::Model RelocM = TM.getRelocationModel();
1172 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1173 // Declare all the text sections up front (before the DWARF sections
1174 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1175 // them together at the beginning of the object file. This helps
1176 // avoid out-of-range branches that are due a fundamental limitation of
1177 // the way symbol offsets are encoded with the current Darwin ARM
1179 const TargetLoweringObjectFileMachO &TLOFMacho =
1180 static_cast<const TargetLoweringObjectFileMachO &>(
1181 getObjFileLowering());
1182 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1183 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1184 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1185 if (RelocM == Reloc::DynamicNoPIC) {
1186 const MCSection *sect =
1187 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1188 MCSectionMachO::S_SYMBOL_STUBS,
1189 12, SectionKind::getText());
1190 OutStreamer.SwitchSection(sect);
1192 const MCSection *sect =
1193 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1194 MCSectionMachO::S_SYMBOL_STUBS,
1195 16, SectionKind::getText());
1196 OutStreamer.SwitchSection(sect);
1198 const MCSection *StaticInitSect =
1199 OutContext.getMachOSection("__TEXT", "__StaticInit",
1200 MCSectionMachO::S_REGULAR |
1201 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1202 SectionKind::getText());
1203 OutStreamer.SwitchSection(StaticInitSect);
1207 // Use unified assembler syntax.
1208 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1210 // Emit ARM Build Attributes
1211 if (Subtarget->isTargetELF()) {
1213 std::string CPUString = Subtarget->getCPUString();
1214 if (CPUString != "generic")
1215 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1217 // FIXME: Emit FPU type
1218 if (Subtarget->hasVFP2())
1219 OutStreamer.EmitRawText("\t.eabi_attribute " +
1220 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1222 // Signal various FP modes.
1223 if (!UnsafeFPMath) {
1224 OutStreamer.EmitRawText("\t.eabi_attribute " +
1225 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1226 OutStreamer.EmitRawText("\t.eabi_attribute " +
1227 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1230 if (NoInfsFPMath && NoNaNsFPMath)
1231 OutStreamer.EmitRawText("\t.eabi_attribute " +
1232 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1234 OutStreamer.EmitRawText("\t.eabi_attribute " +
1235 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1237 // 8-bytes alignment stuff.
1238 OutStreamer.EmitRawText("\t.eabi_attribute " +
1239 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1240 OutStreamer.EmitRawText("\t.eabi_attribute " +
1241 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1243 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1244 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1245 OutStreamer.EmitRawText("\t.eabi_attribute " +
1246 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1247 OutStreamer.EmitRawText("\t.eabi_attribute " +
1248 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1250 // FIXME: Should we signal R9 usage?
1255 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1256 if (Subtarget->isTargetDarwin()) {
1257 // All darwin targets use mach-o.
1258 const TargetLoweringObjectFileMachO &TLOFMacho =
1259 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1260 MachineModuleInfoMachO &MMIMacho =
1261 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1263 // Output non-lazy-pointers for external and common global variables.
1264 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1266 if (!Stubs.empty()) {
1267 // Switch with ".non_lazy_symbol_pointer" directive.
1268 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1270 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1272 OutStreamer.EmitLabel(Stubs[i].first);
1273 // .indirect_symbol _foo
1274 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1275 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1278 // External to current translation unit.
1279 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1281 // Internal to current translation unit.
1283 // When we place the LSDA into the TEXT section, the type info pointers
1284 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1285 // However, sometimes the types are local to the file. So we need to
1286 // fill in the value for the NLP in those cases.
1287 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1289 4/*size*/, 0/*addrspace*/);
1293 OutStreamer.AddBlankLine();
1296 Stubs = MMIMacho.GetHiddenGVStubList();
1297 if (!Stubs.empty()) {
1298 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1300 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1302 OutStreamer.EmitLabel(Stubs[i].first);
1304 OutStreamer.EmitValue(MCSymbolRefExpr::
1305 Create(Stubs[i].second.getPointer(),
1307 4/*size*/, 0/*addrspace*/);
1311 OutStreamer.AddBlankLine();
1314 // Funny Darwin hack: This flag tells the linker that no global symbols
1315 // contain code that falls through to other global symbols (e.g. the obvious
1316 // implementation of multiple entry points). If this doesn't occur, the
1317 // linker can safely perform dead code stripping. Since LLVM never
1318 // generates code that does this, it is always safe to set.
1319 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1323 //===----------------------------------------------------------------------===//
1325 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1326 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1327 switch (MI->getOpcode()) {
1328 case ARM::t2MOVi32imm:
1329 assert(0 && "Should be lowered by thumb2it pass");
1331 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1332 // This is a pseudo op for a label + instruction sequence, which looks like:
1335 // This adds the address of LPC0 to r0.
1338 // FIXME: MOVE TO SHARED PLACE.
1339 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1340 const char *Prefix = MAI->getPrivateGlobalPrefix();
1341 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1342 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1343 OutStreamer.EmitLabel(Label);
1346 // Form and emit tha dd.
1348 AddInst.setOpcode(ARM::ADDrr);
1349 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1350 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1351 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1352 OutStreamer.EmitInstruction(AddInst);
1355 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1356 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1357 /// in the function. The first operand is the ID# for this instruction, the
1358 /// second is the index into the MachineConstantPool that this is, the third
1359 /// is the size in bytes of this constant pool entry.
1360 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1361 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1364 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1366 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1367 if (MCPE.isMachineConstantPoolEntry())
1368 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1370 EmitGlobalConstant(MCPE.Val.ConstVal);
1374 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1375 // This is a hack that lowers as a two instruction sequence.
1376 unsigned DstReg = MI->getOperand(0).getReg();
1377 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1379 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1380 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1384 TmpInst.setOpcode(ARM::MOVi);
1385 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1386 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1389 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1390 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1392 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1393 OutStreamer.EmitInstruction(TmpInst);
1398 TmpInst.setOpcode(ARM::ORRri);
1399 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1400 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1401 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1403 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1404 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1406 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1407 OutStreamer.EmitInstruction(TmpInst);
1411 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1412 // This is a hack that lowers as a two instruction sequence.
1413 unsigned DstReg = MI->getOperand(0).getReg();
1414 const MachineOperand &MO = MI->getOperand(1);
1417 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1418 V1 = MCOperand::CreateImm(ImmVal & 65535);
1419 V2 = MCOperand::CreateImm(ImmVal >> 16);
1420 } else if (MO.isGlobal()) {
1421 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
1422 const MCSymbolRefExpr *SymRef1 =
1423 MCSymbolRefExpr::Create(Symbol,
1424 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1425 const MCSymbolRefExpr *SymRef2 =
1426 MCSymbolRefExpr::Create(Symbol,
1427 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1428 V1 = MCOperand::CreateExpr(SymRef1);
1429 V2 = MCOperand::CreateExpr(SymRef2);
1432 llvm_unreachable("cannot handle this operand");
1437 TmpInst.setOpcode(ARM::MOVi16);
1438 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1439 TmpInst.addOperand(V1); // lower16(imm)
1442 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1443 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1445 OutStreamer.EmitInstruction(TmpInst);
1450 TmpInst.setOpcode(ARM::MOVTi16);
1451 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1452 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1453 TmpInst.addOperand(V2); // upper16(imm)
1456 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1457 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1459 OutStreamer.EmitInstruction(TmpInst);
1467 MCInstLowering.Lower(MI, TmpInst);
1468 OutStreamer.EmitInstruction(TmpInst);
1471 //===----------------------------------------------------------------------===//
1472 // Target Registry Stuff
1473 //===----------------------------------------------------------------------===//
1475 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1476 unsigned SyntaxVariant,
1477 const MCAsmInfo &MAI) {
1478 if (SyntaxVariant == 0)
1479 return new ARMInstPrinter(MAI, false);
1483 // Force static initialization.
1484 extern "C" void LLVMInitializeARMAsmPrinter() {
1485 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1486 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1488 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1489 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);