1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 /// EmitDwarfRegOp - Emit dwarf register operation.
176 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
177 const TargetRegisterInfo *RI = TM.getRegisterInfo();
178 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
179 AsmPrinter::EmitDwarfRegOp(MLoc);
181 unsigned Reg = MLoc.getReg();
182 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
183 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
184 // S registers are described as bit-pieces of a register
185 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
186 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
188 unsigned SReg = Reg - ARM::S0;
189 bool odd = SReg & 0x1;
190 unsigned Rx = 256 + (SReg >> 1);
192 OutStreamer.AddComment("DW_OP_regx for S register");
193 EmitInt8(dwarf::DW_OP_regx);
195 OutStreamer.AddComment(Twine(SReg));
199 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
200 EmitInt8(dwarf::DW_OP_bit_piece);
204 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
205 EmitInt8(dwarf::DW_OP_bit_piece);
209 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
210 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
211 // Q registers Q0-Q15 are described by composing two D registers together.
212 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
214 unsigned QReg = Reg - ARM::Q0;
215 unsigned D1 = 256 + 2 * QReg;
216 unsigned D2 = D1 + 1;
218 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
219 EmitInt8(dwarf::DW_OP_regx);
221 OutStreamer.AddComment("DW_OP_piece 8");
222 EmitInt8(dwarf::DW_OP_piece);
225 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
226 EmitInt8(dwarf::DW_OP_regx);
228 OutStreamer.AddComment("DW_OP_piece 8");
229 EmitInt8(dwarf::DW_OP_piece);
235 void ARMAsmPrinter::EmitFunctionEntryLabel() {
236 if (AFI->isThumbFunction()) {
237 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
238 OutStreamer.EmitThumbFunc(CurrentFnSym);
241 OutStreamer.EmitLabel(CurrentFnSym);
244 /// runOnMachineFunction - This uses the EmitInstruction()
245 /// method to print assembly for each instruction.
247 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
248 AFI = MF.getInfo<ARMFunctionInfo>();
249 MCP = MF.getConstantPool();
251 return AsmPrinter::runOnMachineFunction(MF);
254 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
255 raw_ostream &O, const char *Modifier) {
256 const MachineOperand &MO = MI->getOperand(OpNum);
257 unsigned TF = MO.getTargetFlags();
259 switch (MO.getType()) {
261 assert(0 && "<unknown operand type>");
262 case MachineOperand::MO_Register: {
263 unsigned Reg = MO.getReg();
264 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
265 assert(!MO.getSubReg() && "Subregs should be eliminated!");
266 O << ARMInstPrinter::getRegisterName(Reg);
269 case MachineOperand::MO_Immediate: {
270 int64_t Imm = MO.getImm();
272 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
273 (TF == ARMII::MO_LO16))
275 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
276 (TF == ARMII::MO_HI16))
281 case MachineOperand::MO_MachineBasicBlock:
282 O << *MO.getMBB()->getSymbol();
284 case MachineOperand::MO_GlobalAddress: {
285 const GlobalValue *GV = MO.getGlobal();
286 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
287 (TF & ARMII::MO_LO16))
289 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
290 (TF & ARMII::MO_HI16))
292 O << *Mang->getSymbol(GV);
294 printOffset(MO.getOffset(), O);
295 if (TF == ARMII::MO_PLT)
299 case MachineOperand::MO_ExternalSymbol: {
300 O << *GetExternalSymbolSymbol(MO.getSymbolName());
301 if (TF == ARMII::MO_PLT)
305 case MachineOperand::MO_ConstantPoolIndex:
306 O << *GetCPISymbol(MO.getIndex());
308 case MachineOperand::MO_JumpTableIndex:
309 O << *GetJTISymbol(MO.getIndex());
314 //===--------------------------------------------------------------------===//
316 MCSymbol *ARMAsmPrinter::
317 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
318 const MachineBasicBlock *MBB) const {
319 SmallString<60> Name;
320 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
321 << getFunctionNumber() << '_' << uid << '_' << uid2
322 << "_set_" << MBB->getNumber();
323 return OutContext.GetOrCreateSymbol(Name.str());
326 MCSymbol *ARMAsmPrinter::
327 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
328 SmallString<60> Name;
329 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
330 << getFunctionNumber() << '_' << uid << '_' << uid2;
331 return OutContext.GetOrCreateSymbol(Name.str());
335 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
336 SmallString<60> Name;
337 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
338 << getFunctionNumber();
339 return OutContext.GetOrCreateSymbol(Name.str());
342 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
343 unsigned AsmVariant, const char *ExtraCode,
345 // Does this asm operand have a single letter operand modifier?
346 if (ExtraCode && ExtraCode[0]) {
347 if (ExtraCode[1] != 0) return true; // Unknown modifier.
349 switch (ExtraCode[0]) {
350 default: return true; // Unknown modifier.
351 case 'a': // Print as a memory address.
352 if (MI->getOperand(OpNum).isReg()) {
354 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
359 case 'c': // Don't print "#" before an immediate operand.
360 if (!MI->getOperand(OpNum).isImm())
362 O << MI->getOperand(OpNum).getImm();
364 case 'P': // Print a VFP double precision register.
365 case 'q': // Print a NEON quad precision register.
366 printOperand(MI, OpNum, O);
368 case 'y': // Print a VFP single precision register as indexed double.
369 // This uses the ordering of the alias table to get the first 'd' register
370 // that overlaps the 's' register. Also, s0 is an odd register, hence the
371 // odd modulus check below.
372 if (MI->getOperand(OpNum).isReg()) {
373 unsigned Reg = MI->getOperand(OpNum).getReg();
374 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
375 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
376 (((Reg % 2) == 1) ? "[0]" : "[1]");
380 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
381 if (!MI->getOperand(OpNum).isImm())
383 O << ~(MI->getOperand(OpNum).getImm());
385 case 'L': // The low 16 bits of an immediate constant.
386 if (!MI->getOperand(OpNum).isImm())
388 O << (MI->getOperand(OpNum).getImm() & 0xffff);
390 case 'p': // The high single-precision register of a VFP double-precision
392 case 'e': // The low doubleword register of a NEON quad register.
393 case 'f': // The high doubleword register of a NEON quad register.
394 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
395 case 'M': // A register range suitable for LDM/STM.
396 case 'Q': // The least significant register of a pair.
397 case 'R': // The most significant register of a pair.
398 case 'H': // The highest-numbered register of a pair.
399 // These modifiers are not yet supported.
404 printOperand(MI, OpNum, O);
408 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
409 unsigned OpNum, unsigned AsmVariant,
410 const char *ExtraCode,
412 // Does this asm operand have a single letter operand modifier?
413 if (ExtraCode && ExtraCode[0]) {
414 if (ExtraCode[1] != 0) return true; // Unknown modifier.
416 switch (ExtraCode[0]) {
417 case 'A': // A memory operand for a VLD1/VST1 instruction.
418 default: return true; // Unknown modifier.
419 case 'm': // The base register of a memory operand.
420 if (!MI->getOperand(OpNum).isReg())
422 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
427 const MachineOperand &MO = MI->getOperand(OpNum);
428 assert(MO.isReg() && "unexpected inline asm memory operand");
429 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
433 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
434 if (Subtarget->isTargetDarwin()) {
435 Reloc::Model RelocM = TM.getRelocationModel();
436 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
437 // Declare all the text sections up front (before the DWARF sections
438 // emitted by AsmPrinter::doInitialization) so the assembler will keep
439 // them together at the beginning of the object file. This helps
440 // avoid out-of-range branches that are due a fundamental limitation of
441 // the way symbol offsets are encoded with the current Darwin ARM
443 const TargetLoweringObjectFileMachO &TLOFMacho =
444 static_cast<const TargetLoweringObjectFileMachO &>(
445 getObjFileLowering());
446 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
447 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
448 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
449 if (RelocM == Reloc::DynamicNoPIC) {
450 const MCSection *sect =
451 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
452 MCSectionMachO::S_SYMBOL_STUBS,
453 12, SectionKind::getText());
454 OutStreamer.SwitchSection(sect);
456 const MCSection *sect =
457 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
458 MCSectionMachO::S_SYMBOL_STUBS,
459 16, SectionKind::getText());
460 OutStreamer.SwitchSection(sect);
462 const MCSection *StaticInitSect =
463 OutContext.getMachOSection("__TEXT", "__StaticInit",
464 MCSectionMachO::S_REGULAR |
465 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
466 SectionKind::getText());
467 OutStreamer.SwitchSection(StaticInitSect);
471 // Use unified assembler syntax.
472 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
474 // Emit ARM Build Attributes
475 if (Subtarget->isTargetELF()) {
482 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
483 if (Subtarget->isTargetDarwin()) {
484 // All darwin targets use mach-o.
485 const TargetLoweringObjectFileMachO &TLOFMacho =
486 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
487 MachineModuleInfoMachO &MMIMacho =
488 MMI->getObjFileInfo<MachineModuleInfoMachO>();
490 // Output non-lazy-pointers for external and common global variables.
491 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
493 if (!Stubs.empty()) {
494 // Switch with ".non_lazy_symbol_pointer" directive.
495 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
497 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
499 OutStreamer.EmitLabel(Stubs[i].first);
500 // .indirect_symbol _foo
501 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
502 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
505 // External to current translation unit.
506 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
508 // Internal to current translation unit.
510 // When we place the LSDA into the TEXT section, the type info
511 // pointers need to be indirect and pc-rel. We accomplish this by
512 // using NLPs; however, sometimes the types are local to the file.
513 // We need to fill in the value for the NLP in those cases.
514 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
516 4/*size*/, 0/*addrspace*/);
520 OutStreamer.AddBlankLine();
523 Stubs = MMIMacho.GetHiddenGVStubList();
524 if (!Stubs.empty()) {
525 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
527 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
529 OutStreamer.EmitLabel(Stubs[i].first);
531 OutStreamer.EmitValue(MCSymbolRefExpr::
532 Create(Stubs[i].second.getPointer(),
534 4/*size*/, 0/*addrspace*/);
538 OutStreamer.AddBlankLine();
541 // Funny Darwin hack: This flag tells the linker that no global symbols
542 // contain code that falls through to other global symbols (e.g. the obvious
543 // implementation of multiple entry points). If this doesn't occur, the
544 // linker can safely perform dead code stripping. Since LLVM never
545 // generates code that does this, it is always safe to set.
546 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
550 //===----------------------------------------------------------------------===//
551 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
553 // The following seem like one-off assembler flags, but they actually need
554 // to appear in the .ARM.attributes section in ELF.
555 // Instead of subclassing the MCELFStreamer, we do the work here.
557 void ARMAsmPrinter::emitAttributes() {
559 emitARMAttributeSection();
561 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
562 bool emitFPU = false;
563 AttributeEmitter *AttrEmitter;
564 if (OutStreamer.hasRawTextSupport()) {
565 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
568 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
569 AttrEmitter = new ObjectAttributeEmitter(O);
572 AttrEmitter->MaybeSwitchVendor("aeabi");
574 std::string CPUString = Subtarget->getCPUString();
576 if (CPUString == "cortex-a8" ||
577 Subtarget->isCortexA8()) {
578 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
579 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
580 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
581 ARMBuildAttrs::ApplicationProfile);
582 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
583 ARMBuildAttrs::Allowed);
584 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
585 ARMBuildAttrs::AllowThumb32);
586 // Fixme: figure out when this is emitted.
587 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
588 // ARMBuildAttrs::AllowWMMXv1);
591 /// ADD additional Else-cases here!
592 } else if (CPUString == "xscale") {
593 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
594 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
595 ARMBuildAttrs::Allowed);
596 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
597 ARMBuildAttrs::Allowed);
598 } else if (CPUString == "generic") {
599 // FIXME: Why these defaults?
600 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
601 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
602 ARMBuildAttrs::Allowed);
603 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
604 ARMBuildAttrs::Allowed);
607 if (Subtarget->hasNEON() && emitFPU) {
608 /* NEON is not exactly a VFP architecture, but GAS emit one of
609 * neon/vfpv3/vfpv2 for .fpu parameters */
610 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
611 /* If emitted for NEON, omit from VFP below, since you can have both
612 * NEON and VFP in build attributes but only one .fpu */
617 if (Subtarget->hasVFP3()) {
618 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
619 ARMBuildAttrs::AllowFPv3A);
621 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
624 } else if (Subtarget->hasVFP2()) {
625 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
626 ARMBuildAttrs::AllowFPv2);
628 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
631 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
632 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
633 if (Subtarget->hasNEON()) {
634 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
635 ARMBuildAttrs::Allowed);
638 // Signal various FP modes.
640 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
641 ARMBuildAttrs::Allowed);
642 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
643 ARMBuildAttrs::Allowed);
646 if (NoInfsFPMath && NoNaNsFPMath)
647 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
648 ARMBuildAttrs::Allowed);
650 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
651 ARMBuildAttrs::AllowIEE754);
653 // FIXME: add more flags to ARMBuildAttrs.h
654 // 8-bytes alignment stuff.
655 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
656 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
658 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
659 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
660 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
661 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
663 // FIXME: Should we signal R9 usage?
665 if (Subtarget->hasDivide())
666 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
668 AttrEmitter->Finish();
672 void ARMAsmPrinter::emitARMAttributeSection() {
674 // [ <section-length> "vendor-name"
675 // [ <file-tag> <size> <attribute>*
676 // | <section-tag> <size> <section-number>* 0 <attribute>*
677 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
681 if (OutStreamer.hasRawTextSupport())
684 const ARMElfTargetObjectFile &TLOFELF =
685 static_cast<const ARMElfTargetObjectFile &>
686 (getObjFileLowering());
688 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
691 OutStreamer.EmitIntValue(0x41, 1);
694 //===----------------------------------------------------------------------===//
696 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
697 unsigned LabelId, MCContext &Ctx) {
699 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
700 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
704 static MCSymbolRefExpr::VariantKind
705 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
707 default: llvm_unreachable("Unknown modifier!");
708 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
709 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
710 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
711 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
712 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
713 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
715 return MCSymbolRefExpr::VK_None;
718 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
719 bool isIndirect = Subtarget->isTargetDarwin() &&
720 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
722 return Mang->getSymbol(GV);
724 // FIXME: Remove this when Darwin transition to @GOT like syntax.
725 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
726 MachineModuleInfoMachO &MMIMachO =
727 MMI->getObjFileInfo<MachineModuleInfoMachO>();
728 MachineModuleInfoImpl::StubValueTy &StubSym =
729 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
730 MMIMachO.getGVStubEntry(MCSym);
731 if (StubSym.getPointer() == 0)
732 StubSym = MachineModuleInfoImpl::
733 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
738 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
739 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
741 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
744 if (ACPV->isLSDA()) {
745 SmallString<128> Str;
746 raw_svector_ostream OS(Str);
747 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
748 MCSym = OutContext.GetOrCreateSymbol(OS.str());
749 } else if (ACPV->isBlockAddress()) {
750 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
751 } else if (ACPV->isGlobalValue()) {
752 const GlobalValue *GV = ACPV->getGV();
753 MCSym = GetARMGVSymbol(GV);
755 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
756 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
759 // Create an MCSymbol for the reference.
761 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
764 if (ACPV->getPCAdjustment()) {
765 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
769 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
771 MCBinaryExpr::CreateAdd(PCRelExpr,
772 MCConstantExpr::Create(ACPV->getPCAdjustment(),
775 if (ACPV->mustAddCurrentAddress()) {
776 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
777 // label, so just emit a local label end reference that instead.
778 MCSymbol *DotSym = OutContext.CreateTempSymbol();
779 OutStreamer.EmitLabel(DotSym);
780 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
781 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
783 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
785 OutStreamer.EmitValue(Expr, Size);
788 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
789 unsigned Opcode = MI->getOpcode();
791 if (Opcode == ARM::BR_JTadd)
793 else if (Opcode == ARM::BR_JTm)
796 const MachineOperand &MO1 = MI->getOperand(OpNum);
797 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
798 unsigned JTI = MO1.getIndex();
800 // Emit a label for the jump table.
801 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
802 OutStreamer.EmitLabel(JTISymbol);
804 // Emit each entry of the table.
805 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
806 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
807 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
809 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
810 MachineBasicBlock *MBB = JTBBs[i];
811 // Construct an MCExpr for the entry. We want a value of the form:
812 // (BasicBlockAddr - TableBeginAddr)
814 // For example, a table with entries jumping to basic blocks BB0 and BB1
817 // .word (LBB0 - LJTI_0_0)
818 // .word (LBB1 - LJTI_0_0)
819 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
821 if (TM.getRelocationModel() == Reloc::PIC_)
822 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
825 OutStreamer.EmitValue(Expr, 4);
829 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
830 unsigned Opcode = MI->getOpcode();
831 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
832 const MachineOperand &MO1 = MI->getOperand(OpNum);
833 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
834 unsigned JTI = MO1.getIndex();
836 // Emit a label for the jump table.
837 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
838 OutStreamer.EmitLabel(JTISymbol);
840 // Emit each entry of the table.
841 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
842 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
843 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
844 unsigned OffsetWidth = 4;
845 if (MI->getOpcode() == ARM::t2TBB_JT)
847 else if (MI->getOpcode() == ARM::t2TBH_JT)
850 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
851 MachineBasicBlock *MBB = JTBBs[i];
852 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
854 // If this isn't a TBB or TBH, the entries are direct branch instructions.
855 if (OffsetWidth == 4) {
857 BrInst.setOpcode(ARM::t2B);
858 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
859 OutStreamer.EmitInstruction(BrInst);
862 // Otherwise it's an offset from the dispatch instruction. Construct an
863 // MCExpr for the entry. We want a value of the form:
864 // (BasicBlockAddr - TableBeginAddr) / 2
866 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
869 // .byte (LBB0 - LJTI_0_0) / 2
870 // .byte (LBB1 - LJTI_0_0) / 2
872 MCBinaryExpr::CreateSub(MBBSymbolExpr,
873 MCSymbolRefExpr::Create(JTISymbol, OutContext),
875 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
877 OutStreamer.EmitValue(Expr, OffsetWidth);
881 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
883 unsigned NOps = MI->getNumOperands();
885 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
886 // cast away const; DIetc do not take const operands for some reason.
887 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
890 // Frame address. Currently handles register +- offset only.
891 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
892 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
895 printOperand(MI, NOps-2, OS);
898 static void populateADROperands(MCInst &Inst, unsigned Dest,
899 const MCSymbol *Label,
900 unsigned pred, unsigned ccreg,
902 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
903 Inst.addOperand(MCOperand::CreateReg(Dest));
904 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
905 // Add predicate operands.
906 Inst.addOperand(MCOperand::CreateImm(pred));
907 Inst.addOperand(MCOperand::CreateReg(ccreg));
910 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
914 // Emit the instruction as usual, just patch the opcode.
915 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
916 TmpInst.setOpcode(Opcode);
917 OutStreamer.EmitInstruction(TmpInst);
920 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
921 assert(MI->getFlag(MachineInstr::FrameSetup) &&
922 "Only instruction which are involved into frame setup code are allowed");
924 const MachineFunction &MF = *MI->getParent()->getParent();
925 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
926 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
928 unsigned FramePtr = RegInfo->getFrameRegister(MF);
929 unsigned Opc = MI->getOpcode();
930 unsigned SrcReg, DstReg;
932 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
933 // Two special cases:
934 // 1) tPUSH does not have src/dst regs.
935 // 2) for Thumb1 code we sometimes materialize the constant via constpool
936 // load. Yes, this is pretty fragile, but for now I don't see better
938 SrcReg = DstReg = ARM::SP;
940 SrcReg = MI->getOperand(1).getReg();
941 DstReg = MI->getOperand(0).getReg();
944 // Try to figure out the unwinding opcode out of src / dst regs.
945 if (MI->getDesc().mayStore()) {
947 assert(DstReg == ARM::SP &&
948 "Only stack pointer as a destination reg is supported");
950 SmallVector<unsigned, 4> RegList;
951 // Skip src & dst reg, and pred ops.
952 unsigned StartOp = 2 + 2;
953 // Use all the operands.
954 unsigned NumOffset = 0;
959 assert(0 && "Unsupported opcode for unwinding information");
961 // Special case here: no src & dst reg, but two extra imp ops.
962 StartOp = 2; NumOffset = 2;
964 case ARM::t2STMDB_UPD:
965 case ARM::VSTMDDB_UPD:
966 assert(SrcReg == ARM::SP &&
967 "Only stack pointer as a source reg is supported");
968 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
970 RegList.push_back(MI->getOperand(i).getReg());
973 assert(MI->getOperand(2).getReg() == ARM::SP &&
974 "Only stack pointer as a source reg is supported");
975 RegList.push_back(SrcReg);
978 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
980 // Changes of stack / frame pointer.
981 if (SrcReg == ARM::SP) {
986 assert(0 && "Unsupported opcode for unwinding information");
988 case ARM::tMOVgpr2gpr:
989 case ARM::tMOVgpr2tgpr:
993 Offset = -MI->getOperand(2).getImm();
997 Offset = MI->getOperand(2).getImm();
1000 Offset = MI->getOperand(2).getImm()*4;
1004 Offset = -MI->getOperand(2).getImm()*4;
1006 case ARM::tLDRpci: {
1007 // Grab the constpool index and check, whether it corresponds to
1008 // original or cloned constpool entry.
1009 unsigned CPI = MI->getOperand(1).getIndex();
1010 const MachineConstantPool *MCP = MF.getConstantPool();
1011 if (CPI >= MCP->getConstants().size())
1012 CPI = AFI.getOriginalCPIdx(CPI);
1013 assert(CPI != -1U && "Invalid constpool index");
1015 // Derive the actual offset.
1016 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1017 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1018 // FIXME: Check for user, it should be "add" instruction!
1019 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1024 if (DstReg == FramePtr && FramePtr != ARM::SP)
1025 // Set-up of the frame pointer. Positive values correspond to "add"
1027 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1028 else if (DstReg == ARM::SP) {
1029 // Change of SP by an offset. Positive values correspond to "sub"
1031 OutStreamer.EmitPad(Offset);
1034 assert(0 && "Unsupported opcode for unwinding information");
1036 } else if (DstReg == ARM::SP) {
1037 // FIXME: .movsp goes here
1039 assert(0 && "Unsupported opcode for unwinding information");
1043 assert(0 && "Unsupported opcode for unwinding information");
1048 extern cl::opt<bool> EnableARMEHABI;
1050 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1051 unsigned Opc = MI->getOpcode();
1055 // B is just a Bcc with an 'always' predicate.
1057 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1058 TmpInst.setOpcode(ARM::Bcc);
1059 // Add predicate operands.
1060 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1061 TmpInst.addOperand(MCOperand::CreateReg(0));
1062 OutStreamer.EmitInstruction(TmpInst);
1065 case ARM::LDMIA_RET: {
1066 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
1067 // such has additional code-gen properties and scheduling information.
1068 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
1070 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1071 TmpInst.setOpcode(ARM::LDMIA_UPD);
1072 OutStreamer.EmitInstruction(TmpInst);
1075 case ARM::t2ADDrSPi:
1076 case ARM::t2ADDrSPi12:
1077 case ARM::t2SUBrSPi:
1078 case ARM::t2SUBrSPi12:
1079 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
1080 "Unexpected source register!");
1083 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1084 case ARM::DBG_VALUE: {
1085 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1086 SmallString<128> TmpStr;
1087 raw_svector_ostream OS(TmpStr);
1088 PrintDebugValueComment(MI, OS);
1089 OutStreamer.EmitRawText(StringRef(OS.str()));
1095 TmpInst.setOpcode(ARM::tBL);
1096 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
1097 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
1098 OutStreamer.EmitInstruction(TmpInst);
1102 case ARM::tLEApcrel:
1103 case ARM::t2LEApcrel: {
1104 // FIXME: Need to also handle globals and externals
1106 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1107 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1109 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1110 GetCPISymbol(MI->getOperand(1).getIndex()),
1111 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1113 OutStreamer.EmitInstruction(TmpInst);
1116 case ARM::LEApcrelJT:
1117 case ARM::tLEApcrelJT:
1118 case ARM::t2LEApcrelJT: {
1120 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1121 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1123 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1124 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1125 MI->getOperand(2).getImm()),
1126 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1128 OutStreamer.EmitInstruction(TmpInst);
1131 case ARM::MOVPCRX: {
1133 TmpInst.setOpcode(ARM::MOVr);
1134 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1135 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1136 // Add predicate operands.
1137 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1138 TmpInst.addOperand(MCOperand::CreateReg(0));
1139 // Add 's' bit operand (always reg0 for this)
1140 TmpInst.addOperand(MCOperand::CreateReg(0));
1141 OutStreamer.EmitInstruction(TmpInst);
1144 // Darwin call instructions are just normal call instructions with different
1145 // clobber semantics (they clobber R9).
1147 case ARM::BLr9_pred:
1149 case ARM::BLXr9_pred: {
1153 case ARM::BLr9: newOpc = ARM::BL; break;
1154 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1155 case ARM::BLXr9: newOpc = ARM::BLX; break;
1156 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1159 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1160 TmpInst.setOpcode(newOpc);
1161 OutStreamer.EmitInstruction(TmpInst);
1164 case ARM::BXr9_CALL:
1165 case ARM::BX_CALL: {
1168 TmpInst.setOpcode(ARM::MOVr);
1169 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1170 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1171 // Add predicate operands.
1172 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1173 TmpInst.addOperand(MCOperand::CreateReg(0));
1174 // Add 's' bit operand (always reg0 for this)
1175 TmpInst.addOperand(MCOperand::CreateReg(0));
1176 OutStreamer.EmitInstruction(TmpInst);
1180 TmpInst.setOpcode(ARM::BX);
1181 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1182 OutStreamer.EmitInstruction(TmpInst);
1186 case ARM::tBXr9_CALL:
1187 case ARM::tBX_CALL: {
1190 TmpInst.setOpcode(ARM::tMOVr);
1191 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1192 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1193 OutStreamer.EmitInstruction(TmpInst);
1197 TmpInst.setOpcode(ARM::tBX);
1198 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1199 // Add predicate operands.
1200 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1201 TmpInst.addOperand(MCOperand::CreateReg(0));
1202 OutStreamer.EmitInstruction(TmpInst);
1206 case ARM::BMOVPCRXr9_CALL:
1207 case ARM::BMOVPCRX_CALL: {
1210 TmpInst.setOpcode(ARM::MOVr);
1211 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1212 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1213 // Add predicate operands.
1214 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1215 TmpInst.addOperand(MCOperand::CreateReg(0));
1216 // Add 's' bit operand (always reg0 for this)
1217 TmpInst.addOperand(MCOperand::CreateReg(0));
1218 OutStreamer.EmitInstruction(TmpInst);
1222 TmpInst.setOpcode(ARM::MOVr);
1223 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1224 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1225 // Add predicate operands.
1226 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1227 TmpInst.addOperand(MCOperand::CreateReg(0));
1228 // Add 's' bit operand (always reg0 for this)
1229 TmpInst.addOperand(MCOperand::CreateReg(0));
1230 OutStreamer.EmitInstruction(TmpInst);
1234 case ARM::MOVi16_ga_pcrel:
1235 case ARM::t2MOVi16_ga_pcrel: {
1237 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1238 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1240 unsigned TF = MI->getOperand(1).getTargetFlags();
1241 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1242 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1243 MCSymbol *GVSym = GetARMGVSymbol(GV);
1244 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1246 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1247 getFunctionNumber(),
1248 MI->getOperand(2).getImm(), OutContext);
1249 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1250 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1251 const MCExpr *PCRelExpr =
1252 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1253 MCBinaryExpr::CreateAdd(LabelSymExpr,
1254 MCConstantExpr::Create(PCAdj, OutContext),
1255 OutContext), OutContext), OutContext);
1256 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1258 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1259 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1262 // Add predicate operands.
1263 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1264 TmpInst.addOperand(MCOperand::CreateReg(0));
1265 // Add 's' bit operand (always reg0 for this)
1266 TmpInst.addOperand(MCOperand::CreateReg(0));
1267 OutStreamer.EmitInstruction(TmpInst);
1270 case ARM::MOVTi16_ga_pcrel:
1271 case ARM::t2MOVTi16_ga_pcrel: {
1273 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1274 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1275 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1276 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1278 unsigned TF = MI->getOperand(2).getTargetFlags();
1279 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1280 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1281 MCSymbol *GVSym = GetARMGVSymbol(GV);
1282 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1284 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1285 getFunctionNumber(),
1286 MI->getOperand(3).getImm(), OutContext);
1287 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1288 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1289 const MCExpr *PCRelExpr =
1290 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1291 MCBinaryExpr::CreateAdd(LabelSymExpr,
1292 MCConstantExpr::Create(PCAdj, OutContext),
1293 OutContext), OutContext), OutContext);
1294 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1296 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1297 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1299 // Add predicate operands.
1300 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1301 TmpInst.addOperand(MCOperand::CreateReg(0));
1302 // Add 's' bit operand (always reg0 for this)
1303 TmpInst.addOperand(MCOperand::CreateReg(0));
1304 OutStreamer.EmitInstruction(TmpInst);
1307 case ARM::tPICADD: {
1308 // This is a pseudo op for a label + instruction sequence, which looks like:
1311 // This adds the address of LPC0 to r0.
1314 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1315 getFunctionNumber(), MI->getOperand(2).getImm(),
1318 // Form and emit the add.
1320 AddInst.setOpcode(ARM::tADDhirr);
1321 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1322 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1323 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1324 // Add predicate operands.
1325 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 AddInst.addOperand(MCOperand::CreateReg(0));
1327 OutStreamer.EmitInstruction(AddInst);
1331 // This is a pseudo op for a label + instruction sequence, which looks like:
1334 // This adds the address of LPC0 to r0.
1337 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1338 getFunctionNumber(), MI->getOperand(2).getImm(),
1341 // Form and emit the add.
1343 AddInst.setOpcode(ARM::ADDrr);
1344 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1345 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1346 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1347 // Add predicate operands.
1348 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1349 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1350 // Add 's' bit operand (always reg0 for this)
1351 AddInst.addOperand(MCOperand::CreateReg(0));
1352 OutStreamer.EmitInstruction(AddInst);
1362 case ARM::PICLDRSH: {
1363 // This is a pseudo op for a label + instruction sequence, which looks like:
1366 // The LCP0 label is referenced by a constant pool entry in order to get
1367 // a PC-relative address at the ldr instruction.
1370 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1371 getFunctionNumber(), MI->getOperand(2).getImm(),
1374 // Form and emit the load
1376 switch (MI->getOpcode()) {
1378 llvm_unreachable("Unexpected opcode!");
1379 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1380 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1381 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1382 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1383 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1384 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1385 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1386 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1389 LdStInst.setOpcode(Opcode);
1390 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1391 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1392 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1393 LdStInst.addOperand(MCOperand::CreateImm(0));
1394 // Add predicate operands.
1395 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1396 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1397 OutStreamer.EmitInstruction(LdStInst);
1401 case ARM::CONSTPOOL_ENTRY: {
1402 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1403 /// in the function. The first operand is the ID# for this instruction, the
1404 /// second is the index into the MachineConstantPool that this is, the third
1405 /// is the size in bytes of this constant pool entry.
1406 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1407 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1410 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1412 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1413 if (MCPE.isMachineConstantPoolEntry())
1414 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1416 EmitGlobalConstant(MCPE.Val.ConstVal);
1420 case ARM::t2BR_JT: {
1421 // Lower and emit the instruction itself, then the jump table following it.
1423 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1424 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1425 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1426 // Add predicate operands.
1427 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1428 TmpInst.addOperand(MCOperand::CreateReg(0));
1429 OutStreamer.EmitInstruction(TmpInst);
1430 // Output the data for the jump table itself
1434 case ARM::t2TBB_JT: {
1435 // Lower and emit the instruction itself, then the jump table following it.
1438 TmpInst.setOpcode(ARM::t2TBB);
1439 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1440 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1441 // Add predicate operands.
1442 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1443 TmpInst.addOperand(MCOperand::CreateReg(0));
1444 OutStreamer.EmitInstruction(TmpInst);
1445 // Output the data for the jump table itself
1447 // Make sure the next instruction is 2-byte aligned.
1451 case ARM::t2TBH_JT: {
1452 // Lower and emit the instruction itself, then the jump table following it.
1455 TmpInst.setOpcode(ARM::t2TBH);
1456 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1457 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1458 // Add predicate operands.
1459 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1460 TmpInst.addOperand(MCOperand::CreateReg(0));
1461 OutStreamer.EmitInstruction(TmpInst);
1462 // Output the data for the jump table itself
1468 // Lower and emit the instruction itself, then the jump table following it.
1471 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1472 ARM::MOVr : ARM::tMOVgpr2gpr;
1473 TmpInst.setOpcode(Opc);
1474 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1475 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1476 // Add predicate operands.
1477 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1478 TmpInst.addOperand(MCOperand::CreateReg(0));
1479 // Add 's' bit operand (always reg0 for this)
1480 if (Opc == ARM::MOVr)
1481 TmpInst.addOperand(MCOperand::CreateReg(0));
1482 OutStreamer.EmitInstruction(TmpInst);
1484 // Make sure the Thumb jump table is 4-byte aligned.
1485 if (Opc == ARM::tMOVgpr2gpr)
1488 // Output the data for the jump table itself
1493 // Lower and emit the instruction itself, then the jump table following it.
1496 if (MI->getOperand(1).getReg() == 0) {
1498 TmpInst.setOpcode(ARM::LDRi12);
1499 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1500 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1501 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1503 TmpInst.setOpcode(ARM::LDRrs);
1504 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1505 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1506 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1507 TmpInst.addOperand(MCOperand::CreateImm(0));
1509 // Add predicate operands.
1510 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1511 TmpInst.addOperand(MCOperand::CreateReg(0));
1512 OutStreamer.EmitInstruction(TmpInst);
1514 // Output the data for the jump table itself
1518 case ARM::BR_JTadd: {
1519 // Lower and emit the instruction itself, then the jump table following it.
1520 // add pc, target, idx
1522 TmpInst.setOpcode(ARM::ADDrr);
1523 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1524 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1525 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1526 // Add predicate operands.
1527 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1528 TmpInst.addOperand(MCOperand::CreateReg(0));
1529 // Add 's' bit operand (always reg0 for this)
1530 TmpInst.addOperand(MCOperand::CreateReg(0));
1531 OutStreamer.EmitInstruction(TmpInst);
1533 // Output the data for the jump table itself
1538 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1539 // FIXME: Remove this special case when they do.
1540 if (!Subtarget->isTargetDarwin()) {
1541 //.long 0xe7ffdefe @ trap
1542 uint32_t Val = 0xe7ffdefeUL;
1543 OutStreamer.AddComment("trap");
1544 OutStreamer.EmitIntValue(Val, 4);
1550 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1551 // FIXME: Remove this special case when they do.
1552 if (!Subtarget->isTargetDarwin()) {
1553 //.short 57086 @ trap
1554 uint16_t Val = 0xdefe;
1555 OutStreamer.AddComment("trap");
1556 OutStreamer.EmitIntValue(Val, 2);
1561 case ARM::t2Int_eh_sjlj_setjmp:
1562 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1563 case ARM::tInt_eh_sjlj_setjmp: {
1564 // Two incoming args: GPR:$src, GPR:$val
1567 // str $val, [$src, #4]
1572 unsigned SrcReg = MI->getOperand(0).getReg();
1573 unsigned ValReg = MI->getOperand(1).getReg();
1574 MCSymbol *Label = GetARMSJLJEHLabel();
1577 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1578 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1579 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1581 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1582 OutStreamer.AddComment("eh_setjmp begin");
1583 OutStreamer.EmitInstruction(TmpInst);
1587 TmpInst.setOpcode(ARM::tADDi3);
1588 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1590 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1591 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1592 TmpInst.addOperand(MCOperand::CreateImm(7));
1594 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1595 TmpInst.addOperand(MCOperand::CreateReg(0));
1596 OutStreamer.EmitInstruction(TmpInst);
1600 TmpInst.setOpcode(ARM::tSTRi);
1601 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1602 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1603 // The offset immediate is #4. The operand value is scaled by 4 for the
1604 // tSTR instruction.
1605 TmpInst.addOperand(MCOperand::CreateImm(1));
1607 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1608 TmpInst.addOperand(MCOperand::CreateReg(0));
1609 OutStreamer.EmitInstruction(TmpInst);
1613 TmpInst.setOpcode(ARM::tMOVi8);
1614 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1615 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1616 TmpInst.addOperand(MCOperand::CreateImm(0));
1618 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1619 TmpInst.addOperand(MCOperand::CreateReg(0));
1620 OutStreamer.EmitInstruction(TmpInst);
1623 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1625 TmpInst.setOpcode(ARM::tB);
1626 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1627 OutStreamer.EmitInstruction(TmpInst);
1631 TmpInst.setOpcode(ARM::tMOVi8);
1632 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1633 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1634 TmpInst.addOperand(MCOperand::CreateImm(1));
1636 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1637 TmpInst.addOperand(MCOperand::CreateReg(0));
1638 OutStreamer.AddComment("eh_setjmp end");
1639 OutStreamer.EmitInstruction(TmpInst);
1641 OutStreamer.EmitLabel(Label);
1645 case ARM::Int_eh_sjlj_setjmp_nofp:
1646 case ARM::Int_eh_sjlj_setjmp: {
1647 // Two incoming args: GPR:$src, GPR:$val
1649 // str $val, [$src, #+4]
1653 unsigned SrcReg = MI->getOperand(0).getReg();
1654 unsigned ValReg = MI->getOperand(1).getReg();
1658 TmpInst.setOpcode(ARM::ADDri);
1659 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1660 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1661 TmpInst.addOperand(MCOperand::CreateImm(8));
1663 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1664 TmpInst.addOperand(MCOperand::CreateReg(0));
1665 // 's' bit operand (always reg0 for this).
1666 TmpInst.addOperand(MCOperand::CreateReg(0));
1667 OutStreamer.AddComment("eh_setjmp begin");
1668 OutStreamer.EmitInstruction(TmpInst);
1672 TmpInst.setOpcode(ARM::STRi12);
1673 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1674 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1675 TmpInst.addOperand(MCOperand::CreateImm(4));
1677 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1678 TmpInst.addOperand(MCOperand::CreateReg(0));
1679 OutStreamer.EmitInstruction(TmpInst);
1683 TmpInst.setOpcode(ARM::MOVi);
1684 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1685 TmpInst.addOperand(MCOperand::CreateImm(0));
1687 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1688 TmpInst.addOperand(MCOperand::CreateReg(0));
1689 // 's' bit operand (always reg0 for this).
1690 TmpInst.addOperand(MCOperand::CreateReg(0));
1691 OutStreamer.EmitInstruction(TmpInst);
1695 TmpInst.setOpcode(ARM::ADDri);
1696 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1697 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1698 TmpInst.addOperand(MCOperand::CreateImm(0));
1700 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1701 TmpInst.addOperand(MCOperand::CreateReg(0));
1702 // 's' bit operand (always reg0 for this).
1703 TmpInst.addOperand(MCOperand::CreateReg(0));
1704 OutStreamer.EmitInstruction(TmpInst);
1708 TmpInst.setOpcode(ARM::MOVi);
1709 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1710 TmpInst.addOperand(MCOperand::CreateImm(1));
1712 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1713 TmpInst.addOperand(MCOperand::CreateReg(0));
1714 // 's' bit operand (always reg0 for this).
1715 TmpInst.addOperand(MCOperand::CreateReg(0));
1716 OutStreamer.AddComment("eh_setjmp end");
1717 OutStreamer.EmitInstruction(TmpInst);
1721 case ARM::Int_eh_sjlj_longjmp: {
1722 // ldr sp, [$src, #8]
1723 // ldr $scratch, [$src, #4]
1726 unsigned SrcReg = MI->getOperand(0).getReg();
1727 unsigned ScratchReg = MI->getOperand(1).getReg();
1730 TmpInst.setOpcode(ARM::LDRi12);
1731 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1732 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1733 TmpInst.addOperand(MCOperand::CreateImm(8));
1735 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1736 TmpInst.addOperand(MCOperand::CreateReg(0));
1737 OutStreamer.EmitInstruction(TmpInst);
1741 TmpInst.setOpcode(ARM::LDRi12);
1742 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1743 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1744 TmpInst.addOperand(MCOperand::CreateImm(4));
1746 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1747 TmpInst.addOperand(MCOperand::CreateReg(0));
1748 OutStreamer.EmitInstruction(TmpInst);
1752 TmpInst.setOpcode(ARM::LDRi12);
1753 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1754 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1755 TmpInst.addOperand(MCOperand::CreateImm(0));
1757 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1758 TmpInst.addOperand(MCOperand::CreateReg(0));
1759 OutStreamer.EmitInstruction(TmpInst);
1763 TmpInst.setOpcode(ARM::BX);
1764 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1766 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1767 TmpInst.addOperand(MCOperand::CreateReg(0));
1768 OutStreamer.EmitInstruction(TmpInst);
1772 case ARM::tInt_eh_sjlj_longjmp: {
1773 // ldr $scratch, [$src, #8]
1775 // ldr $scratch, [$src, #4]
1778 unsigned SrcReg = MI->getOperand(0).getReg();
1779 unsigned ScratchReg = MI->getOperand(1).getReg();
1782 TmpInst.setOpcode(ARM::tLDRi);
1783 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1784 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1785 // The offset immediate is #8. The operand value is scaled by 4 for the
1786 // tLDR instruction.
1787 TmpInst.addOperand(MCOperand::CreateImm(2));
1789 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1790 TmpInst.addOperand(MCOperand::CreateReg(0));
1791 OutStreamer.EmitInstruction(TmpInst);
1795 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1796 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1797 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1799 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1800 TmpInst.addOperand(MCOperand::CreateReg(0));
1801 OutStreamer.EmitInstruction(TmpInst);
1805 TmpInst.setOpcode(ARM::tLDRi);
1806 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1807 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1808 TmpInst.addOperand(MCOperand::CreateImm(1));
1810 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1811 TmpInst.addOperand(MCOperand::CreateReg(0));
1812 OutStreamer.EmitInstruction(TmpInst);
1816 TmpInst.setOpcode(ARM::tLDRr);
1817 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1818 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1819 TmpInst.addOperand(MCOperand::CreateReg(0));
1821 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1822 TmpInst.addOperand(MCOperand::CreateReg(0));
1823 OutStreamer.EmitInstruction(TmpInst);
1827 TmpInst.setOpcode(ARM::tBX);
1828 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1830 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1831 TmpInst.addOperand(MCOperand::CreateReg(0));
1832 OutStreamer.EmitInstruction(TmpInst);
1836 // Tail jump branches are really just branch instructions with additional
1837 // code-gen attributes. Convert them to the canonical form here.
1839 case ARM::TAILJMPdND: {
1840 MCInst TmpInst, TmpInst2;
1841 // Lower the instruction as-is to get the operands properly converted.
1842 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1843 TmpInst.setOpcode(ARM::Bcc);
1844 TmpInst.addOperand(TmpInst2.getOperand(0));
1845 // Add predicate operands.
1846 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1847 TmpInst.addOperand(MCOperand::CreateReg(0));
1848 OutStreamer.AddComment("TAILCALL");
1849 OutStreamer.EmitInstruction(TmpInst);
1852 case ARM::tTAILJMPd:
1853 case ARM::tTAILJMPdND: {
1854 MCInst TmpInst, TmpInst2;
1855 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1856 // The Darwin toolchain doesn't support tail call relocations of 16-bit
1858 TmpInst.setOpcode(Opc == ARM::tTAILJMPd ? ARM::t2B : ARM::tB);
1859 TmpInst.addOperand(TmpInst2.getOperand(0));
1860 OutStreamer.AddComment("TAILCALL");
1861 OutStreamer.EmitInstruction(TmpInst);
1864 case ARM::TAILJMPrND:
1865 case ARM::tTAILJMPrND:
1867 case ARM::tTAILJMPr: {
1868 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1869 ? ARM::BX : ARM::tBX;
1871 TmpInst.setOpcode(newOpc);
1872 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1874 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1875 TmpInst.addOperand(MCOperand::CreateReg(0));
1876 OutStreamer.AddComment("TAILCALL");
1877 OutStreamer.EmitInstruction(TmpInst);
1881 // These are the pseudos created to comply with stricter operand restrictions
1882 // on ARMv5. Lower them now to "normal" instructions, since all the
1883 // restrictions are already satisfied.
1885 EmitPatchedInstruction(MI, ARM::MUL);
1888 EmitPatchedInstruction(MI, ARM::MLA);
1891 EmitPatchedInstruction(MI, ARM::SMULL);
1894 EmitPatchedInstruction(MI, ARM::UMULL);
1897 EmitPatchedInstruction(MI, ARM::SMLAL);
1900 EmitPatchedInstruction(MI, ARM::UMLAL);
1903 EmitPatchedInstruction(MI, ARM::UMAAL);
1908 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1910 // Emit unwinding stuff for frame-related instructions
1911 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1912 EmitUnwindingInstruction(MI);
1914 OutStreamer.EmitInstruction(TmpInst);
1917 //===----------------------------------------------------------------------===//
1918 // Target Registry Stuff
1919 //===----------------------------------------------------------------------===//
1921 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1923 unsigned SyntaxVariant,
1924 const MCAsmInfo &MAI) {
1925 if (SyntaxVariant == 0)
1926 return new ARMInstPrinter(TM, MAI);
1930 // Force static initialization.
1931 extern "C" void LLVMInitializeARMAsmPrinter() {
1932 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1933 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1935 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1936 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);