1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/Analysis/DebugInfo.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Module.h"
28 #include "llvm/Type.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/AsmPrinter.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCInst.h"
39 #include "llvm/MC/MCSectionMachO.h"
40 #include "llvm/MC/MCObjectStreamer.h"
41 #include "llvm/MC/MCStreamer.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Target/Mangler.h"
44 #include "llvm/Target/TargetData.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegistry.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/raw_ostream.h"
69 // Per section and per symbol attributes are not supported.
70 // To implement them we would need the ability to delay this emission
71 // until the assembly file is fully parsed/generated as only then do we
72 // know the symbol and section numbers.
73 class AttributeEmitter {
75 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
76 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
77 virtual void Finish() = 0;
80 class AsmAttributeEmitter : public AttributeEmitter {
84 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
85 void MaybeSwitchVendor(StringRef Vendor) { }
87 void EmitAttribute(unsigned Attribute, unsigned Value) {
88 Streamer.EmitRawText("\t.eabi_attribute " +
89 Twine(Attribute) + ", " + Twine(Value));
95 class ObjectAttributeEmitter : public AttributeEmitter {
96 MCObjectStreamer &Streamer;
99 StringRef CurrentVendor;
100 SmallString<64> Contents;
103 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
104 Streamer(Streamer_), CurrentVendor("") { }
106 void MaybeSwitchVendor(StringRef Vendor) {
107 assert(!Vendor.empty() && "Vendor cannot be empty.");
109 if (CurrentVendor.empty())
110 CurrentVendor = Vendor;
111 else if (CurrentVendor == Vendor)
116 CurrentVendor = Vendor;
118 SectionStart = Contents.size();
120 // Length of the data for this vendor.
121 Contents.append(4, (char)0);
123 Contents.append(Vendor.begin(), Vendor.end());
126 Contents += ARMBuildAttrs::File;
128 TagStart = Contents.size();
130 // Length of the data for this tag.
131 Contents.append(4, (char)0);
134 void EmitAttribute(unsigned Attribute, unsigned Value) {
135 // FIXME: should be ULEB
136 Contents += Attribute;
141 size_t EndPos = Contents.size();
144 *((uint32_t*)&Contents[SectionStart]) = EndPos - SectionStart;
146 // +1 since it includes the tag that came before it.
147 *((uint32_t*)&Contents[TagStart]) = EndPos - TagStart + 1;
149 Streamer.EmitBytes(Contents, 0);
153 class ARMAsmPrinter : public AsmPrinter {
155 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
156 /// make the right decision when printing asm code for different targets.
157 const ARMSubtarget *Subtarget;
159 /// AFI - Keep a pointer to ARMFunctionInfo for the current
161 ARMFunctionInfo *AFI;
163 /// MCP - Keep a pointer to constantpool entries of the current
165 const MachineConstantPool *MCP;
168 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
169 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
170 Subtarget = &TM.getSubtarget<ARMSubtarget>();
173 virtual const char *getPassName() const {
174 return "ARM Assembly Printer";
177 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
178 const char *Modifier = 0);
180 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
181 unsigned AsmVariant, const char *ExtraCode,
183 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
185 const char *ExtraCode, raw_ostream &O);
187 void EmitJumpTable(const MachineInstr *MI);
188 void EmitJump2Table(const MachineInstr *MI);
189 virtual void EmitInstruction(const MachineInstr *MI);
190 bool runOnMachineFunction(MachineFunction &F);
192 virtual void EmitConstantPool() {} // we emit constant pools customly!
193 virtual void EmitFunctionEntryLabel();
194 void EmitStartOfAsmFile(Module &M);
195 void EmitEndOfAsmFile(Module &M);
198 // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
199 void emitAttributes();
201 // Helper for ELF .o only
202 void emitARMAttributeSection();
205 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
207 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
208 MachineLocation Location;
209 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
210 // Frame address. Currently handles register +- offset only.
211 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
212 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
214 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
219 virtual unsigned getISAEncoding() {
220 // ARM/Darwin adds ISA to the DWARF info for each function.
221 if (!Subtarget->isTargetDarwin())
223 return Subtarget->isThumb() ?
224 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
227 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
228 const MachineBasicBlock *MBB) const;
229 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
231 MCSymbol *GetARMSJLJEHLabel(void) const;
233 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
235 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
236 SmallString<128> Str;
237 raw_svector_ostream OS(Str);
238 EmitMachineConstantPoolValue(MCPV, OS);
239 OutStreamer.EmitRawText(OS.str());
242 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
244 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
245 case 1: O << MAI->getData8bitsDirective(0); break;
246 case 2: O << MAI->getData16bitsDirective(0); break;
247 case 4: O << MAI->getData32bitsDirective(0); break;
248 default: assert(0 && "Unknown CPV size");
251 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
253 if (ACPV->isLSDA()) {
254 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
255 } else if (ACPV->isBlockAddress()) {
256 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
257 } else if (ACPV->isGlobalValue()) {
258 const GlobalValue *GV = ACPV->getGV();
259 bool isIndirect = Subtarget->isTargetDarwin() &&
260 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
262 O << *Mang->getSymbol(GV);
264 // FIXME: Remove this when Darwin transition to @GOT like syntax.
265 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
268 MachineModuleInfoMachO &MMIMachO =
269 MMI->getObjFileInfo<MachineModuleInfoMachO>();
270 MachineModuleInfoImpl::StubValueTy &StubSym =
271 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
272 MMIMachO.getGVStubEntry(Sym);
273 if (StubSym.getPointer() == 0)
274 StubSym = MachineModuleInfoImpl::
275 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
278 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
279 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
282 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
283 if (ACPV->getPCAdjustment() != 0) {
284 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
285 << getFunctionNumber() << "_" << ACPV->getLabelId()
286 << "+" << (unsigned)ACPV->getPCAdjustment();
287 if (ACPV->mustAddCurrentAddress())
293 } // end of anonymous namespace
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296 if (AFI->isThumbFunction()) {
297 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
298 if (!Subtarget->isTargetDarwin())
299 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
301 // This needs to emit to a temporary string to get properly quoted
302 // MCSymbols when they have spaces in them.
303 SmallString<128> Tmp;
304 raw_svector_ostream OS(Tmp);
305 OS << "\t.thumb_func\t" << *CurrentFnSym;
306 OutStreamer.EmitRawText(OS.str());
310 OutStreamer.EmitLabel(CurrentFnSym);
313 /// runOnMachineFunction - This uses the EmitInstruction()
314 /// method to print assembly for each instruction.
316 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
317 AFI = MF.getInfo<ARMFunctionInfo>();
318 MCP = MF.getConstantPool();
320 return AsmPrinter::runOnMachineFunction(MF);
323 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
324 raw_ostream &O, const char *Modifier) {
325 const MachineOperand &MO = MI->getOperand(OpNum);
326 unsigned TF = MO.getTargetFlags();
328 switch (MO.getType()) {
330 assert(0 && "<unknown operand type>");
331 case MachineOperand::MO_Register: {
332 unsigned Reg = MO.getReg();
333 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
334 assert(!MO.getSubReg() && "Subregs should be eliminated!");
335 O << ARMInstPrinter::getRegisterName(Reg);
338 case MachineOperand::MO_Immediate: {
339 int64_t Imm = MO.getImm();
341 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
342 (TF == ARMII::MO_LO16))
344 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
345 (TF == ARMII::MO_HI16))
350 case MachineOperand::MO_MachineBasicBlock:
351 O << *MO.getMBB()->getSymbol();
353 case MachineOperand::MO_GlobalAddress: {
354 const GlobalValue *GV = MO.getGlobal();
355 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
356 (TF & ARMII::MO_LO16))
358 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
359 (TF & ARMII::MO_HI16))
361 O << *Mang->getSymbol(GV);
363 printOffset(MO.getOffset(), O);
364 if (TF == ARMII::MO_PLT)
368 case MachineOperand::MO_ExternalSymbol: {
369 O << *GetExternalSymbolSymbol(MO.getSymbolName());
370 if (TF == ARMII::MO_PLT)
374 case MachineOperand::MO_ConstantPoolIndex:
375 O << *GetCPISymbol(MO.getIndex());
377 case MachineOperand::MO_JumpTableIndex:
378 O << *GetJTISymbol(MO.getIndex());
383 //===--------------------------------------------------------------------===//
385 MCSymbol *ARMAsmPrinter::
386 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
387 const MachineBasicBlock *MBB) const {
388 SmallString<60> Name;
389 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
390 << getFunctionNumber() << '_' << uid << '_' << uid2
391 << "_set_" << MBB->getNumber();
392 return OutContext.GetOrCreateSymbol(Name.str());
395 MCSymbol *ARMAsmPrinter::
396 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
397 SmallString<60> Name;
398 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
399 << getFunctionNumber() << '_' << uid << '_' << uid2;
400 return OutContext.GetOrCreateSymbol(Name.str());
404 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
405 SmallString<60> Name;
406 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
407 << getFunctionNumber();
408 return OutContext.GetOrCreateSymbol(Name.str());
411 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
412 unsigned AsmVariant, const char *ExtraCode,
414 // Does this asm operand have a single letter operand modifier?
415 if (ExtraCode && ExtraCode[0]) {
416 if (ExtraCode[1] != 0) return true; // Unknown modifier.
418 switch (ExtraCode[0]) {
419 default: return true; // Unknown modifier.
420 case 'a': // Print as a memory address.
421 if (MI->getOperand(OpNum).isReg()) {
423 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
428 case 'c': // Don't print "#" before an immediate operand.
429 if (!MI->getOperand(OpNum).isImm())
431 O << MI->getOperand(OpNum).getImm();
433 case 'P': // Print a VFP double precision register.
434 case 'q': // Print a NEON quad precision register.
435 printOperand(MI, OpNum, O);
440 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
445 printOperand(MI, OpNum, O);
449 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
450 unsigned OpNum, unsigned AsmVariant,
451 const char *ExtraCode,
453 if (ExtraCode && ExtraCode[0])
454 return true; // Unknown modifier.
456 const MachineOperand &MO = MI->getOperand(OpNum);
457 assert(MO.isReg() && "unexpected inline asm memory operand");
458 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
462 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
463 if (Subtarget->isTargetDarwin()) {
464 Reloc::Model RelocM = TM.getRelocationModel();
465 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
466 // Declare all the text sections up front (before the DWARF sections
467 // emitted by AsmPrinter::doInitialization) so the assembler will keep
468 // them together at the beginning of the object file. This helps
469 // avoid out-of-range branches that are due a fundamental limitation of
470 // the way symbol offsets are encoded with the current Darwin ARM
472 const TargetLoweringObjectFileMachO &TLOFMacho =
473 static_cast<const TargetLoweringObjectFileMachO &>(
474 getObjFileLowering());
475 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
476 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
477 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
478 if (RelocM == Reloc::DynamicNoPIC) {
479 const MCSection *sect =
480 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
481 MCSectionMachO::S_SYMBOL_STUBS,
482 12, SectionKind::getText());
483 OutStreamer.SwitchSection(sect);
485 const MCSection *sect =
486 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
487 MCSectionMachO::S_SYMBOL_STUBS,
488 16, SectionKind::getText());
489 OutStreamer.SwitchSection(sect);
491 const MCSection *StaticInitSect =
492 OutContext.getMachOSection("__TEXT", "__StaticInit",
493 MCSectionMachO::S_REGULAR |
494 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
495 SectionKind::getText());
496 OutStreamer.SwitchSection(StaticInitSect);
500 // Use unified assembler syntax.
501 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
503 // Emit ARM Build Attributes
504 if (Subtarget->isTargetELF()) {
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 if (Subtarget->isTargetDarwin()) {
513 // All darwin targets use mach-o.
514 const TargetLoweringObjectFileMachO &TLOFMacho =
515 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
516 MachineModuleInfoMachO &MMIMacho =
517 MMI->getObjFileInfo<MachineModuleInfoMachO>();
519 // Output non-lazy-pointers for external and common global variables.
520 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
522 if (!Stubs.empty()) {
523 // Switch with ".non_lazy_symbol_pointer" directive.
524 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
526 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
528 OutStreamer.EmitLabel(Stubs[i].first);
529 // .indirect_symbol _foo
530 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
531 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
534 // External to current translation unit.
535 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
537 // Internal to current translation unit.
539 // When we place the LSDA into the TEXT section, the type info
540 // pointers need to be indirect and pc-rel. We accomplish this by
541 // using NLPs; however, sometimes the types are local to the file.
542 // We need to fill in the value for the NLP in those cases.
543 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
545 4/*size*/, 0/*addrspace*/);
549 OutStreamer.AddBlankLine();
552 Stubs = MMIMacho.GetHiddenGVStubList();
553 if (!Stubs.empty()) {
554 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
556 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
558 OutStreamer.EmitLabel(Stubs[i].first);
560 OutStreamer.EmitValue(MCSymbolRefExpr::
561 Create(Stubs[i].second.getPointer(),
563 4/*size*/, 0/*addrspace*/);
567 OutStreamer.AddBlankLine();
570 // Funny Darwin hack: This flag tells the linker that no global symbols
571 // contain code that falls through to other global symbols (e.g. the obvious
572 // implementation of multiple entry points). If this doesn't occur, the
573 // linker can safely perform dead code stripping. Since LLVM never
574 // generates code that does this, it is always safe to set.
575 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
579 //===----------------------------------------------------------------------===//
580 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
582 // The following seem like one-off assembler flags, but they actually need
583 // to appear in the .ARM.attributes section in ELF.
584 // Instead of subclassing the MCELFStreamer, we do the work here.
586 void ARMAsmPrinter::emitAttributes() {
588 emitARMAttributeSection();
590 AttributeEmitter *AttrEmitter;
591 if (OutStreamer.hasRawTextSupport())
592 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
594 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
595 AttrEmitter = new ObjectAttributeEmitter(O);
598 AttrEmitter->MaybeSwitchVendor("aeabi");
600 std::string CPUString = Subtarget->getCPUString();
601 if (OutStreamer.hasRawTextSupport()) {
602 if (CPUString != "generic")
603 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
605 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
606 // FIXME: Why these defaults?
607 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
608 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
609 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
612 // FIXME: Emit FPU type
613 if (Subtarget->hasVFP2())
614 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
616 // Signal various FP modes.
618 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
619 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
622 if (NoInfsFPMath && NoNaNsFPMath)
623 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
625 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
627 // 8-bytes alignment stuff.
628 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
629 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
631 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
632 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
633 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
634 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
636 // FIXME: Should we signal R9 usage?
638 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
640 AttrEmitter->Finish();
644 void ARMAsmPrinter::emitARMAttributeSection() {
646 // [ <section-length> "vendor-name"
647 // [ <file-tag> <size> <attribute>*
648 // | <section-tag> <size> <section-number>* 0 <attribute>*
649 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
653 if (OutStreamer.hasRawTextSupport())
656 const ARMElfTargetObjectFile &TLOFELF =
657 static_cast<const ARMElfTargetObjectFile &>
658 (getObjFileLowering());
660 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
663 OutStreamer.EmitIntValue(0x41, 1);
666 //===----------------------------------------------------------------------===//
668 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
669 unsigned LabelId, MCContext &Ctx) {
671 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
672 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
676 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
677 unsigned Opcode = MI->getOpcode();
679 if (Opcode == ARM::BR_JTadd)
681 else if (Opcode == ARM::BR_JTm)
684 const MachineOperand &MO1 = MI->getOperand(OpNum);
685 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
686 unsigned JTI = MO1.getIndex();
688 // Emit a label for the jump table.
689 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
690 OutStreamer.EmitLabel(JTISymbol);
692 // Emit each entry of the table.
693 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
694 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
695 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
697 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
698 MachineBasicBlock *MBB = JTBBs[i];
699 // Construct an MCExpr for the entry. We want a value of the form:
700 // (BasicBlockAddr - TableBeginAddr)
702 // For example, a table with entries jumping to basic blocks BB0 and BB1
705 // .word (LBB0 - LJTI_0_0)
706 // .word (LBB1 - LJTI_0_0)
707 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
709 if (TM.getRelocationModel() == Reloc::PIC_)
710 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
713 OutStreamer.EmitValue(Expr, 4);
717 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
718 unsigned Opcode = MI->getOpcode();
719 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
720 const MachineOperand &MO1 = MI->getOperand(OpNum);
721 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
722 unsigned JTI = MO1.getIndex();
724 // Emit a label for the jump table.
725 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
726 OutStreamer.EmitLabel(JTISymbol);
728 // Emit each entry of the table.
729 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
730 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
731 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
732 unsigned OffsetWidth = 4;
733 if (MI->getOpcode() == ARM::t2TBB)
735 else if (MI->getOpcode() == ARM::t2TBH)
738 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
739 MachineBasicBlock *MBB = JTBBs[i];
740 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
742 // If this isn't a TBB or TBH, the entries are direct branch instructions.
743 if (OffsetWidth == 4) {
745 BrInst.setOpcode(ARM::t2B);
746 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
747 OutStreamer.EmitInstruction(BrInst);
750 // Otherwise it's an offset from the dispatch instruction. Construct an
751 // MCExpr for the entry. We want a value of the form:
752 // (BasicBlockAddr - TableBeginAddr) / 2
754 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
757 // .byte (LBB0 - LJTI_0_0) / 2
758 // .byte (LBB1 - LJTI_0_0) / 2
760 MCBinaryExpr::CreateSub(MBBSymbolExpr,
761 MCSymbolRefExpr::Create(JTISymbol, OutContext),
763 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
765 OutStreamer.EmitValue(Expr, OffsetWidth);
768 // Make sure the instruction that follows TBB is 2-byte aligned.
769 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
770 if (MI->getOpcode() == ARM::t2TBB)
774 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
776 unsigned NOps = MI->getNumOperands();
778 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
779 // cast away const; DIetc do not take const operands for some reason.
780 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
783 // Frame address. Currently handles register +- offset only.
784 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
785 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
788 printOperand(MI, NOps-2, OS);
791 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
792 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
793 switch (MI->getOpcode()) {
794 case ARM::t2MOVi32imm:
795 assert(0 && "Should be lowered by thumb2it pass");
797 case ARM::DBG_VALUE: {
798 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
799 SmallString<128> TmpStr;
800 raw_svector_ostream OS(TmpStr);
801 PrintDebugValueComment(MI, OS);
802 OutStreamer.EmitRawText(StringRef(OS.str()));
807 // This is a pseudo op for a label + instruction sequence, which looks like:
810 // This adds the address of LPC0 to r0.
813 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
814 getFunctionNumber(), MI->getOperand(2).getImm(),
817 // Form and emit the add.
819 AddInst.setOpcode(ARM::tADDhirr);
820 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
821 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
822 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
823 // Add predicate operands.
824 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
825 AddInst.addOperand(MCOperand::CreateReg(0));
826 OutStreamer.EmitInstruction(AddInst);
830 // This is a pseudo op for a label + instruction sequence, which looks like:
833 // This adds the address of LPC0 to r0.
836 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
837 getFunctionNumber(), MI->getOperand(2).getImm(),
840 // Form and emit the add.
842 AddInst.setOpcode(ARM::ADDrr);
843 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
844 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
845 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
846 // Add predicate operands.
847 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
848 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
849 // Add 's' bit operand (always reg0 for this)
850 AddInst.addOperand(MCOperand::CreateReg(0));
851 OutStreamer.EmitInstruction(AddInst);
861 case ARM::PICLDRSH: {
862 // This is a pseudo op for a label + instruction sequence, which looks like:
865 // The LCP0 label is referenced by a constant pool entry in order to get
866 // a PC-relative address at the ldr instruction.
869 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
870 getFunctionNumber(), MI->getOperand(2).getImm(),
873 // Form and emit the load
875 switch (MI->getOpcode()) {
877 llvm_unreachable("Unexpected opcode!");
878 case ARM::PICSTR: Opcode = ARM::STR; break;
879 case ARM::PICSTRB: Opcode = ARM::STRB; break;
880 case ARM::PICSTRH: Opcode = ARM::STRH; break;
881 case ARM::PICLDR: Opcode = ARM::LDR; break;
882 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
883 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
884 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
885 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
888 LdStInst.setOpcode(Opcode);
889 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
890 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
891 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
892 LdStInst.addOperand(MCOperand::CreateImm(0));
893 // Add predicate operands.
894 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
895 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
896 OutStreamer.EmitInstruction(LdStInst);
900 case ARM::CONSTPOOL_ENTRY: {
901 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
902 /// in the function. The first operand is the ID# for this instruction, the
903 /// second is the index into the MachineConstantPool that this is, the third
904 /// is the size in bytes of this constant pool entry.
905 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
906 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
909 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
911 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
912 if (MCPE.isMachineConstantPoolEntry())
913 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
915 EmitGlobalConstant(MCPE.Val.ConstVal);
919 case ARM::MOVi2pieces: {
920 // FIXME: We'd like to remove the asm string in the .td file, but the
921 // This is a hack that lowers as a two instruction sequence.
922 unsigned DstReg = MI->getOperand(0).getReg();
923 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
925 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
926 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
930 TmpInst.setOpcode(ARM::MOVi);
931 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
932 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
935 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
936 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
938 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
939 OutStreamer.EmitInstruction(TmpInst);
944 TmpInst.setOpcode(ARM::ORRri);
945 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
946 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
947 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
949 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
950 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
952 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
953 OutStreamer.EmitInstruction(TmpInst);
957 case ARM::MOVi32imm: {
958 // FIXME: We'd like to remove the asm string in the .td file, but the
959 // This is a hack that lowers as a two instruction sequence.
960 unsigned DstReg = MI->getOperand(0).getReg();
961 const MachineOperand &MO = MI->getOperand(1);
964 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
965 V1 = MCOperand::CreateImm(ImmVal & 65535);
966 V2 = MCOperand::CreateImm(ImmVal >> 16);
967 } else if (MO.isGlobal()) {
968 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
969 const MCSymbolRefExpr *SymRef1 =
970 MCSymbolRefExpr::Create(Symbol,
971 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
972 const MCSymbolRefExpr *SymRef2 =
973 MCSymbolRefExpr::Create(Symbol,
974 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
975 V1 = MCOperand::CreateExpr(SymRef1);
976 V2 = MCOperand::CreateExpr(SymRef2);
978 // FIXME: External symbol?
980 llvm_unreachable("cannot handle this operand");
985 TmpInst.setOpcode(ARM::MOVi16);
986 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
987 TmpInst.addOperand(V1); // lower16(imm)
990 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
991 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
993 OutStreamer.EmitInstruction(TmpInst);
998 TmpInst.setOpcode(ARM::MOVTi16);
999 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1000 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1001 TmpInst.addOperand(V2); // upper16(imm)
1004 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1005 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1007 OutStreamer.EmitInstruction(TmpInst);
1014 case ARM::t2BR_JT: {
1015 // Lower and emit the instruction itself, then the jump table following it.
1017 MCInstLowering.Lower(MI, TmpInst);
1018 OutStreamer.EmitInstruction(TmpInst);
1025 case ARM::BR_JTadd: {
1026 // Lower and emit the instruction itself, then the jump table following it.
1028 MCInstLowering.Lower(MI, TmpInst);
1029 OutStreamer.EmitInstruction(TmpInst);
1034 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1035 // FIXME: Remove this special case when they do.
1036 if (!Subtarget->isTargetDarwin()) {
1037 //.long 0xe7ffdefe @ trap
1038 uint32_t Val = 0xe7ffdefeUL;
1039 OutStreamer.AddComment("trap");
1040 OutStreamer.EmitIntValue(Val, 4);
1046 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1047 // FIXME: Remove this special case when they do.
1048 if (!Subtarget->isTargetDarwin()) {
1049 //.short 57086 @ trap
1050 uint16_t Val = 0xdefe;
1051 OutStreamer.AddComment("trap");
1052 OutStreamer.EmitIntValue(Val, 2);
1057 case ARM::t2Int_eh_sjlj_setjmp:
1058 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1059 case ARM::tInt_eh_sjlj_setjmp: {
1060 // Two incoming args: GPR:$src, GPR:$val
1063 // str $val, [$src, #4]
1068 unsigned SrcReg = MI->getOperand(0).getReg();
1069 unsigned ValReg = MI->getOperand(1).getReg();
1070 MCSymbol *Label = GetARMSJLJEHLabel();
1073 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1074 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1075 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1077 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1078 OutStreamer.AddComment("eh_setjmp begin");
1079 OutStreamer.EmitInstruction(TmpInst);
1083 TmpInst.setOpcode(ARM::tADDi3);
1084 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1086 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1087 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1088 TmpInst.addOperand(MCOperand::CreateImm(7));
1090 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1091 TmpInst.addOperand(MCOperand::CreateReg(0));
1092 OutStreamer.EmitInstruction(TmpInst);
1096 TmpInst.setOpcode(ARM::tSTR);
1097 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1098 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1099 // The offset immediate is #4. The operand value is scaled by 4 for the
1100 // tSTR instruction.
1101 TmpInst.addOperand(MCOperand::CreateImm(1));
1102 TmpInst.addOperand(MCOperand::CreateReg(0));
1104 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1105 TmpInst.addOperand(MCOperand::CreateReg(0));
1106 OutStreamer.EmitInstruction(TmpInst);
1110 TmpInst.setOpcode(ARM::tMOVi8);
1111 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1112 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1113 TmpInst.addOperand(MCOperand::CreateImm(0));
1115 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1116 TmpInst.addOperand(MCOperand::CreateReg(0));
1117 OutStreamer.EmitInstruction(TmpInst);
1120 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1122 TmpInst.setOpcode(ARM::tB);
1123 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1124 OutStreamer.EmitInstruction(TmpInst);
1128 TmpInst.setOpcode(ARM::tMOVi8);
1129 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1130 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1131 TmpInst.addOperand(MCOperand::CreateImm(1));
1133 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1134 TmpInst.addOperand(MCOperand::CreateReg(0));
1135 OutStreamer.AddComment("eh_setjmp end");
1136 OutStreamer.EmitInstruction(TmpInst);
1138 OutStreamer.EmitLabel(Label);
1142 case ARM::Int_eh_sjlj_setjmp_nofp:
1143 case ARM::Int_eh_sjlj_setjmp: {
1144 // Two incoming args: GPR:$src, GPR:$val
1146 // str $val, [$src, #+4]
1150 unsigned SrcReg = MI->getOperand(0).getReg();
1151 unsigned ValReg = MI->getOperand(1).getReg();
1155 TmpInst.setOpcode(ARM::ADDri);
1156 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1157 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1158 TmpInst.addOperand(MCOperand::CreateImm(8));
1160 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1161 TmpInst.addOperand(MCOperand::CreateReg(0));
1162 // 's' bit operand (always reg0 for this).
1163 TmpInst.addOperand(MCOperand::CreateReg(0));
1164 OutStreamer.AddComment("eh_setjmp begin");
1165 OutStreamer.EmitInstruction(TmpInst);
1169 TmpInst.setOpcode(ARM::STR);
1170 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1171 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1172 TmpInst.addOperand(MCOperand::CreateReg(0));
1173 TmpInst.addOperand(MCOperand::CreateImm(4));
1175 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1176 TmpInst.addOperand(MCOperand::CreateReg(0));
1177 OutStreamer.EmitInstruction(TmpInst);
1181 TmpInst.setOpcode(ARM::MOVi);
1182 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1183 TmpInst.addOperand(MCOperand::CreateImm(0));
1185 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1186 TmpInst.addOperand(MCOperand::CreateReg(0));
1187 // 's' bit operand (always reg0 for this).
1188 TmpInst.addOperand(MCOperand::CreateReg(0));
1189 OutStreamer.EmitInstruction(TmpInst);
1193 TmpInst.setOpcode(ARM::ADDri);
1194 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1195 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1196 TmpInst.addOperand(MCOperand::CreateImm(0));
1198 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1199 TmpInst.addOperand(MCOperand::CreateReg(0));
1200 // 's' bit operand (always reg0 for this).
1201 TmpInst.addOperand(MCOperand::CreateReg(0));
1202 OutStreamer.EmitInstruction(TmpInst);
1206 TmpInst.setOpcode(ARM::MOVi);
1207 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1208 TmpInst.addOperand(MCOperand::CreateImm(1));
1210 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1211 TmpInst.addOperand(MCOperand::CreateReg(0));
1212 // 's' bit operand (always reg0 for this).
1213 TmpInst.addOperand(MCOperand::CreateReg(0));
1214 OutStreamer.AddComment("eh_setjmp end");
1215 OutStreamer.EmitInstruction(TmpInst);
1219 case ARM::Int_eh_sjlj_longjmp: {
1220 // ldr sp, [$src, #8]
1221 // ldr $scratch, [$src, #4]
1224 unsigned SrcReg = MI->getOperand(0).getReg();
1225 unsigned ScratchReg = MI->getOperand(1).getReg();
1228 TmpInst.setOpcode(ARM::LDR);
1229 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1230 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1231 TmpInst.addOperand(MCOperand::CreateReg(0));
1232 TmpInst.addOperand(MCOperand::CreateImm(8));
1234 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1235 TmpInst.addOperand(MCOperand::CreateReg(0));
1236 OutStreamer.EmitInstruction(TmpInst);
1240 TmpInst.setOpcode(ARM::LDR);
1241 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1242 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1243 TmpInst.addOperand(MCOperand::CreateReg(0));
1244 TmpInst.addOperand(MCOperand::CreateImm(4));
1246 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1247 TmpInst.addOperand(MCOperand::CreateReg(0));
1248 OutStreamer.EmitInstruction(TmpInst);
1252 TmpInst.setOpcode(ARM::LDR);
1253 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1254 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1255 TmpInst.addOperand(MCOperand::CreateReg(0));
1256 TmpInst.addOperand(MCOperand::CreateImm(0));
1258 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1259 TmpInst.addOperand(MCOperand::CreateReg(0));
1260 OutStreamer.EmitInstruction(TmpInst);
1264 TmpInst.setOpcode(ARM::BRIND);
1265 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1267 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1268 TmpInst.addOperand(MCOperand::CreateReg(0));
1269 OutStreamer.EmitInstruction(TmpInst);
1273 case ARM::tInt_eh_sjlj_longjmp: {
1274 // ldr $scratch, [$src, #8]
1276 // ldr $scratch, [$src, #4]
1279 unsigned SrcReg = MI->getOperand(0).getReg();
1280 unsigned ScratchReg = MI->getOperand(1).getReg();
1283 TmpInst.setOpcode(ARM::tLDR);
1284 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1285 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1286 // The offset immediate is #8. The operand value is scaled by 4 for the
1287 // tSTR instruction.
1288 TmpInst.addOperand(MCOperand::CreateImm(2));
1289 TmpInst.addOperand(MCOperand::CreateReg(0));
1291 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1292 TmpInst.addOperand(MCOperand::CreateReg(0));
1293 OutStreamer.EmitInstruction(TmpInst);
1297 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1298 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1299 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1301 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1302 TmpInst.addOperand(MCOperand::CreateReg(0));
1303 OutStreamer.EmitInstruction(TmpInst);
1307 TmpInst.setOpcode(ARM::tLDR);
1308 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1309 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1310 TmpInst.addOperand(MCOperand::CreateImm(1));
1311 TmpInst.addOperand(MCOperand::CreateReg(0));
1313 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1314 TmpInst.addOperand(MCOperand::CreateReg(0));
1315 OutStreamer.EmitInstruction(TmpInst);
1319 TmpInst.setOpcode(ARM::tLDR);
1320 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1321 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1322 TmpInst.addOperand(MCOperand::CreateImm(0));
1323 TmpInst.addOperand(MCOperand::CreateReg(0));
1325 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 TmpInst.addOperand(MCOperand::CreateReg(0));
1327 OutStreamer.EmitInstruction(TmpInst);
1331 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1332 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1334 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.EmitInstruction(TmpInst);
1343 MCInstLowering.Lower(MI, TmpInst);
1344 OutStreamer.EmitInstruction(TmpInst);
1347 //===----------------------------------------------------------------------===//
1348 // Target Registry Stuff
1349 //===----------------------------------------------------------------------===//
1351 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1352 unsigned SyntaxVariant,
1353 const MCAsmInfo &MAI) {
1354 if (SyntaxVariant == 0)
1355 return new ARMInstPrinter(MAI);
1359 // Force static initialization.
1360 extern "C" void LLVMInitializeARMAsmPrinter() {
1361 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1362 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1364 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1365 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);