1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DebugInfo.h"
30 #include "llvm/Module.h"
31 #include "llvm/Type.h"
32 #include "llvm/Assembly/Writer.h"
33 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/DataLayout.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/TargetRegistry.h"
51 #include "llvm/Support/raw_ostream.h"
57 // Per section and per symbol attributes are not supported.
58 // To implement them we would need the ability to delay this emission
59 // until the assembly file is fully parsed/generated as only then do we
60 // know the symbol and section numbers.
61 class AttributeEmitter {
63 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
64 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
65 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
66 virtual void Finish() = 0;
67 virtual ~AttributeEmitter() {}
70 class AsmAttributeEmitter : public AttributeEmitter {
74 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
75 void MaybeSwitchVendor(StringRef Vendor) { }
77 void EmitAttribute(unsigned Attribute, unsigned Value) {
78 Streamer.EmitRawText("\t.eabi_attribute " +
79 Twine(Attribute) + ", " + Twine(Value));
82 void EmitTextAttribute(unsigned Attribute, StringRef String) {
84 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
85 case ARMBuildAttrs::CPU_name:
86 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
88 /* GAS requires .fpu to be emitted regardless of EABI attribute */
89 case ARMBuildAttrs::Advanced_SIMD_arch:
90 case ARMBuildAttrs::VFP_arch:
91 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
98 class ObjectAttributeEmitter : public AttributeEmitter {
99 // This structure holds all attributes, accounting for
100 // their string/numeric value, so we can later emmit them
101 // in declaration order, keeping all in the same vector
102 struct AttributeItemType {
110 StringRef StringValue;
113 MCObjectStreamer &Streamer;
114 StringRef CurrentVendor;
115 SmallVector<AttributeItemType, 64> Contents;
117 // Account for the ULEB/String size of each item,
118 // not just the number of items
120 // FIXME: this should be in a more generic place, but
121 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
122 size_t getULEBSize(int Value) {
126 Size += sizeof(int8_t); // Is this really necessary?
132 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
133 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
135 void MaybeSwitchVendor(StringRef Vendor) {
136 assert(!Vendor.empty() && "Vendor cannot be empty.");
138 if (CurrentVendor.empty())
139 CurrentVendor = Vendor;
140 else if (CurrentVendor == Vendor)
145 CurrentVendor = Vendor;
147 assert(Contents.size() == 0);
150 void EmitAttribute(unsigned Attribute, unsigned Value) {
151 AttributeItemType attr = {
152 AttributeItemType::NumericAttribute,
157 ContentsSize += getULEBSize(Attribute);
158 ContentsSize += getULEBSize(Value);
159 Contents.push_back(attr);
162 void EmitTextAttribute(unsigned Attribute, StringRef String) {
163 AttributeItemType attr = {
164 AttributeItemType::TextAttribute,
169 ContentsSize += getULEBSize(Attribute);
171 ContentsSize += String.size()+1;
173 Contents.push_back(attr);
177 // Vendor size + Vendor name + '\0'
178 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
181 const size_t TagHeaderSize = 1 + 4;
183 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
184 Streamer.EmitBytes(CurrentVendor, 0);
185 Streamer.EmitIntValue(0, 1); // '\0'
187 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
188 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
190 // Size should have been accounted for already, now
191 // emit each field as its type (ULEB or String)
192 for (unsigned int i=0; i<Contents.size(); ++i) {
193 AttributeItemType item = Contents[i];
194 Streamer.EmitULEB128IntValue(item.Tag, 0);
196 default: llvm_unreachable("Invalid attribute type");
197 case AttributeItemType::NumericAttribute:
198 Streamer.EmitULEB128IntValue(item.IntValue, 0);
200 case AttributeItemType::TextAttribute:
201 Streamer.EmitBytes(item.StringValue.upper(), 0);
202 Streamer.EmitIntValue(0, 1); // '\0'
211 } // end of anonymous namespace
213 MachineLocation ARMAsmPrinter::
214 getDebugValueLocation(const MachineInstr *MI) const {
215 MachineLocation Location;
216 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
217 // Frame address. Currently handles register +- offset only.
218 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
219 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
221 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
226 /// EmitDwarfRegOp - Emit dwarf register operation.
227 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
228 const TargetRegisterInfo *RI = TM.getRegisterInfo();
229 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
230 AsmPrinter::EmitDwarfRegOp(MLoc);
232 unsigned Reg = MLoc.getReg();
233 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
234 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
235 // S registers are described as bit-pieces of a register
236 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
237 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
239 unsigned SReg = Reg - ARM::S0;
240 bool odd = SReg & 0x1;
241 unsigned Rx = 256 + (SReg >> 1);
243 OutStreamer.AddComment("DW_OP_regx for S register");
244 EmitInt8(dwarf::DW_OP_regx);
246 OutStreamer.AddComment(Twine(SReg));
250 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
251 EmitInt8(dwarf::DW_OP_bit_piece);
255 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
261 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
262 // Q registers Q0-Q15 are described by composing two D registers together.
263 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
266 unsigned QReg = Reg - ARM::Q0;
267 unsigned D1 = 256 + 2 * QReg;
268 unsigned D2 = D1 + 1;
270 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
271 EmitInt8(dwarf::DW_OP_regx);
273 OutStreamer.AddComment("DW_OP_piece 8");
274 EmitInt8(dwarf::DW_OP_piece);
277 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
278 EmitInt8(dwarf::DW_OP_regx);
280 OutStreamer.AddComment("DW_OP_piece 8");
281 EmitInt8(dwarf::DW_OP_piece);
287 void ARMAsmPrinter::EmitFunctionBodyEnd() {
288 // Make sure to terminate any constant pools that were at the end
292 InConstantPool = false;
293 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
296 void ARMAsmPrinter::EmitFunctionEntryLabel() {
297 if (AFI->isThumbFunction()) {
298 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
299 OutStreamer.EmitThumbFunc(CurrentFnSym);
302 OutStreamer.EmitLabel(CurrentFnSym);
305 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
306 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
307 assert(Size && "C++ constructor pointer had zero size!");
309 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
310 assert(GV && "C++ constructor pointer was not a GlobalValue!");
312 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
313 (Subtarget->isTargetDarwin()
314 ? MCSymbolRefExpr::VK_None
315 : MCSymbolRefExpr::VK_ARM_TARGET1),
318 OutStreamer.EmitValue(E, Size);
321 /// runOnMachineFunction - This uses the EmitInstruction()
322 /// method to print assembly for each instruction.
324 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
325 AFI = MF.getInfo<ARMFunctionInfo>();
326 MCP = MF.getConstantPool();
328 return AsmPrinter::runOnMachineFunction(MF);
331 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
332 raw_ostream &O, const char *Modifier) {
333 const MachineOperand &MO = MI->getOperand(OpNum);
334 unsigned TF = MO.getTargetFlags();
336 switch (MO.getType()) {
337 default: llvm_unreachable("<unknown operand type>");
338 case MachineOperand::MO_Register: {
339 unsigned Reg = MO.getReg();
340 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
341 assert(!MO.getSubReg() && "Subregs should be eliminated!");
342 O << ARMInstPrinter::getRegisterName(Reg);
345 case MachineOperand::MO_Immediate: {
346 int64_t Imm = MO.getImm();
348 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
349 (TF == ARMII::MO_LO16))
351 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
352 (TF == ARMII::MO_HI16))
357 case MachineOperand::MO_MachineBasicBlock:
358 O << *MO.getMBB()->getSymbol();
360 case MachineOperand::MO_GlobalAddress: {
361 const GlobalValue *GV = MO.getGlobal();
362 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
363 (TF & ARMII::MO_LO16))
365 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
366 (TF & ARMII::MO_HI16))
368 O << *Mang->getSymbol(GV);
370 printOffset(MO.getOffset(), O);
371 if (TF == ARMII::MO_PLT)
375 case MachineOperand::MO_ExternalSymbol: {
376 O << *GetExternalSymbolSymbol(MO.getSymbolName());
377 if (TF == ARMII::MO_PLT)
381 case MachineOperand::MO_ConstantPoolIndex:
382 O << *GetCPISymbol(MO.getIndex());
384 case MachineOperand::MO_JumpTableIndex:
385 O << *GetJTISymbol(MO.getIndex());
390 //===--------------------------------------------------------------------===//
392 MCSymbol *ARMAsmPrinter::
393 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
394 const MachineBasicBlock *MBB) const {
395 SmallString<60> Name;
396 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
397 << getFunctionNumber() << '_' << uid << '_' << uid2
398 << "_set_" << MBB->getNumber();
399 return OutContext.GetOrCreateSymbol(Name.str());
402 MCSymbol *ARMAsmPrinter::
403 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
404 SmallString<60> Name;
405 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
406 << getFunctionNumber() << '_' << uid << '_' << uid2;
407 return OutContext.GetOrCreateSymbol(Name.str());
411 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
412 SmallString<60> Name;
413 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
414 << getFunctionNumber();
415 return OutContext.GetOrCreateSymbol(Name.str());
418 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
419 unsigned AsmVariant, const char *ExtraCode,
421 // Does this asm operand have a single letter operand modifier?
422 if (ExtraCode && ExtraCode[0]) {
423 if (ExtraCode[1] != 0) return true; // Unknown modifier.
425 switch (ExtraCode[0]) {
427 // See if this is a generic print operand
428 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
429 case 'a': // Print as a memory address.
430 if (MI->getOperand(OpNum).isReg()) {
432 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
437 case 'c': // Don't print "#" before an immediate operand.
438 if (!MI->getOperand(OpNum).isImm())
440 O << MI->getOperand(OpNum).getImm();
442 case 'P': // Print a VFP double precision register.
443 case 'q': // Print a NEON quad precision register.
444 printOperand(MI, OpNum, O);
446 case 'y': // Print a VFP single precision register as indexed double.
447 if (MI->getOperand(OpNum).isReg()) {
448 unsigned Reg = MI->getOperand(OpNum).getReg();
449 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
450 // Find the 'd' register that has this 's' register as a sub-register,
451 // and determine the lane number.
452 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
453 if (!ARM::DPRRegClass.contains(*SR))
455 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
456 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
461 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
462 if (!MI->getOperand(OpNum).isImm())
464 O << ~(MI->getOperand(OpNum).getImm());
466 case 'L': // The low 16 bits of an immediate constant.
467 if (!MI->getOperand(OpNum).isImm())
469 O << (MI->getOperand(OpNum).getImm() & 0xffff);
471 case 'M': { // A register range suitable for LDM/STM.
472 if (!MI->getOperand(OpNum).isReg())
474 const MachineOperand &MO = MI->getOperand(OpNum);
475 unsigned RegBegin = MO.getReg();
476 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
477 // already got the operands in registers that are operands to the
478 // inline asm statement.
480 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
482 // FIXME: The register allocator not only may not have given us the
483 // registers in sequence, but may not be in ascending registers. This
484 // will require changes in the register allocator that'll need to be
485 // propagated down here if the operands change.
486 unsigned RegOps = OpNum + 1;
487 while (MI->getOperand(RegOps).isReg()) {
489 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
497 case 'R': // The most significant register of a pair.
498 case 'Q': { // The least significant register of a pair.
501 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
502 if (!FlagsOP.isImm())
504 unsigned Flags = FlagsOP.getImm();
505 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
508 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
509 if (RegOp >= MI->getNumOperands())
511 const MachineOperand &MO = MI->getOperand(RegOp);
514 unsigned Reg = MO.getReg();
515 O << ARMInstPrinter::getRegisterName(Reg);
519 case 'e': // The low doubleword register of a NEON quad register.
520 case 'f': { // The high doubleword register of a NEON quad register.
521 if (!MI->getOperand(OpNum).isReg())
523 unsigned Reg = MI->getOperand(OpNum).getReg();
524 if (!ARM::QPRRegClass.contains(Reg))
526 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
527 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
528 ARM::dsub_0 : ARM::dsub_1);
529 O << ARMInstPrinter::getRegisterName(SubReg);
533 // This modifier is not yet supported.
534 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
536 case 'H': { // The highest-numbered register of a pair.
537 const MachineOperand &MO = MI->getOperand(OpNum);
540 const TargetRegisterClass &RC = ARM::GPRRegClass;
541 const MachineFunction &MF = *MI->getParent()->getParent();
542 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
544 unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
545 RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
547 unsigned Reg = RC.getRegister(RegIdx);
548 O << ARMInstPrinter::getRegisterName(Reg);
554 printOperand(MI, OpNum, O);
558 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
559 unsigned OpNum, unsigned AsmVariant,
560 const char *ExtraCode,
562 // Does this asm operand have a single letter operand modifier?
563 if (ExtraCode && ExtraCode[0]) {
564 if (ExtraCode[1] != 0) return true; // Unknown modifier.
566 switch (ExtraCode[0]) {
567 case 'A': // A memory operand for a VLD1/VST1 instruction.
568 default: return true; // Unknown modifier.
569 case 'm': // The base register of a memory operand.
570 if (!MI->getOperand(OpNum).isReg())
572 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
577 const MachineOperand &MO = MI->getOperand(OpNum);
578 assert(MO.isReg() && "unexpected inline asm memory operand");
579 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
583 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
584 if (Subtarget->isTargetDarwin()) {
585 Reloc::Model RelocM = TM.getRelocationModel();
586 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
587 // Declare all the text sections up front (before the DWARF sections
588 // emitted by AsmPrinter::doInitialization) so the assembler will keep
589 // them together at the beginning of the object file. This helps
590 // avoid out-of-range branches that are due a fundamental limitation of
591 // the way symbol offsets are encoded with the current Darwin ARM
593 const TargetLoweringObjectFileMachO &TLOFMacho =
594 static_cast<const TargetLoweringObjectFileMachO &>(
595 getObjFileLowering());
597 // Collect the set of sections our functions will go into.
598 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
599 SmallPtrSet<const MCSection *, 8> > TextSections;
600 // Default text section comes first.
601 TextSections.insert(TLOFMacho.getTextSection());
602 // Now any user defined text sections from function attributes.
603 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
604 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
605 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
606 // Now the coalescable sections.
607 TextSections.insert(TLOFMacho.getTextCoalSection());
608 TextSections.insert(TLOFMacho.getConstTextCoalSection());
610 // Emit the sections in the .s file header to fix the order.
611 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
612 OutStreamer.SwitchSection(TextSections[i]);
614 if (RelocM == Reloc::DynamicNoPIC) {
615 const MCSection *sect =
616 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
617 MCSectionMachO::S_SYMBOL_STUBS,
618 12, SectionKind::getText());
619 OutStreamer.SwitchSection(sect);
621 const MCSection *sect =
622 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
623 MCSectionMachO::S_SYMBOL_STUBS,
624 16, SectionKind::getText());
625 OutStreamer.SwitchSection(sect);
627 const MCSection *StaticInitSect =
628 OutContext.getMachOSection("__TEXT", "__StaticInit",
629 MCSectionMachO::S_REGULAR |
630 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
631 SectionKind::getText());
632 OutStreamer.SwitchSection(StaticInitSect);
636 // Use unified assembler syntax.
637 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
639 // Emit ARM Build Attributes
640 if (Subtarget->isTargetELF())
645 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
646 if (Subtarget->isTargetDarwin()) {
647 // All darwin targets use mach-o.
648 const TargetLoweringObjectFileMachO &TLOFMacho =
649 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
650 MachineModuleInfoMachO &MMIMacho =
651 MMI->getObjFileInfo<MachineModuleInfoMachO>();
653 // Output non-lazy-pointers for external and common global variables.
654 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
656 if (!Stubs.empty()) {
657 // Switch with ".non_lazy_symbol_pointer" directive.
658 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
660 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
662 OutStreamer.EmitLabel(Stubs[i].first);
663 // .indirect_symbol _foo
664 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
665 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
668 // External to current translation unit.
669 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
671 // Internal to current translation unit.
673 // When we place the LSDA into the TEXT section, the type info
674 // pointers need to be indirect and pc-rel. We accomplish this by
675 // using NLPs; however, sometimes the types are local to the file.
676 // We need to fill in the value for the NLP in those cases.
677 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
679 4/*size*/, 0/*addrspace*/);
683 OutStreamer.AddBlankLine();
686 Stubs = MMIMacho.GetHiddenGVStubList();
687 if (!Stubs.empty()) {
688 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
690 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
692 OutStreamer.EmitLabel(Stubs[i].first);
694 OutStreamer.EmitValue(MCSymbolRefExpr::
695 Create(Stubs[i].second.getPointer(),
697 4/*size*/, 0/*addrspace*/);
701 OutStreamer.AddBlankLine();
704 // Funny Darwin hack: This flag tells the linker that no global symbols
705 // contain code that falls through to other global symbols (e.g. the obvious
706 // implementation of multiple entry points). If this doesn't occur, the
707 // linker can safely perform dead code stripping. Since LLVM never
708 // generates code that does this, it is always safe to set.
709 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
713 //===----------------------------------------------------------------------===//
714 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
716 // The following seem like one-off assembler flags, but they actually need
717 // to appear in the .ARM.attributes section in ELF.
718 // Instead of subclassing the MCELFStreamer, we do the work here.
720 void ARMAsmPrinter::emitAttributes() {
722 emitARMAttributeSection();
724 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
725 bool emitFPU = false;
726 AttributeEmitter *AttrEmitter;
727 if (OutStreamer.hasRawTextSupport()) {
728 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
731 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
732 AttrEmitter = new ObjectAttributeEmitter(O);
735 AttrEmitter->MaybeSwitchVendor("aeabi");
737 std::string CPUString = Subtarget->getCPUString();
739 if (CPUString == "cortex-a8" ||
740 Subtarget->isCortexA8()) {
741 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
742 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
743 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
744 ARMBuildAttrs::ApplicationProfile);
745 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
746 ARMBuildAttrs::Allowed);
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
748 ARMBuildAttrs::AllowThumb32);
749 // Fixme: figure out when this is emitted.
750 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
751 // ARMBuildAttrs::AllowWMMXv1);
754 /// ADD additional Else-cases here!
755 } else if (CPUString == "xscale") {
756 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
758 ARMBuildAttrs::Allowed);
759 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
760 ARMBuildAttrs::Allowed);
761 } else if (CPUString == "generic") {
762 // FIXME: Why these defaults?
763 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
764 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
765 ARMBuildAttrs::Allowed);
766 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
767 ARMBuildAttrs::Allowed);
770 if (Subtarget->hasNEON() && emitFPU) {
771 /* NEON is not exactly a VFP architecture, but GAS emit one of
772 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
773 if (Subtarget->hasVFP4())
774 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
777 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
778 /* If emitted for NEON, omit from VFP below, since you can have both
779 * NEON and VFP in build attributes but only one .fpu */
784 if (Subtarget->hasVFP4()) {
785 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
786 ARMBuildAttrs::AllowFPv4A);
788 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
791 } else if (Subtarget->hasVFP3()) {
792 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
793 ARMBuildAttrs::AllowFPv3A);
795 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
798 } else if (Subtarget->hasVFP2()) {
799 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
800 ARMBuildAttrs::AllowFPv2);
802 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
805 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
806 * since NEON can have 1 (allowed) or 2 (MAC operations) */
807 if (Subtarget->hasNEON()) {
808 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
809 ARMBuildAttrs::Allowed);
812 // Signal various FP modes.
813 if (!TM.Options.UnsafeFPMath) {
814 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
815 ARMBuildAttrs::Allowed);
816 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
817 ARMBuildAttrs::Allowed);
820 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
821 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
822 ARMBuildAttrs::Allowed);
824 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
825 ARMBuildAttrs::AllowIEE754);
827 // FIXME: add more flags to ARMBuildAttrs.h
828 // 8-bytes alignment stuff.
829 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
830 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
832 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
833 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
834 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
835 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
837 // FIXME: Should we signal R9 usage?
839 if (Subtarget->hasDivide())
840 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
842 AttrEmitter->Finish();
846 void ARMAsmPrinter::emitARMAttributeSection() {
848 // [ <section-length> "vendor-name"
849 // [ <file-tag> <size> <attribute>*
850 // | <section-tag> <size> <section-number>* 0 <attribute>*
851 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
855 if (OutStreamer.hasRawTextSupport())
858 const ARMElfTargetObjectFile &TLOFELF =
859 static_cast<const ARMElfTargetObjectFile &>
860 (getObjFileLowering());
862 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
865 OutStreamer.EmitIntValue(0x41, 1);
868 //===----------------------------------------------------------------------===//
870 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
871 unsigned LabelId, MCContext &Ctx) {
873 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
874 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
878 static MCSymbolRefExpr::VariantKind
879 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
881 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
882 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
883 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
884 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
885 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
886 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
888 llvm_unreachable("Invalid ARMCPModifier!");
891 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
892 bool isIndirect = Subtarget->isTargetDarwin() &&
893 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
895 return Mang->getSymbol(GV);
897 // FIXME: Remove this when Darwin transition to @GOT like syntax.
898 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
899 MachineModuleInfoMachO &MMIMachO =
900 MMI->getObjFileInfo<MachineModuleInfoMachO>();
901 MachineModuleInfoImpl::StubValueTy &StubSym =
902 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
903 MMIMachO.getGVStubEntry(MCSym);
904 if (StubSym.getPointer() == 0)
905 StubSym = MachineModuleInfoImpl::
906 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
911 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
912 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
914 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
917 if (ACPV->isLSDA()) {
918 SmallString<128> Str;
919 raw_svector_ostream OS(Str);
920 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
921 MCSym = OutContext.GetOrCreateSymbol(OS.str());
922 } else if (ACPV->isBlockAddress()) {
923 const BlockAddress *BA =
924 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
925 MCSym = GetBlockAddressSymbol(BA);
926 } else if (ACPV->isGlobalValue()) {
927 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
928 MCSym = GetARMGVSymbol(GV);
929 } else if (ACPV->isMachineBasicBlock()) {
930 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
931 MCSym = MBB->getSymbol();
933 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
934 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
935 MCSym = GetExternalSymbolSymbol(Sym);
938 // Create an MCSymbol for the reference.
940 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
943 if (ACPV->getPCAdjustment()) {
944 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
948 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
950 MCBinaryExpr::CreateAdd(PCRelExpr,
951 MCConstantExpr::Create(ACPV->getPCAdjustment(),
954 if (ACPV->mustAddCurrentAddress()) {
955 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
956 // label, so just emit a local label end reference that instead.
957 MCSymbol *DotSym = OutContext.CreateTempSymbol();
958 OutStreamer.EmitLabel(DotSym);
959 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
960 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
962 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
964 OutStreamer.EmitValue(Expr, Size);
967 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
968 unsigned Opcode = MI->getOpcode();
970 if (Opcode == ARM::BR_JTadd)
972 else if (Opcode == ARM::BR_JTm)
975 const MachineOperand &MO1 = MI->getOperand(OpNum);
976 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
977 unsigned JTI = MO1.getIndex();
979 // Emit a label for the jump table.
980 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
981 OutStreamer.EmitLabel(JTISymbol);
983 // Mark the jump table as data-in-code.
984 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
986 // Emit each entry of the table.
987 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
988 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
989 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
991 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
992 MachineBasicBlock *MBB = JTBBs[i];
993 // Construct an MCExpr for the entry. We want a value of the form:
994 // (BasicBlockAddr - TableBeginAddr)
996 // For example, a table with entries jumping to basic blocks BB0 and BB1
999 // .word (LBB0 - LJTI_0_0)
1000 // .word (LBB1 - LJTI_0_0)
1001 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1003 if (TM.getRelocationModel() == Reloc::PIC_)
1004 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1007 // If we're generating a table of Thumb addresses in static relocation
1008 // model, we need to add one to keep interworking correctly.
1009 else if (AFI->isThumbFunction())
1010 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1012 OutStreamer.EmitValue(Expr, 4);
1014 // Mark the end of jump table data-in-code region.
1015 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1018 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1019 unsigned Opcode = MI->getOpcode();
1020 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1021 const MachineOperand &MO1 = MI->getOperand(OpNum);
1022 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1023 unsigned JTI = MO1.getIndex();
1025 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1026 OutStreamer.EmitLabel(JTISymbol);
1028 // Emit each entry of the table.
1029 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1030 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1031 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1032 unsigned OffsetWidth = 4;
1033 if (MI->getOpcode() == ARM::t2TBB_JT) {
1035 // Mark the jump table as data-in-code.
1036 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1037 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1039 // Mark the jump table as data-in-code.
1040 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1043 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1044 MachineBasicBlock *MBB = JTBBs[i];
1045 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1047 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1048 if (OffsetWidth == 4) {
1050 BrInst.setOpcode(ARM::t2B);
1051 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1052 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1053 BrInst.addOperand(MCOperand::CreateReg(0));
1054 OutStreamer.EmitInstruction(BrInst);
1057 // Otherwise it's an offset from the dispatch instruction. Construct an
1058 // MCExpr for the entry. We want a value of the form:
1059 // (BasicBlockAddr - TableBeginAddr) / 2
1061 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1064 // .byte (LBB0 - LJTI_0_0) / 2
1065 // .byte (LBB1 - LJTI_0_0) / 2
1066 const MCExpr *Expr =
1067 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1068 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1070 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1072 OutStreamer.EmitValue(Expr, OffsetWidth);
1074 // Mark the end of jump table data-in-code region. 32-bit offsets use
1075 // actual branch instructions here, so we don't mark those as a data-region
1077 if (OffsetWidth != 4)
1078 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1081 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1083 unsigned NOps = MI->getNumOperands();
1085 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1086 // cast away const; DIetc do not take const operands for some reason.
1087 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1090 // Frame address. Currently handles register +- offset only.
1091 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1092 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1095 printOperand(MI, NOps-2, OS);
1098 static void populateADROperands(MCInst &Inst, unsigned Dest,
1099 const MCSymbol *Label,
1100 unsigned pred, unsigned ccreg,
1102 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1103 Inst.addOperand(MCOperand::CreateReg(Dest));
1104 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1105 // Add predicate operands.
1106 Inst.addOperand(MCOperand::CreateImm(pred));
1107 Inst.addOperand(MCOperand::CreateReg(ccreg));
1110 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1114 // Emit the instruction as usual, just patch the opcode.
1115 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1116 TmpInst.setOpcode(Opcode);
1117 OutStreamer.EmitInstruction(TmpInst);
1120 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1121 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1122 "Only instruction which are involved into frame setup code are allowed");
1124 const MachineFunction &MF = *MI->getParent()->getParent();
1125 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1126 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1128 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1129 unsigned Opc = MI->getOpcode();
1130 unsigned SrcReg, DstReg;
1132 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1133 // Two special cases:
1134 // 1) tPUSH does not have src/dst regs.
1135 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1136 // load. Yes, this is pretty fragile, but for now I don't see better
1138 SrcReg = DstReg = ARM::SP;
1140 SrcReg = MI->getOperand(1).getReg();
1141 DstReg = MI->getOperand(0).getReg();
1144 // Try to figure out the unwinding opcode out of src / dst regs.
1145 if (MI->mayStore()) {
1147 assert(DstReg == ARM::SP &&
1148 "Only stack pointer as a destination reg is supported");
1150 SmallVector<unsigned, 4> RegList;
1151 // Skip src & dst reg, and pred ops.
1152 unsigned StartOp = 2 + 2;
1153 // Use all the operands.
1154 unsigned NumOffset = 0;
1159 llvm_unreachable("Unsupported opcode for unwinding information");
1161 // Special case here: no src & dst reg, but two extra imp ops.
1162 StartOp = 2; NumOffset = 2;
1163 case ARM::STMDB_UPD:
1164 case ARM::t2STMDB_UPD:
1165 case ARM::VSTMDDB_UPD:
1166 assert(SrcReg == ARM::SP &&
1167 "Only stack pointer as a source reg is supported");
1168 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1170 const MachineOperand &MO = MI->getOperand(i);
1171 // Actually, there should never be any impdef stuff here. Skip it
1172 // temporary to workaround PR11902.
1173 if (MO.isImplicit())
1175 RegList.push_back(MO.getReg());
1178 case ARM::STR_PRE_IMM:
1179 case ARM::STR_PRE_REG:
1180 case ARM::t2STR_PRE:
1181 assert(MI->getOperand(2).getReg() == ARM::SP &&
1182 "Only stack pointer as a source reg is supported");
1183 RegList.push_back(SrcReg);
1186 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1188 // Changes of stack / frame pointer.
1189 if (SrcReg == ARM::SP) {
1194 llvm_unreachable("Unsupported opcode for unwinding information");
1200 Offset = -MI->getOperand(2).getImm();
1204 Offset = MI->getOperand(2).getImm();
1207 Offset = MI->getOperand(2).getImm()*4;
1211 Offset = -MI->getOperand(2).getImm()*4;
1213 case ARM::tLDRpci: {
1214 // Grab the constpool index and check, whether it corresponds to
1215 // original or cloned constpool entry.
1216 unsigned CPI = MI->getOperand(1).getIndex();
1217 const MachineConstantPool *MCP = MF.getConstantPool();
1218 if (CPI >= MCP->getConstants().size())
1219 CPI = AFI.getOriginalCPIdx(CPI);
1220 assert(CPI != -1U && "Invalid constpool index");
1222 // Derive the actual offset.
1223 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1224 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1225 // FIXME: Check for user, it should be "add" instruction!
1226 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1231 if (DstReg == FramePtr && FramePtr != ARM::SP)
1232 // Set-up of the frame pointer. Positive values correspond to "add"
1234 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1235 else if (DstReg == ARM::SP) {
1236 // Change of SP by an offset. Positive values correspond to "sub"
1238 OutStreamer.EmitPad(Offset);
1241 llvm_unreachable("Unsupported opcode for unwinding information");
1243 } else if (DstReg == ARM::SP) {
1244 // FIXME: .movsp goes here
1246 llvm_unreachable("Unsupported opcode for unwinding information");
1250 llvm_unreachable("Unsupported opcode for unwinding information");
1255 extern cl::opt<bool> EnableARMEHABI;
1257 // Simple pseudo-instructions have their lowering (with expansion to real
1258 // instructions) auto-generated.
1259 #include "ARMGenMCPseudoLowering.inc"
1261 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1262 // If we just ended a constant pool, mark it as such.
1263 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1264 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1265 InConstantPool = false;
1268 // Emit unwinding stuff for frame-related instructions
1269 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1270 EmitUnwindingInstruction(MI);
1272 // Do any auto-generated pseudo lowerings.
1273 if (emitPseudoExpansionLowering(OutStreamer, MI))
1276 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1277 "Pseudo flag setting opcode should be expanded early");
1279 // Check for manual lowerings.
1280 unsigned Opc = MI->getOpcode();
1282 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1283 case ARM::DBG_VALUE: {
1284 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1285 SmallString<128> TmpStr;
1286 raw_svector_ostream OS(TmpStr);
1287 PrintDebugValueComment(MI, OS);
1288 OutStreamer.EmitRawText(StringRef(OS.str()));
1293 case ARM::tLEApcrel:
1294 case ARM::t2LEApcrel: {
1295 // FIXME: Need to also handle globals and externals
1297 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1298 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1300 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1301 GetCPISymbol(MI->getOperand(1).getIndex()),
1302 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1304 OutStreamer.EmitInstruction(TmpInst);
1307 case ARM::LEApcrelJT:
1308 case ARM::tLEApcrelJT:
1309 case ARM::t2LEApcrelJT: {
1311 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1312 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1314 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1315 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1316 MI->getOperand(2).getImm()),
1317 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1319 OutStreamer.EmitInstruction(TmpInst);
1322 // Darwin call instructions are just normal call instructions with different
1323 // clobber semantics (they clobber R9).
1324 case ARM::BX_CALL: {
1327 TmpInst.setOpcode(ARM::MOVr);
1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1330 // Add predicate operands.
1331 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1332 TmpInst.addOperand(MCOperand::CreateReg(0));
1333 // Add 's' bit operand (always reg0 for this)
1334 TmpInst.addOperand(MCOperand::CreateReg(0));
1335 OutStreamer.EmitInstruction(TmpInst);
1339 TmpInst.setOpcode(ARM::BX);
1340 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1341 OutStreamer.EmitInstruction(TmpInst);
1345 case ARM::tBX_CALL: {
1348 TmpInst.setOpcode(ARM::tMOVr);
1349 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1350 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1351 // Add predicate operands.
1352 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1353 TmpInst.addOperand(MCOperand::CreateReg(0));
1354 OutStreamer.EmitInstruction(TmpInst);
1358 TmpInst.setOpcode(ARM::tBX);
1359 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1360 // Add predicate operands.
1361 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1362 TmpInst.addOperand(MCOperand::CreateReg(0));
1363 OutStreamer.EmitInstruction(TmpInst);
1367 case ARM::BMOVPCRX_CALL: {
1370 TmpInst.setOpcode(ARM::MOVr);
1371 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1372 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1373 // Add predicate operands.
1374 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1375 TmpInst.addOperand(MCOperand::CreateReg(0));
1376 // Add 's' bit operand (always reg0 for this)
1377 TmpInst.addOperand(MCOperand::CreateReg(0));
1378 OutStreamer.EmitInstruction(TmpInst);
1382 TmpInst.setOpcode(ARM::MOVr);
1383 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1384 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1385 // Add predicate operands.
1386 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1387 TmpInst.addOperand(MCOperand::CreateReg(0));
1388 // Add 's' bit operand (always reg0 for this)
1389 TmpInst.addOperand(MCOperand::CreateReg(0));
1390 OutStreamer.EmitInstruction(TmpInst);
1394 case ARM::BMOVPCB_CALL: {
1397 TmpInst.setOpcode(ARM::MOVr);
1398 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1399 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1400 // Add predicate operands.
1401 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1402 TmpInst.addOperand(MCOperand::CreateReg(0));
1403 // Add 's' bit operand (always reg0 for this)
1404 TmpInst.addOperand(MCOperand::CreateReg(0));
1405 OutStreamer.EmitInstruction(TmpInst);
1409 TmpInst.setOpcode(ARM::Bcc);
1410 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1411 MCSymbol *GVSym = Mang->getSymbol(GV);
1412 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1413 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1414 // Add predicate operands.
1415 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1416 TmpInst.addOperand(MCOperand::CreateReg(0));
1417 OutStreamer.EmitInstruction(TmpInst);
1421 case ARM::t2BMOVPCB_CALL: {
1424 TmpInst.setOpcode(ARM::tMOVr);
1425 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1426 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1427 // Add predicate operands.
1428 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1429 TmpInst.addOperand(MCOperand::CreateReg(0));
1430 OutStreamer.EmitInstruction(TmpInst);
1434 TmpInst.setOpcode(ARM::t2B);
1435 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1436 MCSymbol *GVSym = Mang->getSymbol(GV);
1437 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1438 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1439 // Add predicate operands.
1440 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1441 TmpInst.addOperand(MCOperand::CreateReg(0));
1442 OutStreamer.EmitInstruction(TmpInst);
1446 case ARM::MOVi16_ga_pcrel:
1447 case ARM::t2MOVi16_ga_pcrel: {
1449 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1450 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1452 unsigned TF = MI->getOperand(1).getTargetFlags();
1453 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1454 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1455 MCSymbol *GVSym = GetARMGVSymbol(GV);
1456 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1458 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1459 getFunctionNumber(),
1460 MI->getOperand(2).getImm(), OutContext);
1461 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1462 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1463 const MCExpr *PCRelExpr =
1464 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1465 MCBinaryExpr::CreateAdd(LabelSymExpr,
1466 MCConstantExpr::Create(PCAdj, OutContext),
1467 OutContext), OutContext), OutContext);
1468 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1470 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1471 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1474 // Add predicate operands.
1475 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1476 TmpInst.addOperand(MCOperand::CreateReg(0));
1477 // Add 's' bit operand (always reg0 for this)
1478 TmpInst.addOperand(MCOperand::CreateReg(0));
1479 OutStreamer.EmitInstruction(TmpInst);
1482 case ARM::MOVTi16_ga_pcrel:
1483 case ARM::t2MOVTi16_ga_pcrel: {
1485 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1486 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1487 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1488 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1490 unsigned TF = MI->getOperand(2).getTargetFlags();
1491 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1492 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1493 MCSymbol *GVSym = GetARMGVSymbol(GV);
1494 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1496 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1497 getFunctionNumber(),
1498 MI->getOperand(3).getImm(), OutContext);
1499 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1500 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1501 const MCExpr *PCRelExpr =
1502 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1503 MCBinaryExpr::CreateAdd(LabelSymExpr,
1504 MCConstantExpr::Create(PCAdj, OutContext),
1505 OutContext), OutContext), OutContext);
1506 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1508 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1509 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1511 // Add predicate operands.
1512 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1513 TmpInst.addOperand(MCOperand::CreateReg(0));
1514 // Add 's' bit operand (always reg0 for this)
1515 TmpInst.addOperand(MCOperand::CreateReg(0));
1516 OutStreamer.EmitInstruction(TmpInst);
1519 case ARM::tPICADD: {
1520 // This is a pseudo op for a label + instruction sequence, which looks like:
1523 // This adds the address of LPC0 to r0.
1526 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1527 getFunctionNumber(), MI->getOperand(2).getImm(),
1530 // Form and emit the add.
1532 AddInst.setOpcode(ARM::tADDhirr);
1533 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1534 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1535 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1536 // Add predicate operands.
1537 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1538 AddInst.addOperand(MCOperand::CreateReg(0));
1539 OutStreamer.EmitInstruction(AddInst);
1543 // This is a pseudo op for a label + instruction sequence, which looks like:
1546 // This adds the address of LPC0 to r0.
1549 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1550 getFunctionNumber(), MI->getOperand(2).getImm(),
1553 // Form and emit the add.
1555 AddInst.setOpcode(ARM::ADDrr);
1556 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1557 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1558 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1559 // Add predicate operands.
1560 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1561 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1562 // Add 's' bit operand (always reg0 for this)
1563 AddInst.addOperand(MCOperand::CreateReg(0));
1564 OutStreamer.EmitInstruction(AddInst);
1574 case ARM::PICLDRSH: {
1575 // This is a pseudo op for a label + instruction sequence, which looks like:
1578 // The LCP0 label is referenced by a constant pool entry in order to get
1579 // a PC-relative address at the ldr instruction.
1582 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1583 getFunctionNumber(), MI->getOperand(2).getImm(),
1586 // Form and emit the load
1588 switch (MI->getOpcode()) {
1590 llvm_unreachable("Unexpected opcode!");
1591 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1592 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1593 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1594 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1595 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1596 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1597 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1598 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1601 LdStInst.setOpcode(Opcode);
1602 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1603 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1604 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1605 LdStInst.addOperand(MCOperand::CreateImm(0));
1606 // Add predicate operands.
1607 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1608 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1609 OutStreamer.EmitInstruction(LdStInst);
1613 case ARM::CONSTPOOL_ENTRY: {
1614 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1615 /// in the function. The first operand is the ID# for this instruction, the
1616 /// second is the index into the MachineConstantPool that this is, the third
1617 /// is the size in bytes of this constant pool entry.
1618 /// The required alignment is specified on the basic block holding this MI.
1619 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1620 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1622 // If this is the first entry of the pool, mark it.
1623 if (!InConstantPool) {
1624 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1625 InConstantPool = true;
1628 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1630 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1631 if (MCPE.isMachineConstantPoolEntry())
1632 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1634 EmitGlobalConstant(MCPE.Val.ConstVal);
1637 case ARM::t2BR_JT: {
1638 // Lower and emit the instruction itself, then the jump table following it.
1640 TmpInst.setOpcode(ARM::tMOVr);
1641 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1642 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1643 // Add predicate operands.
1644 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1645 TmpInst.addOperand(MCOperand::CreateReg(0));
1646 OutStreamer.EmitInstruction(TmpInst);
1647 // Output the data for the jump table itself
1651 case ARM::t2TBB_JT: {
1652 // Lower and emit the instruction itself, then the jump table following it.
1655 TmpInst.setOpcode(ARM::t2TBB);
1656 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1657 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1658 // Add predicate operands.
1659 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1660 TmpInst.addOperand(MCOperand::CreateReg(0));
1661 OutStreamer.EmitInstruction(TmpInst);
1662 // Output the data for the jump table itself
1664 // Make sure the next instruction is 2-byte aligned.
1668 case ARM::t2TBH_JT: {
1669 // Lower and emit the instruction itself, then the jump table following it.
1672 TmpInst.setOpcode(ARM::t2TBH);
1673 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1674 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1675 // Add predicate operands.
1676 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1677 TmpInst.addOperand(MCOperand::CreateReg(0));
1678 OutStreamer.EmitInstruction(TmpInst);
1679 // Output the data for the jump table itself
1685 // Lower and emit the instruction itself, then the jump table following it.
1688 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1689 ARM::MOVr : ARM::tMOVr;
1690 TmpInst.setOpcode(Opc);
1691 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1692 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1693 // Add predicate operands.
1694 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1695 TmpInst.addOperand(MCOperand::CreateReg(0));
1696 // Add 's' bit operand (always reg0 for this)
1697 if (Opc == ARM::MOVr)
1698 TmpInst.addOperand(MCOperand::CreateReg(0));
1699 OutStreamer.EmitInstruction(TmpInst);
1701 // Make sure the Thumb jump table is 4-byte aligned.
1702 if (Opc == ARM::tMOVr)
1705 // Output the data for the jump table itself
1710 // Lower and emit the instruction itself, then the jump table following it.
1713 if (MI->getOperand(1).getReg() == 0) {
1715 TmpInst.setOpcode(ARM::LDRi12);
1716 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1717 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1718 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1720 TmpInst.setOpcode(ARM::LDRrs);
1721 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1722 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1723 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1724 TmpInst.addOperand(MCOperand::CreateImm(0));
1726 // Add predicate operands.
1727 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1728 TmpInst.addOperand(MCOperand::CreateReg(0));
1729 OutStreamer.EmitInstruction(TmpInst);
1731 // Output the data for the jump table itself
1735 case ARM::BR_JTadd: {
1736 // Lower and emit the instruction itself, then the jump table following it.
1737 // add pc, target, idx
1739 TmpInst.setOpcode(ARM::ADDrr);
1740 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1741 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1742 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1743 // Add predicate operands.
1744 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1745 TmpInst.addOperand(MCOperand::CreateReg(0));
1746 // Add 's' bit operand (always reg0 for this)
1747 TmpInst.addOperand(MCOperand::CreateReg(0));
1748 OutStreamer.EmitInstruction(TmpInst);
1750 // Output the data for the jump table itself
1755 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1756 // FIXME: Remove this special case when they do.
1757 if (!Subtarget->isTargetDarwin()) {
1758 //.long 0xe7ffdefe @ trap
1759 uint32_t Val = 0xe7ffdefeUL;
1760 OutStreamer.AddComment("trap");
1761 OutStreamer.EmitIntValue(Val, 4);
1767 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1768 // FIXME: Remove this special case when they do.
1769 if (!Subtarget->isTargetDarwin()) {
1770 //.short 57086 @ trap
1771 uint16_t Val = 0xdefe;
1772 OutStreamer.AddComment("trap");
1773 OutStreamer.EmitIntValue(Val, 2);
1778 case ARM::t2Int_eh_sjlj_setjmp:
1779 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1780 case ARM::tInt_eh_sjlj_setjmp: {
1781 // Two incoming args: GPR:$src, GPR:$val
1784 // str $val, [$src, #4]
1789 unsigned SrcReg = MI->getOperand(0).getReg();
1790 unsigned ValReg = MI->getOperand(1).getReg();
1791 MCSymbol *Label = GetARMSJLJEHLabel();
1794 TmpInst.setOpcode(ARM::tMOVr);
1795 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1796 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1798 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1799 TmpInst.addOperand(MCOperand::CreateReg(0));
1800 OutStreamer.AddComment("eh_setjmp begin");
1801 OutStreamer.EmitInstruction(TmpInst);
1805 TmpInst.setOpcode(ARM::tADDi3);
1806 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1808 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1809 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1810 TmpInst.addOperand(MCOperand::CreateImm(7));
1812 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1813 TmpInst.addOperand(MCOperand::CreateReg(0));
1814 OutStreamer.EmitInstruction(TmpInst);
1818 TmpInst.setOpcode(ARM::tSTRi);
1819 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1820 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1821 // The offset immediate is #4. The operand value is scaled by 4 for the
1822 // tSTR instruction.
1823 TmpInst.addOperand(MCOperand::CreateImm(1));
1825 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1826 TmpInst.addOperand(MCOperand::CreateReg(0));
1827 OutStreamer.EmitInstruction(TmpInst);
1831 TmpInst.setOpcode(ARM::tMOVi8);
1832 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1833 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1834 TmpInst.addOperand(MCOperand::CreateImm(0));
1836 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1837 TmpInst.addOperand(MCOperand::CreateReg(0));
1838 OutStreamer.EmitInstruction(TmpInst);
1841 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1843 TmpInst.setOpcode(ARM::tB);
1844 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1845 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1846 TmpInst.addOperand(MCOperand::CreateReg(0));
1847 OutStreamer.EmitInstruction(TmpInst);
1851 TmpInst.setOpcode(ARM::tMOVi8);
1852 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1853 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1854 TmpInst.addOperand(MCOperand::CreateImm(1));
1856 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1857 TmpInst.addOperand(MCOperand::CreateReg(0));
1858 OutStreamer.AddComment("eh_setjmp end");
1859 OutStreamer.EmitInstruction(TmpInst);
1861 OutStreamer.EmitLabel(Label);
1865 case ARM::Int_eh_sjlj_setjmp_nofp:
1866 case ARM::Int_eh_sjlj_setjmp: {
1867 // Two incoming args: GPR:$src, GPR:$val
1869 // str $val, [$src, #+4]
1873 unsigned SrcReg = MI->getOperand(0).getReg();
1874 unsigned ValReg = MI->getOperand(1).getReg();
1878 TmpInst.setOpcode(ARM::ADDri);
1879 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1880 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1881 TmpInst.addOperand(MCOperand::CreateImm(8));
1883 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1884 TmpInst.addOperand(MCOperand::CreateReg(0));
1885 // 's' bit operand (always reg0 for this).
1886 TmpInst.addOperand(MCOperand::CreateReg(0));
1887 OutStreamer.AddComment("eh_setjmp begin");
1888 OutStreamer.EmitInstruction(TmpInst);
1892 TmpInst.setOpcode(ARM::STRi12);
1893 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1894 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1895 TmpInst.addOperand(MCOperand::CreateImm(4));
1897 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1898 TmpInst.addOperand(MCOperand::CreateReg(0));
1899 OutStreamer.EmitInstruction(TmpInst);
1903 TmpInst.setOpcode(ARM::MOVi);
1904 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1905 TmpInst.addOperand(MCOperand::CreateImm(0));
1907 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1908 TmpInst.addOperand(MCOperand::CreateReg(0));
1909 // 's' bit operand (always reg0 for this).
1910 TmpInst.addOperand(MCOperand::CreateReg(0));
1911 OutStreamer.EmitInstruction(TmpInst);
1915 TmpInst.setOpcode(ARM::ADDri);
1916 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1917 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1918 TmpInst.addOperand(MCOperand::CreateImm(0));
1920 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1921 TmpInst.addOperand(MCOperand::CreateReg(0));
1922 // 's' bit operand (always reg0 for this).
1923 TmpInst.addOperand(MCOperand::CreateReg(0));
1924 OutStreamer.EmitInstruction(TmpInst);
1928 TmpInst.setOpcode(ARM::MOVi);
1929 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1930 TmpInst.addOperand(MCOperand::CreateImm(1));
1932 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1933 TmpInst.addOperand(MCOperand::CreateReg(0));
1934 // 's' bit operand (always reg0 for this).
1935 TmpInst.addOperand(MCOperand::CreateReg(0));
1936 OutStreamer.AddComment("eh_setjmp end");
1937 OutStreamer.EmitInstruction(TmpInst);
1941 case ARM::Int_eh_sjlj_longjmp: {
1942 // ldr sp, [$src, #8]
1943 // ldr $scratch, [$src, #4]
1946 unsigned SrcReg = MI->getOperand(0).getReg();
1947 unsigned ScratchReg = MI->getOperand(1).getReg();
1950 TmpInst.setOpcode(ARM::LDRi12);
1951 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1952 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1953 TmpInst.addOperand(MCOperand::CreateImm(8));
1955 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1956 TmpInst.addOperand(MCOperand::CreateReg(0));
1957 OutStreamer.EmitInstruction(TmpInst);
1961 TmpInst.setOpcode(ARM::LDRi12);
1962 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1963 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1964 TmpInst.addOperand(MCOperand::CreateImm(4));
1966 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1967 TmpInst.addOperand(MCOperand::CreateReg(0));
1968 OutStreamer.EmitInstruction(TmpInst);
1972 TmpInst.setOpcode(ARM::LDRi12);
1973 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1974 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1975 TmpInst.addOperand(MCOperand::CreateImm(0));
1977 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1978 TmpInst.addOperand(MCOperand::CreateReg(0));
1979 OutStreamer.EmitInstruction(TmpInst);
1983 TmpInst.setOpcode(ARM::BX);
1984 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1986 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1987 TmpInst.addOperand(MCOperand::CreateReg(0));
1988 OutStreamer.EmitInstruction(TmpInst);
1992 case ARM::tInt_eh_sjlj_longjmp: {
1993 // ldr $scratch, [$src, #8]
1995 // ldr $scratch, [$src, #4]
1998 unsigned SrcReg = MI->getOperand(0).getReg();
1999 unsigned ScratchReg = MI->getOperand(1).getReg();
2002 TmpInst.setOpcode(ARM::tLDRi);
2003 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2004 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2005 // The offset immediate is #8. The operand value is scaled by 4 for the
2006 // tLDR instruction.
2007 TmpInst.addOperand(MCOperand::CreateImm(2));
2009 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2010 TmpInst.addOperand(MCOperand::CreateReg(0));
2011 OutStreamer.EmitInstruction(TmpInst);
2015 TmpInst.setOpcode(ARM::tMOVr);
2016 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
2017 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2019 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2020 TmpInst.addOperand(MCOperand::CreateReg(0));
2021 OutStreamer.EmitInstruction(TmpInst);
2025 TmpInst.setOpcode(ARM::tLDRi);
2026 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2027 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2028 TmpInst.addOperand(MCOperand::CreateImm(1));
2030 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2031 TmpInst.addOperand(MCOperand::CreateReg(0));
2032 OutStreamer.EmitInstruction(TmpInst);
2036 TmpInst.setOpcode(ARM::tLDRi);
2037 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2038 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2039 TmpInst.addOperand(MCOperand::CreateImm(0));
2041 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2042 TmpInst.addOperand(MCOperand::CreateReg(0));
2043 OutStreamer.EmitInstruction(TmpInst);
2047 TmpInst.setOpcode(ARM::tBX);
2048 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2050 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2051 TmpInst.addOperand(MCOperand::CreateReg(0));
2052 OutStreamer.EmitInstruction(TmpInst);
2059 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2061 OutStreamer.EmitInstruction(TmpInst);
2064 //===----------------------------------------------------------------------===//
2065 // Target Registry Stuff
2066 //===----------------------------------------------------------------------===//
2068 // Force static initialization.
2069 extern "C" void LLVMInitializeARMAsmPrinter() {
2070 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2071 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);