1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
21 #include "InstPrinter/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DebugInfo.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ARMBuildAttributes.h"
46 #include "llvm/Support/TargetParser.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
61 std::unique_ptr<MCStreamer> Streamer)
62 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
63 InConstantPool(false) {}
65 void ARMAsmPrinter::EmitFunctionBodyEnd() {
66 // Make sure to terminate any constant pools that were at the end
70 InConstantPool = false;
71 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
74 void ARMAsmPrinter::EmitFunctionEntryLabel() {
75 if (AFI->isThumbFunction()) {
76 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
77 OutStreamer->EmitThumbFunc(CurrentFnSym);
80 OutStreamer->EmitLabel(CurrentFnSym);
83 void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
84 uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!");
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!");
90 const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
97 OutStreamer->EmitValue(E, Size);
100 /// runOnMachineFunction - This uses the EmitInstruction()
101 /// method to print assembly for each instruction.
103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
104 AFI = MF.getInfo<ARMFunctionInfo>();
105 MCP = MF.getConstantPool();
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
108 SetupMachineFunction(MF);
110 if (Subtarget->isTargetCOFF()) {
111 bool Internal = MF.getFunction()->hasInternalLinkage();
112 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
113 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
114 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
116 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
117 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
118 OutStreamer->EmitCOFFSymbolType(Type);
119 OutStreamer->EndCOFFSymbolDef();
122 // Emit the rest of the function body.
125 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
126 // These are created per function, rather than per TU, since it's
127 // relatively easy to exceed the thumb branch range within a TU.
128 if (! ThumbIndirectPads.empty()) {
129 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
131 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
132 OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
133 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
134 .addReg(ThumbIndirectPads[i].first)
135 // Add predicate operands.
139 ThumbIndirectPads.clear();
142 // We didn't modify anything.
146 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
148 const MachineOperand &MO = MI->getOperand(OpNum);
149 unsigned TF = MO.getTargetFlags();
151 switch (MO.getType()) {
152 default: llvm_unreachable("<unknown operand type>");
153 case MachineOperand::MO_Register: {
154 unsigned Reg = MO.getReg();
155 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
156 assert(!MO.getSubReg() && "Subregs should be eliminated!");
157 if(ARM::GPRPairRegClass.contains(Reg)) {
158 const MachineFunction &MF = *MI->getParent()->getParent();
159 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
160 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
162 O << ARMInstPrinter::getRegisterName(Reg);
165 case MachineOperand::MO_Immediate: {
166 int64_t Imm = MO.getImm();
168 if (TF == ARMII::MO_LO16)
170 else if (TF == ARMII::MO_HI16)
175 case MachineOperand::MO_MachineBasicBlock:
176 MO.getMBB()->getSymbol()->print(O, MAI);
178 case MachineOperand::MO_GlobalAddress: {
179 const GlobalValue *GV = MO.getGlobal();
180 if (TF & ARMII::MO_LO16)
182 else if (TF & ARMII::MO_HI16)
184 GetARMGVSymbol(GV, TF)->print(O, MAI);
186 printOffset(MO.getOffset(), O);
187 if (TF == ARMII::MO_PLT)
191 case MachineOperand::MO_ConstantPoolIndex:
192 GetCPISymbol(MO.getIndex())->print(O, MAI);
197 //===--------------------------------------------------------------------===//
199 MCSymbol *ARMAsmPrinter::
200 GetARMJTIPICJumpTableLabel(unsigned uid) const {
201 const DataLayout &DL = getDataLayout();
202 SmallString<60> Name;
203 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
204 << getFunctionNumber() << '_' << uid;
205 return OutContext.getOrCreateSymbol(Name);
208 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
209 unsigned AsmVariant, const char *ExtraCode,
211 // Does this asm operand have a single letter operand modifier?
212 if (ExtraCode && ExtraCode[0]) {
213 if (ExtraCode[1] != 0) return true; // Unknown modifier.
215 switch (ExtraCode[0]) {
217 // See if this is a generic print operand
218 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
219 case 'a': // Print as a memory address.
220 if (MI->getOperand(OpNum).isReg()) {
222 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
227 case 'c': // Don't print "#" before an immediate operand.
228 if (!MI->getOperand(OpNum).isImm())
230 O << MI->getOperand(OpNum).getImm();
232 case 'P': // Print a VFP double precision register.
233 case 'q': // Print a NEON quad precision register.
234 printOperand(MI, OpNum, O);
236 case 'y': // Print a VFP single precision register as indexed double.
237 if (MI->getOperand(OpNum).isReg()) {
238 unsigned Reg = MI->getOperand(OpNum).getReg();
239 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
240 // Find the 'd' register that has this 's' register as a sub-register,
241 // and determine the lane number.
242 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
243 if (!ARM::DPRRegClass.contains(*SR))
245 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
246 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
251 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
252 if (!MI->getOperand(OpNum).isImm())
254 O << ~(MI->getOperand(OpNum).getImm());
256 case 'L': // The low 16 bits of an immediate constant.
257 if (!MI->getOperand(OpNum).isImm())
259 O << (MI->getOperand(OpNum).getImm() & 0xffff);
261 case 'M': { // A register range suitable for LDM/STM.
262 if (!MI->getOperand(OpNum).isReg())
264 const MachineOperand &MO = MI->getOperand(OpNum);
265 unsigned RegBegin = MO.getReg();
266 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
267 // already got the operands in registers that are operands to the
268 // inline asm statement.
270 if (ARM::GPRPairRegClass.contains(RegBegin)) {
271 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
272 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
273 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
274 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
276 O << ARMInstPrinter::getRegisterName(RegBegin);
278 // FIXME: The register allocator not only may not have given us the
279 // registers in sequence, but may not be in ascending registers. This
280 // will require changes in the register allocator that'll need to be
281 // propagated down here if the operands change.
282 unsigned RegOps = OpNum + 1;
283 while (MI->getOperand(RegOps).isReg()) {
285 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
293 case 'R': // The most significant register of a pair.
294 case 'Q': { // The least significant register of a pair.
297 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
298 if (!FlagsOP.isImm())
300 unsigned Flags = FlagsOP.getImm();
302 // This operand may not be the one that actually provides the register. If
303 // it's tied to a previous one then we should refer instead to that one
304 // for registers and their classes.
306 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
307 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
308 unsigned OpFlags = MI->getOperand(OpNum).getImm();
309 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
311 Flags = MI->getOperand(OpNum).getImm();
313 // Later code expects OpNum to be pointing at the register rather than
318 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
320 InlineAsm::hasRegClassConstraint(Flags, RC);
321 if (RC == ARM::GPRPairRegClassID) {
324 const MachineOperand &MO = MI->getOperand(OpNum);
327 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
328 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
329 ARM::gsub_0 : ARM::gsub_1);
330 O << ARMInstPrinter::getRegisterName(Reg);
335 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
336 if (RegOp >= MI->getNumOperands())
338 const MachineOperand &MO = MI->getOperand(RegOp);
341 unsigned Reg = MO.getReg();
342 O << ARMInstPrinter::getRegisterName(Reg);
346 case 'e': // The low doubleword register of a NEON quad register.
347 case 'f': { // The high doubleword register of a NEON quad register.
348 if (!MI->getOperand(OpNum).isReg())
350 unsigned Reg = MI->getOperand(OpNum).getReg();
351 if (!ARM::QPRRegClass.contains(Reg))
353 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
354 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
355 ARM::dsub_0 : ARM::dsub_1);
356 O << ARMInstPrinter::getRegisterName(SubReg);
360 // This modifier is not yet supported.
361 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
363 case 'H': { // The highest-numbered register of a pair.
364 const MachineOperand &MO = MI->getOperand(OpNum);
367 const MachineFunction &MF = *MI->getParent()->getParent();
368 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
369 unsigned Reg = MO.getReg();
370 if(!ARM::GPRPairRegClass.contains(Reg))
372 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
373 O << ARMInstPrinter::getRegisterName(Reg);
379 printOperand(MI, OpNum, O);
383 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
384 unsigned OpNum, unsigned AsmVariant,
385 const char *ExtraCode,
387 // Does this asm operand have a single letter operand modifier?
388 if (ExtraCode && ExtraCode[0]) {
389 if (ExtraCode[1] != 0) return true; // Unknown modifier.
391 switch (ExtraCode[0]) {
392 case 'A': // A memory operand for a VLD1/VST1 instruction.
393 default: return true; // Unknown modifier.
394 case 'm': // The base register of a memory operand.
395 if (!MI->getOperand(OpNum).isReg())
397 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
402 const MachineOperand &MO = MI->getOperand(OpNum);
403 assert(MO.isReg() && "unexpected inline asm memory operand");
404 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
408 static bool isThumb(const MCSubtargetInfo& STI) {
409 return STI.getFeatureBits()[ARM::ModeThumb];
412 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
413 const MCSubtargetInfo *EndInfo) const {
414 // If either end mode is unknown (EndInfo == NULL) or different than
415 // the start mode, then restore the start mode.
416 const bool WasThumb = isThumb(StartInfo);
417 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
418 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
422 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
423 const Triple &TT = TM.getTargetTriple();
424 // Use unified assembler syntax.
425 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
427 // Emit ARM Build Attributes
428 if (TT.isOSBinFormatELF())
431 // Use the triple's architecture and subarchitecture to determine
432 // if we're thumb for the purposes of the top level code16 assembler
434 bool isThumb = TT.getArch() == Triple::thumb ||
435 TT.getArch() == Triple::thumbeb ||
436 TT.getSubArch() == Triple::ARMSubArch_v7m ||
437 TT.getSubArch() == Triple::ARMSubArch_v6m;
438 if (!M.getModuleInlineAsm().empty() && isThumb)
439 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
443 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
444 MachineModuleInfoImpl::StubValueTy &MCSym) {
446 OutStreamer.EmitLabel(StubLabel);
447 // .indirect_symbol _foo
448 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
451 // External to current translation unit.
452 OutStreamer.EmitIntValue(0, 4/*size*/);
454 // Internal to current translation unit.
456 // When we place the LSDA into the TEXT section, the type info
457 // pointers need to be indirect and pc-rel. We accomplish this by
458 // using NLPs; however, sometimes the types are local to the file.
459 // We need to fill in the value for the NLP in those cases.
460 OutStreamer.EmitValue(
461 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
466 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
467 const Triple &TT = TM.getTargetTriple();
468 if (TT.isOSBinFormatMachO()) {
469 // All darwin targets use mach-o.
470 const TargetLoweringObjectFileMachO &TLOFMacho =
471 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
472 MachineModuleInfoMachO &MMIMacho =
473 MMI->getObjFileInfo<MachineModuleInfoMachO>();
475 // Output non-lazy-pointers for external and common global variables.
476 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
478 if (!Stubs.empty()) {
479 // Switch with ".non_lazy_symbol_pointer" directive.
480 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
483 for (auto &Stub : Stubs)
484 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
487 OutStreamer->AddBlankLine();
490 Stubs = MMIMacho.GetHiddenGVStubList();
491 if (!Stubs.empty()) {
492 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
495 for (auto &Stub : Stubs)
496 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
499 OutStreamer->AddBlankLine();
502 // Funny Darwin hack: This flag tells the linker that no global symbols
503 // contain code that falls through to other global symbols (e.g. the obvious
504 // implementation of multiple entry points). If this doesn't occur, the
505 // linker can safely perform dead code stripping. Since LLVM never
506 // generates code that does this, it is always safe to set.
507 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
511 //===----------------------------------------------------------------------===//
512 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
514 // The following seem like one-off assembler flags, but they actually need
515 // to appear in the .ARM.attributes section in ELF.
516 // Instead of subclassing the MCELFStreamer, we do the work here.
518 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
519 const ARMSubtarget *Subtarget) {
521 return ARMBuildAttrs::v5TEJ;
523 if (Subtarget->hasV8Ops())
524 return ARMBuildAttrs::v8;
525 else if (Subtarget->hasV7Ops()) {
526 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
527 return ARMBuildAttrs::v7E_M;
528 return ARMBuildAttrs::v7;
529 } else if (Subtarget->hasV6T2Ops())
530 return ARMBuildAttrs::v6T2;
531 else if (Subtarget->hasV6MOps())
532 return ARMBuildAttrs::v6S_M;
533 else if (Subtarget->hasV6Ops())
534 return ARMBuildAttrs::v6;
535 else if (Subtarget->hasV5TEOps())
536 return ARMBuildAttrs::v5TE;
537 else if (Subtarget->hasV5TOps())
538 return ARMBuildAttrs::v5T;
539 else if (Subtarget->hasV4TOps())
540 return ARMBuildAttrs::v4T;
542 return ARMBuildAttrs::v4;
545 void ARMAsmPrinter::emitAttributes() {
546 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
547 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
549 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
551 ATS.switchVendor("aeabi");
553 // Compute ARM ELF Attributes based on the default subtarget that
554 // we'd have constructed. The existing ARM behavior isn't LTO clean
556 // FIXME: For ifunc related functions we could iterate over and look
557 // for a feature string that doesn't match the default one.
558 const Triple &TT = TM.getTargetTriple();
559 StringRef CPU = TM.getTargetCPU();
560 StringRef FS = TM.getTargetFeatureString();
561 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
564 ArchFS = (Twine(ArchFS) + "," + FS).str();
568 const ARMBaseTargetMachine &ATM =
569 static_cast<const ARMBaseTargetMachine &>(TM);
570 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
572 std::string CPUString = STI.getCPUString();
574 if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
575 // FIXME: remove krait check when GNU tools support krait cpu
577 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
578 // We consider krait as a "cortex-a9" + hwdiv CPU
579 // Enable hwdiv through ".arch_extension idiv"
580 if (STI.hasDivide() || STI.hasDivideInARMMode())
581 ATS.emitArchExtension(ARM::AEK_HWDIV);
583 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
586 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
588 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
589 // profile is not applicable (e.g. pre v7, or cross-profile code)".
590 if (STI.hasV7Ops()) {
591 if (STI.isAClass()) {
592 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
593 ARMBuildAttrs::ApplicationProfile);
594 } else if (STI.isRClass()) {
595 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
596 ARMBuildAttrs::RealTimeProfile);
597 } else if (STI.isMClass()) {
598 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
599 ARMBuildAttrs::MicroControllerProfile);
603 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
604 STI.hasARMOps() ? ARMBuildAttrs::Allowed
605 : ARMBuildAttrs::Not_Allowed);
606 if (STI.isThumb1Only()) {
607 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
608 } else if (STI.hasThumb2()) {
609 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
610 ARMBuildAttrs::AllowThumb32);
614 /* NEON is not exactly a VFP architecture, but GAS emit one of
615 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
616 if (STI.hasFPARMv8()) {
618 ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
620 ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
621 } else if (STI.hasVFP4())
622 ATS.emitFPU(ARM::FK_NEON_VFPV4);
624 ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
625 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
627 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
628 STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
629 ARMBuildAttrs::AllowNeonARMv8);
631 if (STI.hasFPARMv8())
632 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
633 // FPU, but there are two different names for it depending on the CPU.
634 ATS.emitFPU(STI.hasD16()
635 ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
637 else if (STI.hasVFP4())
638 ATS.emitFPU(STI.hasD16()
639 ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
641 else if (STI.hasVFP3())
642 ATS.emitFPU(STI.hasD16()
645 ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
646 : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
648 : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
649 else if (STI.hasVFP2())
650 ATS.emitFPU(ARM::FK_VFPV2);
653 if (TM.getRelocationModel() == Reloc::PIC_) {
654 // PIC specific attributes.
655 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
656 ARMBuildAttrs::AddressRWPCRel);
657 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
658 ARMBuildAttrs::AddressROPCRel);
659 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
660 ARMBuildAttrs::AddressGOT);
662 // Allow direct addressing of imported data for all other relocation models.
663 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
664 ARMBuildAttrs::AddressDirect);
667 // Signal various FP modes.
668 if (!TM.Options.UnsafeFPMath) {
669 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
670 ARMBuildAttrs::IEEEDenormals);
671 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
673 // If the user has permitted this code to choose the IEEE 754
674 // rounding at run-time, emit the rounding attribute.
675 if (TM.Options.HonorSignDependentRoundingFPMathOption)
676 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
678 if (!STI.hasVFP2()) {
679 // When the target doesn't have an FPU (by design or
680 // intention), the assumptions made on the software support
681 // mirror that of the equivalent hardware support *if it
682 // existed*. For v7 and better we indicate that denormals are
683 // flushed preserving sign, and for V6 we indicate that
684 // denormals are flushed to positive zero.
686 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
687 ARMBuildAttrs::PreserveFPSign);
688 } else if (STI.hasVFP3()) {
689 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
690 // the sign bit of the zero matches the sign bit of the input or
691 // result that is being flushed to zero.
692 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
693 ARMBuildAttrs::PreserveFPSign);
695 // For VFPv2 implementations it is implementation defined as
696 // to whether denormals are flushed to positive zero or to
697 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
698 // LLVM has chosen to flush this to positive zero (most likely for
699 // GCC compatibility), so that's the chosen value here (the
700 // absence of its emission implies zero).
703 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
704 // equivalent of GCC's -ffinite-math-only flag.
705 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
706 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
707 ARMBuildAttrs::Allowed);
709 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
710 ARMBuildAttrs::AllowIEE754);
712 if (STI.allowsUnalignedMem())
713 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
714 ARMBuildAttrs::Allowed);
716 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
717 ARMBuildAttrs::Not_Allowed);
719 // FIXME: add more flags to ARMBuildAttributes.h
720 // 8-bytes alignment stuff.
721 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
722 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
724 // ABI_HardFP_use attribute to indicate single precision FP.
725 if (STI.isFPOnlySP())
726 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
727 ARMBuildAttrs::HardFPSinglePrecision);
729 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
730 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
731 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
733 // FIXME: Should we signal R9 usage?
736 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
738 // FIXME: To support emitting this build attribute as GCC does, the
739 // -mfp16-format option and associated plumbing must be
740 // supported. For now the __fp16 type is exposed by default, so this
741 // attribute should be emitted with value 1.
742 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
743 ARMBuildAttrs::FP16FormatIEEE);
745 if (STI.hasMPExtension())
746 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
748 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
749 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
750 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
751 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
752 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
753 // otherwise, the default value (AllowDIVIfExists) applies.
754 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
755 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
758 if (const Module *SourceModule = MMI->getModule()) {
759 // ABI_PCS_wchar_t to indicate wchar_t width
760 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
761 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
762 SourceModule->getModuleFlag("wchar_size"))) {
763 int WCharWidth = WCharWidthValue->getZExtValue();
764 assert((WCharWidth == 2 || WCharWidth == 4) &&
765 "wchar_t width must be 2 or 4 bytes");
766 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
769 // ABI_enum_size to indicate enum width
770 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
771 // (all enums contain a value needing 32 bits to encode).
772 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
773 SourceModule->getModuleFlag("min_enum_size"))) {
774 int EnumWidth = EnumWidthValue->getZExtValue();
775 assert((EnumWidth == 1 || EnumWidth == 4) &&
776 "Minimum enum width must be 1 or 4 bytes");
777 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
778 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
783 // TODO: We currently only support either reserving the register, or treating
784 // it as another callee-saved register, but not as SB or a TLS pointer; It
785 // would instead be nicer to push this from the frontend as metadata, as we do
786 // for the wchar and enum size tags
787 if (STI.isR9Reserved())
788 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
790 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
792 if (STI.hasTrustZone() && STI.hasVirtualization())
793 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
794 ARMBuildAttrs::AllowTZVirtualization);
795 else if (STI.hasTrustZone())
796 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
797 ARMBuildAttrs::AllowTZ);
798 else if (STI.hasVirtualization())
799 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
800 ARMBuildAttrs::AllowVirtualization);
802 ATS.finishAttributeSection();
805 //===----------------------------------------------------------------------===//
807 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
808 unsigned LabelId, MCContext &Ctx) {
810 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
811 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
815 static MCSymbolRefExpr::VariantKind
816 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
818 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
819 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
820 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
821 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
822 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
823 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
825 llvm_unreachable("Invalid ARMCPModifier!");
828 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
829 unsigned char TargetFlags) {
830 if (Subtarget->isTargetMachO()) {
831 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
832 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
835 return getSymbol(GV);
837 // FIXME: Remove this when Darwin transition to @GOT like syntax.
838 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
839 MachineModuleInfoMachO &MMIMachO =
840 MMI->getObjFileInfo<MachineModuleInfoMachO>();
841 MachineModuleInfoImpl::StubValueTy &StubSym =
842 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
843 : MMIMachO.getGVStubEntry(MCSym);
844 if (!StubSym.getPointer())
845 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
846 !GV->hasInternalLinkage());
848 } else if (Subtarget->isTargetCOFF()) {
849 assert(Subtarget->isTargetWindows() &&
850 "Windows is the only supported COFF target");
852 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
854 return getSymbol(GV);
856 SmallString<128> Name;
858 getNameWithPrefix(Name, GV);
860 return OutContext.getOrCreateSymbol(Name);
861 } else if (Subtarget->isTargetELF()) {
862 return getSymbol(GV);
864 llvm_unreachable("unexpected target");
868 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
869 const DataLayout &DL = getDataLayout();
870 int Size = DL.getTypeAllocSize(MCPV->getType());
872 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
875 if (ACPV->isLSDA()) {
876 MCSym = getCurExceptionSym();
877 } else if (ACPV->isBlockAddress()) {
878 const BlockAddress *BA =
879 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
880 MCSym = GetBlockAddressSymbol(BA);
881 } else if (ACPV->isGlobalValue()) {
882 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
884 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
885 // flag the global as MO_NONLAZY.
886 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
887 MCSym = GetARMGVSymbol(GV, TF);
888 } else if (ACPV->isMachineBasicBlock()) {
889 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
890 MCSym = MBB->getSymbol();
892 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
893 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
894 MCSym = GetExternalSymbolSymbol(Sym);
897 // Create an MCSymbol for the reference.
899 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
902 if (ACPV->getPCAdjustment()) {
904 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
905 ACPV->getLabelId(), OutContext);
906 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
908 MCBinaryExpr::createAdd(PCRelExpr,
909 MCConstantExpr::create(ACPV->getPCAdjustment(),
912 if (ACPV->mustAddCurrentAddress()) {
913 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
914 // label, so just emit a local label end reference that instead.
915 MCSymbol *DotSym = OutContext.createTempSymbol();
916 OutStreamer->EmitLabel(DotSym);
917 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
918 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
920 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
922 OutStreamer->EmitValue(Expr, Size);
925 void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
926 const MachineOperand &MO1 = MI->getOperand(1);
927 unsigned JTI = MO1.getIndex();
929 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
933 // Emit a label for the jump table.
934 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
935 OutStreamer->EmitLabel(JTISymbol);
937 // Mark the jump table as data-in-code.
938 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
940 // Emit each entry of the table.
941 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
942 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
943 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
945 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
946 MachineBasicBlock *MBB = JTBBs[i];
947 // Construct an MCExpr for the entry. We want a value of the form:
948 // (BasicBlockAddr - TableBeginAddr)
950 // For example, a table with entries jumping to basic blocks BB0 and BB1
953 // .word (LBB0 - LJTI_0_0)
954 // .word (LBB1 - LJTI_0_0)
955 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
957 if (TM.getRelocationModel() == Reloc::PIC_)
958 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
961 // If we're generating a table of Thumb addresses in static relocation
962 // model, we need to add one to keep interworking correctly.
963 else if (AFI->isThumbFunction())
964 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
966 OutStreamer->EmitValue(Expr, 4);
968 // Mark the end of jump table data-in-code region.
969 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
972 void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
973 const MachineOperand &MO1 = MI->getOperand(1);
974 unsigned JTI = MO1.getIndex();
976 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
977 OutStreamer->EmitLabel(JTISymbol);
979 // Emit each entry of the table.
980 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
981 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
982 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
984 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
985 MachineBasicBlock *MBB = JTBBs[i];
986 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
988 // If this isn't a TBB or TBH, the entries are direct branch instructions.
989 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
990 .addExpr(MBBSymbolExpr)
996 void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
997 unsigned OffsetWidth) {
998 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
999 const MachineOperand &MO1 = MI->getOperand(1);
1000 unsigned JTI = MO1.getIndex();
1002 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1003 OutStreamer->EmitLabel(JTISymbol);
1005 // Emit each entry of the table.
1006 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1007 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1008 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1010 // Mark the jump table as data-in-code.
1011 OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1012 : MCDR_DataRegionJT16);
1014 for (auto MBB : JTBBs) {
1015 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1017 // Otherwise it's an offset from the dispatch instruction. Construct an
1018 // MCExpr for the entry. We want a value of the form:
1019 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1021 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1024 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1025 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1026 // where LCPI0_0 is a label defined just before the TBB instruction using
1028 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1029 const MCExpr *Expr = MCBinaryExpr::createAdd(
1030 MCSymbolRefExpr::create(TBInstPC, OutContext),
1031 MCConstantExpr::create(4, OutContext), OutContext);
1032 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1033 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1035 OutStreamer->EmitValue(Expr, OffsetWidth);
1037 // Mark the end of jump table data-in-code region. 32-bit offsets use
1038 // actual branch instructions here, so we don't mark those as a data-region
1040 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1042 // Make sure the next instruction is 2-byte aligned.
1046 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1047 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1048 "Only instruction which are involved into frame setup code are allowed");
1050 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1051 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1052 const MachineFunction &MF = *MI->getParent()->getParent();
1053 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1054 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1056 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1057 unsigned Opc = MI->getOpcode();
1058 unsigned SrcReg, DstReg;
1060 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1061 // Two special cases:
1062 // 1) tPUSH does not have src/dst regs.
1063 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1064 // load. Yes, this is pretty fragile, but for now I don't see better
1066 SrcReg = DstReg = ARM::SP;
1068 SrcReg = MI->getOperand(1).getReg();
1069 DstReg = MI->getOperand(0).getReg();
1072 // Try to figure out the unwinding opcode out of src / dst regs.
1073 if (MI->mayStore()) {
1075 assert(DstReg == ARM::SP &&
1076 "Only stack pointer as a destination reg is supported");
1078 SmallVector<unsigned, 4> RegList;
1079 // Skip src & dst reg, and pred ops.
1080 unsigned StartOp = 2 + 2;
1081 // Use all the operands.
1082 unsigned NumOffset = 0;
1087 llvm_unreachable("Unsupported opcode for unwinding information");
1089 // Special case here: no src & dst reg, but two extra imp ops.
1090 StartOp = 2; NumOffset = 2;
1091 case ARM::STMDB_UPD:
1092 case ARM::t2STMDB_UPD:
1093 case ARM::VSTMDDB_UPD:
1094 assert(SrcReg == ARM::SP &&
1095 "Only stack pointer as a source reg is supported");
1096 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1098 const MachineOperand &MO = MI->getOperand(i);
1099 // Actually, there should never be any impdef stuff here. Skip it
1100 // temporary to workaround PR11902.
1101 if (MO.isImplicit())
1103 RegList.push_back(MO.getReg());
1106 case ARM::STR_PRE_IMM:
1107 case ARM::STR_PRE_REG:
1108 case ARM::t2STR_PRE:
1109 assert(MI->getOperand(2).getReg() == ARM::SP &&
1110 "Only stack pointer as a source reg is supported");
1111 RegList.push_back(SrcReg);
1114 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1115 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1117 // Changes of stack / frame pointer.
1118 if (SrcReg == ARM::SP) {
1123 llvm_unreachable("Unsupported opcode for unwinding information");
1129 Offset = -MI->getOperand(2).getImm();
1133 Offset = MI->getOperand(2).getImm();
1136 Offset = MI->getOperand(2).getImm()*4;
1140 Offset = -MI->getOperand(2).getImm()*4;
1142 case ARM::tLDRpci: {
1143 // Grab the constpool index and check, whether it corresponds to
1144 // original or cloned constpool entry.
1145 unsigned CPI = MI->getOperand(1).getIndex();
1146 const MachineConstantPool *MCP = MF.getConstantPool();
1147 if (CPI >= MCP->getConstants().size())
1148 CPI = AFI.getOriginalCPIdx(CPI);
1149 assert(CPI != -1U && "Invalid constpool index");
1151 // Derive the actual offset.
1152 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1153 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1154 // FIXME: Check for user, it should be "add" instruction!
1155 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1160 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1161 if (DstReg == FramePtr && FramePtr != ARM::SP)
1162 // Set-up of the frame pointer. Positive values correspond to "add"
1164 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1165 else if (DstReg == ARM::SP) {
1166 // Change of SP by an offset. Positive values correspond to "sub"
1168 ATS.emitPad(Offset);
1170 // Move of SP to a register. Positive values correspond to an "add"
1172 ATS.emitMovSP(DstReg, -Offset);
1175 } else if (DstReg == ARM::SP) {
1177 llvm_unreachable("Unsupported opcode for unwinding information");
1181 llvm_unreachable("Unsupported opcode for unwinding information");
1186 // Simple pseudo-instructions have their lowering (with expansion to real
1187 // instructions) auto-generated.
1188 #include "ARMGenMCPseudoLowering.inc"
1190 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1191 const DataLayout &DL = getDataLayout();
1193 // If we just ended a constant pool, mark it as such.
1194 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1195 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1196 InConstantPool = false;
1199 // Emit unwinding stuff for frame-related instructions
1200 if (Subtarget->isTargetEHABICompatible() &&
1201 MI->getFlag(MachineInstr::FrameSetup))
1202 EmitUnwindingInstruction(MI);
1204 // Do any auto-generated pseudo lowerings.
1205 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1208 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1209 "Pseudo flag setting opcode should be expanded early");
1211 // Check for manual lowerings.
1212 unsigned Opc = MI->getOpcode();
1214 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1215 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1217 case ARM::tLEApcrel:
1218 case ARM::t2LEApcrel: {
1219 // FIXME: Need to also handle globals and externals
1220 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1221 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1222 ARM::t2LEApcrel ? ARM::t2ADR
1223 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1225 .addReg(MI->getOperand(0).getReg())
1226 .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1227 // Add predicate operands.
1228 .addImm(MI->getOperand(2).getImm())
1229 .addReg(MI->getOperand(3).getReg()));
1232 case ARM::LEApcrelJT:
1233 case ARM::tLEApcrelJT:
1234 case ARM::t2LEApcrelJT: {
1235 MCSymbol *JTIPICSymbol =
1236 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1237 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1238 ARM::t2LEApcrelJT ? ARM::t2ADR
1239 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1241 .addReg(MI->getOperand(0).getReg())
1242 .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1243 // Add predicate operands.
1244 .addImm(MI->getOperand(2).getImm())
1245 .addReg(MI->getOperand(3).getReg()));
1248 // Darwin call instructions are just normal call instructions with different
1249 // clobber semantics (they clobber R9).
1250 case ARM::BX_CALL: {
1251 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1254 // Add predicate operands.
1257 // Add 's' bit operand (always reg0 for this)
1260 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1261 .addReg(MI->getOperand(0).getReg()));
1264 case ARM::tBX_CALL: {
1265 if (Subtarget->hasV5TOps())
1266 llvm_unreachable("Expected BLX to be selected for v5t+");
1268 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1269 // that the saved lr has its LSB set correctly (the arch doesn't
1271 // So here we generate a bl to a small jump pad that does bx rN.
1272 // The jump pads are emitted after the function body.
1274 unsigned TReg = MI->getOperand(0).getReg();
1275 MCSymbol *TRegSym = nullptr;
1276 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1277 if (ThumbIndirectPads[i].first == TReg) {
1278 TRegSym = ThumbIndirectPads[i].second;
1284 TRegSym = OutContext.createTempSymbol();
1285 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1288 // Create a link-saving branch to the Reg Indirect Jump Pad.
1289 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1290 // Predicate comes first here.
1291 .addImm(ARMCC::AL).addReg(0)
1292 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1295 case ARM::BMOVPCRX_CALL: {
1296 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1299 // Add predicate operands.
1302 // Add 's' bit operand (always reg0 for this)
1305 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1307 .addReg(MI->getOperand(0).getReg())
1308 // Add predicate operands.
1311 // Add 's' bit operand (always reg0 for this)
1315 case ARM::BMOVPCB_CALL: {
1316 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1319 // Add predicate operands.
1322 // Add 's' bit operand (always reg0 for this)
1325 const MachineOperand &Op = MI->getOperand(0);
1326 const GlobalValue *GV = Op.getGlobal();
1327 const unsigned TF = Op.getTargetFlags();
1328 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1329 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1330 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1332 // Add predicate operands.
1337 case ARM::MOVi16_ga_pcrel:
1338 case ARM::t2MOVi16_ga_pcrel: {
1340 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1341 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1343 unsigned TF = MI->getOperand(1).getTargetFlags();
1344 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1345 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1346 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1348 MCSymbol *LabelSym =
1349 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1350 MI->getOperand(2).getImm(), OutContext);
1351 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1352 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1353 const MCExpr *PCRelExpr =
1354 ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1355 MCBinaryExpr::createAdd(LabelSymExpr,
1356 MCConstantExpr::create(PCAdj, OutContext),
1357 OutContext), OutContext), OutContext);
1358 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1360 // Add predicate operands.
1361 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1362 TmpInst.addOperand(MCOperand::createReg(0));
1363 // Add 's' bit operand (always reg0 for this)
1364 TmpInst.addOperand(MCOperand::createReg(0));
1365 EmitToStreamer(*OutStreamer, TmpInst);
1368 case ARM::MOVTi16_ga_pcrel:
1369 case ARM::t2MOVTi16_ga_pcrel: {
1371 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1372 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1373 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1374 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1376 unsigned TF = MI->getOperand(2).getTargetFlags();
1377 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1378 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1379 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1381 MCSymbol *LabelSym =
1382 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1383 MI->getOperand(3).getImm(), OutContext);
1384 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1385 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1386 const MCExpr *PCRelExpr =
1387 ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1388 MCBinaryExpr::createAdd(LabelSymExpr,
1389 MCConstantExpr::create(PCAdj, OutContext),
1390 OutContext), OutContext), OutContext);
1391 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1392 // Add predicate operands.
1393 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1394 TmpInst.addOperand(MCOperand::createReg(0));
1395 // Add 's' bit operand (always reg0 for this)
1396 TmpInst.addOperand(MCOperand::createReg(0));
1397 EmitToStreamer(*OutStreamer, TmpInst);
1400 case ARM::tPICADD: {
1401 // This is a pseudo op for a label + instruction sequence, which looks like:
1404 // This adds the address of LPC0 to r0.
1407 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1408 getFunctionNumber(),
1409 MI->getOperand(2).getImm(), OutContext));
1411 // Form and emit the add.
1412 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1413 .addReg(MI->getOperand(0).getReg())
1414 .addReg(MI->getOperand(0).getReg())
1416 // Add predicate operands.
1422 // This is a pseudo op for a label + instruction sequence, which looks like:
1425 // This adds the address of LPC0 to r0.
1428 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1429 getFunctionNumber(),
1430 MI->getOperand(2).getImm(), OutContext));
1432 // Form and emit the add.
1433 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1434 .addReg(MI->getOperand(0).getReg())
1436 .addReg(MI->getOperand(1).getReg())
1437 // Add predicate operands.
1438 .addImm(MI->getOperand(3).getImm())
1439 .addReg(MI->getOperand(4).getReg())
1440 // Add 's' bit operand (always reg0 for this)
1451 case ARM::PICLDRSH: {
1452 // This is a pseudo op for a label + instruction sequence, which looks like:
1455 // The LCP0 label is referenced by a constant pool entry in order to get
1456 // a PC-relative address at the ldr instruction.
1459 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1460 getFunctionNumber(),
1461 MI->getOperand(2).getImm(), OutContext));
1463 // Form and emit the load
1465 switch (MI->getOpcode()) {
1467 llvm_unreachable("Unexpected opcode!");
1468 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1469 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1470 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1471 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1472 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1473 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1474 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1475 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1477 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1478 .addReg(MI->getOperand(0).getReg())
1480 .addReg(MI->getOperand(1).getReg())
1482 // Add predicate operands.
1483 .addImm(MI->getOperand(3).getImm())
1484 .addReg(MI->getOperand(4).getReg()));
1488 case ARM::CONSTPOOL_ENTRY: {
1489 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1490 /// in the function. The first operand is the ID# for this instruction, the
1491 /// second is the index into the MachineConstantPool that this is, the third
1492 /// is the size in bytes of this constant pool entry.
1493 /// The required alignment is specified on the basic block holding this MI.
1494 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1495 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1497 // If this is the first entry of the pool, mark it.
1498 if (!InConstantPool) {
1499 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1500 InConstantPool = true;
1503 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1505 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1506 if (MCPE.isMachineConstantPoolEntry())
1507 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1509 EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1512 case ARM::JUMPTABLE_ADDRS:
1513 EmitJumpTableAddrs(MI);
1515 case ARM::JUMPTABLE_INSTS:
1516 EmitJumpTableInsts(MI);
1518 case ARM::JUMPTABLE_TBB:
1519 case ARM::JUMPTABLE_TBH:
1520 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1522 case ARM::t2BR_JT: {
1523 // Lower and emit the instruction itself, then the jump table following it.
1524 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1526 .addReg(MI->getOperand(0).getReg())
1527 // Add predicate operands.
1533 case ARM::t2TBH_JT: {
1534 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1535 // Lower and emit the PC label, then the instruction itself.
1536 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1537 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1538 .addReg(MI->getOperand(0).getReg())
1539 .addReg(MI->getOperand(1).getReg())
1540 // Add predicate operands.
1547 // Lower and emit the instruction itself, then the jump table following it.
1550 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1551 ARM::MOVr : ARM::tMOVr;
1552 TmpInst.setOpcode(Opc);
1553 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1554 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1555 // Add predicate operands.
1556 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1557 TmpInst.addOperand(MCOperand::createReg(0));
1558 // Add 's' bit operand (always reg0 for this)
1559 if (Opc == ARM::MOVr)
1560 TmpInst.addOperand(MCOperand::createReg(0));
1561 EmitToStreamer(*OutStreamer, TmpInst);
1565 // Lower and emit the instruction itself, then the jump table following it.
1568 if (MI->getOperand(1).getReg() == 0) {
1570 TmpInst.setOpcode(ARM::LDRi12);
1571 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1572 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1573 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1575 TmpInst.setOpcode(ARM::LDRrs);
1576 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1577 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1578 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1579 TmpInst.addOperand(MCOperand::createImm(0));
1581 // Add predicate operands.
1582 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1583 TmpInst.addOperand(MCOperand::createReg(0));
1584 EmitToStreamer(*OutStreamer, TmpInst);
1587 case ARM::BR_JTadd: {
1588 // Lower and emit the instruction itself, then the jump table following it.
1589 // add pc, target, idx
1590 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1592 .addReg(MI->getOperand(0).getReg())
1593 .addReg(MI->getOperand(1).getReg())
1594 // Add predicate operands.
1597 // Add 's' bit operand (always reg0 for this)
1602 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1605 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1606 // FIXME: Remove this special case when they do.
1607 if (!Subtarget->isTargetMachO()) {
1608 //.long 0xe7ffdefe @ trap
1609 uint32_t Val = 0xe7ffdefeUL;
1610 OutStreamer->AddComment("trap");
1611 OutStreamer->EmitIntValue(Val, 4);
1616 case ARM::TRAPNaCl: {
1617 //.long 0xe7fedef0 @ trap
1618 uint32_t Val = 0xe7fedef0UL;
1619 OutStreamer->AddComment("trap");
1620 OutStreamer->EmitIntValue(Val, 4);
1624 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1625 // FIXME: Remove this special case when they do.
1626 if (!Subtarget->isTargetMachO()) {
1627 //.short 57086 @ trap
1628 uint16_t Val = 0xdefe;
1629 OutStreamer->AddComment("trap");
1630 OutStreamer->EmitIntValue(Val, 2);
1635 case ARM::t2Int_eh_sjlj_setjmp:
1636 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1637 case ARM::tInt_eh_sjlj_setjmp: {
1638 // Two incoming args: GPR:$src, GPR:$val
1641 // str $val, [$src, #4]
1646 unsigned SrcReg = MI->getOperand(0).getReg();
1647 unsigned ValReg = MI->getOperand(1).getReg();
1648 MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1649 OutStreamer->AddComment("eh_setjmp begin");
1650 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1657 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1667 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1670 // The offset immediate is #4. The operand value is scaled by 4 for the
1671 // tSTR instruction.
1677 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1685 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1686 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1687 .addExpr(SymbolExpr)
1691 OutStreamer->AddComment("eh_setjmp end");
1692 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1700 OutStreamer->EmitLabel(Label);
1704 case ARM::Int_eh_sjlj_setjmp_nofp:
1705 case ARM::Int_eh_sjlj_setjmp: {
1706 // Two incoming args: GPR:$src, GPR:$val
1708 // str $val, [$src, #+4]
1712 unsigned SrcReg = MI->getOperand(0).getReg();
1713 unsigned ValReg = MI->getOperand(1).getReg();
1715 OutStreamer->AddComment("eh_setjmp begin");
1716 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1723 // 's' bit operand (always reg0 for this).
1726 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1734 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1740 // 's' bit operand (always reg0 for this).
1743 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1750 // 's' bit operand (always reg0 for this).
1753 OutStreamer->AddComment("eh_setjmp end");
1754 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1760 // 's' bit operand (always reg0 for this).
1764 case ARM::Int_eh_sjlj_longjmp: {
1765 // ldr sp, [$src, #8]
1766 // ldr $scratch, [$src, #4]
1769 unsigned SrcReg = MI->getOperand(0).getReg();
1770 unsigned ScratchReg = MI->getOperand(1).getReg();
1771 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1779 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1787 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1795 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1802 case ARM::tInt_eh_sjlj_longjmp: {
1803 // ldr $scratch, [$src, #8]
1805 // ldr $scratch, [$src, #4]
1808 unsigned SrcReg = MI->getOperand(0).getReg();
1809 unsigned ScratchReg = MI->getOperand(1).getReg();
1810 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1813 // The offset immediate is #8. The operand value is scaled by 4 for the
1814 // tLDR instruction.
1820 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1827 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1835 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1843 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
1853 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1855 EmitToStreamer(*OutStreamer, TmpInst);
1858 //===----------------------------------------------------------------------===//
1859 // Target Registry Stuff
1860 //===----------------------------------------------------------------------===//
1862 // Force static initialization.
1863 extern "C" void LLVMInitializeARMAsmPrinter() {
1864 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1865 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1866 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1867 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);