1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 /// getDwarfRegOpSize - get size required to emit given machine location using
177 unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
178 const TargetRegisterInfo *RI = TM.getRegisterInfo();
179 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
180 return AsmPrinter::getDwarfRegOpSize(MLoc);
182 unsigned Reg = MLoc.getReg();
183 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
184 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
185 // S registers are described as bit-pieces of a register
186 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
187 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
189 unsigned SReg = Reg - ARM::S0;
190 unsigned Rx = 256 + (SReg >> 1);
191 // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
192 // 1 + ULEB(Rx) + 1 + 1 + 1
193 return 4 + MCAsmInfo::getULEB128Size(Rx);
196 if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
197 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
198 // Q registers Q0-Q15 are described by composing two D registers together.
199 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
201 unsigned QReg = Reg - ARM::Q0;
202 unsigned D1 = 256 + 2 * QReg;
203 unsigned D2 = D1 + 1;
205 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
206 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
207 // 6 + ULEB(D1) + ULEB(D2)
208 return 6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2);
214 /// EmitDwarfRegOp - Emit dwarf register operation.
215 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
216 const TargetRegisterInfo *RI = TM.getRegisterInfo();
217 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
218 AsmPrinter::EmitDwarfRegOp(MLoc);
220 unsigned Reg = MLoc.getReg();
221 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
222 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
223 // S registers are described as bit-pieces of a register
224 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
225 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
227 unsigned SReg = Reg - ARM::S0;
228 bool odd = SReg & 0x1;
229 unsigned Rx = 256 + (SReg >> 1);
231 OutStreamer.AddComment("DW_OP_regx for S register");
232 EmitInt8(dwarf::DW_OP_regx);
234 OutStreamer.AddComment(Twine(SReg));
238 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
239 EmitInt8(dwarf::DW_OP_bit_piece);
243 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
244 EmitInt8(dwarf::DW_OP_bit_piece);
248 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
249 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
250 // Q registers Q0-Q15 are described by composing two D registers together.
251 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
253 unsigned QReg = Reg - ARM::Q0;
254 unsigned D1 = 256 + 2 * QReg;
255 unsigned D2 = D1 + 1;
257 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
258 EmitInt8(dwarf::DW_OP_regx);
260 OutStreamer.AddComment("DW_OP_piece 8");
261 EmitInt8(dwarf::DW_OP_piece);
264 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
265 EmitInt8(dwarf::DW_OP_regx);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
274 void ARMAsmPrinter::EmitFunctionEntryLabel() {
275 if (AFI->isThumbFunction()) {
276 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
277 OutStreamer.EmitThumbFunc(CurrentFnSym);
280 OutStreamer.EmitLabel(CurrentFnSym);
283 /// runOnMachineFunction - This uses the EmitInstruction()
284 /// method to print assembly for each instruction.
286 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
287 AFI = MF.getInfo<ARMFunctionInfo>();
288 MCP = MF.getConstantPool();
290 return AsmPrinter::runOnMachineFunction(MF);
293 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
294 raw_ostream &O, const char *Modifier) {
295 const MachineOperand &MO = MI->getOperand(OpNum);
296 unsigned TF = MO.getTargetFlags();
298 switch (MO.getType()) {
300 assert(0 && "<unknown operand type>");
301 case MachineOperand::MO_Register: {
302 unsigned Reg = MO.getReg();
303 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
304 assert(!MO.getSubReg() && "Subregs should be eliminated!");
305 O << ARMInstPrinter::getRegisterName(Reg);
308 case MachineOperand::MO_Immediate: {
309 int64_t Imm = MO.getImm();
311 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
312 (TF == ARMII::MO_LO16))
314 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
315 (TF == ARMII::MO_HI16))
320 case MachineOperand::MO_MachineBasicBlock:
321 O << *MO.getMBB()->getSymbol();
323 case MachineOperand::MO_GlobalAddress: {
324 const GlobalValue *GV = MO.getGlobal();
325 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
326 (TF & ARMII::MO_LO16))
328 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
329 (TF & ARMII::MO_HI16))
331 O << *Mang->getSymbol(GV);
333 printOffset(MO.getOffset(), O);
334 if (TF == ARMII::MO_PLT)
338 case MachineOperand::MO_ExternalSymbol: {
339 O << *GetExternalSymbolSymbol(MO.getSymbolName());
340 if (TF == ARMII::MO_PLT)
344 case MachineOperand::MO_ConstantPoolIndex:
345 O << *GetCPISymbol(MO.getIndex());
347 case MachineOperand::MO_JumpTableIndex:
348 O << *GetJTISymbol(MO.getIndex());
353 //===--------------------------------------------------------------------===//
355 MCSymbol *ARMAsmPrinter::
356 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
357 const MachineBasicBlock *MBB) const {
358 SmallString<60> Name;
359 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
360 << getFunctionNumber() << '_' << uid << '_' << uid2
361 << "_set_" << MBB->getNumber();
362 return OutContext.GetOrCreateSymbol(Name.str());
365 MCSymbol *ARMAsmPrinter::
366 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
367 SmallString<60> Name;
368 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
369 << getFunctionNumber() << '_' << uid << '_' << uid2;
370 return OutContext.GetOrCreateSymbol(Name.str());
374 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
375 SmallString<60> Name;
376 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
377 << getFunctionNumber();
378 return OutContext.GetOrCreateSymbol(Name.str());
381 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
382 unsigned AsmVariant, const char *ExtraCode,
384 // Does this asm operand have a single letter operand modifier?
385 if (ExtraCode && ExtraCode[0]) {
386 if (ExtraCode[1] != 0) return true; // Unknown modifier.
388 switch (ExtraCode[0]) {
389 default: return true; // Unknown modifier.
390 case 'a': // Print as a memory address.
391 if (MI->getOperand(OpNum).isReg()) {
393 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
398 case 'c': // Don't print "#" before an immediate operand.
399 if (!MI->getOperand(OpNum).isImm())
401 O << MI->getOperand(OpNum).getImm();
403 case 'P': // Print a VFP double precision register.
404 case 'q': // Print a NEON quad precision register.
405 printOperand(MI, OpNum, O);
410 // These modifiers are not yet supported.
415 printOperand(MI, OpNum, O);
419 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
420 unsigned OpNum, unsigned AsmVariant,
421 const char *ExtraCode,
423 if (ExtraCode && ExtraCode[0])
424 return true; // Unknown modifier.
426 const MachineOperand &MO = MI->getOperand(OpNum);
427 assert(MO.isReg() && "unexpected inline asm memory operand");
428 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
432 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
433 if (Subtarget->isTargetDarwin()) {
434 Reloc::Model RelocM = TM.getRelocationModel();
435 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
436 // Declare all the text sections up front (before the DWARF sections
437 // emitted by AsmPrinter::doInitialization) so the assembler will keep
438 // them together at the beginning of the object file. This helps
439 // avoid out-of-range branches that are due a fundamental limitation of
440 // the way symbol offsets are encoded with the current Darwin ARM
442 const TargetLoweringObjectFileMachO &TLOFMacho =
443 static_cast<const TargetLoweringObjectFileMachO &>(
444 getObjFileLowering());
445 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
446 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
447 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
448 if (RelocM == Reloc::DynamicNoPIC) {
449 const MCSection *sect =
450 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
451 MCSectionMachO::S_SYMBOL_STUBS,
452 12, SectionKind::getText());
453 OutStreamer.SwitchSection(sect);
455 const MCSection *sect =
456 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
457 MCSectionMachO::S_SYMBOL_STUBS,
458 16, SectionKind::getText());
459 OutStreamer.SwitchSection(sect);
461 const MCSection *StaticInitSect =
462 OutContext.getMachOSection("__TEXT", "__StaticInit",
463 MCSectionMachO::S_REGULAR |
464 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
465 SectionKind::getText());
466 OutStreamer.SwitchSection(StaticInitSect);
470 // Use unified assembler syntax.
471 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
473 // Emit ARM Build Attributes
474 if (Subtarget->isTargetELF()) {
481 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
482 if (Subtarget->isTargetDarwin()) {
483 // All darwin targets use mach-o.
484 const TargetLoweringObjectFileMachO &TLOFMacho =
485 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
486 MachineModuleInfoMachO &MMIMacho =
487 MMI->getObjFileInfo<MachineModuleInfoMachO>();
489 // Output non-lazy-pointers for external and common global variables.
490 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
492 if (!Stubs.empty()) {
493 // Switch with ".non_lazy_symbol_pointer" directive.
494 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
496 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
498 OutStreamer.EmitLabel(Stubs[i].first);
499 // .indirect_symbol _foo
500 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
501 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
504 // External to current translation unit.
505 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
507 // Internal to current translation unit.
509 // When we place the LSDA into the TEXT section, the type info
510 // pointers need to be indirect and pc-rel. We accomplish this by
511 // using NLPs; however, sometimes the types are local to the file.
512 // We need to fill in the value for the NLP in those cases.
513 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
515 4/*size*/, 0/*addrspace*/);
519 OutStreamer.AddBlankLine();
522 Stubs = MMIMacho.GetHiddenGVStubList();
523 if (!Stubs.empty()) {
524 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
526 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
528 OutStreamer.EmitLabel(Stubs[i].first);
530 OutStreamer.EmitValue(MCSymbolRefExpr::
531 Create(Stubs[i].second.getPointer(),
533 4/*size*/, 0/*addrspace*/);
537 OutStreamer.AddBlankLine();
540 // Funny Darwin hack: This flag tells the linker that no global symbols
541 // contain code that falls through to other global symbols (e.g. the obvious
542 // implementation of multiple entry points). If this doesn't occur, the
543 // linker can safely perform dead code stripping. Since LLVM never
544 // generates code that does this, it is always safe to set.
545 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
549 //===----------------------------------------------------------------------===//
550 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
552 // The following seem like one-off assembler flags, but they actually need
553 // to appear in the .ARM.attributes section in ELF.
554 // Instead of subclassing the MCELFStreamer, we do the work here.
556 void ARMAsmPrinter::emitAttributes() {
558 emitARMAttributeSection();
560 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
561 bool emitFPU = false;
562 AttributeEmitter *AttrEmitter;
563 if (OutStreamer.hasRawTextSupport()) {
564 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
567 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
568 AttrEmitter = new ObjectAttributeEmitter(O);
571 AttrEmitter->MaybeSwitchVendor("aeabi");
573 std::string CPUString = Subtarget->getCPUString();
575 if (CPUString == "cortex-a8" ||
576 Subtarget->isCortexA8()) {
577 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
578 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
579 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
580 ARMBuildAttrs::ApplicationProfile);
581 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
582 ARMBuildAttrs::Allowed);
583 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
584 ARMBuildAttrs::AllowThumb32);
585 // Fixme: figure out when this is emitted.
586 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
587 // ARMBuildAttrs::AllowWMMXv1);
590 /// ADD additional Else-cases here!
591 } else if (CPUString == "generic") {
592 // FIXME: Why these defaults?
593 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
594 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
595 ARMBuildAttrs::Allowed);
596 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
597 ARMBuildAttrs::Allowed);
600 if (Subtarget->hasNEON() && emitFPU) {
601 /* NEON is not exactly a VFP architecture, but GAS emit one of
602 * neon/vfpv3/vfpv2 for .fpu parameters */
603 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
604 /* If emitted for NEON, omit from VFP below, since you can have both
605 * NEON and VFP in build attributes but only one .fpu */
610 if (Subtarget->hasVFP3()) {
611 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
612 ARMBuildAttrs::AllowFPv3A);
614 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
617 } else if (Subtarget->hasVFP2()) {
618 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
619 ARMBuildAttrs::AllowFPv2);
621 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
624 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
625 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
626 if (Subtarget->hasNEON()) {
627 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
628 ARMBuildAttrs::Allowed);
631 // Signal various FP modes.
633 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
634 ARMBuildAttrs::Allowed);
635 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
636 ARMBuildAttrs::Allowed);
639 if (NoInfsFPMath && NoNaNsFPMath)
640 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
641 ARMBuildAttrs::Allowed);
643 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
644 ARMBuildAttrs::AllowIEE754);
646 // FIXME: add more flags to ARMBuildAttrs.h
647 // 8-bytes alignment stuff.
648 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
649 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
651 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
652 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
653 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
654 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
656 // FIXME: Should we signal R9 usage?
658 if (Subtarget->hasDivide())
659 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
661 AttrEmitter->Finish();
665 void ARMAsmPrinter::emitARMAttributeSection() {
667 // [ <section-length> "vendor-name"
668 // [ <file-tag> <size> <attribute>*
669 // | <section-tag> <size> <section-number>* 0 <attribute>*
670 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
674 if (OutStreamer.hasRawTextSupport())
677 const ARMElfTargetObjectFile &TLOFELF =
678 static_cast<const ARMElfTargetObjectFile &>
679 (getObjFileLowering());
681 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
684 OutStreamer.EmitIntValue(0x41, 1);
687 //===----------------------------------------------------------------------===//
689 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
690 unsigned LabelId, MCContext &Ctx) {
692 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
693 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
697 static MCSymbolRefExpr::VariantKind
698 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
700 default: llvm_unreachable("Unknown modifier!");
701 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
702 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
703 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
704 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
705 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
706 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
708 return MCSymbolRefExpr::VK_None;
711 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
712 bool isIndirect = Subtarget->isTargetDarwin() &&
713 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
715 return Mang->getSymbol(GV);
717 // FIXME: Remove this when Darwin transition to @GOT like syntax.
718 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
719 MachineModuleInfoMachO &MMIMachO =
720 MMI->getObjFileInfo<MachineModuleInfoMachO>();
721 MachineModuleInfoImpl::StubValueTy &StubSym =
722 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
723 MMIMachO.getGVStubEntry(MCSym);
724 if (StubSym.getPointer() == 0)
725 StubSym = MachineModuleInfoImpl::
726 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
731 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
732 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
734 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
737 if (ACPV->isLSDA()) {
738 SmallString<128> Str;
739 raw_svector_ostream OS(Str);
740 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
741 MCSym = OutContext.GetOrCreateSymbol(OS.str());
742 } else if (ACPV->isBlockAddress()) {
743 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
744 } else if (ACPV->isGlobalValue()) {
745 const GlobalValue *GV = ACPV->getGV();
746 MCSym = GetARMGVSymbol(GV);
748 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
749 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
752 // Create an MCSymbol for the reference.
754 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
757 if (ACPV->getPCAdjustment()) {
758 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
762 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
764 MCBinaryExpr::CreateAdd(PCRelExpr,
765 MCConstantExpr::Create(ACPV->getPCAdjustment(),
768 if (ACPV->mustAddCurrentAddress()) {
769 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
770 // label, so just emit a local label end reference that instead.
771 MCSymbol *DotSym = OutContext.CreateTempSymbol();
772 OutStreamer.EmitLabel(DotSym);
773 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
774 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
776 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
778 OutStreamer.EmitValue(Expr, Size);
781 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
782 unsigned Opcode = MI->getOpcode();
784 if (Opcode == ARM::BR_JTadd)
786 else if (Opcode == ARM::BR_JTm)
789 const MachineOperand &MO1 = MI->getOperand(OpNum);
790 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
791 unsigned JTI = MO1.getIndex();
793 // Emit a label for the jump table.
794 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
795 OutStreamer.EmitLabel(JTISymbol);
797 // Emit each entry of the table.
798 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
799 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
800 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
802 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
803 MachineBasicBlock *MBB = JTBBs[i];
804 // Construct an MCExpr for the entry. We want a value of the form:
805 // (BasicBlockAddr - TableBeginAddr)
807 // For example, a table with entries jumping to basic blocks BB0 and BB1
810 // .word (LBB0 - LJTI_0_0)
811 // .word (LBB1 - LJTI_0_0)
812 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
814 if (TM.getRelocationModel() == Reloc::PIC_)
815 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
818 OutStreamer.EmitValue(Expr, 4);
822 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
823 unsigned Opcode = MI->getOpcode();
824 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
825 const MachineOperand &MO1 = MI->getOperand(OpNum);
826 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
827 unsigned JTI = MO1.getIndex();
829 // Emit a label for the jump table.
830 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
831 OutStreamer.EmitLabel(JTISymbol);
833 // Emit each entry of the table.
834 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
835 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
836 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
837 unsigned OffsetWidth = 4;
838 if (MI->getOpcode() == ARM::t2TBB_JT)
840 else if (MI->getOpcode() == ARM::t2TBH_JT)
843 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
844 MachineBasicBlock *MBB = JTBBs[i];
845 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
847 // If this isn't a TBB or TBH, the entries are direct branch instructions.
848 if (OffsetWidth == 4) {
850 BrInst.setOpcode(ARM::t2B);
851 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
852 OutStreamer.EmitInstruction(BrInst);
855 // Otherwise it's an offset from the dispatch instruction. Construct an
856 // MCExpr for the entry. We want a value of the form:
857 // (BasicBlockAddr - TableBeginAddr) / 2
859 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
862 // .byte (LBB0 - LJTI_0_0) / 2
863 // .byte (LBB1 - LJTI_0_0) / 2
865 MCBinaryExpr::CreateSub(MBBSymbolExpr,
866 MCSymbolRefExpr::Create(JTISymbol, OutContext),
868 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
870 OutStreamer.EmitValue(Expr, OffsetWidth);
874 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
876 unsigned NOps = MI->getNumOperands();
878 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
879 // cast away const; DIetc do not take const operands for some reason.
880 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
883 // Frame address. Currently handles register +- offset only.
884 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
885 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
888 printOperand(MI, NOps-2, OS);
891 static void populateADROperands(MCInst &Inst, unsigned Dest,
892 const MCSymbol *Label,
893 unsigned pred, unsigned ccreg,
895 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
896 Inst.addOperand(MCOperand::CreateReg(Dest));
897 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
898 // Add predicate operands.
899 Inst.addOperand(MCOperand::CreateImm(pred));
900 Inst.addOperand(MCOperand::CreateReg(ccreg));
903 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
907 // Emit the instruction as usual, just patch the opcode.
908 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
909 TmpInst.setOpcode(Opcode);
910 OutStreamer.EmitInstruction(TmpInst);
913 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
914 assert(MI->getFlag(MachineInstr::FrameSetup) &&
915 "Only instruction which are involved into frame setup code are allowed");
917 const MachineFunction &MF = *MI->getParent()->getParent();
918 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
919 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
921 unsigned FramePtr = RegInfo->getFrameRegister(MF);
922 unsigned Opc = MI->getOpcode();
923 unsigned SrcReg, DstReg;
925 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
926 // Two special cases:
927 // 1) tPUSH does not have src/dst regs.
928 // 2) for Thumb1 code we sometimes materialize the constant via constpool
929 // load. Yes, this is pretty fragile, but for now I don't see better
931 SrcReg = DstReg = ARM::SP;
933 SrcReg = MI->getOperand(1).getReg();
934 DstReg = MI->getOperand(0).getReg();
937 // Try to figure out the unwinding opcode out of src / dst regs.
938 if (MI->getDesc().mayStore()) {
940 assert(DstReg == ARM::SP &&
941 "Only stack pointer as a destination reg is supported");
943 SmallVector<unsigned, 4> RegList;
944 // Skip src & dst reg, and pred ops.
945 unsigned StartOp = 2 + 2;
946 // Use all the operands.
947 unsigned NumOffset = 0;
952 assert(0 && "Unsupported opcode for unwinding information");
954 // Special case here: no src & dst reg, but two extra imp ops.
955 StartOp = 2; NumOffset = 2;
957 case ARM::t2STMDB_UPD:
958 case ARM::VSTMDDB_UPD:
959 assert(SrcReg == ARM::SP &&
960 "Only stack pointer as a source reg is supported");
961 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
963 RegList.push_back(MI->getOperand(i).getReg());
966 assert(MI->getOperand(2).getReg() == ARM::SP &&
967 "Only stack pointer as a source reg is supported");
968 RegList.push_back(SrcReg);
971 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
973 // Changes of stack / frame pointer.
974 if (SrcReg == ARM::SP) {
979 assert(0 && "Unsupported opcode for unwinding information");
981 case ARM::tMOVgpr2gpr:
982 case ARM::tMOVgpr2tgpr:
986 Offset = -MI->getOperand(2).getImm();
990 Offset = MI->getOperand(2).getImm();
993 Offset = MI->getOperand(2).getImm()*4;
997 Offset = -MI->getOperand(2).getImm()*4;
1000 // Grab the constpool index and check, whether it corresponds to
1001 // original or cloned constpool entry.
1002 unsigned CPI = MI->getOperand(1).getIndex();
1003 const MachineConstantPool *MCP = MF.getConstantPool();
1004 if (CPI >= MCP->getConstants().size())
1005 CPI = AFI.getOriginalCPIdx(CPI);
1006 assert(CPI != -1U && "Invalid constpool index");
1008 // Derive the actual offset.
1009 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1010 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1011 // FIXME: Check for user, it should be "add" instruction!
1012 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1017 if (DstReg == FramePtr && FramePtr != ARM::SP)
1018 // Set-up of the frame pointer. Positive values correspond to "add"
1020 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1021 else if (DstReg == ARM::SP) {
1022 // Change of SP by an offset. Positive values correspond to "sub"
1024 OutStreamer.EmitPad(Offset);
1027 assert(0 && "Unsupported opcode for unwinding information");
1029 } else if (DstReg == ARM::SP) {
1030 // FIXME: .movsp goes here
1032 assert(0 && "Unsupported opcode for unwinding information");
1036 assert(0 && "Unsupported opcode for unwinding information");
1041 extern cl::opt<bool> EnableARMEHABI;
1043 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1044 unsigned Opc = MI->getOpcode();
1048 // B is just a Bcc with an 'always' predicate.
1050 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1051 TmpInst.setOpcode(ARM::Bcc);
1052 // Add predicate operands.
1053 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1054 TmpInst.addOperand(MCOperand::CreateReg(0));
1055 OutStreamer.EmitInstruction(TmpInst);
1058 case ARM::LDMIA_RET: {
1059 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
1060 // such has additional code-gen properties and scheduling information.
1061 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
1063 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1064 TmpInst.setOpcode(ARM::LDMIA_UPD);
1065 OutStreamer.EmitInstruction(TmpInst);
1068 case ARM::t2ADDrSPi:
1069 case ARM::t2ADDrSPi12:
1070 case ARM::t2SUBrSPi:
1071 case ARM::t2SUBrSPi12:
1072 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
1073 "Unexpected source register!");
1076 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1077 case ARM::DBG_VALUE: {
1078 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1079 SmallString<128> TmpStr;
1080 raw_svector_ostream OS(TmpStr);
1081 PrintDebugValueComment(MI, OS);
1082 OutStreamer.EmitRawText(StringRef(OS.str()));
1088 TmpInst.setOpcode(ARM::tBL);
1089 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
1090 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
1091 OutStreamer.EmitInstruction(TmpInst);
1095 case ARM::tLEApcrel:
1096 case ARM::t2LEApcrel: {
1097 // FIXME: Need to also handle globals and externals
1099 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1100 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1102 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1103 GetCPISymbol(MI->getOperand(1).getIndex()),
1104 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1106 OutStreamer.EmitInstruction(TmpInst);
1109 case ARM::LEApcrelJT:
1110 case ARM::tLEApcrelJT:
1111 case ARM::t2LEApcrelJT: {
1113 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1114 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1116 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1117 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1118 MI->getOperand(2).getImm()),
1119 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1121 OutStreamer.EmitInstruction(TmpInst);
1124 case ARM::MOVPCRX: {
1126 TmpInst.setOpcode(ARM::MOVr);
1127 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1128 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1129 // Add predicate operands.
1130 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1131 TmpInst.addOperand(MCOperand::CreateReg(0));
1132 // Add 's' bit operand (always reg0 for this)
1133 TmpInst.addOperand(MCOperand::CreateReg(0));
1134 OutStreamer.EmitInstruction(TmpInst);
1137 // Darwin call instructions are just normal call instructions with different
1138 // clobber semantics (they clobber R9).
1140 case ARM::BLr9_pred:
1142 case ARM::BLXr9_pred: {
1146 case ARM::BLr9: newOpc = ARM::BL; break;
1147 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1148 case ARM::BLXr9: newOpc = ARM::BLX; break;
1149 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1152 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1153 TmpInst.setOpcode(newOpc);
1154 OutStreamer.EmitInstruction(TmpInst);
1157 case ARM::BXr9_CALL:
1158 case ARM::BX_CALL: {
1161 TmpInst.setOpcode(ARM::MOVr);
1162 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1163 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1164 // Add predicate operands.
1165 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1166 TmpInst.addOperand(MCOperand::CreateReg(0));
1167 // Add 's' bit operand (always reg0 for this)
1168 TmpInst.addOperand(MCOperand::CreateReg(0));
1169 OutStreamer.EmitInstruction(TmpInst);
1173 TmpInst.setOpcode(ARM::BX);
1174 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1175 OutStreamer.EmitInstruction(TmpInst);
1179 case ARM::BMOVPCRXr9_CALL:
1180 case ARM::BMOVPCRX_CALL: {
1183 TmpInst.setOpcode(ARM::MOVr);
1184 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1185 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1186 // Add predicate operands.
1187 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1188 TmpInst.addOperand(MCOperand::CreateReg(0));
1189 // Add 's' bit operand (always reg0 for this)
1190 TmpInst.addOperand(MCOperand::CreateReg(0));
1191 OutStreamer.EmitInstruction(TmpInst);
1195 TmpInst.setOpcode(ARM::MOVr);
1196 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1197 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1198 // Add predicate operands.
1199 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1200 TmpInst.addOperand(MCOperand::CreateReg(0));
1201 // Add 's' bit operand (always reg0 for this)
1202 TmpInst.addOperand(MCOperand::CreateReg(0));
1203 OutStreamer.EmitInstruction(TmpInst);
1207 case ARM::MOVi16_ga_pcrel:
1208 case ARM::t2MOVi16_ga_pcrel: {
1210 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1211 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1213 unsigned TF = MI->getOperand(1).getTargetFlags();
1214 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1215 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1216 MCSymbol *GVSym = GetARMGVSymbol(GV);
1217 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1219 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1220 getFunctionNumber(),
1221 MI->getOperand(2).getImm(), OutContext);
1222 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1223 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1224 const MCExpr *PCRelExpr =
1225 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1226 MCBinaryExpr::CreateAdd(LabelSymExpr,
1227 MCConstantExpr::Create(PCAdj, OutContext),
1228 OutContext), OutContext), OutContext);
1229 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1231 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1232 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1235 // Add predicate operands.
1236 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1237 TmpInst.addOperand(MCOperand::CreateReg(0));
1238 // Add 's' bit operand (always reg0 for this)
1239 TmpInst.addOperand(MCOperand::CreateReg(0));
1240 OutStreamer.EmitInstruction(TmpInst);
1243 case ARM::MOVTi16_ga_pcrel:
1244 case ARM::t2MOVTi16_ga_pcrel: {
1246 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1247 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1248 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1249 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1251 unsigned TF = MI->getOperand(2).getTargetFlags();
1252 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1253 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1254 MCSymbol *GVSym = GetARMGVSymbol(GV);
1255 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1257 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1258 getFunctionNumber(),
1259 MI->getOperand(3).getImm(), OutContext);
1260 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1261 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1262 const MCExpr *PCRelExpr =
1263 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1264 MCBinaryExpr::CreateAdd(LabelSymExpr,
1265 MCConstantExpr::Create(PCAdj, OutContext),
1266 OutContext), OutContext), OutContext);
1267 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1269 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1270 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1272 // Add predicate operands.
1273 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1274 TmpInst.addOperand(MCOperand::CreateReg(0));
1275 // Add 's' bit operand (always reg0 for this)
1276 TmpInst.addOperand(MCOperand::CreateReg(0));
1277 OutStreamer.EmitInstruction(TmpInst);
1280 case ARM::tPICADD: {
1281 // This is a pseudo op for a label + instruction sequence, which looks like:
1284 // This adds the address of LPC0 to r0.
1287 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1288 getFunctionNumber(), MI->getOperand(2).getImm(),
1291 // Form and emit the add.
1293 AddInst.setOpcode(ARM::tADDhirr);
1294 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1295 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1296 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1297 // Add predicate operands.
1298 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1299 AddInst.addOperand(MCOperand::CreateReg(0));
1300 OutStreamer.EmitInstruction(AddInst);
1304 // This is a pseudo op for a label + instruction sequence, which looks like:
1307 // This adds the address of LPC0 to r0.
1310 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1311 getFunctionNumber(), MI->getOperand(2).getImm(),
1314 // Form and emit the add.
1316 AddInst.setOpcode(ARM::ADDrr);
1317 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1318 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1319 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1320 // Add predicate operands.
1321 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1322 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1323 // Add 's' bit operand (always reg0 for this)
1324 AddInst.addOperand(MCOperand::CreateReg(0));
1325 OutStreamer.EmitInstruction(AddInst);
1335 case ARM::PICLDRSH: {
1336 // This is a pseudo op for a label + instruction sequence, which looks like:
1339 // The LCP0 label is referenced by a constant pool entry in order to get
1340 // a PC-relative address at the ldr instruction.
1343 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1344 getFunctionNumber(), MI->getOperand(2).getImm(),
1347 // Form and emit the load
1349 switch (MI->getOpcode()) {
1351 llvm_unreachable("Unexpected opcode!");
1352 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1353 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1354 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1355 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1356 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1357 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1358 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1359 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1362 LdStInst.setOpcode(Opcode);
1363 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1364 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1365 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1366 LdStInst.addOperand(MCOperand::CreateImm(0));
1367 // Add predicate operands.
1368 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1369 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1370 OutStreamer.EmitInstruction(LdStInst);
1374 case ARM::CONSTPOOL_ENTRY: {
1375 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1376 /// in the function. The first operand is the ID# for this instruction, the
1377 /// second is the index into the MachineConstantPool that this is, the third
1378 /// is the size in bytes of this constant pool entry.
1379 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1380 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1383 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1385 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1386 if (MCPE.isMachineConstantPoolEntry())
1387 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1389 EmitGlobalConstant(MCPE.Val.ConstVal);
1393 case ARM::t2BR_JT: {
1394 // Lower and emit the instruction itself, then the jump table following it.
1396 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1397 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1398 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1399 // Add predicate operands.
1400 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1401 TmpInst.addOperand(MCOperand::CreateReg(0));
1402 OutStreamer.EmitInstruction(TmpInst);
1403 // Output the data for the jump table itself
1407 case ARM::t2TBB_JT: {
1408 // Lower and emit the instruction itself, then the jump table following it.
1411 TmpInst.setOpcode(ARM::t2TBB);
1412 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1413 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1414 // Add predicate operands.
1415 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1416 TmpInst.addOperand(MCOperand::CreateReg(0));
1417 OutStreamer.EmitInstruction(TmpInst);
1418 // Output the data for the jump table itself
1420 // Make sure the next instruction is 2-byte aligned.
1424 case ARM::t2TBH_JT: {
1425 // Lower and emit the instruction itself, then the jump table following it.
1428 TmpInst.setOpcode(ARM::t2TBH);
1429 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1430 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1431 // Add predicate operands.
1432 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1433 TmpInst.addOperand(MCOperand::CreateReg(0));
1434 OutStreamer.EmitInstruction(TmpInst);
1435 // Output the data for the jump table itself
1441 // Lower and emit the instruction itself, then the jump table following it.
1444 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1445 ARM::MOVr : ARM::tMOVgpr2gpr;
1446 TmpInst.setOpcode(Opc);
1447 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1448 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1449 // Add predicate operands.
1450 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1451 TmpInst.addOperand(MCOperand::CreateReg(0));
1452 // Add 's' bit operand (always reg0 for this)
1453 if (Opc == ARM::MOVr)
1454 TmpInst.addOperand(MCOperand::CreateReg(0));
1455 OutStreamer.EmitInstruction(TmpInst);
1457 // Make sure the Thumb jump table is 4-byte aligned.
1458 if (Opc == ARM::tMOVgpr2gpr)
1461 // Output the data for the jump table itself
1466 // Lower and emit the instruction itself, then the jump table following it.
1469 if (MI->getOperand(1).getReg() == 0) {
1471 TmpInst.setOpcode(ARM::LDRi12);
1472 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1473 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1474 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1476 TmpInst.setOpcode(ARM::LDRrs);
1477 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1478 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1479 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1480 TmpInst.addOperand(MCOperand::CreateImm(0));
1482 // Add predicate operands.
1483 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1484 TmpInst.addOperand(MCOperand::CreateReg(0));
1485 OutStreamer.EmitInstruction(TmpInst);
1487 // Output the data for the jump table itself
1491 case ARM::BR_JTadd: {
1492 // Lower and emit the instruction itself, then the jump table following it.
1493 // add pc, target, idx
1495 TmpInst.setOpcode(ARM::ADDrr);
1496 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1497 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1498 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1499 // Add predicate operands.
1500 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1501 TmpInst.addOperand(MCOperand::CreateReg(0));
1502 // Add 's' bit operand (always reg0 for this)
1503 TmpInst.addOperand(MCOperand::CreateReg(0));
1504 OutStreamer.EmitInstruction(TmpInst);
1506 // Output the data for the jump table itself
1511 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1512 // FIXME: Remove this special case when they do.
1513 if (!Subtarget->isTargetDarwin()) {
1514 //.long 0xe7ffdefe @ trap
1515 uint32_t Val = 0xe7ffdefeUL;
1516 OutStreamer.AddComment("trap");
1517 OutStreamer.EmitIntValue(Val, 4);
1523 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1524 // FIXME: Remove this special case when they do.
1525 if (!Subtarget->isTargetDarwin()) {
1526 //.short 57086 @ trap
1527 uint16_t Val = 0xdefe;
1528 OutStreamer.AddComment("trap");
1529 OutStreamer.EmitIntValue(Val, 2);
1534 case ARM::t2Int_eh_sjlj_setjmp:
1535 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1536 case ARM::tInt_eh_sjlj_setjmp: {
1537 // Two incoming args: GPR:$src, GPR:$val
1540 // str $val, [$src, #4]
1545 unsigned SrcReg = MI->getOperand(0).getReg();
1546 unsigned ValReg = MI->getOperand(1).getReg();
1547 MCSymbol *Label = GetARMSJLJEHLabel();
1550 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1551 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1552 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1554 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1555 OutStreamer.AddComment("eh_setjmp begin");
1556 OutStreamer.EmitInstruction(TmpInst);
1560 TmpInst.setOpcode(ARM::tADDi3);
1561 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1563 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1564 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1565 TmpInst.addOperand(MCOperand::CreateImm(7));
1567 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1568 TmpInst.addOperand(MCOperand::CreateReg(0));
1569 OutStreamer.EmitInstruction(TmpInst);
1573 TmpInst.setOpcode(ARM::tSTRi);
1574 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1575 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1576 // The offset immediate is #4. The operand value is scaled by 4 for the
1577 // tSTR instruction.
1578 TmpInst.addOperand(MCOperand::CreateImm(1));
1580 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1581 TmpInst.addOperand(MCOperand::CreateReg(0));
1582 OutStreamer.EmitInstruction(TmpInst);
1586 TmpInst.setOpcode(ARM::tMOVi8);
1587 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1588 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1589 TmpInst.addOperand(MCOperand::CreateImm(0));
1591 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1592 TmpInst.addOperand(MCOperand::CreateReg(0));
1593 OutStreamer.EmitInstruction(TmpInst);
1596 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1598 TmpInst.setOpcode(ARM::tB);
1599 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1600 OutStreamer.EmitInstruction(TmpInst);
1604 TmpInst.setOpcode(ARM::tMOVi8);
1605 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1606 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1607 TmpInst.addOperand(MCOperand::CreateImm(1));
1609 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1610 TmpInst.addOperand(MCOperand::CreateReg(0));
1611 OutStreamer.AddComment("eh_setjmp end");
1612 OutStreamer.EmitInstruction(TmpInst);
1614 OutStreamer.EmitLabel(Label);
1618 case ARM::Int_eh_sjlj_setjmp_nofp:
1619 case ARM::Int_eh_sjlj_setjmp: {
1620 // Two incoming args: GPR:$src, GPR:$val
1622 // str $val, [$src, #+4]
1626 unsigned SrcReg = MI->getOperand(0).getReg();
1627 unsigned ValReg = MI->getOperand(1).getReg();
1631 TmpInst.setOpcode(ARM::ADDri);
1632 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1633 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1634 TmpInst.addOperand(MCOperand::CreateImm(8));
1636 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1637 TmpInst.addOperand(MCOperand::CreateReg(0));
1638 // 's' bit operand (always reg0 for this).
1639 TmpInst.addOperand(MCOperand::CreateReg(0));
1640 OutStreamer.AddComment("eh_setjmp begin");
1641 OutStreamer.EmitInstruction(TmpInst);
1645 TmpInst.setOpcode(ARM::STRi12);
1646 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1647 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1648 TmpInst.addOperand(MCOperand::CreateImm(4));
1650 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1651 TmpInst.addOperand(MCOperand::CreateReg(0));
1652 OutStreamer.EmitInstruction(TmpInst);
1656 TmpInst.setOpcode(ARM::MOVi);
1657 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1658 TmpInst.addOperand(MCOperand::CreateImm(0));
1660 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1661 TmpInst.addOperand(MCOperand::CreateReg(0));
1662 // 's' bit operand (always reg0 for this).
1663 TmpInst.addOperand(MCOperand::CreateReg(0));
1664 OutStreamer.EmitInstruction(TmpInst);
1668 TmpInst.setOpcode(ARM::ADDri);
1669 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1670 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1671 TmpInst.addOperand(MCOperand::CreateImm(0));
1673 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1674 TmpInst.addOperand(MCOperand::CreateReg(0));
1675 // 's' bit operand (always reg0 for this).
1676 TmpInst.addOperand(MCOperand::CreateReg(0));
1677 OutStreamer.EmitInstruction(TmpInst);
1681 TmpInst.setOpcode(ARM::MOVi);
1682 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1683 TmpInst.addOperand(MCOperand::CreateImm(1));
1685 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1686 TmpInst.addOperand(MCOperand::CreateReg(0));
1687 // 's' bit operand (always reg0 for this).
1688 TmpInst.addOperand(MCOperand::CreateReg(0));
1689 OutStreamer.AddComment("eh_setjmp end");
1690 OutStreamer.EmitInstruction(TmpInst);
1694 case ARM::Int_eh_sjlj_longjmp: {
1695 // ldr sp, [$src, #8]
1696 // ldr $scratch, [$src, #4]
1699 unsigned SrcReg = MI->getOperand(0).getReg();
1700 unsigned ScratchReg = MI->getOperand(1).getReg();
1703 TmpInst.setOpcode(ARM::LDRi12);
1704 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1705 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1706 TmpInst.addOperand(MCOperand::CreateImm(8));
1708 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1709 TmpInst.addOperand(MCOperand::CreateReg(0));
1710 OutStreamer.EmitInstruction(TmpInst);
1714 TmpInst.setOpcode(ARM::LDRi12);
1715 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1716 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1717 TmpInst.addOperand(MCOperand::CreateImm(4));
1719 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1720 TmpInst.addOperand(MCOperand::CreateReg(0));
1721 OutStreamer.EmitInstruction(TmpInst);
1725 TmpInst.setOpcode(ARM::LDRi12);
1726 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1727 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1728 TmpInst.addOperand(MCOperand::CreateImm(0));
1730 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1731 TmpInst.addOperand(MCOperand::CreateReg(0));
1732 OutStreamer.EmitInstruction(TmpInst);
1736 TmpInst.setOpcode(ARM::BX);
1737 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1739 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1740 TmpInst.addOperand(MCOperand::CreateReg(0));
1741 OutStreamer.EmitInstruction(TmpInst);
1745 case ARM::tInt_eh_sjlj_longjmp: {
1746 // ldr $scratch, [$src, #8]
1748 // ldr $scratch, [$src, #4]
1751 unsigned SrcReg = MI->getOperand(0).getReg();
1752 unsigned ScratchReg = MI->getOperand(1).getReg();
1755 TmpInst.setOpcode(ARM::tLDRi);
1756 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1757 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1758 // The offset immediate is #8. The operand value is scaled by 4 for the
1759 // tLDR instruction.
1760 TmpInst.addOperand(MCOperand::CreateImm(2));
1762 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1763 TmpInst.addOperand(MCOperand::CreateReg(0));
1764 OutStreamer.EmitInstruction(TmpInst);
1768 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1769 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1770 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1772 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1773 TmpInst.addOperand(MCOperand::CreateReg(0));
1774 OutStreamer.EmitInstruction(TmpInst);
1778 TmpInst.setOpcode(ARM::tLDRi);
1779 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1780 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1781 TmpInst.addOperand(MCOperand::CreateImm(1));
1783 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1784 TmpInst.addOperand(MCOperand::CreateReg(0));
1785 OutStreamer.EmitInstruction(TmpInst);
1789 TmpInst.setOpcode(ARM::tLDRr);
1790 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1791 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1792 TmpInst.addOperand(MCOperand::CreateReg(0));
1794 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1795 TmpInst.addOperand(MCOperand::CreateReg(0));
1796 OutStreamer.EmitInstruction(TmpInst);
1800 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1801 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1803 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1804 TmpInst.addOperand(MCOperand::CreateReg(0));
1805 OutStreamer.EmitInstruction(TmpInst);
1809 // Tail jump branches are really just branch instructions with additional
1810 // code-gen attributes. Convert them to the canonical form here.
1812 case ARM::TAILJMPdND: {
1813 MCInst TmpInst, TmpInst2;
1814 // Lower the instruction as-is to get the operands properly converted.
1815 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1816 TmpInst.setOpcode(ARM::Bcc);
1817 TmpInst.addOperand(TmpInst2.getOperand(0));
1818 // Add predicate operands.
1819 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1820 TmpInst.addOperand(MCOperand::CreateReg(0));
1821 OutStreamer.AddComment("TAILCALL");
1822 OutStreamer.EmitInstruction(TmpInst);
1825 case ARM::tTAILJMPd:
1826 case ARM::tTAILJMPdND: {
1827 MCInst TmpInst, TmpInst2;
1828 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1829 TmpInst.setOpcode(ARM::tB);
1830 TmpInst.addOperand(TmpInst2.getOperand(0));
1831 OutStreamer.AddComment("TAILCALL");
1832 OutStreamer.EmitInstruction(TmpInst);
1835 case ARM::TAILJMPrND:
1836 case ARM::tTAILJMPrND:
1838 case ARM::tTAILJMPr: {
1839 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1840 ? ARM::BX : ARM::tBX;
1842 TmpInst.setOpcode(newOpc);
1843 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1845 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1846 TmpInst.addOperand(MCOperand::CreateReg(0));
1847 OutStreamer.AddComment("TAILCALL");
1848 OutStreamer.EmitInstruction(TmpInst);
1852 // These are the pseudos created to comply with stricter operand restrictions
1853 // on ARMv5. Lower them now to "normal" instructions, since all the
1854 // restrictions are already satisfied.
1856 EmitPatchedInstruction(MI, ARM::MUL);
1859 EmitPatchedInstruction(MI, ARM::MLA);
1862 EmitPatchedInstruction(MI, ARM::SMULL);
1865 EmitPatchedInstruction(MI, ARM::UMULL);
1868 EmitPatchedInstruction(MI, ARM::SMLAL);
1871 EmitPatchedInstruction(MI, ARM::UMLAL);
1874 EmitPatchedInstruction(MI, ARM::UMAAL);
1879 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1881 // Emit unwinding stuff for frame-related instructions
1882 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1883 EmitUnwindingInstruction(MI);
1885 OutStreamer.EmitInstruction(TmpInst);
1888 //===----------------------------------------------------------------------===//
1889 // Target Registry Stuff
1890 //===----------------------------------------------------------------------===//
1892 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1894 unsigned SyntaxVariant,
1895 const MCAsmInfo &MAI) {
1896 if (SyntaxVariant == 0)
1897 return new ARMInstPrinter(TM, MAI);
1901 // Force static initialization.
1902 extern "C" void LLVMInitializeARMAsmPrinter() {
1903 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1904 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1906 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1907 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);