1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
73 class AsmAttributeEmitter : public AttributeEmitter {
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
113 StringRef StringValue;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
129 Size += sizeof(int8_t); // Is this really necessary?
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
172 ContentsSize += getULEBSize(Attribute);
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor, 0);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag, 0);
199 default: llvm_unreachable("Invalid attribute type");
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue, 0);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(item.StringValue.upper(), 0);
205 Streamer.EmitIntValue(0, 1); // '\0'
214 } // end of anonymous namespace
216 MachineLocation ARMAsmPrinter::
217 getDebugValueLocation(const MachineInstr *MI) const {
218 MachineLocation Location;
219 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
220 // Frame address. Currently handles register +- offset only.
221 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
222 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
224 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
229 /// EmitDwarfRegOp - Emit dwarf register operation.
230 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
231 const TargetRegisterInfo *RI = TM.getRegisterInfo();
232 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
233 AsmPrinter::EmitDwarfRegOp(MLoc);
235 unsigned Reg = MLoc.getReg();
236 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
237 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
238 // S registers are described as bit-pieces of a register
239 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
240 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
242 unsigned SReg = Reg - ARM::S0;
243 bool odd = SReg & 0x1;
244 unsigned Rx = 256 + (SReg >> 1);
246 OutStreamer.AddComment("DW_OP_regx for S register");
247 EmitInt8(dwarf::DW_OP_regx);
249 OutStreamer.AddComment(Twine(SReg));
253 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
254 EmitInt8(dwarf::DW_OP_bit_piece);
258 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
259 EmitInt8(dwarf::DW_OP_bit_piece);
263 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
264 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
265 // Q registers Q0-Q15 are described by composing two D registers together.
266 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
269 unsigned QReg = Reg - ARM::Q0;
270 unsigned D1 = 256 + 2 * QReg;
271 unsigned D2 = D1 + 1;
273 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
274 EmitInt8(dwarf::DW_OP_regx);
276 OutStreamer.AddComment("DW_OP_piece 8");
277 EmitInt8(dwarf::DW_OP_piece);
280 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
281 EmitInt8(dwarf::DW_OP_regx);
283 OutStreamer.AddComment("DW_OP_piece 8");
284 EmitInt8(dwarf::DW_OP_piece);
290 void ARMAsmPrinter::EmitFunctionEntryLabel() {
291 OutStreamer.ForceCodeRegion();
293 if (AFI->isThumbFunction()) {
294 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
295 OutStreamer.EmitThumbFunc(CurrentFnSym);
298 OutStreamer.EmitLabel(CurrentFnSym);
301 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
302 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
303 assert(Size && "C++ constructor pointer had zero size!");
305 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
306 assert(GV && "C++ constructor pointer was not a GlobalValue!");
308 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
309 (Subtarget->isTargetDarwin()
310 ? MCSymbolRefExpr::VK_None
311 : MCSymbolRefExpr::VK_ARM_TARGET1),
314 OutStreamer.EmitValue(E, Size);
317 /// runOnMachineFunction - This uses the EmitInstruction()
318 /// method to print assembly for each instruction.
320 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
321 AFI = MF.getInfo<ARMFunctionInfo>();
322 MCP = MF.getConstantPool();
324 return AsmPrinter::runOnMachineFunction(MF);
327 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
328 raw_ostream &O, const char *Modifier) {
329 const MachineOperand &MO = MI->getOperand(OpNum);
330 unsigned TF = MO.getTargetFlags();
332 switch (MO.getType()) {
333 default: llvm_unreachable("<unknown operand type>");
334 case MachineOperand::MO_Register: {
335 unsigned Reg = MO.getReg();
336 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
337 assert(!MO.getSubReg() && "Subregs should be eliminated!");
338 O << ARMInstPrinter::getRegisterName(Reg);
341 case MachineOperand::MO_Immediate: {
342 int64_t Imm = MO.getImm();
344 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
345 (TF == ARMII::MO_LO16))
347 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
348 (TF == ARMII::MO_HI16))
353 case MachineOperand::MO_MachineBasicBlock:
354 O << *MO.getMBB()->getSymbol();
356 case MachineOperand::MO_GlobalAddress: {
357 const GlobalValue *GV = MO.getGlobal();
358 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
359 (TF & ARMII::MO_LO16))
361 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
362 (TF & ARMII::MO_HI16))
364 O << *Mang->getSymbol(GV);
366 printOffset(MO.getOffset(), O);
367 if (TF == ARMII::MO_PLT)
371 case MachineOperand::MO_ExternalSymbol: {
372 O << *GetExternalSymbolSymbol(MO.getSymbolName());
373 if (TF == ARMII::MO_PLT)
377 case MachineOperand::MO_ConstantPoolIndex:
378 O << *GetCPISymbol(MO.getIndex());
380 case MachineOperand::MO_JumpTableIndex:
381 O << *GetJTISymbol(MO.getIndex());
386 //===--------------------------------------------------------------------===//
388 MCSymbol *ARMAsmPrinter::
389 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
390 const MachineBasicBlock *MBB) const {
391 SmallString<60> Name;
392 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
393 << getFunctionNumber() << '_' << uid << '_' << uid2
394 << "_set_" << MBB->getNumber();
395 return OutContext.GetOrCreateSymbol(Name.str());
398 MCSymbol *ARMAsmPrinter::
399 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
400 SmallString<60> Name;
401 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
402 << getFunctionNumber() << '_' << uid << '_' << uid2;
403 return OutContext.GetOrCreateSymbol(Name.str());
407 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
408 SmallString<60> Name;
409 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
410 << getFunctionNumber();
411 return OutContext.GetOrCreateSymbol(Name.str());
414 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
415 unsigned AsmVariant, const char *ExtraCode,
417 // Does this asm operand have a single letter operand modifier?
418 if (ExtraCode && ExtraCode[0]) {
419 if (ExtraCode[1] != 0) return true; // Unknown modifier.
421 switch (ExtraCode[0]) {
422 default: return true; // Unknown modifier.
423 case 'a': // Print as a memory address.
424 if (MI->getOperand(OpNum).isReg()) {
426 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
431 case 'c': // Don't print "#" before an immediate operand.
432 if (!MI->getOperand(OpNum).isImm())
434 O << MI->getOperand(OpNum).getImm();
436 case 'P': // Print a VFP double precision register.
437 case 'q': // Print a NEON quad precision register.
438 printOperand(MI, OpNum, O);
440 case 'y': // Print a VFP single precision register as indexed double.
441 // This uses the ordering of the alias table to get the first 'd' register
442 // that overlaps the 's' register. Also, s0 is an odd register, hence the
443 // odd modulus check below.
444 if (MI->getOperand(OpNum).isReg()) {
445 unsigned Reg = MI->getOperand(OpNum).getReg();
446 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
447 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
448 (((Reg % 2) == 1) ? "[0]" : "[1]");
452 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
453 if (!MI->getOperand(OpNum).isImm())
455 O << ~(MI->getOperand(OpNum).getImm());
457 case 'L': // The low 16 bits of an immediate constant.
458 if (!MI->getOperand(OpNum).isImm())
460 O << (MI->getOperand(OpNum).getImm() & 0xffff);
462 case 'M': { // A register range suitable for LDM/STM.
463 if (!MI->getOperand(OpNum).isReg())
465 const MachineOperand &MO = MI->getOperand(OpNum);
466 unsigned RegBegin = MO.getReg();
467 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
468 // already got the operands in registers that are operands to the
469 // inline asm statement.
471 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
473 // FIXME: The register allocator not only may not have given us the
474 // registers in sequence, but may not be in ascending registers. This
475 // will require changes in the register allocator that'll need to be
476 // propagated down here if the operands change.
477 unsigned RegOps = OpNum + 1;
478 while (MI->getOperand(RegOps).isReg()) {
480 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
488 case 'R': // The most significant register of a pair.
489 case 'Q': { // The least significant register of a pair.
492 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
493 if (!FlagsOP.isImm())
495 unsigned Flags = FlagsOP.getImm();
496 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
499 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
500 if (RegOp >= MI->getNumOperands())
502 const MachineOperand &MO = MI->getOperand(RegOp);
505 unsigned Reg = MO.getReg();
506 O << ARMInstPrinter::getRegisterName(Reg);
510 case 'e': // The low doubleword register of a NEON quad register.
511 case 'f': { // The high doubleword register of a NEON quad register.
512 if (!MI->getOperand(OpNum).isReg())
514 unsigned Reg = MI->getOperand(OpNum).getReg();
515 if (!ARM::QPRRegClass.contains(Reg))
517 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
518 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
519 ARM::dsub_0 : ARM::dsub_1);
520 O << ARMInstPrinter::getRegisterName(SubReg);
524 // These modifiers are not yet supported.
525 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
526 case 'H': // The highest-numbered register of a pair.
531 printOperand(MI, OpNum, O);
535 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
536 unsigned OpNum, unsigned AsmVariant,
537 const char *ExtraCode,
539 // Does this asm operand have a single letter operand modifier?
540 if (ExtraCode && ExtraCode[0]) {
541 if (ExtraCode[1] != 0) return true; // Unknown modifier.
543 switch (ExtraCode[0]) {
544 case 'A': // A memory operand for a VLD1/VST1 instruction.
545 default: return true; // Unknown modifier.
546 case 'm': // The base register of a memory operand.
547 if (!MI->getOperand(OpNum).isReg())
549 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
554 const MachineOperand &MO = MI->getOperand(OpNum);
555 assert(MO.isReg() && "unexpected inline asm memory operand");
556 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
560 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
561 if (Subtarget->isTargetDarwin()) {
562 Reloc::Model RelocM = TM.getRelocationModel();
563 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
564 // Declare all the text sections up front (before the DWARF sections
565 // emitted by AsmPrinter::doInitialization) so the assembler will keep
566 // them together at the beginning of the object file. This helps
567 // avoid out-of-range branches that are due a fundamental limitation of
568 // the way symbol offsets are encoded with the current Darwin ARM
570 const TargetLoweringObjectFileMachO &TLOFMacho =
571 static_cast<const TargetLoweringObjectFileMachO &>(
572 getObjFileLowering());
573 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
574 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
575 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
576 if (RelocM == Reloc::DynamicNoPIC) {
577 const MCSection *sect =
578 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
579 MCSectionMachO::S_SYMBOL_STUBS,
580 12, SectionKind::getText());
581 OutStreamer.SwitchSection(sect);
583 const MCSection *sect =
584 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
585 MCSectionMachO::S_SYMBOL_STUBS,
586 16, SectionKind::getText());
587 OutStreamer.SwitchSection(sect);
589 const MCSection *StaticInitSect =
590 OutContext.getMachOSection("__TEXT", "__StaticInit",
591 MCSectionMachO::S_REGULAR |
592 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
593 SectionKind::getText());
594 OutStreamer.SwitchSection(StaticInitSect);
598 // Use unified assembler syntax.
599 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
601 // Emit ARM Build Attributes
602 if (Subtarget->isTargetELF())
607 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
608 if (Subtarget->isTargetDarwin()) {
609 // All darwin targets use mach-o.
610 const TargetLoweringObjectFileMachO &TLOFMacho =
611 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
612 MachineModuleInfoMachO &MMIMacho =
613 MMI->getObjFileInfo<MachineModuleInfoMachO>();
615 // Output non-lazy-pointers for external and common global variables.
616 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
618 if (!Stubs.empty()) {
619 // Switch with ".non_lazy_symbol_pointer" directive.
620 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
622 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
624 OutStreamer.EmitLabel(Stubs[i].first);
625 // .indirect_symbol _foo
626 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
627 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
630 // External to current translation unit.
631 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
633 // Internal to current translation unit.
635 // When we place the LSDA into the TEXT section, the type info
636 // pointers need to be indirect and pc-rel. We accomplish this by
637 // using NLPs; however, sometimes the types are local to the file.
638 // We need to fill in the value for the NLP in those cases.
639 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
641 4/*size*/, 0/*addrspace*/);
645 OutStreamer.AddBlankLine();
648 Stubs = MMIMacho.GetHiddenGVStubList();
649 if (!Stubs.empty()) {
650 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
652 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
654 OutStreamer.EmitLabel(Stubs[i].first);
656 OutStreamer.EmitValue(MCSymbolRefExpr::
657 Create(Stubs[i].second.getPointer(),
659 4/*size*/, 0/*addrspace*/);
663 OutStreamer.AddBlankLine();
666 // Funny Darwin hack: This flag tells the linker that no global symbols
667 // contain code that falls through to other global symbols (e.g. the obvious
668 // implementation of multiple entry points). If this doesn't occur, the
669 // linker can safely perform dead code stripping. Since LLVM never
670 // generates code that does this, it is always safe to set.
671 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
675 //===----------------------------------------------------------------------===//
676 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
678 // The following seem like one-off assembler flags, but they actually need
679 // to appear in the .ARM.attributes section in ELF.
680 // Instead of subclassing the MCELFStreamer, we do the work here.
682 void ARMAsmPrinter::emitAttributes() {
684 emitARMAttributeSection();
686 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
687 bool emitFPU = false;
688 AttributeEmitter *AttrEmitter;
689 if (OutStreamer.hasRawTextSupport()) {
690 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
693 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
694 AttrEmitter = new ObjectAttributeEmitter(O);
697 AttrEmitter->MaybeSwitchVendor("aeabi");
699 std::string CPUString = Subtarget->getCPUString();
701 if (CPUString == "cortex-a8" ||
702 Subtarget->isCortexA8()) {
703 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
704 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
706 ARMBuildAttrs::ApplicationProfile);
707 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
708 ARMBuildAttrs::Allowed);
709 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
710 ARMBuildAttrs::AllowThumb32);
711 // Fixme: figure out when this is emitted.
712 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
713 // ARMBuildAttrs::AllowWMMXv1);
716 /// ADD additional Else-cases here!
717 } else if (CPUString == "xscale") {
718 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
719 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
720 ARMBuildAttrs::Allowed);
721 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
722 ARMBuildAttrs::Allowed);
723 } else if (CPUString == "generic") {
724 // FIXME: Why these defaults?
725 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
726 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
727 ARMBuildAttrs::Allowed);
728 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
729 ARMBuildAttrs::Allowed);
732 if (Subtarget->hasNEON() && emitFPU) {
733 /* NEON is not exactly a VFP architecture, but GAS emit one of
734 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
735 if (Subtarget->hasNEONVFP4())
736 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon-vfpv4");
738 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
739 /* If emitted for NEON, omit from VFP below, since you can have both
740 * NEON and VFP in build attributes but only one .fpu */
745 if (Subtarget->hasVFP4()) {
746 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
747 ARMBuildAttrs::AllowFPv4A);
749 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
752 } else if (Subtarget->hasVFP3()) {
753 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
754 ARMBuildAttrs::AllowFPv3A);
756 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
759 } else if (Subtarget->hasVFP2()) {
760 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
761 ARMBuildAttrs::AllowFPv2);
763 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
766 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
767 * since NEON can have 1 (allowed) or 2 (MAC operations) */
768 if (Subtarget->hasNEON()) {
769 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
770 ARMBuildAttrs::Allowed);
773 // Signal various FP modes.
774 if (!TM.Options.UnsafeFPMath) {
775 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
776 ARMBuildAttrs::Allowed);
777 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
778 ARMBuildAttrs::Allowed);
781 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
782 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
783 ARMBuildAttrs::Allowed);
785 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
786 ARMBuildAttrs::AllowIEE754);
788 // FIXME: add more flags to ARMBuildAttrs.h
789 // 8-bytes alignment stuff.
790 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
791 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
793 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
794 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
795 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
796 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
798 // FIXME: Should we signal R9 usage?
800 if (Subtarget->hasDivide())
801 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
803 AttrEmitter->Finish();
807 void ARMAsmPrinter::emitARMAttributeSection() {
809 // [ <section-length> "vendor-name"
810 // [ <file-tag> <size> <attribute>*
811 // | <section-tag> <size> <section-number>* 0 <attribute>*
812 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
816 if (OutStreamer.hasRawTextSupport())
819 const ARMElfTargetObjectFile &TLOFELF =
820 static_cast<const ARMElfTargetObjectFile &>
821 (getObjFileLowering());
823 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
826 OutStreamer.EmitIntValue(0x41, 1);
829 //===----------------------------------------------------------------------===//
831 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
832 unsigned LabelId, MCContext &Ctx) {
834 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
835 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
839 static MCSymbolRefExpr::VariantKind
840 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
842 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
843 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
844 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
845 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
846 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
847 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
849 llvm_unreachable("Invalid ARMCPModifier!");
852 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
853 bool isIndirect = Subtarget->isTargetDarwin() &&
854 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
856 return Mang->getSymbol(GV);
858 // FIXME: Remove this when Darwin transition to @GOT like syntax.
859 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
860 MachineModuleInfoMachO &MMIMachO =
861 MMI->getObjFileInfo<MachineModuleInfoMachO>();
862 MachineModuleInfoImpl::StubValueTy &StubSym =
863 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
864 MMIMachO.getGVStubEntry(MCSym);
865 if (StubSym.getPointer() == 0)
866 StubSym = MachineModuleInfoImpl::
867 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
872 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
873 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
875 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
878 if (ACPV->isLSDA()) {
879 SmallString<128> Str;
880 raw_svector_ostream OS(Str);
881 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
882 MCSym = OutContext.GetOrCreateSymbol(OS.str());
883 } else if (ACPV->isBlockAddress()) {
884 const BlockAddress *BA =
885 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
886 MCSym = GetBlockAddressSymbol(BA);
887 } else if (ACPV->isGlobalValue()) {
888 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
889 MCSym = GetARMGVSymbol(GV);
890 } else if (ACPV->isMachineBasicBlock()) {
891 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
892 MCSym = MBB->getSymbol();
894 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
895 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
896 MCSym = GetExternalSymbolSymbol(Sym);
899 // Create an MCSymbol for the reference.
901 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
904 if (ACPV->getPCAdjustment()) {
905 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
909 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
911 MCBinaryExpr::CreateAdd(PCRelExpr,
912 MCConstantExpr::Create(ACPV->getPCAdjustment(),
915 if (ACPV->mustAddCurrentAddress()) {
916 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
917 // label, so just emit a local label end reference that instead.
918 MCSymbol *DotSym = OutContext.CreateTempSymbol();
919 OutStreamer.EmitLabel(DotSym);
920 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
921 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
923 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
925 OutStreamer.EmitValue(Expr, Size);
928 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
929 unsigned Opcode = MI->getOpcode();
931 if (Opcode == ARM::BR_JTadd)
933 else if (Opcode == ARM::BR_JTm)
936 const MachineOperand &MO1 = MI->getOperand(OpNum);
937 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
938 unsigned JTI = MO1.getIndex();
940 // Tag the jump table appropriately for precise disassembly.
941 OutStreamer.EmitJumpTable32Region();
943 // Emit a label for the jump table.
944 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
945 OutStreamer.EmitLabel(JTISymbol);
947 // Emit each entry of the table.
948 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
949 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
950 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
952 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
953 MachineBasicBlock *MBB = JTBBs[i];
954 // Construct an MCExpr for the entry. We want a value of the form:
955 // (BasicBlockAddr - TableBeginAddr)
957 // For example, a table with entries jumping to basic blocks BB0 and BB1
960 // .word (LBB0 - LJTI_0_0)
961 // .word (LBB1 - LJTI_0_0)
962 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
964 if (TM.getRelocationModel() == Reloc::PIC_)
965 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
968 // If we're generating a table of Thumb addresses in static relocation
969 // model, we need to add one to keep interworking correctly.
970 else if (AFI->isThumbFunction())
971 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
973 OutStreamer.EmitValue(Expr, 4);
977 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
978 unsigned Opcode = MI->getOpcode();
979 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
980 const MachineOperand &MO1 = MI->getOperand(OpNum);
981 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
982 unsigned JTI = MO1.getIndex();
984 // Emit a label for the jump table.
985 if (MI->getOpcode() == ARM::t2TBB_JT) {
986 OutStreamer.EmitJumpTable8Region();
987 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
988 OutStreamer.EmitJumpTable16Region();
990 OutStreamer.EmitJumpTable32Region();
993 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
994 OutStreamer.EmitLabel(JTISymbol);
996 // Emit each entry of the table.
997 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
998 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
999 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1000 unsigned OffsetWidth = 4;
1001 if (MI->getOpcode() == ARM::t2TBB_JT)
1003 else if (MI->getOpcode() == ARM::t2TBH_JT)
1006 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1007 MachineBasicBlock *MBB = JTBBs[i];
1008 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1010 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1011 if (OffsetWidth == 4) {
1013 BrInst.setOpcode(ARM::t2B);
1014 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1015 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1016 BrInst.addOperand(MCOperand::CreateReg(0));
1017 OutStreamer.EmitInstruction(BrInst);
1020 // Otherwise it's an offset from the dispatch instruction. Construct an
1021 // MCExpr for the entry. We want a value of the form:
1022 // (BasicBlockAddr - TableBeginAddr) / 2
1024 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1027 // .byte (LBB0 - LJTI_0_0) / 2
1028 // .byte (LBB1 - LJTI_0_0) / 2
1029 const MCExpr *Expr =
1030 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1031 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1033 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1035 OutStreamer.EmitValue(Expr, OffsetWidth);
1039 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1041 unsigned NOps = MI->getNumOperands();
1043 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1044 // cast away const; DIetc do not take const operands for some reason.
1045 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1048 // Frame address. Currently handles register +- offset only.
1049 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1050 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1053 printOperand(MI, NOps-2, OS);
1056 static void populateADROperands(MCInst &Inst, unsigned Dest,
1057 const MCSymbol *Label,
1058 unsigned pred, unsigned ccreg,
1060 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1061 Inst.addOperand(MCOperand::CreateReg(Dest));
1062 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1063 // Add predicate operands.
1064 Inst.addOperand(MCOperand::CreateImm(pred));
1065 Inst.addOperand(MCOperand::CreateReg(ccreg));
1068 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1072 // Emit the instruction as usual, just patch the opcode.
1073 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1074 TmpInst.setOpcode(Opcode);
1075 OutStreamer.EmitInstruction(TmpInst);
1078 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1079 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1080 "Only instruction which are involved into frame setup code are allowed");
1082 const MachineFunction &MF = *MI->getParent()->getParent();
1083 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1084 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1086 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1087 unsigned Opc = MI->getOpcode();
1088 unsigned SrcReg, DstReg;
1090 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1091 // Two special cases:
1092 // 1) tPUSH does not have src/dst regs.
1093 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1094 // load. Yes, this is pretty fragile, but for now I don't see better
1096 SrcReg = DstReg = ARM::SP;
1098 SrcReg = MI->getOperand(1).getReg();
1099 DstReg = MI->getOperand(0).getReg();
1102 // Try to figure out the unwinding opcode out of src / dst regs.
1103 if (MI->mayStore()) {
1105 assert(DstReg == ARM::SP &&
1106 "Only stack pointer as a destination reg is supported");
1108 SmallVector<unsigned, 4> RegList;
1109 // Skip src & dst reg, and pred ops.
1110 unsigned StartOp = 2 + 2;
1111 // Use all the operands.
1112 unsigned NumOffset = 0;
1117 llvm_unreachable("Unsupported opcode for unwinding information");
1119 // Special case here: no src & dst reg, but two extra imp ops.
1120 StartOp = 2; NumOffset = 2;
1121 case ARM::STMDB_UPD:
1122 case ARM::t2STMDB_UPD:
1123 case ARM::VSTMDDB_UPD:
1124 assert(SrcReg == ARM::SP &&
1125 "Only stack pointer as a source reg is supported");
1126 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1128 RegList.push_back(MI->getOperand(i).getReg());
1130 case ARM::STR_PRE_IMM:
1131 case ARM::STR_PRE_REG:
1132 case ARM::t2STR_PRE:
1133 assert(MI->getOperand(2).getReg() == ARM::SP &&
1134 "Only stack pointer as a source reg is supported");
1135 RegList.push_back(SrcReg);
1138 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1140 // Changes of stack / frame pointer.
1141 if (SrcReg == ARM::SP) {
1146 llvm_unreachable("Unsupported opcode for unwinding information");
1152 Offset = -MI->getOperand(2).getImm();
1156 Offset = MI->getOperand(2).getImm();
1159 Offset = MI->getOperand(2).getImm()*4;
1163 Offset = -MI->getOperand(2).getImm()*4;
1165 case ARM::tLDRpci: {
1166 // Grab the constpool index and check, whether it corresponds to
1167 // original or cloned constpool entry.
1168 unsigned CPI = MI->getOperand(1).getIndex();
1169 const MachineConstantPool *MCP = MF.getConstantPool();
1170 if (CPI >= MCP->getConstants().size())
1171 CPI = AFI.getOriginalCPIdx(CPI);
1172 assert(CPI != -1U && "Invalid constpool index");
1174 // Derive the actual offset.
1175 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1176 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1177 // FIXME: Check for user, it should be "add" instruction!
1178 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1183 if (DstReg == FramePtr && FramePtr != ARM::SP)
1184 // Set-up of the frame pointer. Positive values correspond to "add"
1186 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1187 else if (DstReg == ARM::SP) {
1188 // Change of SP by an offset. Positive values correspond to "sub"
1190 OutStreamer.EmitPad(Offset);
1193 llvm_unreachable("Unsupported opcode for unwinding information");
1195 } else if (DstReg == ARM::SP) {
1196 // FIXME: .movsp goes here
1198 llvm_unreachable("Unsupported opcode for unwinding information");
1202 llvm_unreachable("Unsupported opcode for unwinding information");
1207 extern cl::opt<bool> EnableARMEHABI;
1209 // Simple pseudo-instructions have their lowering (with expansion to real
1210 // instructions) auto-generated.
1211 #include "ARMGenMCPseudoLowering.inc"
1213 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1214 if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1215 OutStreamer.EmitCodeRegion();
1217 // Emit unwinding stuff for frame-related instructions
1218 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1219 EmitUnwindingInstruction(MI);
1221 // Do any auto-generated pseudo lowerings.
1222 if (emitPseudoExpansionLowering(OutStreamer, MI))
1225 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1226 "Pseudo flag setting opcode should be expanded early");
1228 // Check for manual lowerings.
1229 unsigned Opc = MI->getOpcode();
1231 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1232 case ARM::DBG_VALUE: {
1233 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1234 SmallString<128> TmpStr;
1235 raw_svector_ostream OS(TmpStr);
1236 PrintDebugValueComment(MI, OS);
1237 OutStreamer.EmitRawText(StringRef(OS.str()));
1242 case ARM::tLEApcrel:
1243 case ARM::t2LEApcrel: {
1244 // FIXME: Need to also handle globals and externals
1246 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1247 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1249 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1250 GetCPISymbol(MI->getOperand(1).getIndex()),
1251 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1253 OutStreamer.EmitInstruction(TmpInst);
1256 case ARM::LEApcrelJT:
1257 case ARM::tLEApcrelJT:
1258 case ARM::t2LEApcrelJT: {
1260 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1261 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1263 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1264 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1265 MI->getOperand(2).getImm()),
1266 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1268 OutStreamer.EmitInstruction(TmpInst);
1271 // Darwin call instructions are just normal call instructions with different
1272 // clobber semantics (they clobber R9).
1273 case ARM::BXr9_CALL:
1274 case ARM::BX_CALL: {
1277 TmpInst.setOpcode(ARM::MOVr);
1278 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1279 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1280 // Add predicate operands.
1281 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1282 TmpInst.addOperand(MCOperand::CreateReg(0));
1283 // Add 's' bit operand (always reg0 for this)
1284 TmpInst.addOperand(MCOperand::CreateReg(0));
1285 OutStreamer.EmitInstruction(TmpInst);
1289 TmpInst.setOpcode(ARM::BX);
1290 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1291 OutStreamer.EmitInstruction(TmpInst);
1295 case ARM::tBXr9_CALL:
1296 case ARM::tBX_CALL: {
1299 TmpInst.setOpcode(ARM::tMOVr);
1300 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1301 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1302 // Add predicate operands.
1303 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1304 TmpInst.addOperand(MCOperand::CreateReg(0));
1305 OutStreamer.EmitInstruction(TmpInst);
1309 TmpInst.setOpcode(ARM::tBX);
1310 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1311 // Add predicate operands.
1312 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1313 TmpInst.addOperand(MCOperand::CreateReg(0));
1314 OutStreamer.EmitInstruction(TmpInst);
1318 case ARM::BMOVPCRXr9_CALL:
1319 case ARM::BMOVPCRX_CALL: {
1322 TmpInst.setOpcode(ARM::MOVr);
1323 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1324 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1325 // Add predicate operands.
1326 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1327 TmpInst.addOperand(MCOperand::CreateReg(0));
1328 // Add 's' bit operand (always reg0 for this)
1329 TmpInst.addOperand(MCOperand::CreateReg(0));
1330 OutStreamer.EmitInstruction(TmpInst);
1334 TmpInst.setOpcode(ARM::MOVr);
1335 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1336 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1337 // Add predicate operands.
1338 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1339 TmpInst.addOperand(MCOperand::CreateReg(0));
1340 // Add 's' bit operand (always reg0 for this)
1341 TmpInst.addOperand(MCOperand::CreateReg(0));
1342 OutStreamer.EmitInstruction(TmpInst);
1346 case ARM::BMOVPCBr9_CALL:
1347 case ARM::BMOVPCB_CALL: {
1350 TmpInst.setOpcode(ARM::MOVr);
1351 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1352 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1353 // Add predicate operands.
1354 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1355 TmpInst.addOperand(MCOperand::CreateReg(0));
1356 // Add 's' bit operand (always reg0 for this)
1357 TmpInst.addOperand(MCOperand::CreateReg(0));
1358 OutStreamer.EmitInstruction(TmpInst);
1362 TmpInst.setOpcode(ARM::Bcc);
1363 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1364 MCSymbol *GVSym = Mang->getSymbol(GV);
1365 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1366 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1367 // Add predicate operands.
1368 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1369 TmpInst.addOperand(MCOperand::CreateReg(0));
1370 OutStreamer.EmitInstruction(TmpInst);
1374 case ARM::t2BMOVPCBr9_CALL:
1375 case ARM::t2BMOVPCB_CALL: {
1378 TmpInst.setOpcode(ARM::tMOVr);
1379 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1380 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1381 // Add predicate operands.
1382 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1383 TmpInst.addOperand(MCOperand::CreateReg(0));
1384 OutStreamer.EmitInstruction(TmpInst);
1388 TmpInst.setOpcode(ARM::t2B);
1389 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1390 MCSymbol *GVSym = Mang->getSymbol(GV);
1391 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1392 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1393 // Add predicate operands.
1394 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1395 TmpInst.addOperand(MCOperand::CreateReg(0));
1396 OutStreamer.EmitInstruction(TmpInst);
1400 case ARM::MOVi16_ga_pcrel:
1401 case ARM::t2MOVi16_ga_pcrel: {
1403 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1404 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1406 unsigned TF = MI->getOperand(1).getTargetFlags();
1407 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1408 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1409 MCSymbol *GVSym = GetARMGVSymbol(GV);
1410 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1412 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1413 getFunctionNumber(),
1414 MI->getOperand(2).getImm(), OutContext);
1415 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1416 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1417 const MCExpr *PCRelExpr =
1418 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1419 MCBinaryExpr::CreateAdd(LabelSymExpr,
1420 MCConstantExpr::Create(PCAdj, OutContext),
1421 OutContext), OutContext), OutContext);
1422 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1424 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1425 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1428 // Add predicate operands.
1429 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1430 TmpInst.addOperand(MCOperand::CreateReg(0));
1431 // Add 's' bit operand (always reg0 for this)
1432 TmpInst.addOperand(MCOperand::CreateReg(0));
1433 OutStreamer.EmitInstruction(TmpInst);
1436 case ARM::MOVTi16_ga_pcrel:
1437 case ARM::t2MOVTi16_ga_pcrel: {
1439 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1440 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1441 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1442 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1444 unsigned TF = MI->getOperand(2).getTargetFlags();
1445 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1446 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1447 MCSymbol *GVSym = GetARMGVSymbol(GV);
1448 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1450 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1451 getFunctionNumber(),
1452 MI->getOperand(3).getImm(), OutContext);
1453 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1454 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1455 const MCExpr *PCRelExpr =
1456 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1457 MCBinaryExpr::CreateAdd(LabelSymExpr,
1458 MCConstantExpr::Create(PCAdj, OutContext),
1459 OutContext), OutContext), OutContext);
1460 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1462 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1463 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1465 // Add predicate operands.
1466 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1467 TmpInst.addOperand(MCOperand::CreateReg(0));
1468 // Add 's' bit operand (always reg0 for this)
1469 TmpInst.addOperand(MCOperand::CreateReg(0));
1470 OutStreamer.EmitInstruction(TmpInst);
1473 case ARM::tPICADD: {
1474 // This is a pseudo op for a label + instruction sequence, which looks like:
1477 // This adds the address of LPC0 to r0.
1480 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1481 getFunctionNumber(), MI->getOperand(2).getImm(),
1484 // Form and emit the add.
1486 AddInst.setOpcode(ARM::tADDhirr);
1487 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1488 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1489 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1490 // Add predicate operands.
1491 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1492 AddInst.addOperand(MCOperand::CreateReg(0));
1493 OutStreamer.EmitInstruction(AddInst);
1497 // This is a pseudo op for a label + instruction sequence, which looks like:
1500 // This adds the address of LPC0 to r0.
1503 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1504 getFunctionNumber(), MI->getOperand(2).getImm(),
1507 // Form and emit the add.
1509 AddInst.setOpcode(ARM::ADDrr);
1510 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1511 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1512 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1513 // Add predicate operands.
1514 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1515 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1516 // Add 's' bit operand (always reg0 for this)
1517 AddInst.addOperand(MCOperand::CreateReg(0));
1518 OutStreamer.EmitInstruction(AddInst);
1528 case ARM::PICLDRSH: {
1529 // This is a pseudo op for a label + instruction sequence, which looks like:
1532 // The LCP0 label is referenced by a constant pool entry in order to get
1533 // a PC-relative address at the ldr instruction.
1536 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1537 getFunctionNumber(), MI->getOperand(2).getImm(),
1540 // Form and emit the load
1542 switch (MI->getOpcode()) {
1544 llvm_unreachable("Unexpected opcode!");
1545 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1546 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1547 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1548 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1549 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1550 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1551 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1552 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1555 LdStInst.setOpcode(Opcode);
1556 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1557 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1558 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1559 LdStInst.addOperand(MCOperand::CreateImm(0));
1560 // Add predicate operands.
1561 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1562 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1563 OutStreamer.EmitInstruction(LdStInst);
1567 case ARM::CONSTPOOL_ENTRY: {
1568 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1569 /// in the function. The first operand is the ID# for this instruction, the
1570 /// second is the index into the MachineConstantPool that this is, the third
1571 /// is the size in bytes of this constant pool entry.
1572 /// The required alignment is specified on the basic block holding this MI.
1573 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1574 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1576 // Mark the constant pool entry as data if we're not already in a data
1578 OutStreamer.EmitDataRegion();
1579 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1581 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1582 if (MCPE.isMachineConstantPoolEntry())
1583 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1585 EmitGlobalConstant(MCPE.Val.ConstVal);
1588 case ARM::t2BR_JT: {
1589 // Lower and emit the instruction itself, then the jump table following it.
1591 TmpInst.setOpcode(ARM::tMOVr);
1592 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1593 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1594 // Add predicate operands.
1595 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1596 TmpInst.addOperand(MCOperand::CreateReg(0));
1597 OutStreamer.EmitInstruction(TmpInst);
1598 // Output the data for the jump table itself
1602 case ARM::t2TBB_JT: {
1603 // Lower and emit the instruction itself, then the jump table following it.
1606 TmpInst.setOpcode(ARM::t2TBB);
1607 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1608 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1609 // Add predicate operands.
1610 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1611 TmpInst.addOperand(MCOperand::CreateReg(0));
1612 OutStreamer.EmitInstruction(TmpInst);
1613 // Output the data for the jump table itself
1615 // Make sure the next instruction is 2-byte aligned.
1619 case ARM::t2TBH_JT: {
1620 // Lower and emit the instruction itself, then the jump table following it.
1623 TmpInst.setOpcode(ARM::t2TBH);
1624 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1625 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1626 // Add predicate operands.
1627 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1628 TmpInst.addOperand(MCOperand::CreateReg(0));
1629 OutStreamer.EmitInstruction(TmpInst);
1630 // Output the data for the jump table itself
1636 // Lower and emit the instruction itself, then the jump table following it.
1639 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1640 ARM::MOVr : ARM::tMOVr;
1641 TmpInst.setOpcode(Opc);
1642 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1643 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1644 // Add predicate operands.
1645 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1646 TmpInst.addOperand(MCOperand::CreateReg(0));
1647 // Add 's' bit operand (always reg0 for this)
1648 if (Opc == ARM::MOVr)
1649 TmpInst.addOperand(MCOperand::CreateReg(0));
1650 OutStreamer.EmitInstruction(TmpInst);
1652 // Make sure the Thumb jump table is 4-byte aligned.
1653 if (Opc == ARM::tMOVr)
1656 // Output the data for the jump table itself
1661 // Lower and emit the instruction itself, then the jump table following it.
1664 if (MI->getOperand(1).getReg() == 0) {
1666 TmpInst.setOpcode(ARM::LDRi12);
1667 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1668 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1669 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1671 TmpInst.setOpcode(ARM::LDRrs);
1672 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1673 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1674 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1675 TmpInst.addOperand(MCOperand::CreateImm(0));
1677 // Add predicate operands.
1678 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1679 TmpInst.addOperand(MCOperand::CreateReg(0));
1680 OutStreamer.EmitInstruction(TmpInst);
1682 // Output the data for the jump table itself
1686 case ARM::BR_JTadd: {
1687 // Lower and emit the instruction itself, then the jump table following it.
1688 // add pc, target, idx
1690 TmpInst.setOpcode(ARM::ADDrr);
1691 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1692 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1693 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1694 // Add predicate operands.
1695 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1696 TmpInst.addOperand(MCOperand::CreateReg(0));
1697 // Add 's' bit operand (always reg0 for this)
1698 TmpInst.addOperand(MCOperand::CreateReg(0));
1699 OutStreamer.EmitInstruction(TmpInst);
1701 // Output the data for the jump table itself
1706 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1707 // FIXME: Remove this special case when they do.
1708 if (!Subtarget->isTargetDarwin()) {
1709 //.long 0xe7ffdefe @ trap
1710 uint32_t Val = 0xe7ffdefeUL;
1711 OutStreamer.AddComment("trap");
1712 OutStreamer.EmitIntValue(Val, 4);
1718 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1719 // FIXME: Remove this special case when they do.
1720 if (!Subtarget->isTargetDarwin()) {
1721 //.short 57086 @ trap
1722 uint16_t Val = 0xdefe;
1723 OutStreamer.AddComment("trap");
1724 OutStreamer.EmitIntValue(Val, 2);
1729 case ARM::t2Int_eh_sjlj_setjmp:
1730 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1731 case ARM::tInt_eh_sjlj_setjmp: {
1732 // Two incoming args: GPR:$src, GPR:$val
1735 // str $val, [$src, #4]
1740 unsigned SrcReg = MI->getOperand(0).getReg();
1741 unsigned ValReg = MI->getOperand(1).getReg();
1742 MCSymbol *Label = GetARMSJLJEHLabel();
1745 TmpInst.setOpcode(ARM::tMOVr);
1746 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1747 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1749 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1750 TmpInst.addOperand(MCOperand::CreateReg(0));
1751 OutStreamer.AddComment("eh_setjmp begin");
1752 OutStreamer.EmitInstruction(TmpInst);
1756 TmpInst.setOpcode(ARM::tADDi3);
1757 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1759 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1760 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1761 TmpInst.addOperand(MCOperand::CreateImm(7));
1763 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1764 TmpInst.addOperand(MCOperand::CreateReg(0));
1765 OutStreamer.EmitInstruction(TmpInst);
1769 TmpInst.setOpcode(ARM::tSTRi);
1770 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1771 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1772 // The offset immediate is #4. The operand value is scaled by 4 for the
1773 // tSTR instruction.
1774 TmpInst.addOperand(MCOperand::CreateImm(1));
1776 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1777 TmpInst.addOperand(MCOperand::CreateReg(0));
1778 OutStreamer.EmitInstruction(TmpInst);
1782 TmpInst.setOpcode(ARM::tMOVi8);
1783 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1784 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1785 TmpInst.addOperand(MCOperand::CreateImm(0));
1787 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1788 TmpInst.addOperand(MCOperand::CreateReg(0));
1789 OutStreamer.EmitInstruction(TmpInst);
1792 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1794 TmpInst.setOpcode(ARM::tB);
1795 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1796 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1797 TmpInst.addOperand(MCOperand::CreateReg(0));
1798 OutStreamer.EmitInstruction(TmpInst);
1802 TmpInst.setOpcode(ARM::tMOVi8);
1803 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1804 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1805 TmpInst.addOperand(MCOperand::CreateImm(1));
1807 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1808 TmpInst.addOperand(MCOperand::CreateReg(0));
1809 OutStreamer.AddComment("eh_setjmp end");
1810 OutStreamer.EmitInstruction(TmpInst);
1812 OutStreamer.EmitLabel(Label);
1816 case ARM::Int_eh_sjlj_setjmp_nofp:
1817 case ARM::Int_eh_sjlj_setjmp: {
1818 // Two incoming args: GPR:$src, GPR:$val
1820 // str $val, [$src, #+4]
1824 unsigned SrcReg = MI->getOperand(0).getReg();
1825 unsigned ValReg = MI->getOperand(1).getReg();
1829 TmpInst.setOpcode(ARM::ADDri);
1830 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1831 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1832 TmpInst.addOperand(MCOperand::CreateImm(8));
1834 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1835 TmpInst.addOperand(MCOperand::CreateReg(0));
1836 // 's' bit operand (always reg0 for this).
1837 TmpInst.addOperand(MCOperand::CreateReg(0));
1838 OutStreamer.AddComment("eh_setjmp begin");
1839 OutStreamer.EmitInstruction(TmpInst);
1843 TmpInst.setOpcode(ARM::STRi12);
1844 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1845 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1846 TmpInst.addOperand(MCOperand::CreateImm(4));
1848 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1849 TmpInst.addOperand(MCOperand::CreateReg(0));
1850 OutStreamer.EmitInstruction(TmpInst);
1854 TmpInst.setOpcode(ARM::MOVi);
1855 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1856 TmpInst.addOperand(MCOperand::CreateImm(0));
1858 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1859 TmpInst.addOperand(MCOperand::CreateReg(0));
1860 // 's' bit operand (always reg0 for this).
1861 TmpInst.addOperand(MCOperand::CreateReg(0));
1862 OutStreamer.EmitInstruction(TmpInst);
1866 TmpInst.setOpcode(ARM::ADDri);
1867 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1868 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1869 TmpInst.addOperand(MCOperand::CreateImm(0));
1871 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1872 TmpInst.addOperand(MCOperand::CreateReg(0));
1873 // 's' bit operand (always reg0 for this).
1874 TmpInst.addOperand(MCOperand::CreateReg(0));
1875 OutStreamer.EmitInstruction(TmpInst);
1879 TmpInst.setOpcode(ARM::MOVi);
1880 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1881 TmpInst.addOperand(MCOperand::CreateImm(1));
1883 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1884 TmpInst.addOperand(MCOperand::CreateReg(0));
1885 // 's' bit operand (always reg0 for this).
1886 TmpInst.addOperand(MCOperand::CreateReg(0));
1887 OutStreamer.AddComment("eh_setjmp end");
1888 OutStreamer.EmitInstruction(TmpInst);
1892 case ARM::Int_eh_sjlj_longjmp: {
1893 // ldr sp, [$src, #8]
1894 // ldr $scratch, [$src, #4]
1897 unsigned SrcReg = MI->getOperand(0).getReg();
1898 unsigned ScratchReg = MI->getOperand(1).getReg();
1901 TmpInst.setOpcode(ARM::LDRi12);
1902 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1903 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1904 TmpInst.addOperand(MCOperand::CreateImm(8));
1906 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1907 TmpInst.addOperand(MCOperand::CreateReg(0));
1908 OutStreamer.EmitInstruction(TmpInst);
1912 TmpInst.setOpcode(ARM::LDRi12);
1913 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1914 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1915 TmpInst.addOperand(MCOperand::CreateImm(4));
1917 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1918 TmpInst.addOperand(MCOperand::CreateReg(0));
1919 OutStreamer.EmitInstruction(TmpInst);
1923 TmpInst.setOpcode(ARM::LDRi12);
1924 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1925 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1926 TmpInst.addOperand(MCOperand::CreateImm(0));
1928 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1929 TmpInst.addOperand(MCOperand::CreateReg(0));
1930 OutStreamer.EmitInstruction(TmpInst);
1934 TmpInst.setOpcode(ARM::BX);
1935 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1937 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1938 TmpInst.addOperand(MCOperand::CreateReg(0));
1939 OutStreamer.EmitInstruction(TmpInst);
1943 case ARM::tInt_eh_sjlj_longjmp: {
1944 // ldr $scratch, [$src, #8]
1946 // ldr $scratch, [$src, #4]
1949 unsigned SrcReg = MI->getOperand(0).getReg();
1950 unsigned ScratchReg = MI->getOperand(1).getReg();
1953 TmpInst.setOpcode(ARM::tLDRi);
1954 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1955 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1956 // The offset immediate is #8. The operand value is scaled by 4 for the
1957 // tLDR instruction.
1958 TmpInst.addOperand(MCOperand::CreateImm(2));
1960 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1961 TmpInst.addOperand(MCOperand::CreateReg(0));
1962 OutStreamer.EmitInstruction(TmpInst);
1966 TmpInst.setOpcode(ARM::tMOVr);
1967 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1968 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1970 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1971 TmpInst.addOperand(MCOperand::CreateReg(0));
1972 OutStreamer.EmitInstruction(TmpInst);
1976 TmpInst.setOpcode(ARM::tLDRi);
1977 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1978 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1979 TmpInst.addOperand(MCOperand::CreateImm(1));
1981 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1982 TmpInst.addOperand(MCOperand::CreateReg(0));
1983 OutStreamer.EmitInstruction(TmpInst);
1987 TmpInst.setOpcode(ARM::tLDRr);
1988 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1989 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1990 TmpInst.addOperand(MCOperand::CreateReg(0));
1992 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1993 TmpInst.addOperand(MCOperand::CreateReg(0));
1994 OutStreamer.EmitInstruction(TmpInst);
1998 TmpInst.setOpcode(ARM::tBX);
1999 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2001 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2002 TmpInst.addOperand(MCOperand::CreateReg(0));
2003 OutStreamer.EmitInstruction(TmpInst);
2010 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2012 OutStreamer.EmitInstruction(TmpInst);
2015 //===----------------------------------------------------------------------===//
2016 // Target Registry Stuff
2017 //===----------------------------------------------------------------------===//
2019 // Force static initialization.
2020 extern "C" void LLVMInitializeARMAsmPrinter() {
2021 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2022 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);