1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMFPUName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/DebugInfo.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 void ARMAsmPrinter::EmitFunctionBodyEnd() {
59 // Make sure to terminate any constant pools that were at the end
63 InConstantPool = false;
64 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
67 void ARMAsmPrinter::EmitFunctionEntryLabel() {
68 if (AFI->isThumbFunction()) {
69 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
70 OutStreamer.EmitThumbFunc(CurrentFnSym);
73 OutStreamer.EmitLabel(CurrentFnSym);
76 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
77 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
78 assert(Size && "C++ constructor pointer had zero size!");
80 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
81 assert(GV && "C++ constructor pointer was not a GlobalValue!");
83 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
84 (Subtarget->isTargetELF()
85 ? MCSymbolRefExpr::VK_ARM_TARGET1
86 : MCSymbolRefExpr::VK_None),
89 OutStreamer.EmitValue(E, Size);
92 /// runOnMachineFunction - This uses the EmitInstruction()
93 /// method to print assembly for each instruction.
95 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
96 AFI = MF.getInfo<ARMFunctionInfo>();
97 MCP = MF.getConstantPool();
99 return AsmPrinter::runOnMachineFunction(MF);
102 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
103 raw_ostream &O, const char *Modifier) {
104 const MachineOperand &MO = MI->getOperand(OpNum);
105 unsigned TF = MO.getTargetFlags();
107 switch (MO.getType()) {
108 default: llvm_unreachable("<unknown operand type>");
109 case MachineOperand::MO_Register: {
110 unsigned Reg = MO.getReg();
111 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
112 assert(!MO.getSubReg() && "Subregs should be eliminated!");
113 if(ARM::GPRPairRegClass.contains(Reg)) {
114 const MachineFunction &MF = *MI->getParent()->getParent();
115 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
116 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
118 O << ARMInstPrinter::getRegisterName(Reg);
121 case MachineOperand::MO_Immediate: {
122 int64_t Imm = MO.getImm();
124 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
125 (TF == ARMII::MO_LO16))
127 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
128 (TF == ARMII::MO_HI16))
133 case MachineOperand::MO_MachineBasicBlock:
134 O << *MO.getMBB()->getSymbol();
136 case MachineOperand::MO_GlobalAddress: {
137 const GlobalValue *GV = MO.getGlobal();
138 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
139 (TF & ARMII::MO_LO16))
141 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
142 (TF & ARMII::MO_HI16))
146 printOffset(MO.getOffset(), O);
147 if (TF == ARMII::MO_PLT)
151 case MachineOperand::MO_ConstantPoolIndex:
152 O << *GetCPISymbol(MO.getIndex());
157 //===--------------------------------------------------------------------===//
159 MCSymbol *ARMAsmPrinter::
160 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
161 const DataLayout *DL = TM.getDataLayout();
162 SmallString<60> Name;
163 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
164 << getFunctionNumber() << '_' << uid << '_' << uid2;
165 return OutContext.GetOrCreateSymbol(Name.str());
169 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
170 const DataLayout *DL = TM.getDataLayout();
171 SmallString<60> Name;
172 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
173 << getFunctionNumber();
174 return OutContext.GetOrCreateSymbol(Name.str());
177 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
178 unsigned AsmVariant, const char *ExtraCode,
180 // Does this asm operand have a single letter operand modifier?
181 if (ExtraCode && ExtraCode[0]) {
182 if (ExtraCode[1] != 0) return true; // Unknown modifier.
184 switch (ExtraCode[0]) {
186 // See if this is a generic print operand
187 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
188 case 'a': // Print as a memory address.
189 if (MI->getOperand(OpNum).isReg()) {
191 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
196 case 'c': // Don't print "#" before an immediate operand.
197 if (!MI->getOperand(OpNum).isImm())
199 O << MI->getOperand(OpNum).getImm();
201 case 'P': // Print a VFP double precision register.
202 case 'q': // Print a NEON quad precision register.
203 printOperand(MI, OpNum, O);
205 case 'y': // Print a VFP single precision register as indexed double.
206 if (MI->getOperand(OpNum).isReg()) {
207 unsigned Reg = MI->getOperand(OpNum).getReg();
208 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
209 // Find the 'd' register that has this 's' register as a sub-register,
210 // and determine the lane number.
211 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
212 if (!ARM::DPRRegClass.contains(*SR))
214 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
215 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
220 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
221 if (!MI->getOperand(OpNum).isImm())
223 O << ~(MI->getOperand(OpNum).getImm());
225 case 'L': // The low 16 bits of an immediate constant.
226 if (!MI->getOperand(OpNum).isImm())
228 O << (MI->getOperand(OpNum).getImm() & 0xffff);
230 case 'M': { // A register range suitable for LDM/STM.
231 if (!MI->getOperand(OpNum).isReg())
233 const MachineOperand &MO = MI->getOperand(OpNum);
234 unsigned RegBegin = MO.getReg();
235 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
236 // already got the operands in registers that are operands to the
237 // inline asm statement.
239 if (ARM::GPRPairRegClass.contains(RegBegin)) {
240 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
241 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
242 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
243 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
245 O << ARMInstPrinter::getRegisterName(RegBegin);
247 // FIXME: The register allocator not only may not have given us the
248 // registers in sequence, but may not be in ascending registers. This
249 // will require changes in the register allocator that'll need to be
250 // propagated down here if the operands change.
251 unsigned RegOps = OpNum + 1;
252 while (MI->getOperand(RegOps).isReg()) {
254 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
262 case 'R': // The most significant register of a pair.
263 case 'Q': { // The least significant register of a pair.
266 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
267 if (!FlagsOP.isImm())
269 unsigned Flags = FlagsOP.getImm();
271 // This operand may not be the one that actually provides the register. If
272 // it's tied to a previous one then we should refer instead to that one
273 // for registers and their classes.
275 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
276 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
277 unsigned OpFlags = MI->getOperand(OpNum).getImm();
278 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
280 Flags = MI->getOperand(OpNum).getImm();
282 // Later code expects OpNum to be pointing at the register rather than
287 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
289 InlineAsm::hasRegClassConstraint(Flags, RC);
290 if (RC == ARM::GPRPairRegClassID) {
293 const MachineOperand &MO = MI->getOperand(OpNum);
296 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
297 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
298 ARM::gsub_0 : ARM::gsub_1);
299 O << ARMInstPrinter::getRegisterName(Reg);
304 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
305 if (RegOp >= MI->getNumOperands())
307 const MachineOperand &MO = MI->getOperand(RegOp);
310 unsigned Reg = MO.getReg();
311 O << ARMInstPrinter::getRegisterName(Reg);
315 case 'e': // The low doubleword register of a NEON quad register.
316 case 'f': { // The high doubleword register of a NEON quad register.
317 if (!MI->getOperand(OpNum).isReg())
319 unsigned Reg = MI->getOperand(OpNum).getReg();
320 if (!ARM::QPRRegClass.contains(Reg))
322 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
323 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
324 ARM::dsub_0 : ARM::dsub_1);
325 O << ARMInstPrinter::getRegisterName(SubReg);
329 // This modifier is not yet supported.
330 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
332 case 'H': { // The highest-numbered register of a pair.
333 const MachineOperand &MO = MI->getOperand(OpNum);
336 const MachineFunction &MF = *MI->getParent()->getParent();
337 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
338 unsigned Reg = MO.getReg();
339 if(!ARM::GPRPairRegClass.contains(Reg))
341 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
342 O << ARMInstPrinter::getRegisterName(Reg);
348 printOperand(MI, OpNum, O);
352 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
353 unsigned OpNum, unsigned AsmVariant,
354 const char *ExtraCode,
356 // Does this asm operand have a single letter operand modifier?
357 if (ExtraCode && ExtraCode[0]) {
358 if (ExtraCode[1] != 0) return true; // Unknown modifier.
360 switch (ExtraCode[0]) {
361 case 'A': // A memory operand for a VLD1/VST1 instruction.
362 default: return true; // Unknown modifier.
363 case 'm': // The base register of a memory operand.
364 if (!MI->getOperand(OpNum).isReg())
366 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
371 const MachineOperand &MO = MI->getOperand(OpNum);
372 assert(MO.isReg() && "unexpected inline asm memory operand");
373 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
377 static bool isThumb(const MCSubtargetInfo& STI) {
378 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
381 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
382 const MCSubtargetInfo *EndInfo) const {
383 // If either end mode is unknown (EndInfo == NULL) or different than
384 // the start mode, then restore the start mode.
385 const bool WasThumb = isThumb(StartInfo);
386 if (EndInfo == NULL || WasThumb != isThumb(*EndInfo)) {
387 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
391 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
392 if (Subtarget->isTargetMachO()) {
393 Reloc::Model RelocM = TM.getRelocationModel();
394 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
395 // Declare all the text sections up front (before the DWARF sections
396 // emitted by AsmPrinter::doInitialization) so the assembler will keep
397 // them together at the beginning of the object file. This helps
398 // avoid out-of-range branches that are due a fundamental limitation of
399 // the way symbol offsets are encoded with the current Darwin ARM
401 const TargetLoweringObjectFileMachO &TLOFMacho =
402 static_cast<const TargetLoweringObjectFileMachO &>(
403 getObjFileLowering());
405 // Collect the set of sections our functions will go into.
406 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
407 SmallPtrSet<const MCSection *, 8> > TextSections;
408 // Default text section comes first.
409 TextSections.insert(TLOFMacho.getTextSection());
410 // Now any user defined text sections from function attributes.
411 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
412 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
413 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
414 // Now the coalescable sections.
415 TextSections.insert(TLOFMacho.getTextCoalSection());
416 TextSections.insert(TLOFMacho.getConstTextCoalSection());
418 // Emit the sections in the .s file header to fix the order.
419 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
420 OutStreamer.SwitchSection(TextSections[i]);
422 if (RelocM == Reloc::DynamicNoPIC) {
423 const MCSection *sect =
424 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
425 MCSectionMachO::S_SYMBOL_STUBS,
426 12, SectionKind::getText());
427 OutStreamer.SwitchSection(sect);
429 const MCSection *sect =
430 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
431 MCSectionMachO::S_SYMBOL_STUBS,
432 16, SectionKind::getText());
433 OutStreamer.SwitchSection(sect);
435 const MCSection *StaticInitSect =
436 OutContext.getMachOSection("__TEXT", "__StaticInit",
437 MCSectionMachO::S_REGULAR |
438 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
439 SectionKind::getText());
440 OutStreamer.SwitchSection(StaticInitSect);
443 // Compiling with debug info should not affect the code
444 // generation. Ensure the cstring section comes before the
445 // optional __DWARF secion. Otherwise, PC-relative loads would
446 // have to use different instruction sequences at "-g" in order to
447 // reach global data in the same object file.
448 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
451 // Use unified assembler syntax.
452 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
454 // Emit ARM Build Attributes
455 if (Subtarget->isTargetELF())
460 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
461 if (Subtarget->isTargetMachO()) {
462 // All darwin targets use mach-o.
463 const TargetLoweringObjectFileMachO &TLOFMacho =
464 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
465 MachineModuleInfoMachO &MMIMacho =
466 MMI->getObjFileInfo<MachineModuleInfoMachO>();
468 // Output non-lazy-pointers for external and common global variables.
469 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
471 if (!Stubs.empty()) {
472 // Switch with ".non_lazy_symbol_pointer" directive.
473 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
475 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
477 OutStreamer.EmitLabel(Stubs[i].first);
478 // .indirect_symbol _foo
479 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
480 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
483 // External to current translation unit.
484 OutStreamer.EmitIntValue(0, 4/*size*/);
486 // Internal to current translation unit.
488 // When we place the LSDA into the TEXT section, the type info
489 // pointers need to be indirect and pc-rel. We accomplish this by
490 // using NLPs; however, sometimes the types are local to the file.
491 // We need to fill in the value for the NLP in those cases.
492 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
498 OutStreamer.AddBlankLine();
501 Stubs = MMIMacho.GetHiddenGVStubList();
502 if (!Stubs.empty()) {
503 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
505 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
507 OutStreamer.EmitLabel(Stubs[i].first);
509 OutStreamer.EmitValue(MCSymbolRefExpr::
510 Create(Stubs[i].second.getPointer(),
516 OutStreamer.AddBlankLine();
519 // Funny Darwin hack: This flag tells the linker that no global symbols
520 // contain code that falls through to other global symbols (e.g. the obvious
521 // implementation of multiple entry points). If this doesn't occur, the
522 // linker can safely perform dead code stripping. Since LLVM never
523 // generates code that does this, it is always safe to set.
524 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
528 //===----------------------------------------------------------------------===//
529 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
531 // The following seem like one-off assembler flags, but they actually need
532 // to appear in the .ARM.attributes section in ELF.
533 // Instead of subclassing the MCELFStreamer, we do the work here.
535 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
536 const ARMSubtarget *Subtarget) {
538 return ARMBuildAttrs::v5TEJ;
540 if (Subtarget->hasV8Ops())
541 return ARMBuildAttrs::v8;
542 else if (Subtarget->hasV7Ops()) {
543 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
544 return ARMBuildAttrs::v7E_M;
545 return ARMBuildAttrs::v7;
546 } else if (Subtarget->hasV6T2Ops())
547 return ARMBuildAttrs::v6T2;
548 else if (Subtarget->hasV6MOps())
549 return ARMBuildAttrs::v6S_M;
550 else if (Subtarget->hasV6Ops())
551 return ARMBuildAttrs::v6;
552 else if (Subtarget->hasV5TEOps())
553 return ARMBuildAttrs::v5TE;
554 else if (Subtarget->hasV5TOps())
555 return ARMBuildAttrs::v5T;
556 else if (Subtarget->hasV4TOps())
557 return ARMBuildAttrs::v4T;
559 return ARMBuildAttrs::v4;
562 void ARMAsmPrinter::emitAttributes() {
563 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
564 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
566 ATS.switchVendor("aeabi");
568 std::string CPUString = Subtarget->getCPUString();
570 // FIXME: remove krait check when GNU tools support krait cpu
571 if (CPUString != "generic" && CPUString != "krait")
572 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
574 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
575 getArchForCPU(CPUString, Subtarget));
577 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
578 // profile is not applicable (e.g. pre v7, or cross-profile code)".
579 if (Subtarget->hasV7Ops()) {
580 if (Subtarget->isAClass()) {
581 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
582 ARMBuildAttrs::ApplicationProfile);
583 } else if (Subtarget->isRClass()) {
584 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
585 ARMBuildAttrs::RealTimeProfile);
586 } else if (Subtarget->isMClass()) {
587 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
588 ARMBuildAttrs::MicroControllerProfile);
592 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
593 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
594 if (Subtarget->isThumb1Only()) {
595 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
596 ARMBuildAttrs::Allowed);
597 } else if (Subtarget->hasThumb2()) {
598 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
599 ARMBuildAttrs::AllowThumb32);
602 if (Subtarget->hasNEON()) {
603 /* NEON is not exactly a VFP architecture, but GAS emit one of
604 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
605 if (Subtarget->hasFPARMv8()) {
606 if (Subtarget->hasCrypto())
607 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
609 ATS.emitFPU(ARM::NEON_FP_ARMV8);
611 else if (Subtarget->hasVFP4())
612 ATS.emitFPU(ARM::NEON_VFPV4);
614 ATS.emitFPU(ARM::NEON);
615 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
616 if (Subtarget->hasV8Ops())
617 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
618 ARMBuildAttrs::AllowNeonARMv8);
620 if (Subtarget->hasFPARMv8())
621 ATS.emitFPU(ARM::FP_ARMV8);
622 else if (Subtarget->hasVFP4())
623 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
624 else if (Subtarget->hasVFP3())
625 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
626 else if (Subtarget->hasVFP2())
627 ATS.emitFPU(ARM::VFPV2);
630 // Signal various FP modes.
631 if (!TM.Options.UnsafeFPMath) {
632 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
633 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
634 ARMBuildAttrs::Allowed);
637 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
638 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
639 ARMBuildAttrs::Allowed);
641 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
642 ARMBuildAttrs::AllowIEE754);
644 // FIXME: add more flags to ARMBuildAttributes.h
645 // 8-bytes alignment stuff.
646 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
647 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
649 // ABI_HardFP_use attribute to indicate single precision FP.
650 if (Subtarget->isFPOnlySP())
651 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
652 ARMBuildAttrs::HardFPSinglePrecision);
654 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
655 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
656 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
658 // FIXME: Should we signal R9 usage?
660 if (Subtarget->hasFP16())
661 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
663 if (Subtarget->hasMPExtension())
664 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
666 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
667 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
668 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
669 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
670 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
671 // otherwise, the default value (AllowDIVIfExists) applies.
672 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
673 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
675 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
676 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
677 ARMBuildAttrs::AllowTZVirtualization);
678 else if (Subtarget->hasTrustZone())
679 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
680 ARMBuildAttrs::AllowTZ);
681 else if (Subtarget->hasVirtualization())
682 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
683 ARMBuildAttrs::AllowVirtualization);
685 ATS.finishAttributeSection();
688 //===----------------------------------------------------------------------===//
690 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
691 unsigned LabelId, MCContext &Ctx) {
693 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
694 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
698 static MCSymbolRefExpr::VariantKind
699 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
701 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
702 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
703 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
704 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
705 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
706 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
708 llvm_unreachable("Invalid ARMCPModifier!");
711 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
712 unsigned char TargetFlags) {
713 bool isIndirect = Subtarget->isTargetMachO() &&
714 (TargetFlags & ARMII::MO_NONLAZY) &&
715 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
717 return getSymbol(GV);
719 // FIXME: Remove this when Darwin transition to @GOT like syntax.
720 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
721 MachineModuleInfoMachO &MMIMachO =
722 MMI->getObjFileInfo<MachineModuleInfoMachO>();
723 MachineModuleInfoImpl::StubValueTy &StubSym =
724 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
725 MMIMachO.getGVStubEntry(MCSym);
726 if (StubSym.getPointer() == 0)
727 StubSym = MachineModuleInfoImpl::
728 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
733 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
734 const DataLayout *DL = TM.getDataLayout();
735 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
737 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
740 if (ACPV->isLSDA()) {
741 SmallString<128> Str;
742 raw_svector_ostream OS(Str);
743 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
744 MCSym = OutContext.GetOrCreateSymbol(OS.str());
745 } else if (ACPV->isBlockAddress()) {
746 const BlockAddress *BA =
747 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
748 MCSym = GetBlockAddressSymbol(BA);
749 } else if (ACPV->isGlobalValue()) {
750 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
752 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
753 // flag the global as MO_NONLAZY.
754 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
755 MCSym = GetARMGVSymbol(GV, TF);
756 } else if (ACPV->isMachineBasicBlock()) {
757 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
758 MCSym = MBB->getSymbol();
760 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
761 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
762 MCSym = GetExternalSymbolSymbol(Sym);
765 // Create an MCSymbol for the reference.
767 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
770 if (ACPV->getPCAdjustment()) {
771 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
775 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
777 MCBinaryExpr::CreateAdd(PCRelExpr,
778 MCConstantExpr::Create(ACPV->getPCAdjustment(),
781 if (ACPV->mustAddCurrentAddress()) {
782 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
783 // label, so just emit a local label end reference that instead.
784 MCSymbol *DotSym = OutContext.CreateTempSymbol();
785 OutStreamer.EmitLabel(DotSym);
786 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
787 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
789 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
791 OutStreamer.EmitValue(Expr, Size);
794 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
795 unsigned Opcode = MI->getOpcode();
797 if (Opcode == ARM::BR_JTadd)
799 else if (Opcode == ARM::BR_JTm)
802 const MachineOperand &MO1 = MI->getOperand(OpNum);
803 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
804 unsigned JTI = MO1.getIndex();
806 // Emit a label for the jump table.
807 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
808 OutStreamer.EmitLabel(JTISymbol);
810 // Mark the jump table as data-in-code.
811 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
813 // Emit each entry of the table.
814 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
815 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
816 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
818 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
819 MachineBasicBlock *MBB = JTBBs[i];
820 // Construct an MCExpr for the entry. We want a value of the form:
821 // (BasicBlockAddr - TableBeginAddr)
823 // For example, a table with entries jumping to basic blocks BB0 and BB1
826 // .word (LBB0 - LJTI_0_0)
827 // .word (LBB1 - LJTI_0_0)
828 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
830 if (TM.getRelocationModel() == Reloc::PIC_)
831 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
834 // If we're generating a table of Thumb addresses in static relocation
835 // model, we need to add one to keep interworking correctly.
836 else if (AFI->isThumbFunction())
837 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
839 OutStreamer.EmitValue(Expr, 4);
841 // Mark the end of jump table data-in-code region.
842 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
845 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
846 unsigned Opcode = MI->getOpcode();
847 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
848 const MachineOperand &MO1 = MI->getOperand(OpNum);
849 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
850 unsigned JTI = MO1.getIndex();
852 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
853 OutStreamer.EmitLabel(JTISymbol);
855 // Emit each entry of the table.
856 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
857 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
858 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
859 unsigned OffsetWidth = 4;
860 if (MI->getOpcode() == ARM::t2TBB_JT) {
862 // Mark the jump table as data-in-code.
863 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
864 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
866 // Mark the jump table as data-in-code.
867 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
870 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
871 MachineBasicBlock *MBB = JTBBs[i];
872 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
874 // If this isn't a TBB or TBH, the entries are direct branch instructions.
875 if (OffsetWidth == 4) {
876 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
877 .addExpr(MBBSymbolExpr)
882 // Otherwise it's an offset from the dispatch instruction. Construct an
883 // MCExpr for the entry. We want a value of the form:
884 // (BasicBlockAddr - TableBeginAddr) / 2
886 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
889 // .byte (LBB0 - LJTI_0_0) / 2
890 // .byte (LBB1 - LJTI_0_0) / 2
892 MCBinaryExpr::CreateSub(MBBSymbolExpr,
893 MCSymbolRefExpr::Create(JTISymbol, OutContext),
895 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
897 OutStreamer.EmitValue(Expr, OffsetWidth);
899 // Mark the end of jump table data-in-code region. 32-bit offsets use
900 // actual branch instructions here, so we don't mark those as a data-region
902 if (OffsetWidth != 4)
903 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
906 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
907 assert(MI->getFlag(MachineInstr::FrameSetup) &&
908 "Only instruction which are involved into frame setup code are allowed");
910 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
911 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
912 const MachineFunction &MF = *MI->getParent()->getParent();
913 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
914 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
916 unsigned FramePtr = RegInfo->getFrameRegister(MF);
917 unsigned Opc = MI->getOpcode();
918 unsigned SrcReg, DstReg;
920 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
921 // Two special cases:
922 // 1) tPUSH does not have src/dst regs.
923 // 2) for Thumb1 code we sometimes materialize the constant via constpool
924 // load. Yes, this is pretty fragile, but for now I don't see better
926 SrcReg = DstReg = ARM::SP;
928 SrcReg = MI->getOperand(1).getReg();
929 DstReg = MI->getOperand(0).getReg();
932 // Try to figure out the unwinding opcode out of src / dst regs.
933 if (MI->mayStore()) {
935 assert(DstReg == ARM::SP &&
936 "Only stack pointer as a destination reg is supported");
938 SmallVector<unsigned, 4> RegList;
939 // Skip src & dst reg, and pred ops.
940 unsigned StartOp = 2 + 2;
941 // Use all the operands.
942 unsigned NumOffset = 0;
947 llvm_unreachable("Unsupported opcode for unwinding information");
949 // Special case here: no src & dst reg, but two extra imp ops.
950 StartOp = 2; NumOffset = 2;
952 case ARM::t2STMDB_UPD:
953 case ARM::VSTMDDB_UPD:
954 assert(SrcReg == ARM::SP &&
955 "Only stack pointer as a source reg is supported");
956 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
958 const MachineOperand &MO = MI->getOperand(i);
959 // Actually, there should never be any impdef stuff here. Skip it
960 // temporary to workaround PR11902.
963 RegList.push_back(MO.getReg());
966 case ARM::STR_PRE_IMM:
967 case ARM::STR_PRE_REG:
969 assert(MI->getOperand(2).getReg() == ARM::SP &&
970 "Only stack pointer as a source reg is supported");
971 RegList.push_back(SrcReg);
974 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
976 // Changes of stack / frame pointer.
977 if (SrcReg == ARM::SP) {
982 llvm_unreachable("Unsupported opcode for unwinding information");
988 Offset = -MI->getOperand(2).getImm();
992 Offset = MI->getOperand(2).getImm();
995 Offset = MI->getOperand(2).getImm()*4;
999 Offset = -MI->getOperand(2).getImm()*4;
1001 case ARM::tLDRpci: {
1002 // Grab the constpool index and check, whether it corresponds to
1003 // original or cloned constpool entry.
1004 unsigned CPI = MI->getOperand(1).getIndex();
1005 const MachineConstantPool *MCP = MF.getConstantPool();
1006 if (CPI >= MCP->getConstants().size())
1007 CPI = AFI.getOriginalCPIdx(CPI);
1008 assert(CPI != -1U && "Invalid constpool index");
1010 // Derive the actual offset.
1011 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1012 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1013 // FIXME: Check for user, it should be "add" instruction!
1014 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1019 if (DstReg == FramePtr && FramePtr != ARM::SP)
1020 // Set-up of the frame pointer. Positive values correspond to "add"
1022 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1023 else if (DstReg == ARM::SP) {
1024 // Change of SP by an offset. Positive values correspond to "sub"
1026 ATS.emitPad(Offset);
1028 // Move of SP to a register. Positive values correspond to an "add"
1030 ATS.emitMovSP(DstReg, -Offset);
1032 } else if (DstReg == ARM::SP) {
1034 llvm_unreachable("Unsupported opcode for unwinding information");
1038 llvm_unreachable("Unsupported opcode for unwinding information");
1043 // Simple pseudo-instructions have their lowering (with expansion to real
1044 // instructions) auto-generated.
1045 #include "ARMGenMCPseudoLowering.inc"
1047 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1048 const DataLayout *DL = TM.getDataLayout();
1050 // If we just ended a constant pool, mark it as such.
1051 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1052 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1053 InConstantPool = false;
1056 // Emit unwinding stuff for frame-related instructions
1057 if (Subtarget->isTargetEHABICompatible() &&
1058 MI->getFlag(MachineInstr::FrameSetup))
1059 EmitUnwindingInstruction(MI);
1061 // Do any auto-generated pseudo lowerings.
1062 if (emitPseudoExpansionLowering(OutStreamer, MI))
1065 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1066 "Pseudo flag setting opcode should be expanded early");
1068 // Check for manual lowerings.
1069 unsigned Opc = MI->getOpcode();
1071 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1072 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1074 case ARM::tLEApcrel:
1075 case ARM::t2LEApcrel: {
1076 // FIXME: Need to also handle globals and externals
1077 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1078 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1079 ARM::t2LEApcrel ? ARM::t2ADR
1080 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1082 .addReg(MI->getOperand(0).getReg())
1083 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1084 // Add predicate operands.
1085 .addImm(MI->getOperand(2).getImm())
1086 .addReg(MI->getOperand(3).getReg()));
1089 case ARM::LEApcrelJT:
1090 case ARM::tLEApcrelJT:
1091 case ARM::t2LEApcrelJT: {
1092 MCSymbol *JTIPICSymbol =
1093 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1094 MI->getOperand(2).getImm());
1095 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1096 ARM::t2LEApcrelJT ? ARM::t2ADR
1097 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1099 .addReg(MI->getOperand(0).getReg())
1100 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1101 // Add predicate operands.
1102 .addImm(MI->getOperand(3).getImm())
1103 .addReg(MI->getOperand(4).getReg()));
1106 // Darwin call instructions are just normal call instructions with different
1107 // clobber semantics (they clobber R9).
1108 case ARM::BX_CALL: {
1109 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1112 // Add predicate operands.
1115 // Add 's' bit operand (always reg0 for this)
1118 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1119 .addReg(MI->getOperand(0).getReg()));
1122 case ARM::tBX_CALL: {
1123 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1126 // Add predicate operands.
1130 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1131 .addReg(MI->getOperand(0).getReg())
1132 // Add predicate operands.
1137 case ARM::BMOVPCRX_CALL: {
1138 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1141 // Add predicate operands.
1144 // Add 's' bit operand (always reg0 for this)
1147 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1149 .addReg(MI->getOperand(0).getReg())
1150 // Add predicate operands.
1153 // Add 's' bit operand (always reg0 for this)
1157 case ARM::BMOVPCB_CALL: {
1158 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1161 // Add predicate operands.
1164 // Add 's' bit operand (always reg0 for this)
1167 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1168 MCSymbol *GVSym = getSymbol(GV);
1169 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1170 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1172 // Add predicate operands.
1177 case ARM::MOVi16_ga_pcrel:
1178 case ARM::t2MOVi16_ga_pcrel: {
1180 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1181 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1183 unsigned TF = MI->getOperand(1).getTargetFlags();
1184 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1185 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1186 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1188 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1189 getFunctionNumber(),
1190 MI->getOperand(2).getImm(), OutContext);
1191 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1192 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1193 const MCExpr *PCRelExpr =
1194 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1195 MCBinaryExpr::CreateAdd(LabelSymExpr,
1196 MCConstantExpr::Create(PCAdj, OutContext),
1197 OutContext), OutContext), OutContext);
1198 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1200 // Add predicate operands.
1201 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1202 TmpInst.addOperand(MCOperand::CreateReg(0));
1203 // Add 's' bit operand (always reg0 for this)
1204 TmpInst.addOperand(MCOperand::CreateReg(0));
1205 EmitToStreamer(OutStreamer, TmpInst);
1208 case ARM::MOVTi16_ga_pcrel:
1209 case ARM::t2MOVTi16_ga_pcrel: {
1211 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1212 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1213 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1214 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1216 unsigned TF = MI->getOperand(2).getTargetFlags();
1217 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1218 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1219 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1221 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1222 getFunctionNumber(),
1223 MI->getOperand(3).getImm(), OutContext);
1224 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1225 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1226 const MCExpr *PCRelExpr =
1227 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1228 MCBinaryExpr::CreateAdd(LabelSymExpr,
1229 MCConstantExpr::Create(PCAdj, OutContext),
1230 OutContext), OutContext), OutContext);
1231 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1232 // Add predicate operands.
1233 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1234 TmpInst.addOperand(MCOperand::CreateReg(0));
1235 // Add 's' bit operand (always reg0 for this)
1236 TmpInst.addOperand(MCOperand::CreateReg(0));
1237 EmitToStreamer(OutStreamer, TmpInst);
1240 case ARM::tPICADD: {
1241 // This is a pseudo op for a label + instruction sequence, which looks like:
1244 // This adds the address of LPC0 to r0.
1247 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1248 getFunctionNumber(), MI->getOperand(2).getImm(),
1251 // Form and emit the add.
1252 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1253 .addReg(MI->getOperand(0).getReg())
1254 .addReg(MI->getOperand(0).getReg())
1256 // Add predicate operands.
1262 // This is a pseudo op for a label + instruction sequence, which looks like:
1265 // This adds the address of LPC0 to r0.
1268 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1269 getFunctionNumber(), MI->getOperand(2).getImm(),
1272 // Form and emit the add.
1273 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1274 .addReg(MI->getOperand(0).getReg())
1276 .addReg(MI->getOperand(1).getReg())
1277 // Add predicate operands.
1278 .addImm(MI->getOperand(3).getImm())
1279 .addReg(MI->getOperand(4).getReg())
1280 // Add 's' bit operand (always reg0 for this)
1291 case ARM::PICLDRSH: {
1292 // This is a pseudo op for a label + instruction sequence, which looks like:
1295 // The LCP0 label is referenced by a constant pool entry in order to get
1296 // a PC-relative address at the ldr instruction.
1299 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1300 getFunctionNumber(), MI->getOperand(2).getImm(),
1303 // Form and emit the load
1305 switch (MI->getOpcode()) {
1307 llvm_unreachable("Unexpected opcode!");
1308 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1309 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1310 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1311 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1312 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1313 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1314 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1315 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1317 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1318 .addReg(MI->getOperand(0).getReg())
1320 .addReg(MI->getOperand(1).getReg())
1322 // Add predicate operands.
1323 .addImm(MI->getOperand(3).getImm())
1324 .addReg(MI->getOperand(4).getReg()));
1328 case ARM::CONSTPOOL_ENTRY: {
1329 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1330 /// in the function. The first operand is the ID# for this instruction, the
1331 /// second is the index into the MachineConstantPool that this is, the third
1332 /// is the size in bytes of this constant pool entry.
1333 /// The required alignment is specified on the basic block holding this MI.
1334 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1335 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1337 // If this is the first entry of the pool, mark it.
1338 if (!InConstantPool) {
1339 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1340 InConstantPool = true;
1343 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1345 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1346 if (MCPE.isMachineConstantPoolEntry())
1347 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1349 EmitGlobalConstant(MCPE.Val.ConstVal);
1352 case ARM::t2BR_JT: {
1353 // Lower and emit the instruction itself, then the jump table following it.
1354 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1356 .addReg(MI->getOperand(0).getReg())
1357 // Add predicate operands.
1361 // Output the data for the jump table itself
1365 case ARM::t2TBB_JT: {
1366 // Lower and emit the instruction itself, then the jump table following it.
1367 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1369 .addReg(MI->getOperand(0).getReg())
1370 // Add predicate operands.
1374 // Output the data for the jump table itself
1376 // Make sure the next instruction is 2-byte aligned.
1380 case ARM::t2TBH_JT: {
1381 // Lower and emit the instruction itself, then the jump table following it.
1382 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1384 .addReg(MI->getOperand(0).getReg())
1385 // Add predicate operands.
1389 // Output the data for the jump table itself
1395 // Lower and emit the instruction itself, then the jump table following it.
1398 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1399 ARM::MOVr : ARM::tMOVr;
1400 TmpInst.setOpcode(Opc);
1401 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1402 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1403 // Add predicate operands.
1404 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1405 TmpInst.addOperand(MCOperand::CreateReg(0));
1406 // Add 's' bit operand (always reg0 for this)
1407 if (Opc == ARM::MOVr)
1408 TmpInst.addOperand(MCOperand::CreateReg(0));
1409 EmitToStreamer(OutStreamer, TmpInst);
1411 // Make sure the Thumb jump table is 4-byte aligned.
1412 if (Opc == ARM::tMOVr)
1415 // Output the data for the jump table itself
1420 // Lower and emit the instruction itself, then the jump table following it.
1423 if (MI->getOperand(1).getReg() == 0) {
1425 TmpInst.setOpcode(ARM::LDRi12);
1426 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1427 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1428 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1430 TmpInst.setOpcode(ARM::LDRrs);
1431 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1432 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1433 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1434 TmpInst.addOperand(MCOperand::CreateImm(0));
1436 // Add predicate operands.
1437 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1438 TmpInst.addOperand(MCOperand::CreateReg(0));
1439 EmitToStreamer(OutStreamer, TmpInst);
1441 // Output the data for the jump table itself
1445 case ARM::BR_JTadd: {
1446 // Lower and emit the instruction itself, then the jump table following it.
1447 // add pc, target, idx
1448 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1450 .addReg(MI->getOperand(0).getReg())
1451 .addReg(MI->getOperand(1).getReg())
1452 // Add predicate operands.
1455 // Add 's' bit operand (always reg0 for this)
1458 // Output the data for the jump table itself
1463 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1464 // FIXME: Remove this special case when they do.
1465 if (!Subtarget->isTargetMachO()) {
1466 //.long 0xe7ffdefe @ trap
1467 uint32_t Val = 0xe7ffdefeUL;
1468 OutStreamer.AddComment("trap");
1469 OutStreamer.EmitIntValue(Val, 4);
1474 case ARM::TRAPNaCl: {
1475 //.long 0xe7fedef0 @ trap
1476 uint32_t Val = 0xe7fedef0UL;
1477 OutStreamer.AddComment("trap");
1478 OutStreamer.EmitIntValue(Val, 4);
1482 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1483 // FIXME: Remove this special case when they do.
1484 if (!Subtarget->isTargetMachO()) {
1485 //.short 57086 @ trap
1486 uint16_t Val = 0xdefe;
1487 OutStreamer.AddComment("trap");
1488 OutStreamer.EmitIntValue(Val, 2);
1493 case ARM::t2Int_eh_sjlj_setjmp:
1494 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1495 case ARM::tInt_eh_sjlj_setjmp: {
1496 // Two incoming args: GPR:$src, GPR:$val
1499 // str $val, [$src, #4]
1504 unsigned SrcReg = MI->getOperand(0).getReg();
1505 unsigned ValReg = MI->getOperand(1).getReg();
1506 MCSymbol *Label = GetARMSJLJEHLabel();
1507 OutStreamer.AddComment("eh_setjmp begin");
1508 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1515 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1525 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1528 // The offset immediate is #4. The operand value is scaled by 4 for the
1529 // tSTR instruction.
1535 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1543 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1544 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1545 .addExpr(SymbolExpr)
1549 OutStreamer.AddComment("eh_setjmp end");
1550 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1558 OutStreamer.EmitLabel(Label);
1562 case ARM::Int_eh_sjlj_setjmp_nofp:
1563 case ARM::Int_eh_sjlj_setjmp: {
1564 // Two incoming args: GPR:$src, GPR:$val
1566 // str $val, [$src, #+4]
1570 unsigned SrcReg = MI->getOperand(0).getReg();
1571 unsigned ValReg = MI->getOperand(1).getReg();
1573 OutStreamer.AddComment("eh_setjmp begin");
1574 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1581 // 's' bit operand (always reg0 for this).
1584 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1592 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1598 // 's' bit operand (always reg0 for this).
1601 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1608 // 's' bit operand (always reg0 for this).
1611 OutStreamer.AddComment("eh_setjmp end");
1612 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1618 // 's' bit operand (always reg0 for this).
1622 case ARM::Int_eh_sjlj_longjmp: {
1623 // ldr sp, [$src, #8]
1624 // ldr $scratch, [$src, #4]
1627 unsigned SrcReg = MI->getOperand(0).getReg();
1628 unsigned ScratchReg = MI->getOperand(1).getReg();
1629 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1637 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1645 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1653 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1660 case ARM::tInt_eh_sjlj_longjmp: {
1661 // ldr $scratch, [$src, #8]
1663 // ldr $scratch, [$src, #4]
1666 unsigned SrcReg = MI->getOperand(0).getReg();
1667 unsigned ScratchReg = MI->getOperand(1).getReg();
1668 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1671 // The offset immediate is #8. The operand value is scaled by 4 for the
1672 // tLDR instruction.
1678 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1685 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1693 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1701 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1711 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1713 EmitToStreamer(OutStreamer, TmpInst);
1716 //===----------------------------------------------------------------------===//
1717 // Target Registry Stuff
1718 //===----------------------------------------------------------------------===//
1720 // Force static initialization.
1721 extern "C" void LLVMInitializeARMAsmPrinter() {
1722 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1723 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);