1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 MCObjectStreamer &Streamer;
104 StringRef CurrentVendor;
105 SmallString<64> Contents;
108 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
109 Streamer(Streamer_), CurrentVendor("") { }
111 void MaybeSwitchVendor(StringRef Vendor) {
112 assert(!Vendor.empty() && "Vendor cannot be empty.");
114 if (CurrentVendor.empty())
115 CurrentVendor = Vendor;
116 else if (CurrentVendor == Vendor)
121 CurrentVendor = Vendor;
123 assert(Contents.size() == 0);
126 void EmitAttribute(unsigned Attribute, unsigned Value) {
127 // FIXME: should be ULEB
128 Contents += Attribute;
132 void EmitTextAttribute(unsigned Attribute, StringRef String) {
133 Contents += Attribute;
134 Contents += UppercaseString(String);
139 const size_t ContentsSize = Contents.size();
141 // Vendor size + Vendor name + '\0'
142 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
145 const size_t TagHeaderSize = 1 + 4;
147 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
148 Streamer.EmitBytes(CurrentVendor, 0);
149 Streamer.EmitIntValue(0, 1); // '\0'
151 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
152 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
154 Streamer.EmitBytes(Contents, 0);
160 } // end of anonymous namespace
162 MachineLocation ARMAsmPrinter::
163 getDebugValueLocation(const MachineInstr *MI) const {
164 MachineLocation Location;
165 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
166 // Frame address. Currently handles register +- offset only.
167 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
168 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
170 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
175 /// getDwarfRegOpSize - get size required to emit given machine location using
177 unsigned ARMAsmPrinter::getDwarfRegOpSize(const MachineLocation &MLoc) const {
178 const TargetRegisterInfo *RI = TM.getRegisterInfo();
179 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
180 return AsmPrinter::getDwarfRegOpSize(MLoc);
182 unsigned Reg = MLoc.getReg();
183 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
184 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
185 // S registers are described as bit-pieces of a register
186 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
187 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
189 unsigned SReg = Reg - ARM::S0;
190 unsigned Rx = 256 + (SReg >> 1);
191 // DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
192 // 1 + ULEB(Rx) + 1 + 1 + 1
193 return 4 + MCAsmInfo::getULEB128Size(Rx);
196 if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
197 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
198 // Q registers Q0-Q15 are described by composing two D registers together.
199 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
201 unsigned QReg = Reg - ARM::Q0;
202 unsigned D1 = 256 + 2 * QReg;
203 unsigned D2 = D1 + 1;
205 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
206 // DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
207 // 6 + ULEB(D1) + ULEB(D2)
208 return 6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2);
214 /// EmitDwarfRegOp - Emit dwarf register operation.
215 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
216 const TargetRegisterInfo *RI = TM.getRegisterInfo();
217 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
218 AsmPrinter::EmitDwarfRegOp(MLoc);
220 unsigned Reg = MLoc.getReg();
221 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
222 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
223 // S registers are described as bit-pieces of a register
224 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
225 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
227 unsigned SReg = Reg - ARM::S0;
228 bool odd = SReg & 0x1;
229 unsigned Rx = 256 + (SReg >> 1);
231 OutStreamer.AddComment("DW_OP_regx for S register");
232 EmitInt8(dwarf::DW_OP_regx);
234 OutStreamer.AddComment(Twine(SReg));
238 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
239 EmitInt8(dwarf::DW_OP_bit_piece);
243 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
244 EmitInt8(dwarf::DW_OP_bit_piece);
248 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
249 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
250 // Q registers Q0-Q15 are described by composing two D registers together.
251 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
253 unsigned QReg = Reg - ARM::Q0;
254 unsigned D1 = 256 + 2 * QReg;
255 unsigned D2 = D1 + 1;
257 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
258 EmitInt8(dwarf::DW_OP_regx);
260 OutStreamer.AddComment("DW_OP_piece 8");
261 EmitInt8(dwarf::DW_OP_piece);
264 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
265 EmitInt8(dwarf::DW_OP_regx);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
274 void ARMAsmPrinter::EmitFunctionEntryLabel() {
275 if (AFI->isThumbFunction()) {
276 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
277 OutStreamer.EmitThumbFunc(CurrentFnSym);
280 OutStreamer.EmitLabel(CurrentFnSym);
283 /// runOnMachineFunction - This uses the EmitInstruction()
284 /// method to print assembly for each instruction.
286 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
287 AFI = MF.getInfo<ARMFunctionInfo>();
288 MCP = MF.getConstantPool();
290 return AsmPrinter::runOnMachineFunction(MF);
293 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
294 raw_ostream &O, const char *Modifier) {
295 const MachineOperand &MO = MI->getOperand(OpNum);
296 unsigned TF = MO.getTargetFlags();
298 switch (MO.getType()) {
300 assert(0 && "<unknown operand type>");
301 case MachineOperand::MO_Register: {
302 unsigned Reg = MO.getReg();
303 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
304 assert(!MO.getSubReg() && "Subregs should be eliminated!");
305 O << ARMInstPrinter::getRegisterName(Reg);
308 case MachineOperand::MO_Immediate: {
309 int64_t Imm = MO.getImm();
311 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
312 (TF == ARMII::MO_LO16))
314 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
315 (TF == ARMII::MO_HI16))
320 case MachineOperand::MO_MachineBasicBlock:
321 O << *MO.getMBB()->getSymbol();
323 case MachineOperand::MO_GlobalAddress: {
324 const GlobalValue *GV = MO.getGlobal();
325 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
326 (TF & ARMII::MO_LO16))
328 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
329 (TF & ARMII::MO_HI16))
331 O << *Mang->getSymbol(GV);
333 printOffset(MO.getOffset(), O);
334 if (TF == ARMII::MO_PLT)
338 case MachineOperand::MO_ExternalSymbol: {
339 O << *GetExternalSymbolSymbol(MO.getSymbolName());
340 if (TF == ARMII::MO_PLT)
344 case MachineOperand::MO_ConstantPoolIndex:
345 O << *GetCPISymbol(MO.getIndex());
347 case MachineOperand::MO_JumpTableIndex:
348 O << *GetJTISymbol(MO.getIndex());
353 //===--------------------------------------------------------------------===//
355 MCSymbol *ARMAsmPrinter::
356 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
357 const MachineBasicBlock *MBB) const {
358 SmallString<60> Name;
359 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
360 << getFunctionNumber() << '_' << uid << '_' << uid2
361 << "_set_" << MBB->getNumber();
362 return OutContext.GetOrCreateSymbol(Name.str());
365 MCSymbol *ARMAsmPrinter::
366 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
367 SmallString<60> Name;
368 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
369 << getFunctionNumber() << '_' << uid << '_' << uid2;
370 return OutContext.GetOrCreateSymbol(Name.str());
374 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
375 SmallString<60> Name;
376 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
377 << getFunctionNumber();
378 return OutContext.GetOrCreateSymbol(Name.str());
381 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
382 unsigned AsmVariant, const char *ExtraCode,
384 // Does this asm operand have a single letter operand modifier?
385 if (ExtraCode && ExtraCode[0]) {
386 if (ExtraCode[1] != 0) return true; // Unknown modifier.
388 switch (ExtraCode[0]) {
389 default: return true; // Unknown modifier.
390 case 'a': // Print as a memory address.
391 if (MI->getOperand(OpNum).isReg()) {
393 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
398 case 'c': // Don't print "#" before an immediate operand.
399 if (!MI->getOperand(OpNum).isImm())
401 O << MI->getOperand(OpNum).getImm();
403 case 'P': // Print a VFP double precision register.
404 case 'q': // Print a NEON quad precision register.
405 printOperand(MI, OpNum, O);
407 case 'y': // Print a VFP single precision register as indexed double.
408 // This uses the ordering of the alias table to get the first 'd' register
409 // that overlaps the 's' register. Also, s0 is an odd register, hence the
410 // odd modulus check below.
411 if (MI->getOperand(OpNum).isReg()) {
412 unsigned Reg = MI->getOperand(OpNum).getReg();
413 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
414 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
415 (((Reg % 2) == 1) ? "[0]" : "[1]");
419 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
420 if (!MI->getOperand(OpNum).isImm())
422 O << ~(MI->getOperand(OpNum).getImm());
424 case 'L': // The low 16 bits of an immediate constant.
425 if (!MI->getOperand(OpNum).isImm())
427 O << (MI->getOperand(OpNum).getImm() & 0xffff);
429 case 'M': // A register range suitable for LDM/STM.
430 case 'p': // The high single-precision register of a VFP double-precision
432 case 'e': // The low doubleword register of a NEON quad register.
433 case 'f': // The high doubleword register of a NEON quad register.
434 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
435 case 'A': // A memory operand for a VLD1/VST1 instruction.
436 case 'Q': // The least significant register of a pair.
437 case 'R': // The most significant register of a pair.
438 case 'H': // The highest-numbered register of a pair.
439 // These modifiers are not yet supported.
444 printOperand(MI, OpNum, O);
448 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
449 unsigned OpNum, unsigned AsmVariant,
450 const char *ExtraCode,
452 // Does this asm operand have a single letter operand modifier?
453 if (ExtraCode && ExtraCode[0]) {
454 if (ExtraCode[1] != 0) return true; // Unknown modifier.
456 switch (ExtraCode[0]) {
457 default: return true; // Unknown modifier.
458 case 'm': // The base register of a memory operand.
459 if (!MI->getOperand(OpNum).isReg())
461 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
466 const MachineOperand &MO = MI->getOperand(OpNum);
467 assert(MO.isReg() && "unexpected inline asm memory operand");
468 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
472 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
473 if (Subtarget->isTargetDarwin()) {
474 Reloc::Model RelocM = TM.getRelocationModel();
475 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
476 // Declare all the text sections up front (before the DWARF sections
477 // emitted by AsmPrinter::doInitialization) so the assembler will keep
478 // them together at the beginning of the object file. This helps
479 // avoid out-of-range branches that are due a fundamental limitation of
480 // the way symbol offsets are encoded with the current Darwin ARM
482 const TargetLoweringObjectFileMachO &TLOFMacho =
483 static_cast<const TargetLoweringObjectFileMachO &>(
484 getObjFileLowering());
485 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
486 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
487 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
488 if (RelocM == Reloc::DynamicNoPIC) {
489 const MCSection *sect =
490 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
491 MCSectionMachO::S_SYMBOL_STUBS,
492 12, SectionKind::getText());
493 OutStreamer.SwitchSection(sect);
495 const MCSection *sect =
496 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
497 MCSectionMachO::S_SYMBOL_STUBS,
498 16, SectionKind::getText());
499 OutStreamer.SwitchSection(sect);
501 const MCSection *StaticInitSect =
502 OutContext.getMachOSection("__TEXT", "__StaticInit",
503 MCSectionMachO::S_REGULAR |
504 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
505 SectionKind::getText());
506 OutStreamer.SwitchSection(StaticInitSect);
510 // Use unified assembler syntax.
511 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
513 // Emit ARM Build Attributes
514 if (Subtarget->isTargetELF()) {
521 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
522 if (Subtarget->isTargetDarwin()) {
523 // All darwin targets use mach-o.
524 const TargetLoweringObjectFileMachO &TLOFMacho =
525 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
526 MachineModuleInfoMachO &MMIMacho =
527 MMI->getObjFileInfo<MachineModuleInfoMachO>();
529 // Output non-lazy-pointers for external and common global variables.
530 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
532 if (!Stubs.empty()) {
533 // Switch with ".non_lazy_symbol_pointer" directive.
534 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
536 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
538 OutStreamer.EmitLabel(Stubs[i].first);
539 // .indirect_symbol _foo
540 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
541 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
544 // External to current translation unit.
545 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
547 // Internal to current translation unit.
549 // When we place the LSDA into the TEXT section, the type info
550 // pointers need to be indirect and pc-rel. We accomplish this by
551 // using NLPs; however, sometimes the types are local to the file.
552 // We need to fill in the value for the NLP in those cases.
553 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
555 4/*size*/, 0/*addrspace*/);
559 OutStreamer.AddBlankLine();
562 Stubs = MMIMacho.GetHiddenGVStubList();
563 if (!Stubs.empty()) {
564 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
566 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
568 OutStreamer.EmitLabel(Stubs[i].first);
570 OutStreamer.EmitValue(MCSymbolRefExpr::
571 Create(Stubs[i].second.getPointer(),
573 4/*size*/, 0/*addrspace*/);
577 OutStreamer.AddBlankLine();
580 // Funny Darwin hack: This flag tells the linker that no global symbols
581 // contain code that falls through to other global symbols (e.g. the obvious
582 // implementation of multiple entry points). If this doesn't occur, the
583 // linker can safely perform dead code stripping. Since LLVM never
584 // generates code that does this, it is always safe to set.
585 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
589 //===----------------------------------------------------------------------===//
590 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
592 // The following seem like one-off assembler flags, but they actually need
593 // to appear in the .ARM.attributes section in ELF.
594 // Instead of subclassing the MCELFStreamer, we do the work here.
596 void ARMAsmPrinter::emitAttributes() {
598 emitARMAttributeSection();
600 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
601 bool emitFPU = false;
602 AttributeEmitter *AttrEmitter;
603 if (OutStreamer.hasRawTextSupport()) {
604 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
607 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
608 AttrEmitter = new ObjectAttributeEmitter(O);
611 AttrEmitter->MaybeSwitchVendor("aeabi");
613 std::string CPUString = Subtarget->getCPUString();
615 if (CPUString == "cortex-a8" ||
616 Subtarget->isCortexA8()) {
617 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
618 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
619 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
620 ARMBuildAttrs::ApplicationProfile);
621 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
622 ARMBuildAttrs::Allowed);
623 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
624 ARMBuildAttrs::AllowThumb32);
625 // Fixme: figure out when this is emitted.
626 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
627 // ARMBuildAttrs::AllowWMMXv1);
630 /// ADD additional Else-cases here!
631 } else if (CPUString == "xscale") {
632 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
633 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
634 ARMBuildAttrs::Allowed);
635 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
636 ARMBuildAttrs::Allowed);
637 } else if (CPUString == "generic") {
638 // FIXME: Why these defaults?
639 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
640 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
641 ARMBuildAttrs::Allowed);
642 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
643 ARMBuildAttrs::Allowed);
646 if (Subtarget->hasNEON() && emitFPU) {
647 /* NEON is not exactly a VFP architecture, but GAS emit one of
648 * neon/vfpv3/vfpv2 for .fpu parameters */
649 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
650 /* If emitted for NEON, omit from VFP below, since you can have both
651 * NEON and VFP in build attributes but only one .fpu */
656 if (Subtarget->hasVFP3()) {
657 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
658 ARMBuildAttrs::AllowFPv3A);
660 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
663 } else if (Subtarget->hasVFP2()) {
664 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
665 ARMBuildAttrs::AllowFPv2);
667 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
670 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
671 * since NEON can have 1 (allowed) or 2 (fused MAC operations) */
672 if (Subtarget->hasNEON()) {
673 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
674 ARMBuildAttrs::Allowed);
677 // Signal various FP modes.
679 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
680 ARMBuildAttrs::Allowed);
681 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
682 ARMBuildAttrs::Allowed);
685 if (NoInfsFPMath && NoNaNsFPMath)
686 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
687 ARMBuildAttrs::Allowed);
689 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
690 ARMBuildAttrs::AllowIEE754);
692 // FIXME: add more flags to ARMBuildAttrs.h
693 // 8-bytes alignment stuff.
694 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
695 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
697 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
698 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
699 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
700 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
702 // FIXME: Should we signal R9 usage?
704 if (Subtarget->hasDivide())
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
707 AttrEmitter->Finish();
711 void ARMAsmPrinter::emitARMAttributeSection() {
713 // [ <section-length> "vendor-name"
714 // [ <file-tag> <size> <attribute>*
715 // | <section-tag> <size> <section-number>* 0 <attribute>*
716 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
720 if (OutStreamer.hasRawTextSupport())
723 const ARMElfTargetObjectFile &TLOFELF =
724 static_cast<const ARMElfTargetObjectFile &>
725 (getObjFileLowering());
727 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
730 OutStreamer.EmitIntValue(0x41, 1);
733 //===----------------------------------------------------------------------===//
735 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
736 unsigned LabelId, MCContext &Ctx) {
738 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
739 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
743 static MCSymbolRefExpr::VariantKind
744 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
746 default: llvm_unreachable("Unknown modifier!");
747 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
748 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
749 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
750 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
751 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
752 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
754 return MCSymbolRefExpr::VK_None;
757 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
758 bool isIndirect = Subtarget->isTargetDarwin() &&
759 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
761 return Mang->getSymbol(GV);
763 // FIXME: Remove this when Darwin transition to @GOT like syntax.
764 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
765 MachineModuleInfoMachO &MMIMachO =
766 MMI->getObjFileInfo<MachineModuleInfoMachO>();
767 MachineModuleInfoImpl::StubValueTy &StubSym =
768 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
769 MMIMachO.getGVStubEntry(MCSym);
770 if (StubSym.getPointer() == 0)
771 StubSym = MachineModuleInfoImpl::
772 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
777 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
778 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
780 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
783 if (ACPV->isLSDA()) {
784 SmallString<128> Str;
785 raw_svector_ostream OS(Str);
786 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
787 MCSym = OutContext.GetOrCreateSymbol(OS.str());
788 } else if (ACPV->isBlockAddress()) {
789 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
790 } else if (ACPV->isGlobalValue()) {
791 const GlobalValue *GV = ACPV->getGV();
792 MCSym = GetARMGVSymbol(GV);
794 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
795 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
798 // Create an MCSymbol for the reference.
800 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
803 if (ACPV->getPCAdjustment()) {
804 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
808 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
810 MCBinaryExpr::CreateAdd(PCRelExpr,
811 MCConstantExpr::Create(ACPV->getPCAdjustment(),
814 if (ACPV->mustAddCurrentAddress()) {
815 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
816 // label, so just emit a local label end reference that instead.
817 MCSymbol *DotSym = OutContext.CreateTempSymbol();
818 OutStreamer.EmitLabel(DotSym);
819 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
820 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
822 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
824 OutStreamer.EmitValue(Expr, Size);
827 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
828 unsigned Opcode = MI->getOpcode();
830 if (Opcode == ARM::BR_JTadd)
832 else if (Opcode == ARM::BR_JTm)
835 const MachineOperand &MO1 = MI->getOperand(OpNum);
836 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
837 unsigned JTI = MO1.getIndex();
839 // Emit a label for the jump table.
840 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
841 OutStreamer.EmitLabel(JTISymbol);
843 // Emit each entry of the table.
844 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
845 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
846 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
848 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
849 MachineBasicBlock *MBB = JTBBs[i];
850 // Construct an MCExpr for the entry. We want a value of the form:
851 // (BasicBlockAddr - TableBeginAddr)
853 // For example, a table with entries jumping to basic blocks BB0 and BB1
856 // .word (LBB0 - LJTI_0_0)
857 // .word (LBB1 - LJTI_0_0)
858 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
860 if (TM.getRelocationModel() == Reloc::PIC_)
861 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
864 OutStreamer.EmitValue(Expr, 4);
868 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
869 unsigned Opcode = MI->getOpcode();
870 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
871 const MachineOperand &MO1 = MI->getOperand(OpNum);
872 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
873 unsigned JTI = MO1.getIndex();
875 // Emit a label for the jump table.
876 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
877 OutStreamer.EmitLabel(JTISymbol);
879 // Emit each entry of the table.
880 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
881 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
882 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
883 unsigned OffsetWidth = 4;
884 if (MI->getOpcode() == ARM::t2TBB_JT)
886 else if (MI->getOpcode() == ARM::t2TBH_JT)
889 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
890 MachineBasicBlock *MBB = JTBBs[i];
891 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
893 // If this isn't a TBB or TBH, the entries are direct branch instructions.
894 if (OffsetWidth == 4) {
896 BrInst.setOpcode(ARM::t2B);
897 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
898 OutStreamer.EmitInstruction(BrInst);
901 // Otherwise it's an offset from the dispatch instruction. Construct an
902 // MCExpr for the entry. We want a value of the form:
903 // (BasicBlockAddr - TableBeginAddr) / 2
905 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
908 // .byte (LBB0 - LJTI_0_0) / 2
909 // .byte (LBB1 - LJTI_0_0) / 2
911 MCBinaryExpr::CreateSub(MBBSymbolExpr,
912 MCSymbolRefExpr::Create(JTISymbol, OutContext),
914 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
916 OutStreamer.EmitValue(Expr, OffsetWidth);
920 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
922 unsigned NOps = MI->getNumOperands();
924 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
925 // cast away const; DIetc do not take const operands for some reason.
926 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
929 // Frame address. Currently handles register +- offset only.
930 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
931 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
934 printOperand(MI, NOps-2, OS);
937 static void populateADROperands(MCInst &Inst, unsigned Dest,
938 const MCSymbol *Label,
939 unsigned pred, unsigned ccreg,
941 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
942 Inst.addOperand(MCOperand::CreateReg(Dest));
943 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
944 // Add predicate operands.
945 Inst.addOperand(MCOperand::CreateImm(pred));
946 Inst.addOperand(MCOperand::CreateReg(ccreg));
949 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
953 // Emit the instruction as usual, just patch the opcode.
954 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
955 TmpInst.setOpcode(Opcode);
956 OutStreamer.EmitInstruction(TmpInst);
959 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
960 assert(MI->getFlag(MachineInstr::FrameSetup) &&
961 "Only instruction which are involved into frame setup code are allowed");
963 const MachineFunction &MF = *MI->getParent()->getParent();
964 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
965 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
967 unsigned FramePtr = RegInfo->getFrameRegister(MF);
968 unsigned Opc = MI->getOpcode();
969 unsigned SrcReg, DstReg;
971 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
972 // Two special cases:
973 // 1) tPUSH does not have src/dst regs.
974 // 2) for Thumb1 code we sometimes materialize the constant via constpool
975 // load. Yes, this is pretty fragile, but for now I don't see better
977 SrcReg = DstReg = ARM::SP;
979 SrcReg = MI->getOperand(1).getReg();
980 DstReg = MI->getOperand(0).getReg();
983 // Try to figure out the unwinding opcode out of src / dst regs.
984 if (MI->getDesc().mayStore()) {
986 assert(DstReg == ARM::SP &&
987 "Only stack pointer as a destination reg is supported");
989 SmallVector<unsigned, 4> RegList;
990 // Skip src & dst reg, and pred ops.
991 unsigned StartOp = 2 + 2;
992 // Use all the operands.
993 unsigned NumOffset = 0;
998 assert(0 && "Unsupported opcode for unwinding information");
1000 // Special case here: no src & dst reg, but two extra imp ops.
1001 StartOp = 2; NumOffset = 2;
1002 case ARM::STMDB_UPD:
1003 case ARM::t2STMDB_UPD:
1004 case ARM::VSTMDDB_UPD:
1005 assert(SrcReg == ARM::SP &&
1006 "Only stack pointer as a source reg is supported");
1007 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1009 RegList.push_back(MI->getOperand(i).getReg());
1012 assert(MI->getOperand(2).getReg() == ARM::SP &&
1013 "Only stack pointer as a source reg is supported");
1014 RegList.push_back(SrcReg);
1017 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1019 // Changes of stack / frame pointer.
1020 if (SrcReg == ARM::SP) {
1025 assert(0 && "Unsupported opcode for unwinding information");
1027 case ARM::tMOVgpr2gpr:
1028 case ARM::tMOVgpr2tgpr:
1032 Offset = -MI->getOperand(2).getImm();
1035 case ARM::t2SUBrSPi:
1036 Offset = MI->getOperand(2).getImm();
1039 Offset = MI->getOperand(2).getImm()*4;
1043 Offset = -MI->getOperand(2).getImm()*4;
1045 case ARM::tLDRpci: {
1046 // Grab the constpool index and check, whether it corresponds to
1047 // original or cloned constpool entry.
1048 unsigned CPI = MI->getOperand(1).getIndex();
1049 const MachineConstantPool *MCP = MF.getConstantPool();
1050 if (CPI >= MCP->getConstants().size())
1051 CPI = AFI.getOriginalCPIdx(CPI);
1052 assert(CPI != -1U && "Invalid constpool index");
1054 // Derive the actual offset.
1055 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1056 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1057 // FIXME: Check for user, it should be "add" instruction!
1058 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1063 if (DstReg == FramePtr && FramePtr != ARM::SP)
1064 // Set-up of the frame pointer. Positive values correspond to "add"
1066 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1067 else if (DstReg == ARM::SP) {
1068 // Change of SP by an offset. Positive values correspond to "sub"
1070 OutStreamer.EmitPad(Offset);
1073 assert(0 && "Unsupported opcode for unwinding information");
1075 } else if (DstReg == ARM::SP) {
1076 // FIXME: .movsp goes here
1078 assert(0 && "Unsupported opcode for unwinding information");
1082 assert(0 && "Unsupported opcode for unwinding information");
1087 extern cl::opt<bool> EnableARMEHABI;
1089 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1090 unsigned Opc = MI->getOpcode();
1094 // B is just a Bcc with an 'always' predicate.
1096 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1097 TmpInst.setOpcode(ARM::Bcc);
1098 // Add predicate operands.
1099 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1100 TmpInst.addOperand(MCOperand::CreateReg(0));
1101 OutStreamer.EmitInstruction(TmpInst);
1104 case ARM::LDMIA_RET: {
1105 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
1106 // such has additional code-gen properties and scheduling information.
1107 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
1109 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1110 TmpInst.setOpcode(ARM::LDMIA_UPD);
1111 OutStreamer.EmitInstruction(TmpInst);
1114 case ARM::t2ADDrSPi:
1115 case ARM::t2ADDrSPi12:
1116 case ARM::t2SUBrSPi:
1117 case ARM::t2SUBrSPi12:
1118 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
1119 "Unexpected source register!");
1122 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1123 case ARM::DBG_VALUE: {
1124 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1125 SmallString<128> TmpStr;
1126 raw_svector_ostream OS(TmpStr);
1127 PrintDebugValueComment(MI, OS);
1128 OutStreamer.EmitRawText(StringRef(OS.str()));
1134 TmpInst.setOpcode(ARM::tBL);
1135 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
1136 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
1137 OutStreamer.EmitInstruction(TmpInst);
1141 case ARM::tLEApcrel:
1142 case ARM::t2LEApcrel: {
1143 // FIXME: Need to also handle globals and externals
1145 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1146 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1148 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1149 GetCPISymbol(MI->getOperand(1).getIndex()),
1150 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1152 OutStreamer.EmitInstruction(TmpInst);
1155 case ARM::LEApcrelJT:
1156 case ARM::tLEApcrelJT:
1157 case ARM::t2LEApcrelJT: {
1159 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1160 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1162 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1163 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1164 MI->getOperand(2).getImm()),
1165 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1167 OutStreamer.EmitInstruction(TmpInst);
1170 case ARM::MOVPCRX: {
1172 TmpInst.setOpcode(ARM::MOVr);
1173 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1174 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1175 // Add predicate operands.
1176 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1177 TmpInst.addOperand(MCOperand::CreateReg(0));
1178 // Add 's' bit operand (always reg0 for this)
1179 TmpInst.addOperand(MCOperand::CreateReg(0));
1180 OutStreamer.EmitInstruction(TmpInst);
1183 // Darwin call instructions are just normal call instructions with different
1184 // clobber semantics (they clobber R9).
1186 case ARM::BLr9_pred:
1188 case ARM::BLXr9_pred: {
1192 case ARM::BLr9: newOpc = ARM::BL; break;
1193 case ARM::BLr9_pred: newOpc = ARM::BL_pred; break;
1194 case ARM::BLXr9: newOpc = ARM::BLX; break;
1195 case ARM::BLXr9_pred: newOpc = ARM::BLX_pred; break;
1198 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1199 TmpInst.setOpcode(newOpc);
1200 OutStreamer.EmitInstruction(TmpInst);
1203 case ARM::BXr9_CALL:
1204 case ARM::BX_CALL: {
1207 TmpInst.setOpcode(ARM::MOVr);
1208 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1209 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1210 // Add predicate operands.
1211 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1212 TmpInst.addOperand(MCOperand::CreateReg(0));
1213 // Add 's' bit operand (always reg0 for this)
1214 TmpInst.addOperand(MCOperand::CreateReg(0));
1215 OutStreamer.EmitInstruction(TmpInst);
1219 TmpInst.setOpcode(ARM::BX);
1220 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1221 OutStreamer.EmitInstruction(TmpInst);
1225 case ARM::tBXr9_CALL:
1226 case ARM::tBX_CALL: {
1229 TmpInst.setOpcode(ARM::tMOVr);
1230 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1231 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1232 OutStreamer.EmitInstruction(TmpInst);
1236 TmpInst.setOpcode(ARM::tBX);
1237 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1238 // Add predicate operands.
1239 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1240 TmpInst.addOperand(MCOperand::CreateReg(0));
1241 OutStreamer.EmitInstruction(TmpInst);
1245 case ARM::BMOVPCRXr9_CALL:
1246 case ARM::BMOVPCRX_CALL: {
1249 TmpInst.setOpcode(ARM::MOVr);
1250 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1251 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1252 // Add predicate operands.
1253 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1254 TmpInst.addOperand(MCOperand::CreateReg(0));
1255 // Add 's' bit operand (always reg0 for this)
1256 TmpInst.addOperand(MCOperand::CreateReg(0));
1257 OutStreamer.EmitInstruction(TmpInst);
1261 TmpInst.setOpcode(ARM::MOVr);
1262 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1263 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1264 // Add predicate operands.
1265 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1266 TmpInst.addOperand(MCOperand::CreateReg(0));
1267 // Add 's' bit operand (always reg0 for this)
1268 TmpInst.addOperand(MCOperand::CreateReg(0));
1269 OutStreamer.EmitInstruction(TmpInst);
1273 case ARM::MOVi16_ga_pcrel:
1274 case ARM::t2MOVi16_ga_pcrel: {
1276 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1277 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1279 unsigned TF = MI->getOperand(1).getTargetFlags();
1280 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1281 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1282 MCSymbol *GVSym = GetARMGVSymbol(GV);
1283 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1285 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1286 getFunctionNumber(),
1287 MI->getOperand(2).getImm(), OutContext);
1288 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1289 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1290 const MCExpr *PCRelExpr =
1291 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1292 MCBinaryExpr::CreateAdd(LabelSymExpr,
1293 MCConstantExpr::Create(PCAdj, OutContext),
1294 OutContext), OutContext), OutContext);
1295 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1297 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1298 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1301 // Add predicate operands.
1302 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1303 TmpInst.addOperand(MCOperand::CreateReg(0));
1304 // Add 's' bit operand (always reg0 for this)
1305 TmpInst.addOperand(MCOperand::CreateReg(0));
1306 OutStreamer.EmitInstruction(TmpInst);
1309 case ARM::MOVTi16_ga_pcrel:
1310 case ARM::t2MOVTi16_ga_pcrel: {
1312 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1313 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1314 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1315 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1317 unsigned TF = MI->getOperand(2).getTargetFlags();
1318 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1319 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1320 MCSymbol *GVSym = GetARMGVSymbol(GV);
1321 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1323 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1324 getFunctionNumber(),
1325 MI->getOperand(3).getImm(), OutContext);
1326 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1327 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1328 const MCExpr *PCRelExpr =
1329 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1330 MCBinaryExpr::CreateAdd(LabelSymExpr,
1331 MCConstantExpr::Create(PCAdj, OutContext),
1332 OutContext), OutContext), OutContext);
1333 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1335 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1336 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1338 // Add predicate operands.
1339 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1340 TmpInst.addOperand(MCOperand::CreateReg(0));
1341 // Add 's' bit operand (always reg0 for this)
1342 TmpInst.addOperand(MCOperand::CreateReg(0));
1343 OutStreamer.EmitInstruction(TmpInst);
1346 case ARM::tPICADD: {
1347 // This is a pseudo op for a label + instruction sequence, which looks like:
1350 // This adds the address of LPC0 to r0.
1353 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1354 getFunctionNumber(), MI->getOperand(2).getImm(),
1357 // Form and emit the add.
1359 AddInst.setOpcode(ARM::tADDhirr);
1360 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1361 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1362 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1363 // Add predicate operands.
1364 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1365 AddInst.addOperand(MCOperand::CreateReg(0));
1366 OutStreamer.EmitInstruction(AddInst);
1370 // This is a pseudo op for a label + instruction sequence, which looks like:
1373 // This adds the address of LPC0 to r0.
1376 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1377 getFunctionNumber(), MI->getOperand(2).getImm(),
1380 // Form and emit the add.
1382 AddInst.setOpcode(ARM::ADDrr);
1383 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1384 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1385 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1386 // Add predicate operands.
1387 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1388 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1389 // Add 's' bit operand (always reg0 for this)
1390 AddInst.addOperand(MCOperand::CreateReg(0));
1391 OutStreamer.EmitInstruction(AddInst);
1401 case ARM::PICLDRSH: {
1402 // This is a pseudo op for a label + instruction sequence, which looks like:
1405 // The LCP0 label is referenced by a constant pool entry in order to get
1406 // a PC-relative address at the ldr instruction.
1409 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1410 getFunctionNumber(), MI->getOperand(2).getImm(),
1413 // Form and emit the load
1415 switch (MI->getOpcode()) {
1417 llvm_unreachable("Unexpected opcode!");
1418 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1419 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1420 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1421 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1422 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1423 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1424 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1425 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1428 LdStInst.setOpcode(Opcode);
1429 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1430 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1431 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1432 LdStInst.addOperand(MCOperand::CreateImm(0));
1433 // Add predicate operands.
1434 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1435 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1436 OutStreamer.EmitInstruction(LdStInst);
1440 case ARM::CONSTPOOL_ENTRY: {
1441 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1442 /// in the function. The first operand is the ID# for this instruction, the
1443 /// second is the index into the MachineConstantPool that this is, the third
1444 /// is the size in bytes of this constant pool entry.
1445 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1446 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1449 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1451 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1452 if (MCPE.isMachineConstantPoolEntry())
1453 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1455 EmitGlobalConstant(MCPE.Val.ConstVal);
1459 case ARM::t2BR_JT: {
1460 // Lower and emit the instruction itself, then the jump table following it.
1462 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1463 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1464 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1465 // Add predicate operands.
1466 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1467 TmpInst.addOperand(MCOperand::CreateReg(0));
1468 OutStreamer.EmitInstruction(TmpInst);
1469 // Output the data for the jump table itself
1473 case ARM::t2TBB_JT: {
1474 // Lower and emit the instruction itself, then the jump table following it.
1477 TmpInst.setOpcode(ARM::t2TBB);
1478 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1479 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1480 // Add predicate operands.
1481 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1482 TmpInst.addOperand(MCOperand::CreateReg(0));
1483 OutStreamer.EmitInstruction(TmpInst);
1484 // Output the data for the jump table itself
1486 // Make sure the next instruction is 2-byte aligned.
1490 case ARM::t2TBH_JT: {
1491 // Lower and emit the instruction itself, then the jump table following it.
1494 TmpInst.setOpcode(ARM::t2TBH);
1495 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1496 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1497 // Add predicate operands.
1498 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1499 TmpInst.addOperand(MCOperand::CreateReg(0));
1500 OutStreamer.EmitInstruction(TmpInst);
1501 // Output the data for the jump table itself
1507 // Lower and emit the instruction itself, then the jump table following it.
1510 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1511 ARM::MOVr : ARM::tMOVgpr2gpr;
1512 TmpInst.setOpcode(Opc);
1513 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1514 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1515 // Add predicate operands.
1516 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1517 TmpInst.addOperand(MCOperand::CreateReg(0));
1518 // Add 's' bit operand (always reg0 for this)
1519 if (Opc == ARM::MOVr)
1520 TmpInst.addOperand(MCOperand::CreateReg(0));
1521 OutStreamer.EmitInstruction(TmpInst);
1523 // Make sure the Thumb jump table is 4-byte aligned.
1524 if (Opc == ARM::tMOVgpr2gpr)
1527 // Output the data for the jump table itself
1532 // Lower and emit the instruction itself, then the jump table following it.
1535 if (MI->getOperand(1).getReg() == 0) {
1537 TmpInst.setOpcode(ARM::LDRi12);
1538 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1539 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1540 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1542 TmpInst.setOpcode(ARM::LDRrs);
1543 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1544 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1545 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1546 TmpInst.addOperand(MCOperand::CreateImm(0));
1548 // Add predicate operands.
1549 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1550 TmpInst.addOperand(MCOperand::CreateReg(0));
1551 OutStreamer.EmitInstruction(TmpInst);
1553 // Output the data for the jump table itself
1557 case ARM::BR_JTadd: {
1558 // Lower and emit the instruction itself, then the jump table following it.
1559 // add pc, target, idx
1561 TmpInst.setOpcode(ARM::ADDrr);
1562 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1563 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1564 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1565 // Add predicate operands.
1566 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1567 TmpInst.addOperand(MCOperand::CreateReg(0));
1568 // Add 's' bit operand (always reg0 for this)
1569 TmpInst.addOperand(MCOperand::CreateReg(0));
1570 OutStreamer.EmitInstruction(TmpInst);
1572 // Output the data for the jump table itself
1577 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1578 // FIXME: Remove this special case when they do.
1579 if (!Subtarget->isTargetDarwin()) {
1580 //.long 0xe7ffdefe @ trap
1581 uint32_t Val = 0xe7ffdefeUL;
1582 OutStreamer.AddComment("trap");
1583 OutStreamer.EmitIntValue(Val, 4);
1589 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1590 // FIXME: Remove this special case when they do.
1591 if (!Subtarget->isTargetDarwin()) {
1592 //.short 57086 @ trap
1593 uint16_t Val = 0xdefe;
1594 OutStreamer.AddComment("trap");
1595 OutStreamer.EmitIntValue(Val, 2);
1600 case ARM::t2Int_eh_sjlj_setjmp:
1601 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1602 case ARM::tInt_eh_sjlj_setjmp: {
1603 // Two incoming args: GPR:$src, GPR:$val
1606 // str $val, [$src, #4]
1611 unsigned SrcReg = MI->getOperand(0).getReg();
1612 unsigned ValReg = MI->getOperand(1).getReg();
1613 MCSymbol *Label = GetARMSJLJEHLabel();
1616 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1617 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1618 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1620 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1621 OutStreamer.AddComment("eh_setjmp begin");
1622 OutStreamer.EmitInstruction(TmpInst);
1626 TmpInst.setOpcode(ARM::tADDi3);
1627 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1629 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1630 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1631 TmpInst.addOperand(MCOperand::CreateImm(7));
1633 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1634 TmpInst.addOperand(MCOperand::CreateReg(0));
1635 OutStreamer.EmitInstruction(TmpInst);
1639 TmpInst.setOpcode(ARM::tSTRi);
1640 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1641 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1642 // The offset immediate is #4. The operand value is scaled by 4 for the
1643 // tSTR instruction.
1644 TmpInst.addOperand(MCOperand::CreateImm(1));
1646 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1647 TmpInst.addOperand(MCOperand::CreateReg(0));
1648 OutStreamer.EmitInstruction(TmpInst);
1652 TmpInst.setOpcode(ARM::tMOVi8);
1653 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1654 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1655 TmpInst.addOperand(MCOperand::CreateImm(0));
1657 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1658 TmpInst.addOperand(MCOperand::CreateReg(0));
1659 OutStreamer.EmitInstruction(TmpInst);
1662 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1664 TmpInst.setOpcode(ARM::tB);
1665 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1666 OutStreamer.EmitInstruction(TmpInst);
1670 TmpInst.setOpcode(ARM::tMOVi8);
1671 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1672 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1673 TmpInst.addOperand(MCOperand::CreateImm(1));
1675 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1676 TmpInst.addOperand(MCOperand::CreateReg(0));
1677 OutStreamer.AddComment("eh_setjmp end");
1678 OutStreamer.EmitInstruction(TmpInst);
1680 OutStreamer.EmitLabel(Label);
1684 case ARM::Int_eh_sjlj_setjmp_nofp:
1685 case ARM::Int_eh_sjlj_setjmp: {
1686 // Two incoming args: GPR:$src, GPR:$val
1688 // str $val, [$src, #+4]
1692 unsigned SrcReg = MI->getOperand(0).getReg();
1693 unsigned ValReg = MI->getOperand(1).getReg();
1697 TmpInst.setOpcode(ARM::ADDri);
1698 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1699 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1700 TmpInst.addOperand(MCOperand::CreateImm(8));
1702 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1703 TmpInst.addOperand(MCOperand::CreateReg(0));
1704 // 's' bit operand (always reg0 for this).
1705 TmpInst.addOperand(MCOperand::CreateReg(0));
1706 OutStreamer.AddComment("eh_setjmp begin");
1707 OutStreamer.EmitInstruction(TmpInst);
1711 TmpInst.setOpcode(ARM::STRi12);
1712 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1713 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1714 TmpInst.addOperand(MCOperand::CreateImm(4));
1716 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1717 TmpInst.addOperand(MCOperand::CreateReg(0));
1718 OutStreamer.EmitInstruction(TmpInst);
1722 TmpInst.setOpcode(ARM::MOVi);
1723 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1724 TmpInst.addOperand(MCOperand::CreateImm(0));
1726 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1727 TmpInst.addOperand(MCOperand::CreateReg(0));
1728 // 's' bit operand (always reg0 for this).
1729 TmpInst.addOperand(MCOperand::CreateReg(0));
1730 OutStreamer.EmitInstruction(TmpInst);
1734 TmpInst.setOpcode(ARM::ADDri);
1735 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1736 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1737 TmpInst.addOperand(MCOperand::CreateImm(0));
1739 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1740 TmpInst.addOperand(MCOperand::CreateReg(0));
1741 // 's' bit operand (always reg0 for this).
1742 TmpInst.addOperand(MCOperand::CreateReg(0));
1743 OutStreamer.EmitInstruction(TmpInst);
1747 TmpInst.setOpcode(ARM::MOVi);
1748 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1749 TmpInst.addOperand(MCOperand::CreateImm(1));
1751 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1752 TmpInst.addOperand(MCOperand::CreateReg(0));
1753 // 's' bit operand (always reg0 for this).
1754 TmpInst.addOperand(MCOperand::CreateReg(0));
1755 OutStreamer.AddComment("eh_setjmp end");
1756 OutStreamer.EmitInstruction(TmpInst);
1760 case ARM::Int_eh_sjlj_longjmp: {
1761 // ldr sp, [$src, #8]
1762 // ldr $scratch, [$src, #4]
1765 unsigned SrcReg = MI->getOperand(0).getReg();
1766 unsigned ScratchReg = MI->getOperand(1).getReg();
1769 TmpInst.setOpcode(ARM::LDRi12);
1770 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1771 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1772 TmpInst.addOperand(MCOperand::CreateImm(8));
1774 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1775 TmpInst.addOperand(MCOperand::CreateReg(0));
1776 OutStreamer.EmitInstruction(TmpInst);
1780 TmpInst.setOpcode(ARM::LDRi12);
1781 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1782 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1783 TmpInst.addOperand(MCOperand::CreateImm(4));
1785 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1786 TmpInst.addOperand(MCOperand::CreateReg(0));
1787 OutStreamer.EmitInstruction(TmpInst);
1791 TmpInst.setOpcode(ARM::LDRi12);
1792 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1793 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1794 TmpInst.addOperand(MCOperand::CreateImm(0));
1796 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1797 TmpInst.addOperand(MCOperand::CreateReg(0));
1798 OutStreamer.EmitInstruction(TmpInst);
1802 TmpInst.setOpcode(ARM::BX);
1803 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1805 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1806 TmpInst.addOperand(MCOperand::CreateReg(0));
1807 OutStreamer.EmitInstruction(TmpInst);
1811 case ARM::tInt_eh_sjlj_longjmp: {
1812 // ldr $scratch, [$src, #8]
1814 // ldr $scratch, [$src, #4]
1817 unsigned SrcReg = MI->getOperand(0).getReg();
1818 unsigned ScratchReg = MI->getOperand(1).getReg();
1821 TmpInst.setOpcode(ARM::tLDRi);
1822 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1823 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1824 // The offset immediate is #8. The operand value is scaled by 4 for the
1825 // tLDR instruction.
1826 TmpInst.addOperand(MCOperand::CreateImm(2));
1828 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1829 TmpInst.addOperand(MCOperand::CreateReg(0));
1830 OutStreamer.EmitInstruction(TmpInst);
1834 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1835 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1836 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1838 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1839 TmpInst.addOperand(MCOperand::CreateReg(0));
1840 OutStreamer.EmitInstruction(TmpInst);
1844 TmpInst.setOpcode(ARM::tLDRi);
1845 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1846 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1847 TmpInst.addOperand(MCOperand::CreateImm(1));
1849 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1850 TmpInst.addOperand(MCOperand::CreateReg(0));
1851 OutStreamer.EmitInstruction(TmpInst);
1855 TmpInst.setOpcode(ARM::tLDRr);
1856 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1857 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1858 TmpInst.addOperand(MCOperand::CreateReg(0));
1860 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1861 TmpInst.addOperand(MCOperand::CreateReg(0));
1862 OutStreamer.EmitInstruction(TmpInst);
1866 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1867 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1869 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1870 TmpInst.addOperand(MCOperand::CreateReg(0));
1871 OutStreamer.EmitInstruction(TmpInst);
1875 // Tail jump branches are really just branch instructions with additional
1876 // code-gen attributes. Convert them to the canonical form here.
1878 case ARM::TAILJMPdND: {
1879 MCInst TmpInst, TmpInst2;
1880 // Lower the instruction as-is to get the operands properly converted.
1881 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1882 TmpInst.setOpcode(ARM::Bcc);
1883 TmpInst.addOperand(TmpInst2.getOperand(0));
1884 // Add predicate operands.
1885 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1886 TmpInst.addOperand(MCOperand::CreateReg(0));
1887 OutStreamer.AddComment("TAILCALL");
1888 OutStreamer.EmitInstruction(TmpInst);
1891 case ARM::tTAILJMPd:
1892 case ARM::tTAILJMPdND: {
1893 MCInst TmpInst, TmpInst2;
1894 LowerARMMachineInstrToMCInst(MI, TmpInst2, *this);
1895 // The Darwin toolchain doesn't support tail call relocations of 16-bit
1897 TmpInst.setOpcode(Opc == ARM::tTAILJMPd ? ARM::t2B : ARM::tB);
1898 TmpInst.addOperand(TmpInst2.getOperand(0));
1899 OutStreamer.AddComment("TAILCALL");
1900 OutStreamer.EmitInstruction(TmpInst);
1903 case ARM::TAILJMPrND:
1904 case ARM::tTAILJMPrND:
1906 case ARM::tTAILJMPr: {
1907 unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
1908 ? ARM::BX : ARM::tBX;
1910 TmpInst.setOpcode(newOpc);
1911 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1913 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1914 TmpInst.addOperand(MCOperand::CreateReg(0));
1915 OutStreamer.AddComment("TAILCALL");
1916 OutStreamer.EmitInstruction(TmpInst);
1920 // These are the pseudos created to comply with stricter operand restrictions
1921 // on ARMv5. Lower them now to "normal" instructions, since all the
1922 // restrictions are already satisfied.
1924 EmitPatchedInstruction(MI, ARM::MUL);
1927 EmitPatchedInstruction(MI, ARM::MLA);
1930 EmitPatchedInstruction(MI, ARM::SMULL);
1933 EmitPatchedInstruction(MI, ARM::UMULL);
1936 EmitPatchedInstruction(MI, ARM::SMLAL);
1939 EmitPatchedInstruction(MI, ARM::UMLAL);
1942 EmitPatchedInstruction(MI, ARM::UMAAL);
1947 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1949 // Emit unwinding stuff for frame-related instructions
1950 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1951 EmitUnwindingInstruction(MI);
1953 OutStreamer.EmitInstruction(TmpInst);
1956 //===----------------------------------------------------------------------===//
1957 // Target Registry Stuff
1958 //===----------------------------------------------------------------------===//
1960 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1962 unsigned SyntaxVariant,
1963 const MCAsmInfo &MAI) {
1964 if (SyntaxVariant == 0)
1965 return new ARMInstPrinter(TM, MAI);
1969 // Force static initialization.
1970 extern "C" void LLVMInitializeARMAsmPrinter() {
1971 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1972 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1974 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1975 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);