1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
57 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
58 cl::desc("enable experimental asmprinter gunk in the arm backend"));
70 class ARMAsmPrinter : public AsmPrinter {
72 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
73 /// make the right decision when printing asm code for different targets.
74 const ARMSubtarget *Subtarget;
76 /// AFI - Keep a pointer to ARMFunctionInfo for the current
80 /// MCP - Keep a pointer to constantpool entries of the current
82 const MachineConstantPool *MCP;
85 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
86 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
87 Subtarget = &TM.getSubtarget<ARMSubtarget>();
90 virtual const char *getPassName() const {
91 return "ARM Assembly Printer";
94 void printInstructionThroughMCStreamer(const MachineInstr *MI);
97 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
98 const char *Modifier = 0);
99 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
100 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
102 void printSORegOperand(const MachineInstr *MI, int OpNum,
104 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
106 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
108 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
110 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
112 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
113 const char *Modifier = 0);
114 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
115 const char *Modifier = 0);
116 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
118 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
120 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
122 const char *Modifier = 0);
123 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
125 void printMemBOption(const MachineInstr *MI, int OpNum,
127 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
130 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
132 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
133 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
135 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
138 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
140 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
142 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
147 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
148 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
150 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
152 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
154 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
156 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
158 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
161 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
163 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
165 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
167 void printPredicateOperand(const MachineInstr *MI, int OpNum,
169 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
171 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
173 void printPCLabel(const MachineInstr *MI, int OpNum,
175 void printRegisterList(const MachineInstr *MI, int OpNum,
177 void printCPInstOperand(const MachineInstr *MI, int OpNum,
179 const char *Modifier);
180 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
182 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
184 void printTBAddrMode(const MachineInstr *MI, int OpNum,
186 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
188 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
190 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
192 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
195 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
196 unsigned AsmVariant, const char *ExtraCode,
198 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
200 const char *ExtraCode, raw_ostream &O);
202 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
203 static const char *getRegisterName(unsigned RegNo);
205 virtual void EmitInstruction(const MachineInstr *MI);
206 bool runOnMachineFunction(MachineFunction &F);
208 virtual void EmitConstantPool() {} // we emit constant pools customly!
209 virtual void EmitFunctionEntryLabel();
210 void EmitStartOfAsmFile(Module &M);
211 void EmitEndOfAsmFile(Module &M);
213 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 virtual unsigned getISAEncoding() {
226 // ARM/Darwin adds ISA to the DWARF info for each function.
227 if (!Subtarget->isTargetDarwin())
229 return Subtarget->isThumb() ?
230 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
233 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
234 const MachineBasicBlock *MBB) const;
235 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
237 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
239 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
240 SmallString<128> Str;
241 raw_svector_ostream OS(Str);
242 EmitMachineConstantPoolValue(MCPV, OS);
243 OutStreamer.EmitRawText(OS.str());
246 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
248 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
249 case 1: O << MAI->getData8bitsDirective(0); break;
250 case 2: O << MAI->getData16bitsDirective(0); break;
251 case 4: O << MAI->getData32bitsDirective(0); break;
252 default: assert(0 && "Unknown CPV size");
255 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
257 if (ACPV->isLSDA()) {
258 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
259 } else if (ACPV->isBlockAddress()) {
260 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
261 } else if (ACPV->isGlobalValue()) {
262 const GlobalValue *GV = ACPV->getGV();
263 bool isIndirect = Subtarget->isTargetDarwin() &&
264 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
266 O << *Mang->getSymbol(GV);
268 // FIXME: Remove this when Darwin transition to @GOT like syntax.
269 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
272 MachineModuleInfoMachO &MMIMachO =
273 MMI->getObjFileInfo<MachineModuleInfoMachO>();
274 MachineModuleInfoImpl::StubValueTy &StubSym =
275 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
276 MMIMachO.getGVStubEntry(Sym);
277 if (StubSym.getPointer() == 0)
278 StubSym = MachineModuleInfoImpl::
279 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
282 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
283 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
286 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
287 if (ACPV->getPCAdjustment() != 0) {
288 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
289 << getFunctionNumber() << "_" << ACPV->getLabelId()
290 << "+" << (unsigned)ACPV->getPCAdjustment();
291 if (ACPV->mustAddCurrentAddress())
297 } // end of anonymous namespace
299 #include "ARMGenAsmWriter.inc"
301 void ARMAsmPrinter::EmitFunctionEntryLabel() {
302 if (AFI->isThumbFunction()) {
303 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
304 if (!Subtarget->isTargetDarwin())
305 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
307 // This needs to emit to a temporary string to get properly quoted
308 // MCSymbols when they have spaces in them.
309 SmallString<128> Tmp;
310 raw_svector_ostream OS(Tmp);
311 OS << "\t.thumb_func\t" << *CurrentFnSym;
312 OutStreamer.EmitRawText(OS.str());
316 OutStreamer.EmitLabel(CurrentFnSym);
319 /// runOnMachineFunction - This uses the printInstruction()
320 /// method to print assembly for each instruction.
322 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
323 AFI = MF.getInfo<ARMFunctionInfo>();
324 MCP = MF.getConstantPool();
326 return AsmPrinter::runOnMachineFunction(MF);
329 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
330 raw_ostream &O, const char *Modifier) {
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 unsigned TF = MO.getTargetFlags();
334 switch (MO.getType()) {
336 assert(0 && "<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 if (Modifier && strcmp(Modifier, "lane") == 0) {
341 unsigned RegNum = getARMRegisterNumbering(Reg);
343 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
344 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
345 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
347 assert(!MO.getSubReg() && "Subregs should be eliminated!");
348 O << getRegisterName(Reg);
352 case MachineOperand::MO_Immediate: {
353 int64_t Imm = MO.getImm();
355 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
356 (TF & ARMII::MO_LO16))
358 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
359 (TF & ARMII::MO_HI16))
364 case MachineOperand::MO_MachineBasicBlock:
365 O << *MO.getMBB()->getSymbol();
367 case MachineOperand::MO_GlobalAddress: {
368 bool isCallOp = Modifier && !strcmp(Modifier, "call");
369 const GlobalValue *GV = MO.getGlobal();
371 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
372 (TF & ARMII::MO_LO16))
374 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
375 (TF & ARMII::MO_HI16))
377 O << *Mang->getSymbol(GV);
379 printOffset(MO.getOffset(), O);
381 if (isCallOp && Subtarget->isTargetELF() &&
382 TM.getRelocationModel() == Reloc::PIC_)
386 case MachineOperand::MO_ExternalSymbol: {
387 bool isCallOp = Modifier && !strcmp(Modifier, "call");
388 O << *GetExternalSymbolSymbol(MO.getSymbolName());
390 if (isCallOp && Subtarget->isTargetELF() &&
391 TM.getRelocationModel() == Reloc::PIC_)
395 case MachineOperand::MO_ConstantPoolIndex:
396 O << *GetCPISymbol(MO.getIndex());
398 case MachineOperand::MO_JumpTableIndex:
399 O << *GetJTISymbol(MO.getIndex());
404 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
405 const MCAsmInfo *MAI) {
406 // Break it up into two parts that make up a shifter immediate.
407 V = ARM_AM::getSOImmVal(V);
408 assert(V != -1 && "Not a valid so_imm value!");
410 unsigned Imm = ARM_AM::getSOImmValImm(V);
411 unsigned Rot = ARM_AM::getSOImmValRot(V);
413 // Print low-level immediate formation info, per
414 // A5.1.3: "Data-processing operands - Immediate".
416 O << "#" << Imm << ", " << Rot;
417 // Pretty printed version.
419 O << "\t" << MAI->getCommentString() << ' ';
420 O << (int)ARM_AM::rotr32(Imm, Rot);
427 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
428 /// immediate in bits 0-7.
429 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
431 const MachineOperand &MO = MI->getOperand(OpNum);
432 assert(MO.isImm() && "Not a valid so_imm value!");
433 printSOImm(O, MO.getImm(), isVerbose(), MAI);
436 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
437 /// followed by an 'orr' to materialize.
438 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
440 const MachineOperand &MO = MI->getOperand(OpNum);
441 assert(MO.isImm() && "Not a valid so_imm value!");
442 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
443 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
444 printSOImm(O, V1, isVerbose(), MAI);
446 printPredicateOperand(MI, 2, O);
448 printOperand(MI, 0, O);
450 printOperand(MI, 0, O);
452 printSOImm(O, V2, isVerbose(), MAI);
455 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
456 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
458 // REG REG 0,SH_OPC - e.g. R5, ROR R3
459 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
460 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
462 const MachineOperand &MO1 = MI->getOperand(Op);
463 const MachineOperand &MO2 = MI->getOperand(Op+1);
464 const MachineOperand &MO3 = MI->getOperand(Op+2);
466 O << getRegisterName(MO1.getReg());
468 // Print the shift opc.
469 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
470 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
472 O << ' ' << getRegisterName(MO2.getReg());
473 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
474 } else if (ShOpc != ARM_AM::rrx) {
475 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
479 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
481 const MachineOperand &MO1 = MI->getOperand(Op);
482 const MachineOperand &MO2 = MI->getOperand(Op+1);
483 const MachineOperand &MO3 = MI->getOperand(Op+2);
485 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
486 printOperand(MI, Op, O);
490 O << "[" << getRegisterName(MO1.getReg());
493 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
495 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
496 << ARM_AM::getAM2Offset(MO3.getImm());
502 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
503 << getRegisterName(MO2.getReg());
505 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
507 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
512 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
514 const MachineOperand &MO1 = MI->getOperand(Op);
515 const MachineOperand &MO2 = MI->getOperand(Op+1);
518 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
520 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
525 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
526 << getRegisterName(MO1.getReg());
528 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
530 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
534 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
536 const MachineOperand &MO1 = MI->getOperand(Op);
537 const MachineOperand &MO2 = MI->getOperand(Op+1);
538 const MachineOperand &MO3 = MI->getOperand(Op+2);
540 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
541 O << "[" << getRegisterName(MO1.getReg());
545 << (char)ARM_AM::getAM3Op(MO3.getImm())
546 << getRegisterName(MO2.getReg())
551 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
553 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
558 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
560 const MachineOperand &MO1 = MI->getOperand(Op);
561 const MachineOperand &MO2 = MI->getOperand(Op+1);
564 O << (char)ARM_AM::getAM3Op(MO2.getImm())
565 << getRegisterName(MO1.getReg());
569 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
571 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
575 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
577 const char *Modifier) {
578 const MachineOperand &MO2 = MI->getOperand(Op+1);
579 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
580 if (Modifier && strcmp(Modifier, "submode") == 0) {
581 O << ARM_AM::getAMSubModeStr(Mode);
582 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
583 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
584 if (Mode == ARM_AM::ia)
587 printOperand(MI, Op, O);
591 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
593 const char *Modifier) {
594 const MachineOperand &MO1 = MI->getOperand(Op);
595 const MachineOperand &MO2 = MI->getOperand(Op+1);
597 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
598 printOperand(MI, Op, O);
602 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
604 O << "[" << getRegisterName(MO1.getReg());
606 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
608 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
614 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
616 const MachineOperand &MO1 = MI->getOperand(Op);
617 const MachineOperand &MO2 = MI->getOperand(Op+1);
619 O << "[" << getRegisterName(MO1.getReg());
621 // FIXME: Both darwin as and GNU as violate ARM docs here.
622 O << ", :" << (MO2.getImm() << 3);
627 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
629 const MachineOperand &MO = MI->getOperand(Op);
630 if (MO.getReg() == 0)
633 O << ", " << getRegisterName(MO.getReg());
636 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
638 const char *Modifier) {
639 if (Modifier && strcmp(Modifier, "label") == 0) {
640 printPCLabel(MI, Op+1, O);
644 const MachineOperand &MO1 = MI->getOperand(Op);
645 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
646 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
650 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
652 const MachineOperand &MO = MI->getOperand(Op);
653 uint32_t v = ~MO.getImm();
654 int32_t lsb = CountTrailingZeros_32(v);
655 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
656 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
657 O << "#" << lsb << ", #" << width;
661 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
663 unsigned val = MI->getOperand(OpNum).getImm();
664 O << ARM_MB::MemBOptToString(val);
667 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
669 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
670 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
672 case ARM_AM::no_shift:
681 assert(0 && "unexpected shift opcode for shift immediate operand");
683 O << ARM_AM::getSORegOffset(ShiftOp);
686 //===--------------------------------------------------------------------===//
688 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
690 O << "#" << MI->getOperand(Op).getImm() * 4;
694 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
696 // (3 - the number of trailing zeros) is the number of then / else.
697 unsigned Mask = MI->getOperand(Op).getImm();
698 unsigned CondBit0 = Mask >> 4 & 1;
699 unsigned NumTZ = CountTrailingZeros_32(Mask);
700 assert(NumTZ <= 3 && "Invalid IT mask!");
701 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
702 bool T = ((Mask >> Pos) & 1) == CondBit0;
711 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
713 const MachineOperand &MO1 = MI->getOperand(Op);
714 const MachineOperand &MO2 = MI->getOperand(Op+1);
715 O << "[" << getRegisterName(MO1.getReg());
716 O << ", " << getRegisterName(MO2.getReg()) << "]";
720 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
723 const MachineOperand &MO1 = MI->getOperand(Op);
724 const MachineOperand &MO2 = MI->getOperand(Op+1);
725 const MachineOperand &MO3 = MI->getOperand(Op+2);
727 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
728 printOperand(MI, Op, O);
732 O << "[" << getRegisterName(MO1.getReg());
734 O << ", " << getRegisterName(MO3.getReg());
735 else if (unsigned ImmOffs = MO2.getImm())
736 O << ", #" << ImmOffs * Scale;
741 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
743 printThumbAddrModeRI5Operand(MI, Op, O, 1);
746 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
748 printThumbAddrModeRI5Operand(MI, Op, O, 2);
751 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
753 printThumbAddrModeRI5Operand(MI, Op, O, 4);
756 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
758 const MachineOperand &MO1 = MI->getOperand(Op);
759 const MachineOperand &MO2 = MI->getOperand(Op+1);
760 O << "[" << getRegisterName(MO1.getReg());
761 if (unsigned ImmOffs = MO2.getImm())
762 O << ", #" << ImmOffs*4;
766 //===--------------------------------------------------------------------===//
768 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
769 // register with shift forms.
771 // REG IMM, SH_OPC - e.g. R5, LSL #3
772 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
774 const MachineOperand &MO1 = MI->getOperand(OpNum);
775 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
777 unsigned Reg = MO1.getReg();
778 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
779 O << getRegisterName(Reg);
781 // Print the shift opc.
782 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
783 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
784 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
785 if (ShOpc != ARM_AM::rrx)
786 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
789 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
792 const MachineOperand &MO1 = MI->getOperand(OpNum);
793 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
795 O << "[" << getRegisterName(MO1.getReg());
797 unsigned OffImm = MO2.getImm();
798 if (OffImm) // Don't print +0.
799 O << ", #" << OffImm;
803 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
806 const MachineOperand &MO1 = MI->getOperand(OpNum);
807 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
809 O << "[" << getRegisterName(MO1.getReg());
811 int32_t OffImm = (int32_t)MO2.getImm();
814 O << ", #-" << -OffImm;
816 O << ", #" << OffImm;
820 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
823 const MachineOperand &MO1 = MI->getOperand(OpNum);
824 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
826 O << "[" << getRegisterName(MO1.getReg());
828 int32_t OffImm = (int32_t)MO2.getImm() / 4;
831 O << ", #-" << -OffImm * 4;
833 O << ", #" << OffImm * 4;
837 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
840 const MachineOperand &MO1 = MI->getOperand(OpNum);
841 int32_t OffImm = (int32_t)MO1.getImm();
844 O << "#-" << -OffImm;
849 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
852 const MachineOperand &MO1 = MI->getOperand(OpNum);
853 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
854 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
856 O << "[" << getRegisterName(MO1.getReg());
858 assert(MO2.getReg() && "Invalid so_reg load / store address!");
859 O << ", " << getRegisterName(MO2.getReg());
861 unsigned ShAmt = MO3.getImm();
863 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
864 O << ", lsl #" << ShAmt;
870 //===--------------------------------------------------------------------===//
872 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
874 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
876 O << ARMCondCodeToString(CC);
879 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
882 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
883 O << ARMCondCodeToString(CC);
886 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
888 unsigned Reg = MI->getOperand(OpNum).getReg();
890 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
895 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
897 int Id = (int)MI->getOperand(OpNum).getImm();
898 O << MAI->getPrivateGlobalPrefix()
899 << "PC" << getFunctionNumber() << "_" << Id;
902 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
905 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
906 if (MI->getOperand(i).isImplicit())
908 if ((int)i != OpNum) O << ", ";
909 printOperand(MI, i, O);
914 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
915 raw_ostream &O, const char *Modifier) {
916 assert(Modifier && "This operand only works with a modifier!");
917 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
919 if (!strcmp(Modifier, "label")) {
920 unsigned ID = MI->getOperand(OpNum).getImm();
921 OutStreamer.EmitLabel(GetCPISymbol(ID));
923 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
924 unsigned CPI = MI->getOperand(OpNum).getIndex();
926 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
928 if (MCPE.isMachineConstantPoolEntry()) {
929 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
931 EmitGlobalConstant(MCPE.Val.ConstVal);
936 MCSymbol *ARMAsmPrinter::
937 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
938 const MachineBasicBlock *MBB) const {
939 SmallString<60> Name;
940 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
941 << getFunctionNumber() << '_' << uid << '_' << uid2
942 << "_set_" << MBB->getNumber();
943 return OutContext.GetOrCreateSymbol(Name.str());
946 MCSymbol *ARMAsmPrinter::
947 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
948 SmallString<60> Name;
949 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
950 << getFunctionNumber() << '_' << uid << '_' << uid2;
951 return OutContext.GetOrCreateSymbol(Name.str());
954 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
956 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
958 const MachineOperand &MO1 = MI->getOperand(OpNum);
959 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
961 unsigned JTI = MO1.getIndex();
962 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
963 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
965 O << "\n" << *JTISymbol << ":\n";
967 const char *JTEntryDirective = MAI->getData32bitsDirective();
969 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
970 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
971 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
972 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
973 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
974 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
975 MachineBasicBlock *MBB = JTBBs[i];
976 bool isNew = JTSets.insert(MBB);
978 if (UseSet && isNew) {
980 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
981 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
984 O << JTEntryDirective << ' ';
986 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
987 else if (TM.getRelocationModel() == Reloc::PIC_)
988 O << *MBB->getSymbol() << '-' << *JTISymbol;
990 O << *MBB->getSymbol();
997 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
999 const MachineOperand &MO1 = MI->getOperand(OpNum);
1000 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1001 unsigned JTI = MO1.getIndex();
1003 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1005 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
1007 O << "\n" << *JTISymbol << ":\n";
1009 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1010 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1011 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1012 bool ByteOffset = false, HalfWordOffset = false;
1013 if (MI->getOpcode() == ARM::t2TBB)
1015 else if (MI->getOpcode() == ARM::t2TBH)
1016 HalfWordOffset = true;
1018 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1019 MachineBasicBlock *MBB = JTBBs[i];
1021 O << MAI->getData8bitsDirective();
1022 else if (HalfWordOffset)
1023 O << MAI->getData16bitsDirective();
1025 if (ByteOffset || HalfWordOffset)
1026 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1028 O << "\tb.w " << *MBB->getSymbol();
1035 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1037 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1038 if (MI->getOpcode() == ARM::t2TBH)
1043 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1045 O << MI->getOperand(OpNum).getImm();
1048 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1050 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1051 O << '#' << FP->getValueAPF().convertToFloat();
1053 O << "\t\t" << MAI->getCommentString() << ' ';
1054 WriteAsOperand(O, FP, /*PrintType=*/false);
1058 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1060 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1061 O << '#' << FP->getValueAPF().convertToDouble();
1063 O << "\t\t" << MAI->getCommentString() << ' ';
1064 WriteAsOperand(O, FP, /*PrintType=*/false);
1068 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1070 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1072 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1073 O << "#0x" << utohexstr(Val);
1076 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1077 unsigned AsmVariant, const char *ExtraCode,
1079 // Does this asm operand have a single letter operand modifier?
1080 if (ExtraCode && ExtraCode[0]) {
1081 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1083 switch (ExtraCode[0]) {
1084 default: return true; // Unknown modifier.
1085 case 'a': // Print as a memory address.
1086 if (MI->getOperand(OpNum).isReg()) {
1087 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1091 case 'c': // Don't print "#" before an immediate operand.
1092 if (!MI->getOperand(OpNum).isImm())
1094 printNoHashImmediate(MI, OpNum, O);
1096 case 'P': // Print a VFP double precision register.
1097 case 'q': // Print a NEON quad precision register.
1098 printOperand(MI, OpNum, O);
1103 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1108 printOperand(MI, OpNum, O);
1112 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1113 unsigned OpNum, unsigned AsmVariant,
1114 const char *ExtraCode,
1116 if (ExtraCode && ExtraCode[0])
1117 return true; // Unknown modifier.
1119 const MachineOperand &MO = MI->getOperand(OpNum);
1120 assert(MO.isReg() && "unexpected inline asm memory operand");
1121 O << "[" << getRegisterName(MO.getReg()) << "]";
1125 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1127 printInstructionThroughMCStreamer(MI);
1131 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1134 SmallString<128> Str;
1135 raw_svector_ostream OS(Str);
1136 if (MI->getOpcode() == ARM::DBG_VALUE) {
1137 unsigned NOps = MI->getNumOperands();
1139 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1140 // cast away const; DIetc do not take const operands for some reason.
1141 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1144 // Frame address. Currently handles register +- offset only.
1145 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1146 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1149 printOperand(MI, NOps-2, OS);
1150 } else if (MI->getOpcode() == ARM::MOVs) {
1151 // FIXME: Thumb variants?
1152 const MachineOperand &Dst = MI->getOperand(0);
1153 const MachineOperand &MO1 = MI->getOperand(1);
1154 const MachineOperand &MO2 = MI->getOperand(2);
1155 const MachineOperand &MO3 = MI->getOperand(3);
1157 OS << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
1158 printSBitModifierOperand(MI, 6, OS);
1159 printPredicateOperand(MI, 4, OS);
1161 OS << '\t' << getRegisterName(Dst.getReg())
1162 << ", " << getRegisterName(MO1.getReg());
1164 if (ARM_AM::getSORegShOp(MO3.getImm()) != ARM_AM::rrx) {
1168 OS << getRegisterName(MO2.getReg());
1169 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
1171 OS << "#" << ARM_AM::getSORegOffset(MO3.getImm());
1176 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
1177 MI->getOperand(0).getReg() == ARM::SP) {
1178 const MachineOperand &MO1 = MI->getOperand(2);
1179 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
1180 OS << '\t' << "push";
1181 printPredicateOperand(MI, 3, OS);
1183 printRegisterList(MI, 5, OS);
1187 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
1188 MI->getOperand(0).getReg() == ARM::SP) {
1189 const MachineOperand &MO1 = MI->getOperand(2);
1190 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
1191 OS << '\t' << "pop";
1192 printPredicateOperand(MI, 3, OS);
1194 printRegisterList(MI, 5, OS);
1198 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
1199 MI->getOperand(0).getReg() == ARM::SP) {
1200 const MachineOperand &MO1 = MI->getOperand(2);
1201 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
1202 OS << '\t' << "vpush";
1203 printPredicateOperand(MI, 3, OS);
1205 printRegisterList(MI, 5, OS);
1209 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
1210 MI->getOperand(0).getReg() == ARM::SP) {
1211 const MachineOperand &MO1 = MI->getOperand(2);
1212 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
1213 OS << '\t' << "vpop";
1214 printPredicateOperand(MI, 3, OS);
1216 printRegisterList(MI, 5, OS);
1219 printInstruction(MI, OS);
1221 // Output the instruction to the stream
1222 OutStreamer.EmitRawText(OS.str());
1224 // Make sure the instruction that follows TBB is 2-byte aligned.
1225 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1226 if (MI->getOpcode() == ARM::t2TBB)
1230 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1231 if (Subtarget->isTargetDarwin()) {
1232 Reloc::Model RelocM = TM.getRelocationModel();
1233 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1234 // Declare all the text sections up front (before the DWARF sections
1235 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1236 // them together at the beginning of the object file. This helps
1237 // avoid out-of-range branches that are due a fundamental limitation of
1238 // the way symbol offsets are encoded with the current Darwin ARM
1240 const TargetLoweringObjectFileMachO &TLOFMacho =
1241 static_cast<const TargetLoweringObjectFileMachO &>(
1242 getObjFileLowering());
1243 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1244 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1245 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1246 if (RelocM == Reloc::DynamicNoPIC) {
1247 const MCSection *sect =
1248 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1249 MCSectionMachO::S_SYMBOL_STUBS,
1250 12, SectionKind::getText());
1251 OutStreamer.SwitchSection(sect);
1253 const MCSection *sect =
1254 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1255 MCSectionMachO::S_SYMBOL_STUBS,
1256 16, SectionKind::getText());
1257 OutStreamer.SwitchSection(sect);
1259 const MCSection *StaticInitSect =
1260 OutContext.getMachOSection("__TEXT", "__StaticInit",
1261 MCSectionMachO::S_REGULAR |
1262 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1263 SectionKind::getText());
1264 OutStreamer.SwitchSection(StaticInitSect);
1268 // Use unified assembler syntax.
1269 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1271 // Emit ARM Build Attributes
1272 if (Subtarget->isTargetELF()) {
1274 std::string CPUString = Subtarget->getCPUString();
1275 if (CPUString != "generic")
1276 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1278 // FIXME: Emit FPU type
1279 if (Subtarget->hasVFP2())
1280 OutStreamer.EmitRawText("\t.eabi_attribute " +
1281 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1283 // Signal various FP modes.
1284 if (!UnsafeFPMath) {
1285 OutStreamer.EmitRawText("\t.eabi_attribute " +
1286 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1287 OutStreamer.EmitRawText("\t.eabi_attribute " +
1288 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1291 if (NoInfsFPMath && NoNaNsFPMath)
1292 OutStreamer.EmitRawText("\t.eabi_attribute " +
1293 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1295 OutStreamer.EmitRawText("\t.eabi_attribute " +
1296 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1298 // 8-bytes alignment stuff.
1299 OutStreamer.EmitRawText("\t.eabi_attribute " +
1300 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1301 OutStreamer.EmitRawText("\t.eabi_attribute " +
1302 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1304 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1305 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1306 OutStreamer.EmitRawText("\t.eabi_attribute " +
1307 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1308 OutStreamer.EmitRawText("\t.eabi_attribute " +
1309 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1311 // FIXME: Should we signal R9 usage?
1316 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1317 if (Subtarget->isTargetDarwin()) {
1318 // All darwin targets use mach-o.
1319 const TargetLoweringObjectFileMachO &TLOFMacho =
1320 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1321 MachineModuleInfoMachO &MMIMacho =
1322 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1324 // Output non-lazy-pointers for external and common global variables.
1325 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1327 if (!Stubs.empty()) {
1328 // Switch with ".non_lazy_symbol_pointer" directive.
1329 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1331 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1333 OutStreamer.EmitLabel(Stubs[i].first);
1334 // .indirect_symbol _foo
1335 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1336 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1339 // External to current translation unit.
1340 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1342 // Internal to current translation unit.
1344 // When we place the LSDA into the TEXT section, the type info pointers
1345 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1346 // However, sometimes the types are local to the file. So we need to
1347 // fill in the value for the NLP in those cases.
1348 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1350 4/*size*/, 0/*addrspace*/);
1354 OutStreamer.AddBlankLine();
1357 Stubs = MMIMacho.GetHiddenGVStubList();
1358 if (!Stubs.empty()) {
1359 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1361 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1363 OutStreamer.EmitLabel(Stubs[i].first);
1365 OutStreamer.EmitValue(MCSymbolRefExpr::
1366 Create(Stubs[i].second.getPointer(),
1368 4/*size*/, 0/*addrspace*/);
1372 OutStreamer.AddBlankLine();
1375 // Funny Darwin hack: This flag tells the linker that no global symbols
1376 // contain code that falls through to other global symbols (e.g. the obvious
1377 // implementation of multiple entry points). If this doesn't occur, the
1378 // linker can safely perform dead code stripping. Since LLVM never
1379 // generates code that does this, it is always safe to set.
1380 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1384 //===----------------------------------------------------------------------===//
1386 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1387 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1388 switch (MI->getOpcode()) {
1389 case ARM::t2MOVi32imm:
1390 assert(0 && "Should be lowered by thumb2it pass");
1392 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1393 // This is a pseudo op for a label + instruction sequence, which looks like:
1396 // This adds the address of LPC0 to r0.
1399 // FIXME: MOVE TO SHARED PLACE.
1400 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1401 const char *Prefix = MAI->getPrivateGlobalPrefix();
1402 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1403 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1404 OutStreamer.EmitLabel(Label);
1407 // Form and emit the add.
1409 AddInst.setOpcode(ARM::ADDrr);
1410 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1411 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1412 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1413 // Add predicate operands.
1414 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1415 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1416 // Add 's' bit operand (always reg0 for this)
1417 AddInst.addOperand(MCOperand::CreateReg(0));
1418 OutStreamer.EmitInstruction(AddInst);
1428 case ARM::PICLDRSH: {
1429 // This is a pseudo op for a label + instruction sequence, which looks like:
1432 // The LCP0 label is referenced by a constant pool entry in order to get
1433 // a PC-relative address at the ldr instruction.
1436 // FIXME: MOVE TO SHARED PLACE.
1437 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1438 const char *Prefix = MAI->getPrivateGlobalPrefix();
1439 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1440 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1441 OutStreamer.EmitLabel(Label);
1443 // Form and emit the load
1445 switch (MI->getOpcode()) {
1447 llvm_unreachable("Unexpected opcode!");
1448 case ARM::PICSTR: Opcode = ARM::STR; break;
1449 case ARM::PICSTRB: Opcode = ARM::STRB; break;
1450 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1451 case ARM::PICLDR: Opcode = ARM::LDR; break;
1452 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
1453 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1454 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1455 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1458 LdStInst.setOpcode(Opcode);
1459 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1460 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1461 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1462 LdStInst.addOperand(MCOperand::CreateImm(0));
1463 // Add predicate operands.
1464 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1465 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1466 OutStreamer.EmitInstruction(LdStInst);
1470 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1471 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1472 /// in the function. The first operand is the ID# for this instruction, the
1473 /// second is the index into the MachineConstantPool that this is, the third
1474 /// is the size in bytes of this constant pool entry.
1475 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1476 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1479 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1481 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1482 if (MCPE.isMachineConstantPoolEntry())
1483 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1485 EmitGlobalConstant(MCPE.Val.ConstVal);
1489 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1490 // This is a hack that lowers as a two instruction sequence.
1491 unsigned DstReg = MI->getOperand(0).getReg();
1492 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1494 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1495 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1499 TmpInst.setOpcode(ARM::MOVi);
1500 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1501 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1504 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1505 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1507 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1508 OutStreamer.EmitInstruction(TmpInst);
1513 TmpInst.setOpcode(ARM::ORRri);
1514 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1515 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1516 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1518 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1519 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1521 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1522 OutStreamer.EmitInstruction(TmpInst);
1526 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1527 // This is a hack that lowers as a two instruction sequence.
1528 unsigned DstReg = MI->getOperand(0).getReg();
1529 const MachineOperand &MO = MI->getOperand(1);
1532 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1533 V1 = MCOperand::CreateImm(ImmVal & 65535);
1534 V2 = MCOperand::CreateImm(ImmVal >> 16);
1535 } else if (MO.isGlobal()) {
1536 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
1537 const MCSymbolRefExpr *SymRef1 =
1538 MCSymbolRefExpr::Create(Symbol,
1539 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1540 const MCSymbolRefExpr *SymRef2 =
1541 MCSymbolRefExpr::Create(Symbol,
1542 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1543 V1 = MCOperand::CreateExpr(SymRef1);
1544 V2 = MCOperand::CreateExpr(SymRef2);
1547 llvm_unreachable("cannot handle this operand");
1552 TmpInst.setOpcode(ARM::MOVi16);
1553 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1554 TmpInst.addOperand(V1); // lower16(imm)
1557 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1558 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1560 OutStreamer.EmitInstruction(TmpInst);
1565 TmpInst.setOpcode(ARM::MOVTi16);
1566 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1567 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1568 TmpInst.addOperand(V2); // upper16(imm)
1571 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1572 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1574 OutStreamer.EmitInstruction(TmpInst);
1582 MCInstLowering.Lower(MI, TmpInst);
1583 OutStreamer.EmitInstruction(TmpInst);
1586 //===----------------------------------------------------------------------===//
1587 // Target Registry Stuff
1588 //===----------------------------------------------------------------------===//
1590 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1591 unsigned SyntaxVariant,
1592 const MCAsmInfo &MAI) {
1593 if (SyntaxVariant == 0)
1594 return new ARMInstPrinter(MAI);
1598 // Force static initialization.
1599 extern "C" void LLVMInitializeARMAsmPrinter() {
1600 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1601 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1603 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1604 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);