1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMBuildAttrs.h"
20 #include "ARMBaseRegisterInfo.h"
21 #include "ARMConstantPoolValue.h"
22 #include "ARMMachineFunctionInfo.h"
23 #include "ARMMCExpr.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "InstPrinter/ARMInstPrinter.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/Target/TargetRegistry.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/SmallString.h"
51 #include "llvm/ADT/StringExtras.h"
52 #include "llvm/Support/CommandLine.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 MCObjectStreamer &Streamer;
99 StringRef CurrentVendor;
100 SmallString<64> Contents;
103 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
104 Streamer(Streamer_), CurrentVendor("") { }
106 void MaybeSwitchVendor(StringRef Vendor) {
107 assert(!Vendor.empty() && "Vendor cannot be empty.");
109 if (CurrentVendor.empty())
110 CurrentVendor = Vendor;
111 else if (CurrentVendor == Vendor)
116 CurrentVendor = Vendor;
118 assert(Contents.size() == 0);
121 void EmitAttribute(unsigned Attribute, unsigned Value) {
122 // FIXME: should be ULEB
123 Contents += Attribute;
127 void EmitTextAttribute(unsigned Attribute, StringRef String) {
128 Contents += Attribute;
129 Contents += UppercaseString(String);
134 const size_t ContentsSize = Contents.size();
136 // Vendor size + Vendor name + '\0'
137 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
140 const size_t TagHeaderSize = 1 + 4;
142 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
143 Streamer.EmitBytes(CurrentVendor, 0);
144 Streamer.EmitIntValue(0, 1); // '\0'
146 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
147 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
149 Streamer.EmitBytes(Contents, 0);
155 } // end of anonymous namespace
157 MachineLocation ARMAsmPrinter::
158 getDebugValueLocation(const MachineInstr *MI) const {
159 MachineLocation Location;
160 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
161 // Frame address. Currently handles register +- offset only.
162 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
163 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
165 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
170 void ARMAsmPrinter::EmitFunctionEntryLabel() {
171 if (AFI->isThumbFunction()) {
172 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
173 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
176 OutStreamer.EmitLabel(CurrentFnSym);
179 /// runOnMachineFunction - This uses the EmitInstruction()
180 /// method to print assembly for each instruction.
182 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
183 AFI = MF.getInfo<ARMFunctionInfo>();
184 MCP = MF.getConstantPool();
186 return AsmPrinter::runOnMachineFunction(MF);
189 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
190 raw_ostream &O, const char *Modifier) {
191 const MachineOperand &MO = MI->getOperand(OpNum);
192 unsigned TF = MO.getTargetFlags();
194 switch (MO.getType()) {
196 assert(0 && "<unknown operand type>");
197 case MachineOperand::MO_Register: {
198 unsigned Reg = MO.getReg();
199 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
200 assert(!MO.getSubReg() && "Subregs should be eliminated!");
201 O << ARMInstPrinter::getRegisterName(Reg);
204 case MachineOperand::MO_Immediate: {
205 int64_t Imm = MO.getImm();
207 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
208 (TF == ARMII::MO_LO16))
210 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
211 (TF == ARMII::MO_HI16))
216 case MachineOperand::MO_MachineBasicBlock:
217 O << *MO.getMBB()->getSymbol();
219 case MachineOperand::MO_GlobalAddress: {
220 const GlobalValue *GV = MO.getGlobal();
221 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
222 (TF & ARMII::MO_LO16))
224 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
225 (TF & ARMII::MO_HI16))
227 O << *Mang->getSymbol(GV);
229 printOffset(MO.getOffset(), O);
230 if (TF == ARMII::MO_PLT)
234 case MachineOperand::MO_ExternalSymbol: {
235 O << *GetExternalSymbolSymbol(MO.getSymbolName());
236 if (TF == ARMII::MO_PLT)
240 case MachineOperand::MO_ConstantPoolIndex:
241 O << *GetCPISymbol(MO.getIndex());
243 case MachineOperand::MO_JumpTableIndex:
244 O << *GetJTISymbol(MO.getIndex());
249 //===--------------------------------------------------------------------===//
251 MCSymbol *ARMAsmPrinter::
252 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
253 const MachineBasicBlock *MBB) const {
254 SmallString<60> Name;
255 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
256 << getFunctionNumber() << '_' << uid << '_' << uid2
257 << "_set_" << MBB->getNumber();
258 return OutContext.GetOrCreateSymbol(Name.str());
261 MCSymbol *ARMAsmPrinter::
262 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
263 SmallString<60> Name;
264 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
265 << getFunctionNumber() << '_' << uid << '_' << uid2;
266 return OutContext.GetOrCreateSymbol(Name.str());
270 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
271 SmallString<60> Name;
272 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
273 << getFunctionNumber();
274 return OutContext.GetOrCreateSymbol(Name.str());
277 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
278 unsigned AsmVariant, const char *ExtraCode,
280 // Does this asm operand have a single letter operand modifier?
281 if (ExtraCode && ExtraCode[0]) {
282 if (ExtraCode[1] != 0) return true; // Unknown modifier.
284 switch (ExtraCode[0]) {
285 default: return true; // Unknown modifier.
286 case 'a': // Print as a memory address.
287 if (MI->getOperand(OpNum).isReg()) {
289 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
294 case 'c': // Don't print "#" before an immediate operand.
295 if (!MI->getOperand(OpNum).isImm())
297 O << MI->getOperand(OpNum).getImm();
299 case 'P': // Print a VFP double precision register.
300 case 'q': // Print a NEON quad precision register.
301 printOperand(MI, OpNum, O);
306 // These modifiers are not yet supported.
311 printOperand(MI, OpNum, O);
315 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
316 unsigned OpNum, unsigned AsmVariant,
317 const char *ExtraCode,
319 if (ExtraCode && ExtraCode[0])
320 return true; // Unknown modifier.
322 const MachineOperand &MO = MI->getOperand(OpNum);
323 assert(MO.isReg() && "unexpected inline asm memory operand");
324 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
328 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
329 if (Subtarget->isTargetDarwin()) {
330 Reloc::Model RelocM = TM.getRelocationModel();
331 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
332 // Declare all the text sections up front (before the DWARF sections
333 // emitted by AsmPrinter::doInitialization) so the assembler will keep
334 // them together at the beginning of the object file. This helps
335 // avoid out-of-range branches that are due a fundamental limitation of
336 // the way symbol offsets are encoded with the current Darwin ARM
338 const TargetLoweringObjectFileMachO &TLOFMacho =
339 static_cast<const TargetLoweringObjectFileMachO &>(
340 getObjFileLowering());
341 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
342 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
343 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
344 if (RelocM == Reloc::DynamicNoPIC) {
345 const MCSection *sect =
346 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
347 MCSectionMachO::S_SYMBOL_STUBS,
348 12, SectionKind::getText());
349 OutStreamer.SwitchSection(sect);
351 const MCSection *sect =
352 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
353 MCSectionMachO::S_SYMBOL_STUBS,
354 16, SectionKind::getText());
355 OutStreamer.SwitchSection(sect);
357 const MCSection *StaticInitSect =
358 OutContext.getMachOSection("__TEXT", "__StaticInit",
359 MCSectionMachO::S_REGULAR |
360 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
361 SectionKind::getText());
362 OutStreamer.SwitchSection(StaticInitSect);
366 // Use unified assembler syntax.
367 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
369 // Emit ARM Build Attributes
370 if (Subtarget->isTargetELF()) {
377 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
378 if (Subtarget->isTargetDarwin()) {
379 // All darwin targets use mach-o.
380 const TargetLoweringObjectFileMachO &TLOFMacho =
381 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
382 MachineModuleInfoMachO &MMIMacho =
383 MMI->getObjFileInfo<MachineModuleInfoMachO>();
385 // Output non-lazy-pointers for external and common global variables.
386 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
388 if (!Stubs.empty()) {
389 // Switch with ".non_lazy_symbol_pointer" directive.
390 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
392 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
394 OutStreamer.EmitLabel(Stubs[i].first);
395 // .indirect_symbol _foo
396 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
397 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
400 // External to current translation unit.
401 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
403 // Internal to current translation unit.
405 // When we place the LSDA into the TEXT section, the type info
406 // pointers need to be indirect and pc-rel. We accomplish this by
407 // using NLPs; however, sometimes the types are local to the file.
408 // We need to fill in the value for the NLP in those cases.
409 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
411 4/*size*/, 0/*addrspace*/);
415 OutStreamer.AddBlankLine();
418 Stubs = MMIMacho.GetHiddenGVStubList();
419 if (!Stubs.empty()) {
420 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
422 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
424 OutStreamer.EmitLabel(Stubs[i].first);
426 OutStreamer.EmitValue(MCSymbolRefExpr::
427 Create(Stubs[i].second.getPointer(),
429 4/*size*/, 0/*addrspace*/);
433 OutStreamer.AddBlankLine();
436 // Funny Darwin hack: This flag tells the linker that no global symbols
437 // contain code that falls through to other global symbols (e.g. the obvious
438 // implementation of multiple entry points). If this doesn't occur, the
439 // linker can safely perform dead code stripping. Since LLVM never
440 // generates code that does this, it is always safe to set.
441 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
445 //===----------------------------------------------------------------------===//
446 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
448 // The following seem like one-off assembler flags, but they actually need
449 // to appear in the .ARM.attributes section in ELF.
450 // Instead of subclassing the MCELFStreamer, we do the work here.
452 void ARMAsmPrinter::emitAttributes() {
454 emitARMAttributeSection();
456 AttributeEmitter *AttrEmitter;
457 if (OutStreamer.hasRawTextSupport())
458 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
460 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
461 AttrEmitter = new ObjectAttributeEmitter(O);
464 AttrEmitter->MaybeSwitchVendor("aeabi");
466 std::string CPUString = Subtarget->getCPUString();
468 if (CPUString == "cortex-a8" ||
469 Subtarget->isCortexA8()) {
470 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
471 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
472 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
473 ARMBuildAttrs::ApplicationProfile);
474 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
475 ARMBuildAttrs::Allowed);
476 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
477 ARMBuildAttrs::AllowThumb32);
478 // Fixme: figure out when this is emitted.
479 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
480 // ARMBuildAttrs::AllowWMMXv1);
483 /// ADD additional Else-cases here!
484 } else if (CPUString == "generic") {
485 // FIXME: Why these defaults?
486 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
487 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
488 ARMBuildAttrs::Allowed);
489 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
490 ARMBuildAttrs::Allowed);
493 // FIXME: Emit FPU type
494 if (Subtarget->hasVFP2())
495 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
496 ARMBuildAttrs::AllowFPv2);
498 // Signal various FP modes.
500 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
501 ARMBuildAttrs::Allowed);
502 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
503 ARMBuildAttrs::Allowed);
506 if (NoInfsFPMath && NoNaNsFPMath)
507 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
508 ARMBuildAttrs::Allowed);
510 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
511 ARMBuildAttrs::AllowIEE754);
513 // FIXME: add more flags to ARMBuildAttrs.h
514 // 8-bytes alignment stuff.
515 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
516 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
518 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
519 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
520 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
521 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
523 // FIXME: Should we signal R9 usage?
525 if (Subtarget->hasDivide())
526 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
528 AttrEmitter->Finish();
532 void ARMAsmPrinter::emitARMAttributeSection() {
534 // [ <section-length> "vendor-name"
535 // [ <file-tag> <size> <attribute>*
536 // | <section-tag> <size> <section-number>* 0 <attribute>*
537 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
541 if (OutStreamer.hasRawTextSupport())
544 const ARMElfTargetObjectFile &TLOFELF =
545 static_cast<const ARMElfTargetObjectFile &>
546 (getObjFileLowering());
548 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
551 OutStreamer.EmitIntValue(0x41, 1);
554 //===----------------------------------------------------------------------===//
556 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
557 unsigned LabelId, MCContext &Ctx) {
559 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
560 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
564 static MCSymbolRefExpr::VariantKind
565 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
567 default: llvm_unreachable("Unknown modifier!");
568 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
569 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
570 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
571 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
572 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
573 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
575 return MCSymbolRefExpr::VK_None;
578 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
579 bool isIndirect = Subtarget->isTargetDarwin() &&
580 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
582 return Mang->getSymbol(GV);
584 // FIXME: Remove this when Darwin transition to @GOT like syntax.
585 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
586 MachineModuleInfoMachO &MMIMachO =
587 MMI->getObjFileInfo<MachineModuleInfoMachO>();
588 MachineModuleInfoImpl::StubValueTy &StubSym =
589 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
590 MMIMachO.getGVStubEntry(MCSym);
591 if (StubSym.getPointer() == 0)
592 StubSym = MachineModuleInfoImpl::
593 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
598 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
599 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
601 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
604 if (ACPV->isLSDA()) {
605 SmallString<128> Str;
606 raw_svector_ostream OS(Str);
607 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
608 MCSym = OutContext.GetOrCreateSymbol(OS.str());
609 } else if (ACPV->isBlockAddress()) {
610 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
611 } else if (ACPV->isGlobalValue()) {
612 const GlobalValue *GV = ACPV->getGV();
613 MCSym = GetARMGVSymbol(GV);
615 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
616 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
619 // Create an MCSymbol for the reference.
621 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
624 if (ACPV->getPCAdjustment()) {
625 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
629 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
631 MCBinaryExpr::CreateAdd(PCRelExpr,
632 MCConstantExpr::Create(ACPV->getPCAdjustment(),
635 if (ACPV->mustAddCurrentAddress()) {
636 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
637 // label, so just emit a local label end reference that instead.
638 MCSymbol *DotSym = OutContext.CreateTempSymbol();
639 OutStreamer.EmitLabel(DotSym);
640 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
641 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
643 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
645 OutStreamer.EmitValue(Expr, Size);
648 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
649 unsigned Opcode = MI->getOpcode();
651 if (Opcode == ARM::BR_JTadd)
653 else if (Opcode == ARM::BR_JTm)
656 const MachineOperand &MO1 = MI->getOperand(OpNum);
657 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
658 unsigned JTI = MO1.getIndex();
660 // Emit a label for the jump table.
661 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
662 OutStreamer.EmitLabel(JTISymbol);
664 // Emit each entry of the table.
665 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
666 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
667 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
669 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
670 MachineBasicBlock *MBB = JTBBs[i];
671 // Construct an MCExpr for the entry. We want a value of the form:
672 // (BasicBlockAddr - TableBeginAddr)
674 // For example, a table with entries jumping to basic blocks BB0 and BB1
677 // .word (LBB0 - LJTI_0_0)
678 // .word (LBB1 - LJTI_0_0)
679 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
681 if (TM.getRelocationModel() == Reloc::PIC_)
682 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
685 OutStreamer.EmitValue(Expr, 4);
689 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
690 unsigned Opcode = MI->getOpcode();
691 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
692 const MachineOperand &MO1 = MI->getOperand(OpNum);
693 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
694 unsigned JTI = MO1.getIndex();
696 // Emit a label for the jump table.
697 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
698 OutStreamer.EmitLabel(JTISymbol);
700 // Emit each entry of the table.
701 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
702 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
703 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
704 unsigned OffsetWidth = 4;
705 if (MI->getOpcode() == ARM::t2TBB_JT)
707 else if (MI->getOpcode() == ARM::t2TBH_JT)
710 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
711 MachineBasicBlock *MBB = JTBBs[i];
712 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
714 // If this isn't a TBB or TBH, the entries are direct branch instructions.
715 if (OffsetWidth == 4) {
717 BrInst.setOpcode(ARM::t2B);
718 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
719 OutStreamer.EmitInstruction(BrInst);
722 // Otherwise it's an offset from the dispatch instruction. Construct an
723 // MCExpr for the entry. We want a value of the form:
724 // (BasicBlockAddr - TableBeginAddr) / 2
726 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
729 // .byte (LBB0 - LJTI_0_0) / 2
730 // .byte (LBB1 - LJTI_0_0) / 2
732 MCBinaryExpr::CreateSub(MBBSymbolExpr,
733 MCSymbolRefExpr::Create(JTISymbol, OutContext),
735 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
737 OutStreamer.EmitValue(Expr, OffsetWidth);
741 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
743 unsigned NOps = MI->getNumOperands();
745 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
746 // cast away const; DIetc do not take const operands for some reason.
747 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
750 // Frame address. Currently handles register +- offset only.
751 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
752 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
755 printOperand(MI, NOps-2, OS);
758 static void populateADROperands(MCInst &Inst, unsigned Dest,
759 const MCSymbol *Label,
760 unsigned pred, unsigned ccreg,
762 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
763 Inst.addOperand(MCOperand::CreateReg(Dest));
764 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
765 // Add predicate operands.
766 Inst.addOperand(MCOperand::CreateImm(pred));
767 Inst.addOperand(MCOperand::CreateReg(ccreg));
770 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
774 // Emit the instruction as usual, just patch the opcode.
775 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
776 TmpInst.setOpcode(Opcode);
777 OutStreamer.EmitInstruction(TmpInst);
780 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
781 unsigned Opc = MI->getOpcode();
785 case ARM::t2ADDrSPi12:
787 case ARM::t2SUBrSPi12:
788 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
789 "Unexpected source register!");
792 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
793 case ARM::DBG_VALUE: {
794 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
795 SmallString<128> TmpStr;
796 raw_svector_ostream OS(TmpStr);
797 PrintDebugValueComment(MI, OS);
798 OutStreamer.EmitRawText(StringRef(OS.str()));
804 TmpInst.setOpcode(ARM::tBL);
805 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
806 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
807 OutStreamer.EmitInstruction(TmpInst);
812 case ARM::t2LEApcrel: {
813 // FIXME: Need to also handle globals and externals
815 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
816 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
818 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
819 GetCPISymbol(MI->getOperand(1).getIndex()),
820 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
822 OutStreamer.EmitInstruction(TmpInst);
825 case ARM::LEApcrelJT:
826 case ARM::tLEApcrelJT:
827 case ARM::t2LEApcrelJT: {
829 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
830 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
832 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
833 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
834 MI->getOperand(2).getImm()),
835 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
837 OutStreamer.EmitInstruction(TmpInst);
842 TmpInst.setOpcode(ARM::MOVr);
843 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
844 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
845 // Add predicate operands.
846 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
847 TmpInst.addOperand(MCOperand::CreateReg(0));
848 // Add 's' bit operand (always reg0 for this)
849 TmpInst.addOperand(MCOperand::CreateReg(0));
850 OutStreamer.EmitInstruction(TmpInst);
857 TmpInst.setOpcode(ARM::MOVr);
858 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
859 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
860 // Add predicate operands.
861 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
862 TmpInst.addOperand(MCOperand::CreateReg(0));
863 // Add 's' bit operand (always reg0 for this)
864 TmpInst.addOperand(MCOperand::CreateReg(0));
865 OutStreamer.EmitInstruction(TmpInst);
869 TmpInst.setOpcode(ARM::BX);
870 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
871 OutStreamer.EmitInstruction(TmpInst);
875 case ARM::BMOVPCRXr9_CALL:
876 case ARM::BMOVPCRX_CALL: {
879 TmpInst.setOpcode(ARM::MOVr);
880 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
881 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
882 // Add predicate operands.
883 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
884 TmpInst.addOperand(MCOperand::CreateReg(0));
885 // Add 's' bit operand (always reg0 for this)
886 TmpInst.addOperand(MCOperand::CreateReg(0));
887 OutStreamer.EmitInstruction(TmpInst);
891 TmpInst.setOpcode(ARM::MOVr);
892 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
893 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
894 // Add predicate operands.
895 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
896 TmpInst.addOperand(MCOperand::CreateReg(0));
897 // Add 's' bit operand (always reg0 for this)
898 TmpInst.addOperand(MCOperand::CreateReg(0));
899 OutStreamer.EmitInstruction(TmpInst);
903 case ARM::MOVi16_ga_pcrel:
904 case ARM::t2MOVi16_ga_pcrel: {
906 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
907 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
909 unsigned TF = MI->getOperand(1).getTargetFlags();
910 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
911 const GlobalValue *GV = MI->getOperand(1).getGlobal();
912 MCSymbol *GVSym = GetARMGVSymbol(GV);
913 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
915 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
917 MI->getOperand(2).getImm(), OutContext);
918 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
919 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
920 const MCExpr *PCRelExpr =
921 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
922 MCBinaryExpr::CreateAdd(LabelSymExpr,
923 MCConstantExpr::Create(PCAdj, OutContext),
924 OutContext), OutContext), OutContext);
925 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
927 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
928 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
931 // Add predicate operands.
932 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
933 TmpInst.addOperand(MCOperand::CreateReg(0));
934 // Add 's' bit operand (always reg0 for this)
935 TmpInst.addOperand(MCOperand::CreateReg(0));
936 OutStreamer.EmitInstruction(TmpInst);
939 case ARM::MOVTi16_ga_pcrel:
940 case ARM::t2MOVTi16_ga_pcrel: {
942 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
943 ? ARM::MOVTi16 : ARM::t2MOVTi16);
944 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
945 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
947 unsigned TF = MI->getOperand(2).getTargetFlags();
948 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
949 const GlobalValue *GV = MI->getOperand(2).getGlobal();
950 MCSymbol *GVSym = GetARMGVSymbol(GV);
951 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
953 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
955 MI->getOperand(3).getImm(), OutContext);
956 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
957 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
958 const MCExpr *PCRelExpr =
959 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
960 MCBinaryExpr::CreateAdd(LabelSymExpr,
961 MCConstantExpr::Create(PCAdj, OutContext),
962 OutContext), OutContext), OutContext);
963 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
965 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
966 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
968 // Add predicate operands.
969 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
970 TmpInst.addOperand(MCOperand::CreateReg(0));
971 // Add 's' bit operand (always reg0 for this)
972 TmpInst.addOperand(MCOperand::CreateReg(0));
973 OutStreamer.EmitInstruction(TmpInst);
977 // This is a pseudo op for a label + instruction sequence, which looks like:
980 // This adds the address of LPC0 to r0.
983 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
984 getFunctionNumber(), MI->getOperand(2).getImm(),
987 // Form and emit the add.
989 AddInst.setOpcode(ARM::tADDhirr);
990 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
991 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
992 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
993 // Add predicate operands.
994 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
995 AddInst.addOperand(MCOperand::CreateReg(0));
996 OutStreamer.EmitInstruction(AddInst);
1000 // This is a pseudo op for a label + instruction sequence, which looks like:
1003 // This adds the address of LPC0 to r0.
1006 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1007 getFunctionNumber(), MI->getOperand(2).getImm(),
1010 // Form and emit the add.
1012 AddInst.setOpcode(ARM::ADDrr);
1013 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1014 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1015 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1016 // Add predicate operands.
1017 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1018 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1019 // Add 's' bit operand (always reg0 for this)
1020 AddInst.addOperand(MCOperand::CreateReg(0));
1021 OutStreamer.EmitInstruction(AddInst);
1031 case ARM::PICLDRSH: {
1032 // This is a pseudo op for a label + instruction sequence, which looks like:
1035 // The LCP0 label is referenced by a constant pool entry in order to get
1036 // a PC-relative address at the ldr instruction.
1039 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1040 getFunctionNumber(), MI->getOperand(2).getImm(),
1043 // Form and emit the load
1045 switch (MI->getOpcode()) {
1047 llvm_unreachable("Unexpected opcode!");
1048 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1049 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1050 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1051 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1052 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1053 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1054 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1055 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1058 LdStInst.setOpcode(Opcode);
1059 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1060 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1061 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1062 LdStInst.addOperand(MCOperand::CreateImm(0));
1063 // Add predicate operands.
1064 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1065 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1066 OutStreamer.EmitInstruction(LdStInst);
1070 case ARM::CONSTPOOL_ENTRY: {
1071 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1072 /// in the function. The first operand is the ID# for this instruction, the
1073 /// second is the index into the MachineConstantPool that this is, the third
1074 /// is the size in bytes of this constant pool entry.
1075 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1076 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1079 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1081 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1082 if (MCPE.isMachineConstantPoolEntry())
1083 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1085 EmitGlobalConstant(MCPE.Val.ConstVal);
1089 case ARM::t2BR_JT: {
1090 // Lower and emit the instruction itself, then the jump table following it.
1092 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
1093 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1094 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1095 // Add predicate operands.
1096 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1097 TmpInst.addOperand(MCOperand::CreateReg(0));
1098 OutStreamer.EmitInstruction(TmpInst);
1099 // Output the data for the jump table itself
1103 case ARM::t2TBB_JT: {
1104 // Lower and emit the instruction itself, then the jump table following it.
1107 TmpInst.setOpcode(ARM::t2TBB);
1108 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1109 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1110 // Add predicate operands.
1111 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1112 TmpInst.addOperand(MCOperand::CreateReg(0));
1113 OutStreamer.EmitInstruction(TmpInst);
1114 // Output the data for the jump table itself
1116 // Make sure the next instruction is 2-byte aligned.
1120 case ARM::t2TBH_JT: {
1121 // Lower and emit the instruction itself, then the jump table following it.
1124 TmpInst.setOpcode(ARM::t2TBH);
1125 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1126 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1127 // Add predicate operands.
1128 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1129 TmpInst.addOperand(MCOperand::CreateReg(0));
1130 OutStreamer.EmitInstruction(TmpInst);
1131 // Output the data for the jump table itself
1137 // Lower and emit the instruction itself, then the jump table following it.
1140 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1141 ARM::MOVr : ARM::tMOVgpr2gpr;
1142 TmpInst.setOpcode(Opc);
1143 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1144 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1145 // Add predicate operands.
1146 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1147 TmpInst.addOperand(MCOperand::CreateReg(0));
1148 // Add 's' bit operand (always reg0 for this)
1149 if (Opc == ARM::MOVr)
1150 TmpInst.addOperand(MCOperand::CreateReg(0));
1151 OutStreamer.EmitInstruction(TmpInst);
1153 // Make sure the Thumb jump table is 4-byte aligned.
1154 if (Opc == ARM::tMOVgpr2gpr)
1157 // Output the data for the jump table itself
1162 // Lower and emit the instruction itself, then the jump table following it.
1165 if (MI->getOperand(1).getReg() == 0) {
1167 TmpInst.setOpcode(ARM::LDRi12);
1168 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1169 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1170 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1172 TmpInst.setOpcode(ARM::LDRrs);
1173 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1174 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1175 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1176 TmpInst.addOperand(MCOperand::CreateImm(0));
1178 // Add predicate operands.
1179 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1180 TmpInst.addOperand(MCOperand::CreateReg(0));
1181 OutStreamer.EmitInstruction(TmpInst);
1183 // Output the data for the jump table itself
1187 case ARM::BR_JTadd: {
1188 // Lower and emit the instruction itself, then the jump table following it.
1189 // add pc, target, idx
1191 TmpInst.setOpcode(ARM::ADDrr);
1192 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1193 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1194 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1195 // Add predicate operands.
1196 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1197 TmpInst.addOperand(MCOperand::CreateReg(0));
1198 // Add 's' bit operand (always reg0 for this)
1199 TmpInst.addOperand(MCOperand::CreateReg(0));
1200 OutStreamer.EmitInstruction(TmpInst);
1202 // Output the data for the jump table itself
1207 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1208 // FIXME: Remove this special case when they do.
1209 if (!Subtarget->isTargetDarwin()) {
1210 //.long 0xe7ffdefe @ trap
1211 uint32_t Val = 0xe7ffdefeUL;
1212 OutStreamer.AddComment("trap");
1213 OutStreamer.EmitIntValue(Val, 4);
1219 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1220 // FIXME: Remove this special case when they do.
1221 if (!Subtarget->isTargetDarwin()) {
1222 //.short 57086 @ trap
1223 uint16_t Val = 0xdefe;
1224 OutStreamer.AddComment("trap");
1225 OutStreamer.EmitIntValue(Val, 2);
1230 case ARM::t2Int_eh_sjlj_setjmp:
1231 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1232 case ARM::tInt_eh_sjlj_setjmp: {
1233 // Two incoming args: GPR:$src, GPR:$val
1236 // str $val, [$src, #4]
1241 unsigned SrcReg = MI->getOperand(0).getReg();
1242 unsigned ValReg = MI->getOperand(1).getReg();
1243 MCSymbol *Label = GetARMSJLJEHLabel();
1246 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1247 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1248 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1250 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1251 OutStreamer.AddComment("eh_setjmp begin");
1252 OutStreamer.EmitInstruction(TmpInst);
1256 TmpInst.setOpcode(ARM::tADDi3);
1257 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1259 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1260 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1261 TmpInst.addOperand(MCOperand::CreateImm(7));
1263 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1264 TmpInst.addOperand(MCOperand::CreateReg(0));
1265 OutStreamer.EmitInstruction(TmpInst);
1269 TmpInst.setOpcode(ARM::tSTRi);
1270 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1271 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1272 // The offset immediate is #4. The operand value is scaled by 4 for the
1273 // tSTR instruction.
1274 TmpInst.addOperand(MCOperand::CreateImm(1));
1276 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1277 TmpInst.addOperand(MCOperand::CreateReg(0));
1278 OutStreamer.EmitInstruction(TmpInst);
1282 TmpInst.setOpcode(ARM::tMOVi8);
1283 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1284 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1285 TmpInst.addOperand(MCOperand::CreateImm(0));
1287 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1288 TmpInst.addOperand(MCOperand::CreateReg(0));
1289 OutStreamer.EmitInstruction(TmpInst);
1292 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1294 TmpInst.setOpcode(ARM::tB);
1295 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1296 OutStreamer.EmitInstruction(TmpInst);
1300 TmpInst.setOpcode(ARM::tMOVi8);
1301 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1302 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1303 TmpInst.addOperand(MCOperand::CreateImm(1));
1305 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1306 TmpInst.addOperand(MCOperand::CreateReg(0));
1307 OutStreamer.AddComment("eh_setjmp end");
1308 OutStreamer.EmitInstruction(TmpInst);
1310 OutStreamer.EmitLabel(Label);
1314 case ARM::Int_eh_sjlj_setjmp_nofp:
1315 case ARM::Int_eh_sjlj_setjmp: {
1316 // Two incoming args: GPR:$src, GPR:$val
1318 // str $val, [$src, #+4]
1322 unsigned SrcReg = MI->getOperand(0).getReg();
1323 unsigned ValReg = MI->getOperand(1).getReg();
1327 TmpInst.setOpcode(ARM::ADDri);
1328 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1330 TmpInst.addOperand(MCOperand::CreateImm(8));
1332 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 // 's' bit operand (always reg0 for this).
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.AddComment("eh_setjmp begin");
1337 OutStreamer.EmitInstruction(TmpInst);
1341 TmpInst.setOpcode(ARM::STRi12);
1342 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1343 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1344 TmpInst.addOperand(MCOperand::CreateImm(4));
1346 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1347 TmpInst.addOperand(MCOperand::CreateReg(0));
1348 OutStreamer.EmitInstruction(TmpInst);
1352 TmpInst.setOpcode(ARM::MOVi);
1353 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1354 TmpInst.addOperand(MCOperand::CreateImm(0));
1356 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1357 TmpInst.addOperand(MCOperand::CreateReg(0));
1358 // 's' bit operand (always reg0 for this).
1359 TmpInst.addOperand(MCOperand::CreateReg(0));
1360 OutStreamer.EmitInstruction(TmpInst);
1364 TmpInst.setOpcode(ARM::ADDri);
1365 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1366 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1367 TmpInst.addOperand(MCOperand::CreateImm(0));
1369 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1370 TmpInst.addOperand(MCOperand::CreateReg(0));
1371 // 's' bit operand (always reg0 for this).
1372 TmpInst.addOperand(MCOperand::CreateReg(0));
1373 OutStreamer.EmitInstruction(TmpInst);
1377 TmpInst.setOpcode(ARM::MOVi);
1378 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1379 TmpInst.addOperand(MCOperand::CreateImm(1));
1381 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 // 's' bit operand (always reg0 for this).
1384 TmpInst.addOperand(MCOperand::CreateReg(0));
1385 OutStreamer.AddComment("eh_setjmp end");
1386 OutStreamer.EmitInstruction(TmpInst);
1390 case ARM::Int_eh_sjlj_longjmp: {
1391 // ldr sp, [$src, #8]
1392 // ldr $scratch, [$src, #4]
1395 unsigned SrcReg = MI->getOperand(0).getReg();
1396 unsigned ScratchReg = MI->getOperand(1).getReg();
1399 TmpInst.setOpcode(ARM::LDRi12);
1400 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1401 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1402 TmpInst.addOperand(MCOperand::CreateImm(8));
1404 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1405 TmpInst.addOperand(MCOperand::CreateReg(0));
1406 OutStreamer.EmitInstruction(TmpInst);
1410 TmpInst.setOpcode(ARM::LDRi12);
1411 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1412 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1413 TmpInst.addOperand(MCOperand::CreateImm(4));
1415 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1416 TmpInst.addOperand(MCOperand::CreateReg(0));
1417 OutStreamer.EmitInstruction(TmpInst);
1421 TmpInst.setOpcode(ARM::LDRi12);
1422 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1423 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1424 TmpInst.addOperand(MCOperand::CreateImm(0));
1426 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1427 TmpInst.addOperand(MCOperand::CreateReg(0));
1428 OutStreamer.EmitInstruction(TmpInst);
1432 TmpInst.setOpcode(ARM::BX);
1433 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1435 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1436 TmpInst.addOperand(MCOperand::CreateReg(0));
1437 OutStreamer.EmitInstruction(TmpInst);
1441 case ARM::tInt_eh_sjlj_longjmp: {
1442 // ldr $scratch, [$src, #8]
1444 // ldr $scratch, [$src, #4]
1447 unsigned SrcReg = MI->getOperand(0).getReg();
1448 unsigned ScratchReg = MI->getOperand(1).getReg();
1451 TmpInst.setOpcode(ARM::tLDRi);
1452 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1453 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1454 // The offset immediate is #8. The operand value is scaled by 4 for the
1455 // tLDR instruction.
1456 TmpInst.addOperand(MCOperand::CreateImm(2));
1458 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1459 TmpInst.addOperand(MCOperand::CreateReg(0));
1460 OutStreamer.EmitInstruction(TmpInst);
1464 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1465 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1466 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1468 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1469 TmpInst.addOperand(MCOperand::CreateReg(0));
1470 OutStreamer.EmitInstruction(TmpInst);
1474 TmpInst.setOpcode(ARM::tLDRi);
1475 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1476 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1477 TmpInst.addOperand(MCOperand::CreateImm(1));
1479 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1480 TmpInst.addOperand(MCOperand::CreateReg(0));
1481 OutStreamer.EmitInstruction(TmpInst);
1485 TmpInst.setOpcode(ARM::tLDRr);
1486 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1487 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1488 TmpInst.addOperand(MCOperand::CreateReg(0));
1490 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1491 TmpInst.addOperand(MCOperand::CreateReg(0));
1492 OutStreamer.EmitInstruction(TmpInst);
1496 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1497 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1499 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1500 TmpInst.addOperand(MCOperand::CreateReg(0));
1501 OutStreamer.EmitInstruction(TmpInst);
1505 // These are the pseudos created to comply with stricter operand restrictions
1506 // on ARMv5. Lower them now to "normal" instructions, since all the
1507 // restrictions are already satisfied.
1509 EmitPatchedInstruction(MI, ARM::MUL);
1512 EmitPatchedInstruction(MI, ARM::MLA);
1515 EmitPatchedInstruction(MI, ARM::SMULL);
1518 EmitPatchedInstruction(MI, ARM::UMULL);
1521 EmitPatchedInstruction(MI, ARM::SMLAL);
1524 EmitPatchedInstruction(MI, ARM::UMLAL);
1527 EmitPatchedInstruction(MI, ARM::UMAAL);
1532 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1533 OutStreamer.EmitInstruction(TmpInst);
1536 //===----------------------------------------------------------------------===//
1537 // Target Registry Stuff
1538 //===----------------------------------------------------------------------===//
1540 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1541 unsigned SyntaxVariant,
1542 const MCAsmInfo &MAI) {
1543 if (SyntaxVariant == 0)
1544 return new ARMInstPrinter(MAI);
1548 // Force static initialization.
1549 extern "C" void LLVMInitializeARMAsmPrinter() {
1550 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1551 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1553 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1554 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);