1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionBodyEnd() {
287 // Make sure to terminate any constant pools that were at the end
291 InConstantPool = false;
292 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296 if (AFI->isThumbFunction()) {
297 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
298 OutStreamer.EmitThumbFunc(CurrentFnSym);
301 OutStreamer.EmitLabel(CurrentFnSym);
304 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306 assert(Size && "C++ constructor pointer had zero size!");
308 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
309 assert(GV && "C++ constructor pointer was not a GlobalValue!");
311 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312 (Subtarget->isTargetDarwin()
313 ? MCSymbolRefExpr::VK_None
314 : MCSymbolRefExpr::VK_ARM_TARGET1),
317 OutStreamer.EmitValue(E, Size);
320 /// runOnMachineFunction - This uses the EmitInstruction()
321 /// method to print assembly for each instruction.
323 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
324 AFI = MF.getInfo<ARMFunctionInfo>();
325 MCP = MF.getConstantPool();
327 return AsmPrinter::runOnMachineFunction(MF);
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
331 raw_ostream &O, const char *Modifier) {
332 const MachineOperand &MO = MI->getOperand(OpNum);
333 unsigned TF = MO.getTargetFlags();
335 switch (MO.getType()) {
336 default: llvm_unreachable("<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 assert(!MO.getSubReg() && "Subregs should be eliminated!");
341 O << ARMInstPrinter::getRegisterName(Reg);
344 case MachineOperand::MO_Immediate: {
345 int64_t Imm = MO.getImm();
347 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
348 (TF == ARMII::MO_LO16))
350 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
351 (TF == ARMII::MO_HI16))
356 case MachineOperand::MO_MachineBasicBlock:
357 O << *MO.getMBB()->getSymbol();
359 case MachineOperand::MO_GlobalAddress: {
360 const GlobalValue *GV = MO.getGlobal();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
367 O << *Mang->getSymbol(GV);
369 printOffset(MO.getOffset(), O);
370 if (TF == ARMII::MO_PLT)
374 case MachineOperand::MO_ExternalSymbol: {
375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
376 if (TF == ARMII::MO_PLT)
380 case MachineOperand::MO_ConstantPoolIndex:
381 O << *GetCPISymbol(MO.getIndex());
383 case MachineOperand::MO_JumpTableIndex:
384 O << *GetJTISymbol(MO.getIndex());
389 //===--------------------------------------------------------------------===//
391 MCSymbol *ARMAsmPrinter::
392 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393 const MachineBasicBlock *MBB) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
396 << getFunctionNumber() << '_' << uid << '_' << uid2
397 << "_set_" << MBB->getNumber();
398 return OutContext.GetOrCreateSymbol(Name.str());
401 MCSymbol *ARMAsmPrinter::
402 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403 SmallString<60> Name;
404 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
405 << getFunctionNumber() << '_' << uid << '_' << uid2;
406 return OutContext.GetOrCreateSymbol(Name.str());
410 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411 SmallString<60> Name;
412 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413 << getFunctionNumber();
414 return OutContext.GetOrCreateSymbol(Name.str());
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
418 unsigned AsmVariant, const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
426 // See if this is a generic print operand
427 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
428 case 'a': // Print as a memory address.
429 if (MI->getOperand(OpNum).isReg()) {
431 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
436 case 'c': // Don't print "#" before an immediate operand.
437 if (!MI->getOperand(OpNum).isImm())
439 O << MI->getOperand(OpNum).getImm();
441 case 'P': // Print a VFP double precision register.
442 case 'q': // Print a NEON quad precision register.
443 printOperand(MI, OpNum, O);
445 case 'y': // Print a VFP single precision register as indexed double.
446 if (MI->getOperand(OpNum).isReg()) {
447 unsigned Reg = MI->getOperand(OpNum).getReg();
448 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
449 // Find the 'd' register that has this 's' register as a sub-register,
450 // and determine the lane number.
451 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
452 if (!ARM::DPRRegClass.contains(*SR))
454 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
455 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
460 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
461 if (!MI->getOperand(OpNum).isImm())
463 O << ~(MI->getOperand(OpNum).getImm());
465 case 'L': // The low 16 bits of an immediate constant.
466 if (!MI->getOperand(OpNum).isImm())
468 O << (MI->getOperand(OpNum).getImm() & 0xffff);
470 case 'M': { // A register range suitable for LDM/STM.
471 if (!MI->getOperand(OpNum).isReg())
473 const MachineOperand &MO = MI->getOperand(OpNum);
474 unsigned RegBegin = MO.getReg();
475 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
476 // already got the operands in registers that are operands to the
477 // inline asm statement.
479 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
481 // FIXME: The register allocator not only may not have given us the
482 // registers in sequence, but may not be in ascending registers. This
483 // will require changes in the register allocator that'll need to be
484 // propagated down here if the operands change.
485 unsigned RegOps = OpNum + 1;
486 while (MI->getOperand(RegOps).isReg()) {
488 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
496 case 'R': // The most significant register of a pair.
497 case 'Q': { // The least significant register of a pair.
500 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
501 if (!FlagsOP.isImm())
503 unsigned Flags = FlagsOP.getImm();
504 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
507 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
508 if (RegOp >= MI->getNumOperands())
510 const MachineOperand &MO = MI->getOperand(RegOp);
513 unsigned Reg = MO.getReg();
514 O << ARMInstPrinter::getRegisterName(Reg);
518 case 'e': // The low doubleword register of a NEON quad register.
519 case 'f': { // The high doubleword register of a NEON quad register.
520 if (!MI->getOperand(OpNum).isReg())
522 unsigned Reg = MI->getOperand(OpNum).getReg();
523 if (!ARM::QPRRegClass.contains(Reg))
525 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
526 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
527 ARM::dsub_0 : ARM::dsub_1);
528 O << ARMInstPrinter::getRegisterName(SubReg);
532 // These modifiers are not yet supported.
533 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
534 case 'H': // The highest-numbered register of a pair.
539 printOperand(MI, OpNum, O);
543 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
544 unsigned OpNum, unsigned AsmVariant,
545 const char *ExtraCode,
547 // Does this asm operand have a single letter operand modifier?
548 if (ExtraCode && ExtraCode[0]) {
549 if (ExtraCode[1] != 0) return true; // Unknown modifier.
551 switch (ExtraCode[0]) {
552 case 'A': // A memory operand for a VLD1/VST1 instruction.
553 default: return true; // Unknown modifier.
554 case 'm': // The base register of a memory operand.
555 if (!MI->getOperand(OpNum).isReg())
557 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
562 const MachineOperand &MO = MI->getOperand(OpNum);
563 assert(MO.isReg() && "unexpected inline asm memory operand");
564 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
568 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
569 if (Subtarget->isTargetDarwin()) {
570 Reloc::Model RelocM = TM.getRelocationModel();
571 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
572 // Declare all the text sections up front (before the DWARF sections
573 // emitted by AsmPrinter::doInitialization) so the assembler will keep
574 // them together at the beginning of the object file. This helps
575 // avoid out-of-range branches that are due a fundamental limitation of
576 // the way symbol offsets are encoded with the current Darwin ARM
578 const TargetLoweringObjectFileMachO &TLOFMacho =
579 static_cast<const TargetLoweringObjectFileMachO &>(
580 getObjFileLowering());
581 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
582 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
583 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
584 if (RelocM == Reloc::DynamicNoPIC) {
585 const MCSection *sect =
586 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
587 MCSectionMachO::S_SYMBOL_STUBS,
588 12, SectionKind::getText());
589 OutStreamer.SwitchSection(sect);
591 const MCSection *sect =
592 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
593 MCSectionMachO::S_SYMBOL_STUBS,
594 16, SectionKind::getText());
595 OutStreamer.SwitchSection(sect);
597 const MCSection *StaticInitSect =
598 OutContext.getMachOSection("__TEXT", "__StaticInit",
599 MCSectionMachO::S_REGULAR |
600 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
601 SectionKind::getText());
602 OutStreamer.SwitchSection(StaticInitSect);
606 // Use unified assembler syntax.
607 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
609 // Emit ARM Build Attributes
610 if (Subtarget->isTargetELF())
615 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
616 if (Subtarget->isTargetDarwin()) {
617 // All darwin targets use mach-o.
618 const TargetLoweringObjectFileMachO &TLOFMacho =
619 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
620 MachineModuleInfoMachO &MMIMacho =
621 MMI->getObjFileInfo<MachineModuleInfoMachO>();
623 // Output non-lazy-pointers for external and common global variables.
624 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
626 if (!Stubs.empty()) {
627 // Switch with ".non_lazy_symbol_pointer" directive.
628 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
630 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
632 OutStreamer.EmitLabel(Stubs[i].first);
633 // .indirect_symbol _foo
634 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
635 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
638 // External to current translation unit.
639 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
641 // Internal to current translation unit.
643 // When we place the LSDA into the TEXT section, the type info
644 // pointers need to be indirect and pc-rel. We accomplish this by
645 // using NLPs; however, sometimes the types are local to the file.
646 // We need to fill in the value for the NLP in those cases.
647 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
649 4/*size*/, 0/*addrspace*/);
653 OutStreamer.AddBlankLine();
656 Stubs = MMIMacho.GetHiddenGVStubList();
657 if (!Stubs.empty()) {
658 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
660 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
662 OutStreamer.EmitLabel(Stubs[i].first);
664 OutStreamer.EmitValue(MCSymbolRefExpr::
665 Create(Stubs[i].second.getPointer(),
667 4/*size*/, 0/*addrspace*/);
671 OutStreamer.AddBlankLine();
674 // Funny Darwin hack: This flag tells the linker that no global symbols
675 // contain code that falls through to other global symbols (e.g. the obvious
676 // implementation of multiple entry points). If this doesn't occur, the
677 // linker can safely perform dead code stripping. Since LLVM never
678 // generates code that does this, it is always safe to set.
679 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
683 //===----------------------------------------------------------------------===//
684 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
686 // The following seem like one-off assembler flags, but they actually need
687 // to appear in the .ARM.attributes section in ELF.
688 // Instead of subclassing the MCELFStreamer, we do the work here.
690 void ARMAsmPrinter::emitAttributes() {
692 emitARMAttributeSection();
694 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
695 bool emitFPU = false;
696 AttributeEmitter *AttrEmitter;
697 if (OutStreamer.hasRawTextSupport()) {
698 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
701 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
702 AttrEmitter = new ObjectAttributeEmitter(O);
705 AttrEmitter->MaybeSwitchVendor("aeabi");
707 std::string CPUString = Subtarget->getCPUString();
709 if (CPUString == "cortex-a8" ||
710 Subtarget->isCortexA8()) {
711 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
712 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
713 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
714 ARMBuildAttrs::ApplicationProfile);
715 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
716 ARMBuildAttrs::Allowed);
717 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
718 ARMBuildAttrs::AllowThumb32);
719 // Fixme: figure out when this is emitted.
720 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
721 // ARMBuildAttrs::AllowWMMXv1);
724 /// ADD additional Else-cases here!
725 } else if (CPUString == "xscale") {
726 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
727 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
728 ARMBuildAttrs::Allowed);
729 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
730 ARMBuildAttrs::Allowed);
731 } else if (CPUString == "generic") {
732 // FIXME: Why these defaults?
733 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
734 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
735 ARMBuildAttrs::Allowed);
736 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
737 ARMBuildAttrs::Allowed);
740 if (Subtarget->hasNEON() && emitFPU) {
741 /* NEON is not exactly a VFP architecture, but GAS emit one of
742 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
743 if (Subtarget->hasVFP4())
744 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
747 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
748 /* If emitted for NEON, omit from VFP below, since you can have both
749 * NEON and VFP in build attributes but only one .fpu */
754 if (Subtarget->hasVFP4()) {
755 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
756 ARMBuildAttrs::AllowFPv4A);
758 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
761 } else if (Subtarget->hasVFP3()) {
762 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
763 ARMBuildAttrs::AllowFPv3A);
765 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
768 } else if (Subtarget->hasVFP2()) {
769 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
770 ARMBuildAttrs::AllowFPv2);
772 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
775 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
776 * since NEON can have 1 (allowed) or 2 (MAC operations) */
777 if (Subtarget->hasNEON()) {
778 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
779 ARMBuildAttrs::Allowed);
782 // Signal various FP modes.
783 if (!TM.Options.UnsafeFPMath) {
784 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
785 ARMBuildAttrs::Allowed);
786 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
787 ARMBuildAttrs::Allowed);
790 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
791 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
792 ARMBuildAttrs::Allowed);
794 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
795 ARMBuildAttrs::AllowIEE754);
797 // FIXME: add more flags to ARMBuildAttrs.h
798 // 8-bytes alignment stuff.
799 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
800 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
802 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
803 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
804 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
805 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
807 // FIXME: Should we signal R9 usage?
809 if (Subtarget->hasDivide())
810 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
812 AttrEmitter->Finish();
816 void ARMAsmPrinter::emitARMAttributeSection() {
818 // [ <section-length> "vendor-name"
819 // [ <file-tag> <size> <attribute>*
820 // | <section-tag> <size> <section-number>* 0 <attribute>*
821 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
825 if (OutStreamer.hasRawTextSupport())
828 const ARMElfTargetObjectFile &TLOFELF =
829 static_cast<const ARMElfTargetObjectFile &>
830 (getObjFileLowering());
832 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
835 OutStreamer.EmitIntValue(0x41, 1);
838 //===----------------------------------------------------------------------===//
840 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
841 unsigned LabelId, MCContext &Ctx) {
843 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
844 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
848 static MCSymbolRefExpr::VariantKind
849 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
851 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
852 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
853 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
854 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
855 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
856 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
858 llvm_unreachable("Invalid ARMCPModifier!");
861 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
862 bool isIndirect = Subtarget->isTargetDarwin() &&
863 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
865 return Mang->getSymbol(GV);
867 // FIXME: Remove this when Darwin transition to @GOT like syntax.
868 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
869 MachineModuleInfoMachO &MMIMachO =
870 MMI->getObjFileInfo<MachineModuleInfoMachO>();
871 MachineModuleInfoImpl::StubValueTy &StubSym =
872 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
873 MMIMachO.getGVStubEntry(MCSym);
874 if (StubSym.getPointer() == 0)
875 StubSym = MachineModuleInfoImpl::
876 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
881 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
882 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
884 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
887 if (ACPV->isLSDA()) {
888 SmallString<128> Str;
889 raw_svector_ostream OS(Str);
890 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
891 MCSym = OutContext.GetOrCreateSymbol(OS.str());
892 } else if (ACPV->isBlockAddress()) {
893 const BlockAddress *BA =
894 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
895 MCSym = GetBlockAddressSymbol(BA);
896 } else if (ACPV->isGlobalValue()) {
897 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
898 MCSym = GetARMGVSymbol(GV);
899 } else if (ACPV->isMachineBasicBlock()) {
900 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
901 MCSym = MBB->getSymbol();
903 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
904 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
905 MCSym = GetExternalSymbolSymbol(Sym);
908 // Create an MCSymbol for the reference.
910 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
913 if (ACPV->getPCAdjustment()) {
914 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
918 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
920 MCBinaryExpr::CreateAdd(PCRelExpr,
921 MCConstantExpr::Create(ACPV->getPCAdjustment(),
924 if (ACPV->mustAddCurrentAddress()) {
925 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
926 // label, so just emit a local label end reference that instead.
927 MCSymbol *DotSym = OutContext.CreateTempSymbol();
928 OutStreamer.EmitLabel(DotSym);
929 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
930 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
932 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
934 OutStreamer.EmitValue(Expr, Size);
937 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
938 unsigned Opcode = MI->getOpcode();
940 if (Opcode == ARM::BR_JTadd)
942 else if (Opcode == ARM::BR_JTm)
945 const MachineOperand &MO1 = MI->getOperand(OpNum);
946 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
947 unsigned JTI = MO1.getIndex();
949 // Emit a label for the jump table.
950 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
951 OutStreamer.EmitLabel(JTISymbol);
953 // Mark the jump table as data-in-code.
954 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
956 // Emit each entry of the table.
957 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
958 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
959 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
961 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
962 MachineBasicBlock *MBB = JTBBs[i];
963 // Construct an MCExpr for the entry. We want a value of the form:
964 // (BasicBlockAddr - TableBeginAddr)
966 // For example, a table with entries jumping to basic blocks BB0 and BB1
969 // .word (LBB0 - LJTI_0_0)
970 // .word (LBB1 - LJTI_0_0)
971 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
973 if (TM.getRelocationModel() == Reloc::PIC_)
974 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
977 // If we're generating a table of Thumb addresses in static relocation
978 // model, we need to add one to keep interworking correctly.
979 else if (AFI->isThumbFunction())
980 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
982 OutStreamer.EmitValue(Expr, 4);
984 // Mark the end of jump table data-in-code region.
985 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
988 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
989 unsigned Opcode = MI->getOpcode();
990 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
991 const MachineOperand &MO1 = MI->getOperand(OpNum);
992 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
993 unsigned JTI = MO1.getIndex();
995 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
996 OutStreamer.EmitLabel(JTISymbol);
998 // Emit each entry of the table.
999 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1000 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1001 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1002 unsigned OffsetWidth = 4;
1003 if (MI->getOpcode() == ARM::t2TBB_JT) {
1005 // Mark the jump table as data-in-code.
1006 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1007 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1009 // Mark the jump table as data-in-code.
1010 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1013 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1014 MachineBasicBlock *MBB = JTBBs[i];
1015 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1017 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1018 if (OffsetWidth == 4) {
1020 BrInst.setOpcode(ARM::t2B);
1021 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1022 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1023 BrInst.addOperand(MCOperand::CreateReg(0));
1024 OutStreamer.EmitInstruction(BrInst);
1027 // Otherwise it's an offset from the dispatch instruction. Construct an
1028 // MCExpr for the entry. We want a value of the form:
1029 // (BasicBlockAddr - TableBeginAddr) / 2
1031 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1034 // .byte (LBB0 - LJTI_0_0) / 2
1035 // .byte (LBB1 - LJTI_0_0) / 2
1036 const MCExpr *Expr =
1037 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1038 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1040 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1042 OutStreamer.EmitValue(Expr, OffsetWidth);
1044 // Mark the end of jump table data-in-code region. 32-bit offsets use
1045 // actual branch instructions here, so we don't mark those as a data-region
1047 if (OffsetWidth != 4)
1048 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1051 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1053 unsigned NOps = MI->getNumOperands();
1055 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1056 // cast away const; DIetc do not take const operands for some reason.
1057 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1060 // Frame address. Currently handles register +- offset only.
1061 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1062 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1065 printOperand(MI, NOps-2, OS);
1068 static void populateADROperands(MCInst &Inst, unsigned Dest,
1069 const MCSymbol *Label,
1070 unsigned pred, unsigned ccreg,
1072 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1073 Inst.addOperand(MCOperand::CreateReg(Dest));
1074 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1075 // Add predicate operands.
1076 Inst.addOperand(MCOperand::CreateImm(pred));
1077 Inst.addOperand(MCOperand::CreateReg(ccreg));
1080 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1084 // Emit the instruction as usual, just patch the opcode.
1085 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1086 TmpInst.setOpcode(Opcode);
1087 OutStreamer.EmitInstruction(TmpInst);
1090 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1091 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1092 "Only instruction which are involved into frame setup code are allowed");
1094 const MachineFunction &MF = *MI->getParent()->getParent();
1095 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1096 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1098 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1099 unsigned Opc = MI->getOpcode();
1100 unsigned SrcReg, DstReg;
1102 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1103 // Two special cases:
1104 // 1) tPUSH does not have src/dst regs.
1105 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1106 // load. Yes, this is pretty fragile, but for now I don't see better
1108 SrcReg = DstReg = ARM::SP;
1110 SrcReg = MI->getOperand(1).getReg();
1111 DstReg = MI->getOperand(0).getReg();
1114 // Try to figure out the unwinding opcode out of src / dst regs.
1115 if (MI->mayStore()) {
1117 assert(DstReg == ARM::SP &&
1118 "Only stack pointer as a destination reg is supported");
1120 SmallVector<unsigned, 4> RegList;
1121 // Skip src & dst reg, and pred ops.
1122 unsigned StartOp = 2 + 2;
1123 // Use all the operands.
1124 unsigned NumOffset = 0;
1129 llvm_unreachable("Unsupported opcode for unwinding information");
1131 // Special case here: no src & dst reg, but two extra imp ops.
1132 StartOp = 2; NumOffset = 2;
1133 case ARM::STMDB_UPD:
1134 case ARM::t2STMDB_UPD:
1135 case ARM::VSTMDDB_UPD:
1136 assert(SrcReg == ARM::SP &&
1137 "Only stack pointer as a source reg is supported");
1138 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1140 RegList.push_back(MI->getOperand(i).getReg());
1142 case ARM::STR_PRE_IMM:
1143 case ARM::STR_PRE_REG:
1144 case ARM::t2STR_PRE:
1145 assert(MI->getOperand(2).getReg() == ARM::SP &&
1146 "Only stack pointer as a source reg is supported");
1147 RegList.push_back(SrcReg);
1150 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1152 // Changes of stack / frame pointer.
1153 if (SrcReg == ARM::SP) {
1158 llvm_unreachable("Unsupported opcode for unwinding information");
1164 Offset = -MI->getOperand(2).getImm();
1168 Offset = MI->getOperand(2).getImm();
1171 Offset = MI->getOperand(2).getImm()*4;
1175 Offset = -MI->getOperand(2).getImm()*4;
1177 case ARM::tLDRpci: {
1178 // Grab the constpool index and check, whether it corresponds to
1179 // original or cloned constpool entry.
1180 unsigned CPI = MI->getOperand(1).getIndex();
1181 const MachineConstantPool *MCP = MF.getConstantPool();
1182 if (CPI >= MCP->getConstants().size())
1183 CPI = AFI.getOriginalCPIdx(CPI);
1184 assert(CPI != -1U && "Invalid constpool index");
1186 // Derive the actual offset.
1187 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1188 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1189 // FIXME: Check for user, it should be "add" instruction!
1190 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1195 if (DstReg == FramePtr && FramePtr != ARM::SP)
1196 // Set-up of the frame pointer. Positive values correspond to "add"
1198 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1199 else if (DstReg == ARM::SP) {
1200 // Change of SP by an offset. Positive values correspond to "sub"
1202 OutStreamer.EmitPad(Offset);
1205 llvm_unreachable("Unsupported opcode for unwinding information");
1207 } else if (DstReg == ARM::SP) {
1208 // FIXME: .movsp goes here
1210 llvm_unreachable("Unsupported opcode for unwinding information");
1214 llvm_unreachable("Unsupported opcode for unwinding information");
1219 extern cl::opt<bool> EnableARMEHABI;
1221 // Simple pseudo-instructions have their lowering (with expansion to real
1222 // instructions) auto-generated.
1223 #include "ARMGenMCPseudoLowering.inc"
1225 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1226 // If we just ended a constant pool, mark it as such.
1227 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1228 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1229 InConstantPool = false;
1232 // Emit unwinding stuff for frame-related instructions
1233 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1234 EmitUnwindingInstruction(MI);
1236 // Do any auto-generated pseudo lowerings.
1237 if (emitPseudoExpansionLowering(OutStreamer, MI))
1240 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1241 "Pseudo flag setting opcode should be expanded early");
1243 // Check for manual lowerings.
1244 unsigned Opc = MI->getOpcode();
1246 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1247 case ARM::DBG_VALUE: {
1248 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1249 SmallString<128> TmpStr;
1250 raw_svector_ostream OS(TmpStr);
1251 PrintDebugValueComment(MI, OS);
1252 OutStreamer.EmitRawText(StringRef(OS.str()));
1257 case ARM::tLEApcrel:
1258 case ARM::t2LEApcrel: {
1259 // FIXME: Need to also handle globals and externals
1261 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1262 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1264 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1265 GetCPISymbol(MI->getOperand(1).getIndex()),
1266 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1268 OutStreamer.EmitInstruction(TmpInst);
1271 case ARM::LEApcrelJT:
1272 case ARM::tLEApcrelJT:
1273 case ARM::t2LEApcrelJT: {
1275 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1276 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1278 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1279 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1280 MI->getOperand(2).getImm()),
1281 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1283 OutStreamer.EmitInstruction(TmpInst);
1286 // Darwin call instructions are just normal call instructions with different
1287 // clobber semantics (they clobber R9).
1288 case ARM::BX_CALL: {
1291 TmpInst.setOpcode(ARM::MOVr);
1292 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1293 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1294 // Add predicate operands.
1295 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1296 TmpInst.addOperand(MCOperand::CreateReg(0));
1297 // Add 's' bit operand (always reg0 for this)
1298 TmpInst.addOperand(MCOperand::CreateReg(0));
1299 OutStreamer.EmitInstruction(TmpInst);
1303 TmpInst.setOpcode(ARM::BX);
1304 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1305 OutStreamer.EmitInstruction(TmpInst);
1309 case ARM::tBX_CALL: {
1312 TmpInst.setOpcode(ARM::tMOVr);
1313 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1314 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1315 // Add predicate operands.
1316 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
1318 OutStreamer.EmitInstruction(TmpInst);
1322 TmpInst.setOpcode(ARM::tBX);
1323 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1324 // Add predicate operands.
1325 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 TmpInst.addOperand(MCOperand::CreateReg(0));
1327 OutStreamer.EmitInstruction(TmpInst);
1331 case ARM::BMOVPCRX_CALL: {
1334 TmpInst.setOpcode(ARM::MOVr);
1335 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1336 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1337 // Add predicate operands.
1338 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1339 TmpInst.addOperand(MCOperand::CreateReg(0));
1340 // Add 's' bit operand (always reg0 for this)
1341 TmpInst.addOperand(MCOperand::CreateReg(0));
1342 OutStreamer.EmitInstruction(TmpInst);
1346 TmpInst.setOpcode(ARM::MOVr);
1347 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1348 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1349 // Add predicate operands.
1350 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1351 TmpInst.addOperand(MCOperand::CreateReg(0));
1352 // Add 's' bit operand (always reg0 for this)
1353 TmpInst.addOperand(MCOperand::CreateReg(0));
1354 OutStreamer.EmitInstruction(TmpInst);
1358 case ARM::BMOVPCB_CALL: {
1361 TmpInst.setOpcode(ARM::MOVr);
1362 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1363 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1364 // Add predicate operands.
1365 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1366 TmpInst.addOperand(MCOperand::CreateReg(0));
1367 // Add 's' bit operand (always reg0 for this)
1368 TmpInst.addOperand(MCOperand::CreateReg(0));
1369 OutStreamer.EmitInstruction(TmpInst);
1373 TmpInst.setOpcode(ARM::Bcc);
1374 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1375 MCSymbol *GVSym = Mang->getSymbol(GV);
1376 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1377 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1378 // Add predicate operands.
1379 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1380 TmpInst.addOperand(MCOperand::CreateReg(0));
1381 OutStreamer.EmitInstruction(TmpInst);
1385 case ARM::t2BMOVPCB_CALL: {
1388 TmpInst.setOpcode(ARM::tMOVr);
1389 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1390 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1391 // Add predicate operands.
1392 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1393 TmpInst.addOperand(MCOperand::CreateReg(0));
1394 OutStreamer.EmitInstruction(TmpInst);
1398 TmpInst.setOpcode(ARM::t2B);
1399 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1400 MCSymbol *GVSym = Mang->getSymbol(GV);
1401 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1402 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1403 // Add predicate operands.
1404 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1405 TmpInst.addOperand(MCOperand::CreateReg(0));
1406 OutStreamer.EmitInstruction(TmpInst);
1410 case ARM::MOVi16_ga_pcrel:
1411 case ARM::t2MOVi16_ga_pcrel: {
1413 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1414 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1416 unsigned TF = MI->getOperand(1).getTargetFlags();
1417 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1418 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1419 MCSymbol *GVSym = GetARMGVSymbol(GV);
1420 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1422 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1423 getFunctionNumber(),
1424 MI->getOperand(2).getImm(), OutContext);
1425 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1426 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1427 const MCExpr *PCRelExpr =
1428 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1429 MCBinaryExpr::CreateAdd(LabelSymExpr,
1430 MCConstantExpr::Create(PCAdj, OutContext),
1431 OutContext), OutContext), OutContext);
1432 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1434 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1435 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1438 // Add predicate operands.
1439 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1440 TmpInst.addOperand(MCOperand::CreateReg(0));
1441 // Add 's' bit operand (always reg0 for this)
1442 TmpInst.addOperand(MCOperand::CreateReg(0));
1443 OutStreamer.EmitInstruction(TmpInst);
1446 case ARM::MOVTi16_ga_pcrel:
1447 case ARM::t2MOVTi16_ga_pcrel: {
1449 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1450 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1451 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1452 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1454 unsigned TF = MI->getOperand(2).getTargetFlags();
1455 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1456 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1457 MCSymbol *GVSym = GetARMGVSymbol(GV);
1458 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1460 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1461 getFunctionNumber(),
1462 MI->getOperand(3).getImm(), OutContext);
1463 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1464 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1465 const MCExpr *PCRelExpr =
1466 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1467 MCBinaryExpr::CreateAdd(LabelSymExpr,
1468 MCConstantExpr::Create(PCAdj, OutContext),
1469 OutContext), OutContext), OutContext);
1470 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1472 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1473 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1475 // Add predicate operands.
1476 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1477 TmpInst.addOperand(MCOperand::CreateReg(0));
1478 // Add 's' bit operand (always reg0 for this)
1479 TmpInst.addOperand(MCOperand::CreateReg(0));
1480 OutStreamer.EmitInstruction(TmpInst);
1483 case ARM::tPICADD: {
1484 // This is a pseudo op for a label + instruction sequence, which looks like:
1487 // This adds the address of LPC0 to r0.
1490 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1491 getFunctionNumber(), MI->getOperand(2).getImm(),
1494 // Form and emit the add.
1496 AddInst.setOpcode(ARM::tADDhirr);
1497 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1498 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1499 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1500 // Add predicate operands.
1501 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1502 AddInst.addOperand(MCOperand::CreateReg(0));
1503 OutStreamer.EmitInstruction(AddInst);
1507 // This is a pseudo op for a label + instruction sequence, which looks like:
1510 // This adds the address of LPC0 to r0.
1513 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1514 getFunctionNumber(), MI->getOperand(2).getImm(),
1517 // Form and emit the add.
1519 AddInst.setOpcode(ARM::ADDrr);
1520 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1521 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1522 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1523 // Add predicate operands.
1524 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1525 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1526 // Add 's' bit operand (always reg0 for this)
1527 AddInst.addOperand(MCOperand::CreateReg(0));
1528 OutStreamer.EmitInstruction(AddInst);
1538 case ARM::PICLDRSH: {
1539 // This is a pseudo op for a label + instruction sequence, which looks like:
1542 // The LCP0 label is referenced by a constant pool entry in order to get
1543 // a PC-relative address at the ldr instruction.
1546 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1547 getFunctionNumber(), MI->getOperand(2).getImm(),
1550 // Form and emit the load
1552 switch (MI->getOpcode()) {
1554 llvm_unreachable("Unexpected opcode!");
1555 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1556 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1557 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1558 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1559 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1560 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1561 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1562 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1565 LdStInst.setOpcode(Opcode);
1566 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1567 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1568 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1569 LdStInst.addOperand(MCOperand::CreateImm(0));
1570 // Add predicate operands.
1571 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1572 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1573 OutStreamer.EmitInstruction(LdStInst);
1577 case ARM::CONSTPOOL_ENTRY: {
1578 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1579 /// in the function. The first operand is the ID# for this instruction, the
1580 /// second is the index into the MachineConstantPool that this is, the third
1581 /// is the size in bytes of this constant pool entry.
1582 /// The required alignment is specified on the basic block holding this MI.
1583 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1584 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1586 // If this is the first entry of the pool, mark it.
1587 if (!InConstantPool) {
1588 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1589 InConstantPool = true;
1592 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1594 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1595 if (MCPE.isMachineConstantPoolEntry())
1596 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1598 EmitGlobalConstant(MCPE.Val.ConstVal);
1601 case ARM::t2BR_JT: {
1602 // Lower and emit the instruction itself, then the jump table following it.
1604 TmpInst.setOpcode(ARM::tMOVr);
1605 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1606 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1607 // Add predicate operands.
1608 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1609 TmpInst.addOperand(MCOperand::CreateReg(0));
1610 OutStreamer.EmitInstruction(TmpInst);
1611 // Output the data for the jump table itself
1615 case ARM::t2TBB_JT: {
1616 // Lower and emit the instruction itself, then the jump table following it.
1619 TmpInst.setOpcode(ARM::t2TBB);
1620 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1621 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1622 // Add predicate operands.
1623 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1624 TmpInst.addOperand(MCOperand::CreateReg(0));
1625 OutStreamer.EmitInstruction(TmpInst);
1626 // Output the data for the jump table itself
1628 // Make sure the next instruction is 2-byte aligned.
1632 case ARM::t2TBH_JT: {
1633 // Lower and emit the instruction itself, then the jump table following it.
1636 TmpInst.setOpcode(ARM::t2TBH);
1637 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1638 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1639 // Add predicate operands.
1640 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1641 TmpInst.addOperand(MCOperand::CreateReg(0));
1642 OutStreamer.EmitInstruction(TmpInst);
1643 // Output the data for the jump table itself
1649 // Lower and emit the instruction itself, then the jump table following it.
1652 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1653 ARM::MOVr : ARM::tMOVr;
1654 TmpInst.setOpcode(Opc);
1655 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1656 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1657 // Add predicate operands.
1658 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1659 TmpInst.addOperand(MCOperand::CreateReg(0));
1660 // Add 's' bit operand (always reg0 for this)
1661 if (Opc == ARM::MOVr)
1662 TmpInst.addOperand(MCOperand::CreateReg(0));
1663 OutStreamer.EmitInstruction(TmpInst);
1665 // Make sure the Thumb jump table is 4-byte aligned.
1666 if (Opc == ARM::tMOVr)
1669 // Output the data for the jump table itself
1674 // Lower and emit the instruction itself, then the jump table following it.
1677 if (MI->getOperand(1).getReg() == 0) {
1679 TmpInst.setOpcode(ARM::LDRi12);
1680 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1681 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1682 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1684 TmpInst.setOpcode(ARM::LDRrs);
1685 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1686 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1687 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1688 TmpInst.addOperand(MCOperand::CreateImm(0));
1690 // Add predicate operands.
1691 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1692 TmpInst.addOperand(MCOperand::CreateReg(0));
1693 OutStreamer.EmitInstruction(TmpInst);
1695 // Output the data for the jump table itself
1699 case ARM::BR_JTadd: {
1700 // Lower and emit the instruction itself, then the jump table following it.
1701 // add pc, target, idx
1703 TmpInst.setOpcode(ARM::ADDrr);
1704 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1705 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1706 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1707 // Add predicate operands.
1708 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1709 TmpInst.addOperand(MCOperand::CreateReg(0));
1710 // Add 's' bit operand (always reg0 for this)
1711 TmpInst.addOperand(MCOperand::CreateReg(0));
1712 OutStreamer.EmitInstruction(TmpInst);
1714 // Output the data for the jump table itself
1719 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1720 // FIXME: Remove this special case when they do.
1721 if (!Subtarget->isTargetDarwin()) {
1722 //.long 0xe7ffdefe @ trap
1723 uint32_t Val = 0xe7ffdefeUL;
1724 OutStreamer.AddComment("trap");
1725 OutStreamer.EmitIntValue(Val, 4);
1731 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1732 // FIXME: Remove this special case when they do.
1733 if (!Subtarget->isTargetDarwin()) {
1734 //.short 57086 @ trap
1735 uint16_t Val = 0xdefe;
1736 OutStreamer.AddComment("trap");
1737 OutStreamer.EmitIntValue(Val, 2);
1742 case ARM::t2Int_eh_sjlj_setjmp:
1743 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1744 case ARM::tInt_eh_sjlj_setjmp: {
1745 // Two incoming args: GPR:$src, GPR:$val
1748 // str $val, [$src, #4]
1753 unsigned SrcReg = MI->getOperand(0).getReg();
1754 unsigned ValReg = MI->getOperand(1).getReg();
1755 MCSymbol *Label = GetARMSJLJEHLabel();
1758 TmpInst.setOpcode(ARM::tMOVr);
1759 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1760 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1762 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1763 TmpInst.addOperand(MCOperand::CreateReg(0));
1764 OutStreamer.AddComment("eh_setjmp begin");
1765 OutStreamer.EmitInstruction(TmpInst);
1769 TmpInst.setOpcode(ARM::tADDi3);
1770 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1772 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1773 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1774 TmpInst.addOperand(MCOperand::CreateImm(7));
1776 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1777 TmpInst.addOperand(MCOperand::CreateReg(0));
1778 OutStreamer.EmitInstruction(TmpInst);
1782 TmpInst.setOpcode(ARM::tSTRi);
1783 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1784 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1785 // The offset immediate is #4. The operand value is scaled by 4 for the
1786 // tSTR instruction.
1787 TmpInst.addOperand(MCOperand::CreateImm(1));
1789 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1790 TmpInst.addOperand(MCOperand::CreateReg(0));
1791 OutStreamer.EmitInstruction(TmpInst);
1795 TmpInst.setOpcode(ARM::tMOVi8);
1796 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1797 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1798 TmpInst.addOperand(MCOperand::CreateImm(0));
1800 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1801 TmpInst.addOperand(MCOperand::CreateReg(0));
1802 OutStreamer.EmitInstruction(TmpInst);
1805 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1807 TmpInst.setOpcode(ARM::tB);
1808 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1809 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1810 TmpInst.addOperand(MCOperand::CreateReg(0));
1811 OutStreamer.EmitInstruction(TmpInst);
1815 TmpInst.setOpcode(ARM::tMOVi8);
1816 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1817 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1818 TmpInst.addOperand(MCOperand::CreateImm(1));
1820 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1821 TmpInst.addOperand(MCOperand::CreateReg(0));
1822 OutStreamer.AddComment("eh_setjmp end");
1823 OutStreamer.EmitInstruction(TmpInst);
1825 OutStreamer.EmitLabel(Label);
1829 case ARM::Int_eh_sjlj_setjmp_nofp:
1830 case ARM::Int_eh_sjlj_setjmp: {
1831 // Two incoming args: GPR:$src, GPR:$val
1833 // str $val, [$src, #+4]
1837 unsigned SrcReg = MI->getOperand(0).getReg();
1838 unsigned ValReg = MI->getOperand(1).getReg();
1842 TmpInst.setOpcode(ARM::ADDri);
1843 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1844 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1845 TmpInst.addOperand(MCOperand::CreateImm(8));
1847 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1848 TmpInst.addOperand(MCOperand::CreateReg(0));
1849 // 's' bit operand (always reg0 for this).
1850 TmpInst.addOperand(MCOperand::CreateReg(0));
1851 OutStreamer.AddComment("eh_setjmp begin");
1852 OutStreamer.EmitInstruction(TmpInst);
1856 TmpInst.setOpcode(ARM::STRi12);
1857 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1858 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1859 TmpInst.addOperand(MCOperand::CreateImm(4));
1861 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1862 TmpInst.addOperand(MCOperand::CreateReg(0));
1863 OutStreamer.EmitInstruction(TmpInst);
1867 TmpInst.setOpcode(ARM::MOVi);
1868 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1869 TmpInst.addOperand(MCOperand::CreateImm(0));
1871 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1872 TmpInst.addOperand(MCOperand::CreateReg(0));
1873 // 's' bit operand (always reg0 for this).
1874 TmpInst.addOperand(MCOperand::CreateReg(0));
1875 OutStreamer.EmitInstruction(TmpInst);
1879 TmpInst.setOpcode(ARM::ADDri);
1880 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1881 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1882 TmpInst.addOperand(MCOperand::CreateImm(0));
1884 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1885 TmpInst.addOperand(MCOperand::CreateReg(0));
1886 // 's' bit operand (always reg0 for this).
1887 TmpInst.addOperand(MCOperand::CreateReg(0));
1888 OutStreamer.EmitInstruction(TmpInst);
1892 TmpInst.setOpcode(ARM::MOVi);
1893 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1894 TmpInst.addOperand(MCOperand::CreateImm(1));
1896 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1897 TmpInst.addOperand(MCOperand::CreateReg(0));
1898 // 's' bit operand (always reg0 for this).
1899 TmpInst.addOperand(MCOperand::CreateReg(0));
1900 OutStreamer.AddComment("eh_setjmp end");
1901 OutStreamer.EmitInstruction(TmpInst);
1905 case ARM::Int_eh_sjlj_longjmp: {
1906 // ldr sp, [$src, #8]
1907 // ldr $scratch, [$src, #4]
1910 unsigned SrcReg = MI->getOperand(0).getReg();
1911 unsigned ScratchReg = MI->getOperand(1).getReg();
1914 TmpInst.setOpcode(ARM::LDRi12);
1915 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1916 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1917 TmpInst.addOperand(MCOperand::CreateImm(8));
1919 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1920 TmpInst.addOperand(MCOperand::CreateReg(0));
1921 OutStreamer.EmitInstruction(TmpInst);
1925 TmpInst.setOpcode(ARM::LDRi12);
1926 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1927 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1928 TmpInst.addOperand(MCOperand::CreateImm(4));
1930 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1931 TmpInst.addOperand(MCOperand::CreateReg(0));
1932 OutStreamer.EmitInstruction(TmpInst);
1936 TmpInst.setOpcode(ARM::LDRi12);
1937 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1938 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1939 TmpInst.addOperand(MCOperand::CreateImm(0));
1941 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1942 TmpInst.addOperand(MCOperand::CreateReg(0));
1943 OutStreamer.EmitInstruction(TmpInst);
1947 TmpInst.setOpcode(ARM::BX);
1948 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1950 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1951 TmpInst.addOperand(MCOperand::CreateReg(0));
1952 OutStreamer.EmitInstruction(TmpInst);
1956 case ARM::tInt_eh_sjlj_longjmp: {
1957 // ldr $scratch, [$src, #8]
1959 // ldr $scratch, [$src, #4]
1962 unsigned SrcReg = MI->getOperand(0).getReg();
1963 unsigned ScratchReg = MI->getOperand(1).getReg();
1966 TmpInst.setOpcode(ARM::tLDRi);
1967 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1968 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1969 // The offset immediate is #8. The operand value is scaled by 4 for the
1970 // tLDR instruction.
1971 TmpInst.addOperand(MCOperand::CreateImm(2));
1973 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1974 TmpInst.addOperand(MCOperand::CreateReg(0));
1975 OutStreamer.EmitInstruction(TmpInst);
1979 TmpInst.setOpcode(ARM::tMOVr);
1980 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1981 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1983 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1984 TmpInst.addOperand(MCOperand::CreateReg(0));
1985 OutStreamer.EmitInstruction(TmpInst);
1989 TmpInst.setOpcode(ARM::tLDRi);
1990 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1991 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1992 TmpInst.addOperand(MCOperand::CreateImm(1));
1994 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1995 TmpInst.addOperand(MCOperand::CreateReg(0));
1996 OutStreamer.EmitInstruction(TmpInst);
2000 TmpInst.setOpcode(ARM::tLDRi);
2001 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2002 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2003 TmpInst.addOperand(MCOperand::CreateImm(0));
2005 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2006 TmpInst.addOperand(MCOperand::CreateReg(0));
2007 OutStreamer.EmitInstruction(TmpInst);
2011 TmpInst.setOpcode(ARM::tBX);
2012 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2014 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2015 TmpInst.addOperand(MCOperand::CreateReg(0));
2016 OutStreamer.EmitInstruction(TmpInst);
2023 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2025 OutStreamer.EmitInstruction(TmpInst);
2028 //===----------------------------------------------------------------------===//
2029 // Target Registry Stuff
2030 //===----------------------------------------------------------------------===//
2032 // Force static initialization.
2033 extern "C" void LLVMInitializeARMAsmPrinter() {
2034 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2035 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);