1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionBodyEnd() {
287 // Make sure to terminate any constant pools that were at the end
291 InConstantPool = false;
292 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296 if (AFI->isThumbFunction()) {
297 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
298 OutStreamer.EmitThumbFunc(CurrentFnSym);
301 OutStreamer.EmitLabel(CurrentFnSym);
304 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306 assert(Size && "C++ constructor pointer had zero size!");
308 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
309 assert(GV && "C++ constructor pointer was not a GlobalValue!");
311 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312 (Subtarget->isTargetDarwin()
313 ? MCSymbolRefExpr::VK_None
314 : MCSymbolRefExpr::VK_ARM_TARGET1),
317 OutStreamer.EmitValue(E, Size);
320 /// runOnMachineFunction - This uses the EmitInstruction()
321 /// method to print assembly for each instruction.
323 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
324 AFI = MF.getInfo<ARMFunctionInfo>();
325 MCP = MF.getConstantPool();
327 return AsmPrinter::runOnMachineFunction(MF);
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
331 raw_ostream &O, const char *Modifier) {
332 const MachineOperand &MO = MI->getOperand(OpNum);
333 unsigned TF = MO.getTargetFlags();
335 switch (MO.getType()) {
336 default: llvm_unreachable("<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 assert(!MO.getSubReg() && "Subregs should be eliminated!");
341 O << ARMInstPrinter::getRegisterName(Reg);
344 case MachineOperand::MO_Immediate: {
345 int64_t Imm = MO.getImm();
347 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
348 (TF == ARMII::MO_LO16))
350 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
351 (TF == ARMII::MO_HI16))
356 case MachineOperand::MO_MachineBasicBlock:
357 O << *MO.getMBB()->getSymbol();
359 case MachineOperand::MO_GlobalAddress: {
360 const GlobalValue *GV = MO.getGlobal();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
367 O << *Mang->getSymbol(GV);
369 printOffset(MO.getOffset(), O);
370 if (TF == ARMII::MO_PLT)
374 case MachineOperand::MO_ExternalSymbol: {
375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
376 if (TF == ARMII::MO_PLT)
380 case MachineOperand::MO_ConstantPoolIndex:
381 O << *GetCPISymbol(MO.getIndex());
383 case MachineOperand::MO_JumpTableIndex:
384 O << *GetJTISymbol(MO.getIndex());
389 //===--------------------------------------------------------------------===//
391 MCSymbol *ARMAsmPrinter::
392 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393 const MachineBasicBlock *MBB) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
396 << getFunctionNumber() << '_' << uid << '_' << uid2
397 << "_set_" << MBB->getNumber();
398 return OutContext.GetOrCreateSymbol(Name.str());
401 MCSymbol *ARMAsmPrinter::
402 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403 SmallString<60> Name;
404 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
405 << getFunctionNumber() << '_' << uid << '_' << uid2;
406 return OutContext.GetOrCreateSymbol(Name.str());
410 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411 SmallString<60> Name;
412 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413 << getFunctionNumber();
414 return OutContext.GetOrCreateSymbol(Name.str());
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
418 unsigned AsmVariant, const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
425 default: return true; // Unknown modifier.
426 case 'a': // Print as a memory address.
427 if (MI->getOperand(OpNum).isReg()) {
429 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
434 case 'c': // Don't print "#" before an immediate operand.
435 if (!MI->getOperand(OpNum).isImm())
437 O << MI->getOperand(OpNum).getImm();
439 case 'P': // Print a VFP double precision register.
440 case 'q': // Print a NEON quad precision register.
441 printOperand(MI, OpNum, O);
443 case 'y': // Print a VFP single precision register as indexed double.
444 // This uses the ordering of the alias table to get the first 'd' register
445 // that overlaps the 's' register. Also, s0 is an odd register, hence the
446 // odd modulus check below.
447 if (MI->getOperand(OpNum).isReg()) {
448 unsigned Reg = MI->getOperand(OpNum).getReg();
449 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
450 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
451 (((Reg % 2) == 1) ? "[0]" : "[1]");
455 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
456 if (!MI->getOperand(OpNum).isImm())
458 O << ~(MI->getOperand(OpNum).getImm());
460 case 'L': // The low 16 bits of an immediate constant.
461 if (!MI->getOperand(OpNum).isImm())
463 O << (MI->getOperand(OpNum).getImm() & 0xffff);
465 case 'M': { // A register range suitable for LDM/STM.
466 if (!MI->getOperand(OpNum).isReg())
468 const MachineOperand &MO = MI->getOperand(OpNum);
469 unsigned RegBegin = MO.getReg();
470 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
471 // already got the operands in registers that are operands to the
472 // inline asm statement.
474 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
476 // FIXME: The register allocator not only may not have given us the
477 // registers in sequence, but may not be in ascending registers. This
478 // will require changes in the register allocator that'll need to be
479 // propagated down here if the operands change.
480 unsigned RegOps = OpNum + 1;
481 while (MI->getOperand(RegOps).isReg()) {
483 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
491 case 'R': // The most significant register of a pair.
492 case 'Q': { // The least significant register of a pair.
495 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
496 if (!FlagsOP.isImm())
498 unsigned Flags = FlagsOP.getImm();
499 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
502 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
503 if (RegOp >= MI->getNumOperands())
505 const MachineOperand &MO = MI->getOperand(RegOp);
508 unsigned Reg = MO.getReg();
509 O << ARMInstPrinter::getRegisterName(Reg);
513 case 'e': // The low doubleword register of a NEON quad register.
514 case 'f': { // The high doubleword register of a NEON quad register.
515 if (!MI->getOperand(OpNum).isReg())
517 unsigned Reg = MI->getOperand(OpNum).getReg();
518 if (!ARM::QPRRegClass.contains(Reg))
520 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
521 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
522 ARM::dsub_0 : ARM::dsub_1);
523 O << ARMInstPrinter::getRegisterName(SubReg);
527 // These modifiers are not yet supported.
528 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
529 case 'H': // The highest-numbered register of a pair.
534 printOperand(MI, OpNum, O);
538 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
539 unsigned OpNum, unsigned AsmVariant,
540 const char *ExtraCode,
542 // Does this asm operand have a single letter operand modifier?
543 if (ExtraCode && ExtraCode[0]) {
544 if (ExtraCode[1] != 0) return true; // Unknown modifier.
546 switch (ExtraCode[0]) {
547 case 'A': // A memory operand for a VLD1/VST1 instruction.
548 default: return true; // Unknown modifier.
549 case 'm': // The base register of a memory operand.
550 if (!MI->getOperand(OpNum).isReg())
552 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
557 const MachineOperand &MO = MI->getOperand(OpNum);
558 assert(MO.isReg() && "unexpected inline asm memory operand");
559 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
563 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
564 if (Subtarget->isTargetDarwin()) {
565 Reloc::Model RelocM = TM.getRelocationModel();
566 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
567 // Declare all the text sections up front (before the DWARF sections
568 // emitted by AsmPrinter::doInitialization) so the assembler will keep
569 // them together at the beginning of the object file. This helps
570 // avoid out-of-range branches that are due a fundamental limitation of
571 // the way symbol offsets are encoded with the current Darwin ARM
573 const TargetLoweringObjectFileMachO &TLOFMacho =
574 static_cast<const TargetLoweringObjectFileMachO &>(
575 getObjFileLowering());
576 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
577 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
578 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
579 if (RelocM == Reloc::DynamicNoPIC) {
580 const MCSection *sect =
581 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
582 MCSectionMachO::S_SYMBOL_STUBS,
583 12, SectionKind::getText());
584 OutStreamer.SwitchSection(sect);
586 const MCSection *sect =
587 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
588 MCSectionMachO::S_SYMBOL_STUBS,
589 16, SectionKind::getText());
590 OutStreamer.SwitchSection(sect);
592 const MCSection *StaticInitSect =
593 OutContext.getMachOSection("__TEXT", "__StaticInit",
594 MCSectionMachO::S_REGULAR |
595 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
596 SectionKind::getText());
597 OutStreamer.SwitchSection(StaticInitSect);
601 // Use unified assembler syntax.
602 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
604 // Emit ARM Build Attributes
605 if (Subtarget->isTargetELF())
610 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
611 if (Subtarget->isTargetDarwin()) {
612 // All darwin targets use mach-o.
613 const TargetLoweringObjectFileMachO &TLOFMacho =
614 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
615 MachineModuleInfoMachO &MMIMacho =
616 MMI->getObjFileInfo<MachineModuleInfoMachO>();
618 // Output non-lazy-pointers for external and common global variables.
619 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
621 if (!Stubs.empty()) {
622 // Switch with ".non_lazy_symbol_pointer" directive.
623 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
625 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
627 OutStreamer.EmitLabel(Stubs[i].first);
628 // .indirect_symbol _foo
629 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
630 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
633 // External to current translation unit.
634 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
636 // Internal to current translation unit.
638 // When we place the LSDA into the TEXT section, the type info
639 // pointers need to be indirect and pc-rel. We accomplish this by
640 // using NLPs; however, sometimes the types are local to the file.
641 // We need to fill in the value for the NLP in those cases.
642 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
644 4/*size*/, 0/*addrspace*/);
648 OutStreamer.AddBlankLine();
651 Stubs = MMIMacho.GetHiddenGVStubList();
652 if (!Stubs.empty()) {
653 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
655 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
657 OutStreamer.EmitLabel(Stubs[i].first);
659 OutStreamer.EmitValue(MCSymbolRefExpr::
660 Create(Stubs[i].second.getPointer(),
662 4/*size*/, 0/*addrspace*/);
666 OutStreamer.AddBlankLine();
669 // Funny Darwin hack: This flag tells the linker that no global symbols
670 // contain code that falls through to other global symbols (e.g. the obvious
671 // implementation of multiple entry points). If this doesn't occur, the
672 // linker can safely perform dead code stripping. Since LLVM never
673 // generates code that does this, it is always safe to set.
674 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
678 //===----------------------------------------------------------------------===//
679 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
681 // The following seem like one-off assembler flags, but they actually need
682 // to appear in the .ARM.attributes section in ELF.
683 // Instead of subclassing the MCELFStreamer, we do the work here.
685 void ARMAsmPrinter::emitAttributes() {
687 emitARMAttributeSection();
689 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
690 bool emitFPU = false;
691 AttributeEmitter *AttrEmitter;
692 if (OutStreamer.hasRawTextSupport()) {
693 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
696 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
697 AttrEmitter = new ObjectAttributeEmitter(O);
700 AttrEmitter->MaybeSwitchVendor("aeabi");
702 std::string CPUString = Subtarget->getCPUString();
704 if (CPUString == "cortex-a8" ||
705 Subtarget->isCortexA8()) {
706 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
707 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
708 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
709 ARMBuildAttrs::ApplicationProfile);
710 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
711 ARMBuildAttrs::Allowed);
712 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
713 ARMBuildAttrs::AllowThumb32);
714 // Fixme: figure out when this is emitted.
715 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
716 // ARMBuildAttrs::AllowWMMXv1);
719 /// ADD additional Else-cases here!
720 } else if (CPUString == "xscale") {
721 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
722 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
723 ARMBuildAttrs::Allowed);
724 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
725 ARMBuildAttrs::Allowed);
726 } else if (CPUString == "generic") {
727 // FIXME: Why these defaults?
728 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
729 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
730 ARMBuildAttrs::Allowed);
731 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
732 ARMBuildAttrs::Allowed);
735 if (Subtarget->hasNEON() && emitFPU) {
736 /* NEON is not exactly a VFP architecture, but GAS emit one of
737 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
738 if (Subtarget->hasVFP4())
739 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
742 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
743 /* If emitted for NEON, omit from VFP below, since you can have both
744 * NEON and VFP in build attributes but only one .fpu */
749 if (Subtarget->hasVFP4()) {
750 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
751 ARMBuildAttrs::AllowFPv4A);
753 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
756 } else if (Subtarget->hasVFP3()) {
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
758 ARMBuildAttrs::AllowFPv3A);
760 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
763 } else if (Subtarget->hasVFP2()) {
764 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
765 ARMBuildAttrs::AllowFPv2);
767 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
770 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
771 * since NEON can have 1 (allowed) or 2 (MAC operations) */
772 if (Subtarget->hasNEON()) {
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
774 ARMBuildAttrs::Allowed);
777 // Signal various FP modes.
778 if (!TM.Options.UnsafeFPMath) {
779 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
780 ARMBuildAttrs::Allowed);
781 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
782 ARMBuildAttrs::Allowed);
785 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
786 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
787 ARMBuildAttrs::Allowed);
789 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
790 ARMBuildAttrs::AllowIEE754);
792 // FIXME: add more flags to ARMBuildAttrs.h
793 // 8-bytes alignment stuff.
794 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
795 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
797 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
798 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
799 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
800 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
802 // FIXME: Should we signal R9 usage?
804 if (Subtarget->hasDivide())
805 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
807 AttrEmitter->Finish();
811 void ARMAsmPrinter::emitARMAttributeSection() {
813 // [ <section-length> "vendor-name"
814 // [ <file-tag> <size> <attribute>*
815 // | <section-tag> <size> <section-number>* 0 <attribute>*
816 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
820 if (OutStreamer.hasRawTextSupport())
823 const ARMElfTargetObjectFile &TLOFELF =
824 static_cast<const ARMElfTargetObjectFile &>
825 (getObjFileLowering());
827 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
830 OutStreamer.EmitIntValue(0x41, 1);
833 //===----------------------------------------------------------------------===//
835 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
836 unsigned LabelId, MCContext &Ctx) {
838 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
839 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
843 static MCSymbolRefExpr::VariantKind
844 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
846 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
847 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
848 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
849 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
850 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
851 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
853 llvm_unreachable("Invalid ARMCPModifier!");
856 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
857 bool isIndirect = Subtarget->isTargetDarwin() &&
858 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
860 return Mang->getSymbol(GV);
862 // FIXME: Remove this when Darwin transition to @GOT like syntax.
863 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
864 MachineModuleInfoMachO &MMIMachO =
865 MMI->getObjFileInfo<MachineModuleInfoMachO>();
866 MachineModuleInfoImpl::StubValueTy &StubSym =
867 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
868 MMIMachO.getGVStubEntry(MCSym);
869 if (StubSym.getPointer() == 0)
870 StubSym = MachineModuleInfoImpl::
871 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
876 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
877 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
879 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
882 if (ACPV->isLSDA()) {
883 SmallString<128> Str;
884 raw_svector_ostream OS(Str);
885 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
886 MCSym = OutContext.GetOrCreateSymbol(OS.str());
887 } else if (ACPV->isBlockAddress()) {
888 const BlockAddress *BA =
889 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
890 MCSym = GetBlockAddressSymbol(BA);
891 } else if (ACPV->isGlobalValue()) {
892 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
893 MCSym = GetARMGVSymbol(GV);
894 } else if (ACPV->isMachineBasicBlock()) {
895 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
896 MCSym = MBB->getSymbol();
898 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
899 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
900 MCSym = GetExternalSymbolSymbol(Sym);
903 // Create an MCSymbol for the reference.
905 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
908 if (ACPV->getPCAdjustment()) {
909 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
913 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
915 MCBinaryExpr::CreateAdd(PCRelExpr,
916 MCConstantExpr::Create(ACPV->getPCAdjustment(),
919 if (ACPV->mustAddCurrentAddress()) {
920 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
921 // label, so just emit a local label end reference that instead.
922 MCSymbol *DotSym = OutContext.CreateTempSymbol();
923 OutStreamer.EmitLabel(DotSym);
924 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
925 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
927 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
929 OutStreamer.EmitValue(Expr, Size);
932 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
933 unsigned Opcode = MI->getOpcode();
935 if (Opcode == ARM::BR_JTadd)
937 else if (Opcode == ARM::BR_JTm)
940 const MachineOperand &MO1 = MI->getOperand(OpNum);
941 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
942 unsigned JTI = MO1.getIndex();
944 // Emit a label for the jump table.
945 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
946 OutStreamer.EmitLabel(JTISymbol);
948 // Mark the jump table as data-in-code.
949 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
951 // Emit each entry of the table.
952 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
953 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
954 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
956 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
957 MachineBasicBlock *MBB = JTBBs[i];
958 // Construct an MCExpr for the entry. We want a value of the form:
959 // (BasicBlockAddr - TableBeginAddr)
961 // For example, a table with entries jumping to basic blocks BB0 and BB1
964 // .word (LBB0 - LJTI_0_0)
965 // .word (LBB1 - LJTI_0_0)
966 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
968 if (TM.getRelocationModel() == Reloc::PIC_)
969 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
972 // If we're generating a table of Thumb addresses in static relocation
973 // model, we need to add one to keep interworking correctly.
974 else if (AFI->isThumbFunction())
975 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
977 OutStreamer.EmitValue(Expr, 4);
979 // Mark the end of jump table data-in-code region.
980 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
983 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
984 unsigned Opcode = MI->getOpcode();
985 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
986 const MachineOperand &MO1 = MI->getOperand(OpNum);
987 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
988 unsigned JTI = MO1.getIndex();
990 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
991 OutStreamer.EmitLabel(JTISymbol);
993 // Emit each entry of the table.
994 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
995 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
996 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
997 unsigned OffsetWidth = 4;
998 if (MI->getOpcode() == ARM::t2TBB_JT) {
1000 // Mark the jump table as data-in-code.
1001 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1002 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1004 // Mark the jump table as data-in-code.
1005 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1008 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1009 MachineBasicBlock *MBB = JTBBs[i];
1010 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1012 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1013 if (OffsetWidth == 4) {
1015 BrInst.setOpcode(ARM::t2B);
1016 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1017 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1018 BrInst.addOperand(MCOperand::CreateReg(0));
1019 OutStreamer.EmitInstruction(BrInst);
1022 // Otherwise it's an offset from the dispatch instruction. Construct an
1023 // MCExpr for the entry. We want a value of the form:
1024 // (BasicBlockAddr - TableBeginAddr) / 2
1026 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1029 // .byte (LBB0 - LJTI_0_0) / 2
1030 // .byte (LBB1 - LJTI_0_0) / 2
1031 const MCExpr *Expr =
1032 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1033 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1035 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1037 OutStreamer.EmitValue(Expr, OffsetWidth);
1039 // Mark the end of jump table data-in-code region.
1040 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1043 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1045 unsigned NOps = MI->getNumOperands();
1047 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1048 // cast away const; DIetc do not take const operands for some reason.
1049 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1052 // Frame address. Currently handles register +- offset only.
1053 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1054 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1057 printOperand(MI, NOps-2, OS);
1060 static void populateADROperands(MCInst &Inst, unsigned Dest,
1061 const MCSymbol *Label,
1062 unsigned pred, unsigned ccreg,
1064 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1065 Inst.addOperand(MCOperand::CreateReg(Dest));
1066 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1067 // Add predicate operands.
1068 Inst.addOperand(MCOperand::CreateImm(pred));
1069 Inst.addOperand(MCOperand::CreateReg(ccreg));
1072 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1076 // Emit the instruction as usual, just patch the opcode.
1077 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1078 TmpInst.setOpcode(Opcode);
1079 OutStreamer.EmitInstruction(TmpInst);
1082 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1083 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1084 "Only instruction which are involved into frame setup code are allowed");
1086 const MachineFunction &MF = *MI->getParent()->getParent();
1087 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1088 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1090 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1091 unsigned Opc = MI->getOpcode();
1092 unsigned SrcReg, DstReg;
1094 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1095 // Two special cases:
1096 // 1) tPUSH does not have src/dst regs.
1097 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1098 // load. Yes, this is pretty fragile, but for now I don't see better
1100 SrcReg = DstReg = ARM::SP;
1102 SrcReg = MI->getOperand(1).getReg();
1103 DstReg = MI->getOperand(0).getReg();
1106 // Try to figure out the unwinding opcode out of src / dst regs.
1107 if (MI->mayStore()) {
1109 assert(DstReg == ARM::SP &&
1110 "Only stack pointer as a destination reg is supported");
1112 SmallVector<unsigned, 4> RegList;
1113 // Skip src & dst reg, and pred ops.
1114 unsigned StartOp = 2 + 2;
1115 // Use all the operands.
1116 unsigned NumOffset = 0;
1121 llvm_unreachable("Unsupported opcode for unwinding information");
1123 // Special case here: no src & dst reg, but two extra imp ops.
1124 StartOp = 2; NumOffset = 2;
1125 case ARM::STMDB_UPD:
1126 case ARM::t2STMDB_UPD:
1127 case ARM::VSTMDDB_UPD:
1128 assert(SrcReg == ARM::SP &&
1129 "Only stack pointer as a source reg is supported");
1130 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1132 RegList.push_back(MI->getOperand(i).getReg());
1134 case ARM::STR_PRE_IMM:
1135 case ARM::STR_PRE_REG:
1136 case ARM::t2STR_PRE:
1137 assert(MI->getOperand(2).getReg() == ARM::SP &&
1138 "Only stack pointer as a source reg is supported");
1139 RegList.push_back(SrcReg);
1142 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1144 // Changes of stack / frame pointer.
1145 if (SrcReg == ARM::SP) {
1150 llvm_unreachable("Unsupported opcode for unwinding information");
1156 Offset = -MI->getOperand(2).getImm();
1160 Offset = MI->getOperand(2).getImm();
1163 Offset = MI->getOperand(2).getImm()*4;
1167 Offset = -MI->getOperand(2).getImm()*4;
1169 case ARM::tLDRpci: {
1170 // Grab the constpool index and check, whether it corresponds to
1171 // original or cloned constpool entry.
1172 unsigned CPI = MI->getOperand(1).getIndex();
1173 const MachineConstantPool *MCP = MF.getConstantPool();
1174 if (CPI >= MCP->getConstants().size())
1175 CPI = AFI.getOriginalCPIdx(CPI);
1176 assert(CPI != -1U && "Invalid constpool index");
1178 // Derive the actual offset.
1179 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1180 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1181 // FIXME: Check for user, it should be "add" instruction!
1182 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1187 if (DstReg == FramePtr && FramePtr != ARM::SP)
1188 // Set-up of the frame pointer. Positive values correspond to "add"
1190 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1191 else if (DstReg == ARM::SP) {
1192 // Change of SP by an offset. Positive values correspond to "sub"
1194 OutStreamer.EmitPad(Offset);
1197 llvm_unreachable("Unsupported opcode for unwinding information");
1199 } else if (DstReg == ARM::SP) {
1200 // FIXME: .movsp goes here
1202 llvm_unreachable("Unsupported opcode for unwinding information");
1206 llvm_unreachable("Unsupported opcode for unwinding information");
1211 extern cl::opt<bool> EnableARMEHABI;
1213 // Simple pseudo-instructions have their lowering (with expansion to real
1214 // instructions) auto-generated.
1215 #include "ARMGenMCPseudoLowering.inc"
1217 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1218 // If we just ended a constant pool, mark it as such.
1219 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1220 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1221 InConstantPool = false;
1224 // Emit unwinding stuff for frame-related instructions
1225 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1226 EmitUnwindingInstruction(MI);
1228 // Do any auto-generated pseudo lowerings.
1229 if (emitPseudoExpansionLowering(OutStreamer, MI))
1232 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1233 "Pseudo flag setting opcode should be expanded early");
1235 // Check for manual lowerings.
1236 unsigned Opc = MI->getOpcode();
1238 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1239 case ARM::DBG_VALUE: {
1240 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1241 SmallString<128> TmpStr;
1242 raw_svector_ostream OS(TmpStr);
1243 PrintDebugValueComment(MI, OS);
1244 OutStreamer.EmitRawText(StringRef(OS.str()));
1249 case ARM::tLEApcrel:
1250 case ARM::t2LEApcrel: {
1251 // FIXME: Need to also handle globals and externals
1253 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1254 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1256 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1257 GetCPISymbol(MI->getOperand(1).getIndex()),
1258 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1260 OutStreamer.EmitInstruction(TmpInst);
1263 case ARM::LEApcrelJT:
1264 case ARM::tLEApcrelJT:
1265 case ARM::t2LEApcrelJT: {
1267 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1268 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1270 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1271 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1272 MI->getOperand(2).getImm()),
1273 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1275 OutStreamer.EmitInstruction(TmpInst);
1278 // Darwin call instructions are just normal call instructions with different
1279 // clobber semantics (they clobber R9).
1280 case ARM::BX_CALL: {
1283 TmpInst.setOpcode(ARM::MOVr);
1284 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1285 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1286 // Add predicate operands.
1287 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1288 TmpInst.addOperand(MCOperand::CreateReg(0));
1289 // Add 's' bit operand (always reg0 for this)
1290 TmpInst.addOperand(MCOperand::CreateReg(0));
1291 OutStreamer.EmitInstruction(TmpInst);
1295 TmpInst.setOpcode(ARM::BX);
1296 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1297 OutStreamer.EmitInstruction(TmpInst);
1301 case ARM::tBX_CALL: {
1304 TmpInst.setOpcode(ARM::tMOVr);
1305 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1306 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1307 // Add predicate operands.
1308 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1309 TmpInst.addOperand(MCOperand::CreateReg(0));
1310 OutStreamer.EmitInstruction(TmpInst);
1314 TmpInst.setOpcode(ARM::tBX);
1315 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1316 // Add predicate operands.
1317 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1318 TmpInst.addOperand(MCOperand::CreateReg(0));
1319 OutStreamer.EmitInstruction(TmpInst);
1323 case ARM::BMOVPCRX_CALL: {
1326 TmpInst.setOpcode(ARM::MOVr);
1327 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1329 // Add predicate operands.
1330 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1331 TmpInst.addOperand(MCOperand::CreateReg(0));
1332 // Add 's' bit operand (always reg0 for this)
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 OutStreamer.EmitInstruction(TmpInst);
1338 TmpInst.setOpcode(ARM::MOVr);
1339 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1340 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1341 // Add predicate operands.
1342 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1343 TmpInst.addOperand(MCOperand::CreateReg(0));
1344 // Add 's' bit operand (always reg0 for this)
1345 TmpInst.addOperand(MCOperand::CreateReg(0));
1346 OutStreamer.EmitInstruction(TmpInst);
1350 case ARM::BMOVPCB_CALL: {
1353 TmpInst.setOpcode(ARM::MOVr);
1354 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1355 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1356 // Add predicate operands.
1357 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1358 TmpInst.addOperand(MCOperand::CreateReg(0));
1359 // Add 's' bit operand (always reg0 for this)
1360 TmpInst.addOperand(MCOperand::CreateReg(0));
1361 OutStreamer.EmitInstruction(TmpInst);
1365 TmpInst.setOpcode(ARM::Bcc);
1366 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1367 MCSymbol *GVSym = Mang->getSymbol(GV);
1368 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1369 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1370 // Add predicate operands.
1371 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1372 TmpInst.addOperand(MCOperand::CreateReg(0));
1373 OutStreamer.EmitInstruction(TmpInst);
1377 case ARM::t2BMOVPCB_CALL: {
1380 TmpInst.setOpcode(ARM::tMOVr);
1381 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1382 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1383 // Add predicate operands.
1384 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1385 TmpInst.addOperand(MCOperand::CreateReg(0));
1386 OutStreamer.EmitInstruction(TmpInst);
1390 TmpInst.setOpcode(ARM::t2B);
1391 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1392 MCSymbol *GVSym = Mang->getSymbol(GV);
1393 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1394 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1395 // Add predicate operands.
1396 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1397 TmpInst.addOperand(MCOperand::CreateReg(0));
1398 OutStreamer.EmitInstruction(TmpInst);
1402 case ARM::MOVi16_ga_pcrel:
1403 case ARM::t2MOVi16_ga_pcrel: {
1405 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1406 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1408 unsigned TF = MI->getOperand(1).getTargetFlags();
1409 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1410 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1411 MCSymbol *GVSym = GetARMGVSymbol(GV);
1412 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1414 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1415 getFunctionNumber(),
1416 MI->getOperand(2).getImm(), OutContext);
1417 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1418 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1419 const MCExpr *PCRelExpr =
1420 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1421 MCBinaryExpr::CreateAdd(LabelSymExpr,
1422 MCConstantExpr::Create(PCAdj, OutContext),
1423 OutContext), OutContext), OutContext);
1424 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1426 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1427 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1430 // Add predicate operands.
1431 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1432 TmpInst.addOperand(MCOperand::CreateReg(0));
1433 // Add 's' bit operand (always reg0 for this)
1434 TmpInst.addOperand(MCOperand::CreateReg(0));
1435 OutStreamer.EmitInstruction(TmpInst);
1438 case ARM::MOVTi16_ga_pcrel:
1439 case ARM::t2MOVTi16_ga_pcrel: {
1441 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1442 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1443 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1444 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1446 unsigned TF = MI->getOperand(2).getTargetFlags();
1447 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1448 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1449 MCSymbol *GVSym = GetARMGVSymbol(GV);
1450 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1452 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1453 getFunctionNumber(),
1454 MI->getOperand(3).getImm(), OutContext);
1455 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1456 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1457 const MCExpr *PCRelExpr =
1458 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1459 MCBinaryExpr::CreateAdd(LabelSymExpr,
1460 MCConstantExpr::Create(PCAdj, OutContext),
1461 OutContext), OutContext), OutContext);
1462 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1464 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1465 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1467 // Add predicate operands.
1468 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1469 TmpInst.addOperand(MCOperand::CreateReg(0));
1470 // Add 's' bit operand (always reg0 for this)
1471 TmpInst.addOperand(MCOperand::CreateReg(0));
1472 OutStreamer.EmitInstruction(TmpInst);
1475 case ARM::tPICADD: {
1476 // This is a pseudo op for a label + instruction sequence, which looks like:
1479 // This adds the address of LPC0 to r0.
1482 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1483 getFunctionNumber(), MI->getOperand(2).getImm(),
1486 // Form and emit the add.
1488 AddInst.setOpcode(ARM::tADDhirr);
1489 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1490 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1491 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1492 // Add predicate operands.
1493 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1494 AddInst.addOperand(MCOperand::CreateReg(0));
1495 OutStreamer.EmitInstruction(AddInst);
1499 // This is a pseudo op for a label + instruction sequence, which looks like:
1502 // This adds the address of LPC0 to r0.
1505 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1506 getFunctionNumber(), MI->getOperand(2).getImm(),
1509 // Form and emit the add.
1511 AddInst.setOpcode(ARM::ADDrr);
1512 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1513 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1514 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1515 // Add predicate operands.
1516 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1517 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1518 // Add 's' bit operand (always reg0 for this)
1519 AddInst.addOperand(MCOperand::CreateReg(0));
1520 OutStreamer.EmitInstruction(AddInst);
1530 case ARM::PICLDRSH: {
1531 // This is a pseudo op for a label + instruction sequence, which looks like:
1534 // The LCP0 label is referenced by a constant pool entry in order to get
1535 // a PC-relative address at the ldr instruction.
1538 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1539 getFunctionNumber(), MI->getOperand(2).getImm(),
1542 // Form and emit the load
1544 switch (MI->getOpcode()) {
1546 llvm_unreachable("Unexpected opcode!");
1547 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1548 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1549 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1550 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1551 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1552 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1553 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1554 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1557 LdStInst.setOpcode(Opcode);
1558 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1559 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1560 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1561 LdStInst.addOperand(MCOperand::CreateImm(0));
1562 // Add predicate operands.
1563 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1564 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1565 OutStreamer.EmitInstruction(LdStInst);
1569 case ARM::CONSTPOOL_ENTRY: {
1570 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1571 /// in the function. The first operand is the ID# for this instruction, the
1572 /// second is the index into the MachineConstantPool that this is, the third
1573 /// is the size in bytes of this constant pool entry.
1574 /// The required alignment is specified on the basic block holding this MI.
1575 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1576 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1578 // If this is the first entry of the pool, mark it.
1579 if (!InConstantPool) {
1580 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1581 InConstantPool = true;
1584 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1586 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1587 if (MCPE.isMachineConstantPoolEntry())
1588 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1590 EmitGlobalConstant(MCPE.Val.ConstVal);
1593 case ARM::t2BR_JT: {
1594 // Lower and emit the instruction itself, then the jump table following it.
1596 TmpInst.setOpcode(ARM::tMOVr);
1597 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1598 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1599 // Add predicate operands.
1600 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1601 TmpInst.addOperand(MCOperand::CreateReg(0));
1602 OutStreamer.EmitInstruction(TmpInst);
1603 // Output the data for the jump table itself
1607 case ARM::t2TBB_JT: {
1608 // Lower and emit the instruction itself, then the jump table following it.
1611 TmpInst.setOpcode(ARM::t2TBB);
1612 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1613 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1614 // Add predicate operands.
1615 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1616 TmpInst.addOperand(MCOperand::CreateReg(0));
1617 OutStreamer.EmitInstruction(TmpInst);
1618 // Output the data for the jump table itself
1620 // Make sure the next instruction is 2-byte aligned.
1624 case ARM::t2TBH_JT: {
1625 // Lower and emit the instruction itself, then the jump table following it.
1628 TmpInst.setOpcode(ARM::t2TBH);
1629 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1630 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1631 // Add predicate operands.
1632 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1633 TmpInst.addOperand(MCOperand::CreateReg(0));
1634 OutStreamer.EmitInstruction(TmpInst);
1635 // Output the data for the jump table itself
1641 // Lower and emit the instruction itself, then the jump table following it.
1644 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1645 ARM::MOVr : ARM::tMOVr;
1646 TmpInst.setOpcode(Opc);
1647 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1648 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1649 // Add predicate operands.
1650 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1651 TmpInst.addOperand(MCOperand::CreateReg(0));
1652 // Add 's' bit operand (always reg0 for this)
1653 if (Opc == ARM::MOVr)
1654 TmpInst.addOperand(MCOperand::CreateReg(0));
1655 OutStreamer.EmitInstruction(TmpInst);
1657 // Make sure the Thumb jump table is 4-byte aligned.
1658 if (Opc == ARM::tMOVr)
1661 // Output the data for the jump table itself
1666 // Lower and emit the instruction itself, then the jump table following it.
1669 if (MI->getOperand(1).getReg() == 0) {
1671 TmpInst.setOpcode(ARM::LDRi12);
1672 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1673 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1674 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1676 TmpInst.setOpcode(ARM::LDRrs);
1677 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1678 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1679 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1680 TmpInst.addOperand(MCOperand::CreateImm(0));
1682 // Add predicate operands.
1683 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1684 TmpInst.addOperand(MCOperand::CreateReg(0));
1685 OutStreamer.EmitInstruction(TmpInst);
1687 // Output the data for the jump table itself
1691 case ARM::BR_JTadd: {
1692 // Lower and emit the instruction itself, then the jump table following it.
1693 // add pc, target, idx
1695 TmpInst.setOpcode(ARM::ADDrr);
1696 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1697 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1698 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1699 // Add predicate operands.
1700 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1701 TmpInst.addOperand(MCOperand::CreateReg(0));
1702 // Add 's' bit operand (always reg0 for this)
1703 TmpInst.addOperand(MCOperand::CreateReg(0));
1704 OutStreamer.EmitInstruction(TmpInst);
1706 // Output the data for the jump table itself
1711 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1712 // FIXME: Remove this special case when they do.
1713 if (!Subtarget->isTargetDarwin()) {
1714 //.long 0xe7ffdefe @ trap
1715 uint32_t Val = 0xe7ffdefeUL;
1716 OutStreamer.AddComment("trap");
1717 OutStreamer.EmitIntValue(Val, 4);
1723 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1724 // FIXME: Remove this special case when they do.
1725 if (!Subtarget->isTargetDarwin()) {
1726 //.short 57086 @ trap
1727 uint16_t Val = 0xdefe;
1728 OutStreamer.AddComment("trap");
1729 OutStreamer.EmitIntValue(Val, 2);
1734 case ARM::t2Int_eh_sjlj_setjmp:
1735 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1736 case ARM::tInt_eh_sjlj_setjmp: {
1737 // Two incoming args: GPR:$src, GPR:$val
1740 // str $val, [$src, #4]
1745 unsigned SrcReg = MI->getOperand(0).getReg();
1746 unsigned ValReg = MI->getOperand(1).getReg();
1747 MCSymbol *Label = GetARMSJLJEHLabel();
1750 TmpInst.setOpcode(ARM::tMOVr);
1751 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1752 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1754 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1755 TmpInst.addOperand(MCOperand::CreateReg(0));
1756 OutStreamer.AddComment("eh_setjmp begin");
1757 OutStreamer.EmitInstruction(TmpInst);
1761 TmpInst.setOpcode(ARM::tADDi3);
1762 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1764 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1765 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1766 TmpInst.addOperand(MCOperand::CreateImm(7));
1768 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1769 TmpInst.addOperand(MCOperand::CreateReg(0));
1770 OutStreamer.EmitInstruction(TmpInst);
1774 TmpInst.setOpcode(ARM::tSTRi);
1775 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1776 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1777 // The offset immediate is #4. The operand value is scaled by 4 for the
1778 // tSTR instruction.
1779 TmpInst.addOperand(MCOperand::CreateImm(1));
1781 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1782 TmpInst.addOperand(MCOperand::CreateReg(0));
1783 OutStreamer.EmitInstruction(TmpInst);
1787 TmpInst.setOpcode(ARM::tMOVi8);
1788 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1789 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1790 TmpInst.addOperand(MCOperand::CreateImm(0));
1792 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1793 TmpInst.addOperand(MCOperand::CreateReg(0));
1794 OutStreamer.EmitInstruction(TmpInst);
1797 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1799 TmpInst.setOpcode(ARM::tB);
1800 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1801 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1802 TmpInst.addOperand(MCOperand::CreateReg(0));
1803 OutStreamer.EmitInstruction(TmpInst);
1807 TmpInst.setOpcode(ARM::tMOVi8);
1808 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1809 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1810 TmpInst.addOperand(MCOperand::CreateImm(1));
1812 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1813 TmpInst.addOperand(MCOperand::CreateReg(0));
1814 OutStreamer.AddComment("eh_setjmp end");
1815 OutStreamer.EmitInstruction(TmpInst);
1817 OutStreamer.EmitLabel(Label);
1821 case ARM::Int_eh_sjlj_setjmp_nofp:
1822 case ARM::Int_eh_sjlj_setjmp: {
1823 // Two incoming args: GPR:$src, GPR:$val
1825 // str $val, [$src, #+4]
1829 unsigned SrcReg = MI->getOperand(0).getReg();
1830 unsigned ValReg = MI->getOperand(1).getReg();
1834 TmpInst.setOpcode(ARM::ADDri);
1835 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1836 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1837 TmpInst.addOperand(MCOperand::CreateImm(8));
1839 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1840 TmpInst.addOperand(MCOperand::CreateReg(0));
1841 // 's' bit operand (always reg0 for this).
1842 TmpInst.addOperand(MCOperand::CreateReg(0));
1843 OutStreamer.AddComment("eh_setjmp begin");
1844 OutStreamer.EmitInstruction(TmpInst);
1848 TmpInst.setOpcode(ARM::STRi12);
1849 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1850 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1851 TmpInst.addOperand(MCOperand::CreateImm(4));
1853 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1854 TmpInst.addOperand(MCOperand::CreateReg(0));
1855 OutStreamer.EmitInstruction(TmpInst);
1859 TmpInst.setOpcode(ARM::MOVi);
1860 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1861 TmpInst.addOperand(MCOperand::CreateImm(0));
1863 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1864 TmpInst.addOperand(MCOperand::CreateReg(0));
1865 // 's' bit operand (always reg0 for this).
1866 TmpInst.addOperand(MCOperand::CreateReg(0));
1867 OutStreamer.EmitInstruction(TmpInst);
1871 TmpInst.setOpcode(ARM::ADDri);
1872 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1873 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1874 TmpInst.addOperand(MCOperand::CreateImm(0));
1876 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1877 TmpInst.addOperand(MCOperand::CreateReg(0));
1878 // 's' bit operand (always reg0 for this).
1879 TmpInst.addOperand(MCOperand::CreateReg(0));
1880 OutStreamer.EmitInstruction(TmpInst);
1884 TmpInst.setOpcode(ARM::MOVi);
1885 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1886 TmpInst.addOperand(MCOperand::CreateImm(1));
1888 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1889 TmpInst.addOperand(MCOperand::CreateReg(0));
1890 // 's' bit operand (always reg0 for this).
1891 TmpInst.addOperand(MCOperand::CreateReg(0));
1892 OutStreamer.AddComment("eh_setjmp end");
1893 OutStreamer.EmitInstruction(TmpInst);
1897 case ARM::Int_eh_sjlj_longjmp: {
1898 // ldr sp, [$src, #8]
1899 // ldr $scratch, [$src, #4]
1902 unsigned SrcReg = MI->getOperand(0).getReg();
1903 unsigned ScratchReg = MI->getOperand(1).getReg();
1906 TmpInst.setOpcode(ARM::LDRi12);
1907 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1908 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1909 TmpInst.addOperand(MCOperand::CreateImm(8));
1911 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1912 TmpInst.addOperand(MCOperand::CreateReg(0));
1913 OutStreamer.EmitInstruction(TmpInst);
1917 TmpInst.setOpcode(ARM::LDRi12);
1918 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1919 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1920 TmpInst.addOperand(MCOperand::CreateImm(4));
1922 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1923 TmpInst.addOperand(MCOperand::CreateReg(0));
1924 OutStreamer.EmitInstruction(TmpInst);
1928 TmpInst.setOpcode(ARM::LDRi12);
1929 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1930 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1931 TmpInst.addOperand(MCOperand::CreateImm(0));
1933 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1934 TmpInst.addOperand(MCOperand::CreateReg(0));
1935 OutStreamer.EmitInstruction(TmpInst);
1939 TmpInst.setOpcode(ARM::BX);
1940 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1942 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1943 TmpInst.addOperand(MCOperand::CreateReg(0));
1944 OutStreamer.EmitInstruction(TmpInst);
1948 case ARM::tInt_eh_sjlj_longjmp: {
1949 // ldr $scratch, [$src, #8]
1951 // ldr $scratch, [$src, #4]
1954 unsigned SrcReg = MI->getOperand(0).getReg();
1955 unsigned ScratchReg = MI->getOperand(1).getReg();
1958 TmpInst.setOpcode(ARM::tLDRi);
1959 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1960 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1961 // The offset immediate is #8. The operand value is scaled by 4 for the
1962 // tLDR instruction.
1963 TmpInst.addOperand(MCOperand::CreateImm(2));
1965 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1966 TmpInst.addOperand(MCOperand::CreateReg(0));
1967 OutStreamer.EmitInstruction(TmpInst);
1971 TmpInst.setOpcode(ARM::tMOVr);
1972 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1973 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1975 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1976 TmpInst.addOperand(MCOperand::CreateReg(0));
1977 OutStreamer.EmitInstruction(TmpInst);
1981 TmpInst.setOpcode(ARM::tLDRi);
1982 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1983 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1984 TmpInst.addOperand(MCOperand::CreateImm(1));
1986 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1987 TmpInst.addOperand(MCOperand::CreateReg(0));
1988 OutStreamer.EmitInstruction(TmpInst);
1992 TmpInst.setOpcode(ARM::tLDRi);
1993 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1994 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1995 TmpInst.addOperand(MCOperand::CreateImm(0));
1997 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1998 TmpInst.addOperand(MCOperand::CreateReg(0));
1999 OutStreamer.EmitInstruction(TmpInst);
2003 TmpInst.setOpcode(ARM::tBX);
2004 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2006 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2007 TmpInst.addOperand(MCOperand::CreateReg(0));
2008 OutStreamer.EmitInstruction(TmpInst);
2015 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2017 OutStreamer.EmitInstruction(TmpInst);
2020 //===----------------------------------------------------------------------===//
2021 // Target Registry Stuff
2022 //===----------------------------------------------------------------------===//
2024 // Force static initialization.
2025 extern "C" void LLVMInitializeARMAsmPrinter() {
2026 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2027 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);