1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
57 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
58 cl::desc("enable experimental asmprinter gunk in the arm backend"));
70 class ARMAsmPrinter : public AsmPrinter {
72 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
73 /// make the right decision when printing asm code for different targets.
74 const ARMSubtarget *Subtarget;
76 /// AFI - Keep a pointer to ARMFunctionInfo for the current
80 /// MCP - Keep a pointer to constantpool entries of the current
82 const MachineConstantPool *MCP;
85 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
86 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
87 Subtarget = &TM.getSubtarget<ARMSubtarget>();
90 virtual const char *getPassName() const {
91 return "ARM Assembly Printer";
94 void printInstructionThroughMCStreamer(const MachineInstr *MI);
97 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
98 const char *Modifier = 0);
99 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
100 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
102 void printSORegOperand(const MachineInstr *MI, int OpNum,
104 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
106 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
108 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
110 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
112 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
113 const char *Modifier = 0);
114 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
115 const char *Modifier = 0);
116 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
118 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
120 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
122 const char *Modifier = 0);
123 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
125 void printMemBOption(const MachineInstr *MI, int OpNum,
127 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
130 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
132 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
133 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
135 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
138 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
140 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
142 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
147 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
148 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
150 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
152 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
154 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
156 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
158 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
161 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
163 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
165 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
167 void printPredicateOperand(const MachineInstr *MI, int OpNum,
169 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
171 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
173 void printPCLabel(const MachineInstr *MI, int OpNum,
175 void printRegisterList(const MachineInstr *MI, int OpNum,
177 void printCPInstOperand(const MachineInstr *MI, int OpNum,
179 const char *Modifier);
180 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
182 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
184 void printTBAddrMode(const MachineInstr *MI, int OpNum,
186 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
188 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
190 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
192 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
195 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
196 unsigned AsmVariant, const char *ExtraCode,
198 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
200 const char *ExtraCode, raw_ostream &O);
202 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
203 static const char *getRegisterName(unsigned RegNo);
205 virtual void EmitInstruction(const MachineInstr *MI);
206 bool runOnMachineFunction(MachineFunction &F);
208 virtual void EmitConstantPool() {} // we emit constant pools customly!
209 virtual void EmitFunctionEntryLabel();
210 void EmitStartOfAsmFile(Module &M);
211 void EmitEndOfAsmFile(Module &M);
213 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 virtual unsigned getISAEncoding() {
226 // ARM/Darwin adds ISA to the DWARF info for each function.
227 if (!Subtarget->isTargetDarwin())
229 return Subtarget->isThumb() ?
230 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
233 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
234 const MachineBasicBlock *MBB) const;
235 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
237 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
239 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
240 SmallString<128> Str;
241 raw_svector_ostream OS(Str);
242 EmitMachineConstantPoolValue(MCPV, OS);
243 OutStreamer.EmitRawText(OS.str());
246 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
248 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
249 case 1: O << MAI->getData8bitsDirective(0); break;
250 case 2: O << MAI->getData16bitsDirective(0); break;
251 case 4: O << MAI->getData32bitsDirective(0); break;
252 default: assert(0 && "Unknown CPV size");
255 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
257 if (ACPV->isLSDA()) {
258 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
259 } else if (ACPV->isBlockAddress()) {
260 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
261 } else if (ACPV->isGlobalValue()) {
262 const GlobalValue *GV = ACPV->getGV();
263 bool isIndirect = Subtarget->isTargetDarwin() &&
264 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
266 O << *Mang->getSymbol(GV);
268 // FIXME: Remove this when Darwin transition to @GOT like syntax.
269 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
272 MachineModuleInfoMachO &MMIMachO =
273 MMI->getObjFileInfo<MachineModuleInfoMachO>();
274 MachineModuleInfoImpl::StubValueTy &StubSym =
275 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
276 MMIMachO.getGVStubEntry(Sym);
277 if (StubSym.getPointer() == 0)
278 StubSym = MachineModuleInfoImpl::
279 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
282 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
283 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
286 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
287 if (ACPV->getPCAdjustment() != 0) {
288 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
289 << getFunctionNumber() << "_" << ACPV->getLabelId()
290 << "+" << (unsigned)ACPV->getPCAdjustment();
291 if (ACPV->mustAddCurrentAddress())
297 } // end of anonymous namespace
299 #include "ARMGenAsmWriter.inc"
301 void ARMAsmPrinter::EmitFunctionEntryLabel() {
302 if (AFI->isThumbFunction()) {
303 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
304 if (!Subtarget->isTargetDarwin())
305 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
307 // This needs to emit to a temporary string to get properly quoted
308 // MCSymbols when they have spaces in them.
309 SmallString<128> Tmp;
310 raw_svector_ostream OS(Tmp);
311 OS << "\t.thumb_func\t" << *CurrentFnSym;
312 OutStreamer.EmitRawText(OS.str());
316 OutStreamer.EmitLabel(CurrentFnSym);
319 /// runOnMachineFunction - This uses the printInstruction()
320 /// method to print assembly for each instruction.
322 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
323 AFI = MF.getInfo<ARMFunctionInfo>();
324 MCP = MF.getConstantPool();
326 return AsmPrinter::runOnMachineFunction(MF);
329 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
330 raw_ostream &O, const char *Modifier) {
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 unsigned TF = MO.getTargetFlags();
334 switch (MO.getType()) {
336 assert(0 && "<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
341 unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
342 unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
344 << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi)
346 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
347 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
349 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
350 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
351 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
353 assert(!MO.getSubReg() && "Subregs should be eliminated!");
354 O << getRegisterName(Reg);
358 case MachineOperand::MO_Immediate: {
359 int64_t Imm = MO.getImm();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
370 case MachineOperand::MO_MachineBasicBlock:
371 O << *MO.getMBB()->getSymbol();
373 case MachineOperand::MO_GlobalAddress: {
374 bool isCallOp = Modifier && !strcmp(Modifier, "call");
375 const GlobalValue *GV = MO.getGlobal();
377 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
378 (TF & ARMII::MO_LO16))
380 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
381 (TF & ARMII::MO_HI16))
383 O << *Mang->getSymbol(GV);
385 printOffset(MO.getOffset(), O);
387 if (isCallOp && Subtarget->isTargetELF() &&
388 TM.getRelocationModel() == Reloc::PIC_)
392 case MachineOperand::MO_ExternalSymbol: {
393 bool isCallOp = Modifier && !strcmp(Modifier, "call");
394 O << *GetExternalSymbolSymbol(MO.getSymbolName());
396 if (isCallOp && Subtarget->isTargetELF() &&
397 TM.getRelocationModel() == Reloc::PIC_)
401 case MachineOperand::MO_ConstantPoolIndex:
402 O << *GetCPISymbol(MO.getIndex());
404 case MachineOperand::MO_JumpTableIndex:
405 O << *GetJTISymbol(MO.getIndex());
410 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
411 const MCAsmInfo *MAI) {
412 // Break it up into two parts that make up a shifter immediate.
413 V = ARM_AM::getSOImmVal(V);
414 assert(V != -1 && "Not a valid so_imm value!");
416 unsigned Imm = ARM_AM::getSOImmValImm(V);
417 unsigned Rot = ARM_AM::getSOImmValRot(V);
419 // Print low-level immediate formation info, per
420 // A5.1.3: "Data-processing operands - Immediate".
422 O << "#" << Imm << ", " << Rot;
423 // Pretty printed version.
425 O << "\t" << MAI->getCommentString() << ' ';
426 O << (int)ARM_AM::rotr32(Imm, Rot);
433 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
434 /// immediate in bits 0-7.
435 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
437 const MachineOperand &MO = MI->getOperand(OpNum);
438 assert(MO.isImm() && "Not a valid so_imm value!");
439 printSOImm(O, MO.getImm(), isVerbose(), MAI);
442 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
443 /// followed by an 'orr' to materialize.
444 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
446 const MachineOperand &MO = MI->getOperand(OpNum);
447 assert(MO.isImm() && "Not a valid so_imm value!");
448 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
449 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
450 printSOImm(O, V1, isVerbose(), MAI);
452 printPredicateOperand(MI, 2, O);
454 printOperand(MI, 0, O);
456 printOperand(MI, 0, O);
458 printSOImm(O, V2, isVerbose(), MAI);
461 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
462 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
464 // REG REG 0,SH_OPC - e.g. R5, ROR R3
465 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
466 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
468 const MachineOperand &MO1 = MI->getOperand(Op);
469 const MachineOperand &MO2 = MI->getOperand(Op+1);
470 const MachineOperand &MO3 = MI->getOperand(Op+2);
472 O << getRegisterName(MO1.getReg());
474 // Print the shift opc.
475 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
476 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
478 O << ' ' << getRegisterName(MO2.getReg());
479 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
480 } else if (ShOpc != ARM_AM::rrx) {
481 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
485 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
487 const MachineOperand &MO1 = MI->getOperand(Op);
488 const MachineOperand &MO2 = MI->getOperand(Op+1);
489 const MachineOperand &MO3 = MI->getOperand(Op+2);
491 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
492 printOperand(MI, Op, O);
496 O << "[" << getRegisterName(MO1.getReg());
499 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
501 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
502 << ARM_AM::getAM2Offset(MO3.getImm());
508 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
509 << getRegisterName(MO2.getReg());
511 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
513 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
518 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
520 const MachineOperand &MO1 = MI->getOperand(Op);
521 const MachineOperand &MO2 = MI->getOperand(Op+1);
524 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
526 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
531 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
532 << getRegisterName(MO1.getReg());
534 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
536 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
540 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
542 const MachineOperand &MO1 = MI->getOperand(Op);
543 const MachineOperand &MO2 = MI->getOperand(Op+1);
544 const MachineOperand &MO3 = MI->getOperand(Op+2);
546 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
547 O << "[" << getRegisterName(MO1.getReg());
551 << (char)ARM_AM::getAM3Op(MO3.getImm())
552 << getRegisterName(MO2.getReg())
557 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
559 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
564 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
566 const MachineOperand &MO1 = MI->getOperand(Op);
567 const MachineOperand &MO2 = MI->getOperand(Op+1);
570 O << (char)ARM_AM::getAM3Op(MO2.getImm())
571 << getRegisterName(MO1.getReg());
575 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
577 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
581 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
583 const char *Modifier) {
584 const MachineOperand &MO2 = MI->getOperand(Op+1);
585 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
586 if (Modifier && strcmp(Modifier, "submode") == 0) {
587 O << ARM_AM::getAMSubModeStr(Mode);
588 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
589 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
590 if (Mode == ARM_AM::ia)
593 printOperand(MI, Op, O);
597 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
599 const char *Modifier) {
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
604 printOperand(MI, Op, O);
608 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
610 if (Modifier && strcmp(Modifier, "submode") == 0) {
611 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
612 O << ARM_AM::getAMSubModeStr(Mode);
614 } else if (Modifier && strcmp(Modifier, "base") == 0) {
615 // Used for FSTM{D|S} and LSTM{D|S} operations.
616 O << getRegisterName(MO1.getReg());
620 O << "[" << getRegisterName(MO1.getReg());
622 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
624 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
630 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
632 const MachineOperand &MO1 = MI->getOperand(Op);
633 const MachineOperand &MO2 = MI->getOperand(Op+1);
635 O << "[" << getRegisterName(MO1.getReg());
637 // FIXME: Both darwin as and GNU as violate ARM docs here.
638 O << ", :" << (MO2.getImm() << 3);
643 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
645 const MachineOperand &MO = MI->getOperand(Op);
646 if (MO.getReg() == 0)
649 O << ", " << getRegisterName(MO.getReg());
652 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
654 const char *Modifier) {
655 if (Modifier && strcmp(Modifier, "label") == 0) {
656 printPCLabel(MI, Op+1, O);
660 const MachineOperand &MO1 = MI->getOperand(Op);
661 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
662 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
666 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
668 const MachineOperand &MO = MI->getOperand(Op);
669 uint32_t v = ~MO.getImm();
670 int32_t lsb = CountTrailingZeros_32(v);
671 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
672 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
673 O << "#" << lsb << ", #" << width;
677 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
679 unsigned val = MI->getOperand(OpNum).getImm();
680 O << ARM_MB::MemBOptToString(val);
683 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
685 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
686 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
688 case ARM_AM::no_shift:
697 assert(0 && "unexpected shift opcode for shift immediate operand");
699 O << ARM_AM::getSORegOffset(ShiftOp);
702 //===--------------------------------------------------------------------===//
704 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
706 O << "#" << MI->getOperand(Op).getImm() * 4;
710 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
712 // (3 - the number of trailing zeros) is the number of then / else.
713 unsigned Mask = MI->getOperand(Op).getImm();
714 unsigned CondBit0 = Mask >> 4 & 1;
715 unsigned NumTZ = CountTrailingZeros_32(Mask);
716 assert(NumTZ <= 3 && "Invalid IT mask!");
717 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
718 bool T = ((Mask >> Pos) & 1) == CondBit0;
727 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
729 const MachineOperand &MO1 = MI->getOperand(Op);
730 const MachineOperand &MO2 = MI->getOperand(Op+1);
731 O << "[" << getRegisterName(MO1.getReg());
732 O << ", " << getRegisterName(MO2.getReg()) << "]";
736 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
739 const MachineOperand &MO1 = MI->getOperand(Op);
740 const MachineOperand &MO2 = MI->getOperand(Op+1);
741 const MachineOperand &MO3 = MI->getOperand(Op+2);
743 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
744 printOperand(MI, Op, O);
748 O << "[" << getRegisterName(MO1.getReg());
750 O << ", " << getRegisterName(MO3.getReg());
751 else if (unsigned ImmOffs = MO2.getImm())
752 O << ", #" << ImmOffs * Scale;
757 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
759 printThumbAddrModeRI5Operand(MI, Op, O, 1);
762 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
764 printThumbAddrModeRI5Operand(MI, Op, O, 2);
767 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
769 printThumbAddrModeRI5Operand(MI, Op, O, 4);
772 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
774 const MachineOperand &MO1 = MI->getOperand(Op);
775 const MachineOperand &MO2 = MI->getOperand(Op+1);
776 O << "[" << getRegisterName(MO1.getReg());
777 if (unsigned ImmOffs = MO2.getImm())
778 O << ", #" << ImmOffs*4;
782 //===--------------------------------------------------------------------===//
784 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
785 // register with shift forms.
787 // REG IMM, SH_OPC - e.g. R5, LSL #3
788 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
790 const MachineOperand &MO1 = MI->getOperand(OpNum);
791 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
793 unsigned Reg = MO1.getReg();
794 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
795 O << getRegisterName(Reg);
797 // Print the shift opc.
798 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
799 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
800 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
801 if (ShOpc != ARM_AM::rrx)
802 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
805 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
808 const MachineOperand &MO1 = MI->getOperand(OpNum);
809 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
811 O << "[" << getRegisterName(MO1.getReg());
813 unsigned OffImm = MO2.getImm();
814 if (OffImm) // Don't print +0.
815 O << ", #" << OffImm;
819 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
822 const MachineOperand &MO1 = MI->getOperand(OpNum);
823 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
825 O << "[" << getRegisterName(MO1.getReg());
827 int32_t OffImm = (int32_t)MO2.getImm();
830 O << ", #-" << -OffImm;
832 O << ", #" << OffImm;
836 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
839 const MachineOperand &MO1 = MI->getOperand(OpNum);
840 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
842 O << "[" << getRegisterName(MO1.getReg());
844 int32_t OffImm = (int32_t)MO2.getImm() / 4;
847 O << ", #-" << -OffImm * 4;
849 O << ", #" << OffImm * 4;
853 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
856 const MachineOperand &MO1 = MI->getOperand(OpNum);
857 int32_t OffImm = (int32_t)MO1.getImm();
860 O << "#-" << -OffImm;
865 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
868 const MachineOperand &MO1 = MI->getOperand(OpNum);
869 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
870 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
872 O << "[" << getRegisterName(MO1.getReg());
874 assert(MO2.getReg() && "Invalid so_reg load / store address!");
875 O << ", " << getRegisterName(MO2.getReg());
877 unsigned ShAmt = MO3.getImm();
879 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
880 O << ", lsl #" << ShAmt;
886 //===--------------------------------------------------------------------===//
888 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
890 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
892 O << ARMCondCodeToString(CC);
895 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
898 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
899 O << ARMCondCodeToString(CC);
902 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
904 unsigned Reg = MI->getOperand(OpNum).getReg();
906 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
911 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
913 int Id = (int)MI->getOperand(OpNum).getImm();
914 O << MAI->getPrivateGlobalPrefix()
915 << "PC" << getFunctionNumber() << "_" << Id;
918 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
921 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
922 if (MI->getOperand(i).isImplicit())
924 if ((int)i != OpNum) O << ", ";
925 printOperand(MI, i, O);
930 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
931 raw_ostream &O, const char *Modifier) {
932 assert(Modifier && "This operand only works with a modifier!");
933 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
935 if (!strcmp(Modifier, "label")) {
936 unsigned ID = MI->getOperand(OpNum).getImm();
937 OutStreamer.EmitLabel(GetCPISymbol(ID));
939 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
940 unsigned CPI = MI->getOperand(OpNum).getIndex();
942 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
944 if (MCPE.isMachineConstantPoolEntry()) {
945 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
947 EmitGlobalConstant(MCPE.Val.ConstVal);
952 MCSymbol *ARMAsmPrinter::
953 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
954 const MachineBasicBlock *MBB) const {
955 SmallString<60> Name;
956 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
957 << getFunctionNumber() << '_' << uid << '_' << uid2
958 << "_set_" << MBB->getNumber();
959 return OutContext.GetOrCreateSymbol(Name.str());
962 MCSymbol *ARMAsmPrinter::
963 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
964 SmallString<60> Name;
965 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
966 << getFunctionNumber() << '_' << uid << '_' << uid2;
967 return OutContext.GetOrCreateSymbol(Name.str());
970 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
972 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
974 const MachineOperand &MO1 = MI->getOperand(OpNum);
975 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
977 unsigned JTI = MO1.getIndex();
978 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
979 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
981 O << "\n" << *JTISymbol << ":\n";
983 const char *JTEntryDirective = MAI->getData32bitsDirective();
985 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
986 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
987 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
988 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
989 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
990 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
991 MachineBasicBlock *MBB = JTBBs[i];
992 bool isNew = JTSets.insert(MBB);
994 if (UseSet && isNew) {
996 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
997 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
1000 O << JTEntryDirective << ' ';
1002 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
1003 else if (TM.getRelocationModel() == Reloc::PIC_)
1004 O << *MBB->getSymbol() << '-' << *JTISymbol;
1006 O << *MBB->getSymbol();
1013 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
1015 const MachineOperand &MO1 = MI->getOperand(OpNum);
1016 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1017 unsigned JTI = MO1.getIndex();
1019 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1021 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
1023 O << "\n" << *JTISymbol << ":\n";
1025 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1026 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1027 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1028 bool ByteOffset = false, HalfWordOffset = false;
1029 if (MI->getOpcode() == ARM::t2TBB)
1031 else if (MI->getOpcode() == ARM::t2TBH)
1032 HalfWordOffset = true;
1034 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1035 MachineBasicBlock *MBB = JTBBs[i];
1037 O << MAI->getData8bitsDirective();
1038 else if (HalfWordOffset)
1039 O << MAI->getData16bitsDirective();
1041 if (ByteOffset || HalfWordOffset)
1042 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1044 O << "\tb.w " << *MBB->getSymbol();
1051 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1053 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1054 if (MI->getOpcode() == ARM::t2TBH)
1059 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1061 O << MI->getOperand(OpNum).getImm();
1064 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1066 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1067 O << '#' << FP->getValueAPF().convertToFloat();
1069 O << "\t\t" << MAI->getCommentString() << ' ';
1070 WriteAsOperand(O, FP, /*PrintType=*/false);
1074 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1076 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1077 O << '#' << FP->getValueAPF().convertToDouble();
1079 O << "\t\t" << MAI->getCommentString() << ' ';
1080 WriteAsOperand(O, FP, /*PrintType=*/false);
1084 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1086 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1088 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1089 O << "#0x" << utohexstr(Val);
1092 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1093 unsigned AsmVariant, const char *ExtraCode,
1095 // Does this asm operand have a single letter operand modifier?
1096 if (ExtraCode && ExtraCode[0]) {
1097 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1099 switch (ExtraCode[0]) {
1100 default: return true; // Unknown modifier.
1101 case 'a': // Print as a memory address.
1102 if (MI->getOperand(OpNum).isReg()) {
1103 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1107 case 'c': // Don't print "#" before an immediate operand.
1108 if (!MI->getOperand(OpNum).isImm())
1110 printNoHashImmediate(MI, OpNum, O);
1112 case 'P': // Print a VFP double precision register.
1113 case 'q': // Print a NEON quad precision register.
1114 printOperand(MI, OpNum, O);
1119 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1124 printOperand(MI, OpNum, O);
1128 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1129 unsigned OpNum, unsigned AsmVariant,
1130 const char *ExtraCode,
1132 if (ExtraCode && ExtraCode[0])
1133 return true; // Unknown modifier.
1135 const MachineOperand &MO = MI->getOperand(OpNum);
1136 assert(MO.isReg() && "unexpected inline asm memory operand");
1137 O << "[" << getRegisterName(MO.getReg()) << "]";
1141 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1143 printInstructionThroughMCStreamer(MI);
1147 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1150 SmallString<128> Str;
1151 raw_svector_ostream OS(Str);
1152 if (MI->getOpcode() == ARM::DBG_VALUE) {
1153 unsigned NOps = MI->getNumOperands();
1155 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1156 // cast away const; DIetc do not take const operands for some reason.
1157 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1160 // Frame address. Currently handles register +- offset only.
1161 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1162 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1165 printOperand(MI, NOps-2, OS);
1166 OutStreamer.EmitRawText(OS.str());
1170 printInstruction(MI, OS);
1171 OutStreamer.EmitRawText(OS.str());
1173 // Make sure the instruction that follows TBB is 2-byte aligned.
1174 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1175 if (MI->getOpcode() == ARM::t2TBB)
1179 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1180 if (Subtarget->isTargetDarwin()) {
1181 Reloc::Model RelocM = TM.getRelocationModel();
1182 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1183 // Declare all the text sections up front (before the DWARF sections
1184 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1185 // them together at the beginning of the object file. This helps
1186 // avoid out-of-range branches that are due a fundamental limitation of
1187 // the way symbol offsets are encoded with the current Darwin ARM
1189 const TargetLoweringObjectFileMachO &TLOFMacho =
1190 static_cast<const TargetLoweringObjectFileMachO &>(
1191 getObjFileLowering());
1192 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1193 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1194 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1195 if (RelocM == Reloc::DynamicNoPIC) {
1196 const MCSection *sect =
1197 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1198 MCSectionMachO::S_SYMBOL_STUBS,
1199 12, SectionKind::getText());
1200 OutStreamer.SwitchSection(sect);
1202 const MCSection *sect =
1203 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1204 MCSectionMachO::S_SYMBOL_STUBS,
1205 16, SectionKind::getText());
1206 OutStreamer.SwitchSection(sect);
1208 const MCSection *StaticInitSect =
1209 OutContext.getMachOSection("__TEXT", "__StaticInit",
1210 MCSectionMachO::S_REGULAR |
1211 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1212 SectionKind::getText());
1213 OutStreamer.SwitchSection(StaticInitSect);
1217 // Use unified assembler syntax.
1218 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1220 // Emit ARM Build Attributes
1221 if (Subtarget->isTargetELF()) {
1223 std::string CPUString = Subtarget->getCPUString();
1224 if (CPUString != "generic")
1225 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1227 // FIXME: Emit FPU type
1228 if (Subtarget->hasVFP2())
1229 OutStreamer.EmitRawText("\t.eabi_attribute " +
1230 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1232 // Signal various FP modes.
1233 if (!UnsafeFPMath) {
1234 OutStreamer.EmitRawText("\t.eabi_attribute " +
1235 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1236 OutStreamer.EmitRawText("\t.eabi_attribute " +
1237 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1240 if (NoInfsFPMath && NoNaNsFPMath)
1241 OutStreamer.EmitRawText("\t.eabi_attribute " +
1242 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1244 OutStreamer.EmitRawText("\t.eabi_attribute " +
1245 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1247 // 8-bytes alignment stuff.
1248 OutStreamer.EmitRawText("\t.eabi_attribute " +
1249 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1250 OutStreamer.EmitRawText("\t.eabi_attribute " +
1251 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1253 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1254 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1255 OutStreamer.EmitRawText("\t.eabi_attribute " +
1256 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1257 OutStreamer.EmitRawText("\t.eabi_attribute " +
1258 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1260 // FIXME: Should we signal R9 usage?
1265 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1266 if (Subtarget->isTargetDarwin()) {
1267 // All darwin targets use mach-o.
1268 const TargetLoweringObjectFileMachO &TLOFMacho =
1269 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1270 MachineModuleInfoMachO &MMIMacho =
1271 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1273 // Output non-lazy-pointers for external and common global variables.
1274 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1276 if (!Stubs.empty()) {
1277 // Switch with ".non_lazy_symbol_pointer" directive.
1278 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1280 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1282 OutStreamer.EmitLabel(Stubs[i].first);
1283 // .indirect_symbol _foo
1284 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1285 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1288 // External to current translation unit.
1289 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1291 // Internal to current translation unit.
1293 // When we place the LSDA into the TEXT section, the type info pointers
1294 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1295 // However, sometimes the types are local to the file. So we need to
1296 // fill in the value for the NLP in those cases.
1297 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1299 4/*size*/, 0/*addrspace*/);
1303 OutStreamer.AddBlankLine();
1306 Stubs = MMIMacho.GetHiddenGVStubList();
1307 if (!Stubs.empty()) {
1308 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1310 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1312 OutStreamer.EmitLabel(Stubs[i].first);
1314 OutStreamer.EmitValue(MCSymbolRefExpr::
1315 Create(Stubs[i].second.getPointer(),
1317 4/*size*/, 0/*addrspace*/);
1321 OutStreamer.AddBlankLine();
1324 // Funny Darwin hack: This flag tells the linker that no global symbols
1325 // contain code that falls through to other global symbols (e.g. the obvious
1326 // implementation of multiple entry points). If this doesn't occur, the
1327 // linker can safely perform dead code stripping. Since LLVM never
1328 // generates code that does this, it is always safe to set.
1329 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1333 //===----------------------------------------------------------------------===//
1335 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1336 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1337 switch (MI->getOpcode()) {
1338 case ARM::t2MOVi32imm:
1339 assert(0 && "Should be lowered by thumb2it pass");
1341 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1342 // This is a pseudo op for a label + instruction sequence, which looks like:
1345 // This adds the address of LPC0 to r0.
1348 // FIXME: MOVE TO SHARED PLACE.
1349 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1350 const char *Prefix = MAI->getPrivateGlobalPrefix();
1351 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1352 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1353 OutStreamer.EmitLabel(Label);
1356 // Form and emit tha dd.
1358 AddInst.setOpcode(ARM::ADDrr);
1359 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1360 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1361 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1362 OutStreamer.EmitInstruction(AddInst);
1365 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1366 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1367 /// in the function. The first operand is the ID# for this instruction, the
1368 /// second is the index into the MachineConstantPool that this is, the third
1369 /// is the size in bytes of this constant pool entry.
1370 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1371 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1374 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1376 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1377 if (MCPE.isMachineConstantPoolEntry())
1378 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1380 EmitGlobalConstant(MCPE.Val.ConstVal);
1384 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1385 // This is a hack that lowers as a two instruction sequence.
1386 unsigned DstReg = MI->getOperand(0).getReg();
1387 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1389 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1390 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1394 TmpInst.setOpcode(ARM::MOVi);
1395 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1396 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1399 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1400 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1402 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1403 OutStreamer.EmitInstruction(TmpInst);
1408 TmpInst.setOpcode(ARM::ORRri);
1409 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1410 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1411 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1413 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1414 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1416 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1417 OutStreamer.EmitInstruction(TmpInst);
1421 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1422 // This is a hack that lowers as a two instruction sequence.
1423 unsigned DstReg = MI->getOperand(0).getReg();
1424 const MachineOperand &MO = MI->getOperand(1);
1427 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1428 V1 = MCOperand::CreateImm(ImmVal & 65535);
1429 V2 = MCOperand::CreateImm(ImmVal >> 16);
1430 } else if (MO.isGlobal()) {
1431 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
1432 const MCSymbolRefExpr *SymRef1 =
1433 MCSymbolRefExpr::Create(Symbol,
1434 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1435 const MCSymbolRefExpr *SymRef2 =
1436 MCSymbolRefExpr::Create(Symbol,
1437 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1438 V1 = MCOperand::CreateExpr(SymRef1);
1439 V2 = MCOperand::CreateExpr(SymRef2);
1442 llvm_unreachable("cannot handle this operand");
1447 TmpInst.setOpcode(ARM::MOVi16);
1448 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1449 TmpInst.addOperand(V1); // lower16(imm)
1452 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1453 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1455 OutStreamer.EmitInstruction(TmpInst);
1460 TmpInst.setOpcode(ARM::MOVTi16);
1461 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1462 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1463 TmpInst.addOperand(V2); // upper16(imm)
1466 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1467 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1469 OutStreamer.EmitInstruction(TmpInst);
1477 MCInstLowering.Lower(MI, TmpInst);
1478 OutStreamer.EmitInstruction(TmpInst);
1481 //===----------------------------------------------------------------------===//
1482 // Target Registry Stuff
1483 //===----------------------------------------------------------------------===//
1485 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1486 unsigned SyntaxVariant,
1487 const MCAsmInfo &MAI) {
1488 if (SyntaxVariant == 0)
1489 return new ARMInstPrinter(MAI, false);
1493 // Force static initialization.
1494 extern "C" void LLVMInitializeARMAsmPrinter() {
1495 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1496 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1498 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1499 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);