1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DebugInfo.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionBodyEnd() {
287 // Make sure to terminate any constant pools that were at the end
291 InConstantPool = false;
292 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
295 void ARMAsmPrinter::EmitFunctionEntryLabel() {
296 if (AFI->isThumbFunction()) {
297 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
298 OutStreamer.EmitThumbFunc(CurrentFnSym);
301 OutStreamer.EmitLabel(CurrentFnSym);
304 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
305 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
306 assert(Size && "C++ constructor pointer had zero size!");
308 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
309 assert(GV && "C++ constructor pointer was not a GlobalValue!");
311 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
312 (Subtarget->isTargetDarwin()
313 ? MCSymbolRefExpr::VK_None
314 : MCSymbolRefExpr::VK_ARM_TARGET1),
317 OutStreamer.EmitValue(E, Size);
320 /// runOnMachineFunction - This uses the EmitInstruction()
321 /// method to print assembly for each instruction.
323 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
324 AFI = MF.getInfo<ARMFunctionInfo>();
325 MCP = MF.getConstantPool();
327 return AsmPrinter::runOnMachineFunction(MF);
330 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
331 raw_ostream &O, const char *Modifier) {
332 const MachineOperand &MO = MI->getOperand(OpNum);
333 unsigned TF = MO.getTargetFlags();
335 switch (MO.getType()) {
336 default: llvm_unreachable("<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 assert(!MO.getSubReg() && "Subregs should be eliminated!");
341 O << ARMInstPrinter::getRegisterName(Reg);
344 case MachineOperand::MO_Immediate: {
345 int64_t Imm = MO.getImm();
347 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
348 (TF == ARMII::MO_LO16))
350 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
351 (TF == ARMII::MO_HI16))
356 case MachineOperand::MO_MachineBasicBlock:
357 O << *MO.getMBB()->getSymbol();
359 case MachineOperand::MO_GlobalAddress: {
360 const GlobalValue *GV = MO.getGlobal();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
367 O << *Mang->getSymbol(GV);
369 printOffset(MO.getOffset(), O);
370 if (TF == ARMII::MO_PLT)
374 case MachineOperand::MO_ExternalSymbol: {
375 O << *GetExternalSymbolSymbol(MO.getSymbolName());
376 if (TF == ARMII::MO_PLT)
380 case MachineOperand::MO_ConstantPoolIndex:
381 O << *GetCPISymbol(MO.getIndex());
383 case MachineOperand::MO_JumpTableIndex:
384 O << *GetJTISymbol(MO.getIndex());
389 //===--------------------------------------------------------------------===//
391 MCSymbol *ARMAsmPrinter::
392 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
393 const MachineBasicBlock *MBB) const {
394 SmallString<60> Name;
395 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
396 << getFunctionNumber() << '_' << uid << '_' << uid2
397 << "_set_" << MBB->getNumber();
398 return OutContext.GetOrCreateSymbol(Name.str());
401 MCSymbol *ARMAsmPrinter::
402 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
403 SmallString<60> Name;
404 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
405 << getFunctionNumber() << '_' << uid << '_' << uid2;
406 return OutContext.GetOrCreateSymbol(Name.str());
410 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
411 SmallString<60> Name;
412 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
413 << getFunctionNumber();
414 return OutContext.GetOrCreateSymbol(Name.str());
417 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
418 unsigned AsmVariant, const char *ExtraCode,
420 // Does this asm operand have a single letter operand modifier?
421 if (ExtraCode && ExtraCode[0]) {
422 if (ExtraCode[1] != 0) return true; // Unknown modifier.
424 switch (ExtraCode[0]) {
426 // See if this is a generic print operand
427 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
428 case 'a': // Print as a memory address.
429 if (MI->getOperand(OpNum).isReg()) {
431 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
436 case 'c': // Don't print "#" before an immediate operand.
437 if (!MI->getOperand(OpNum).isImm())
439 O << MI->getOperand(OpNum).getImm();
441 case 'P': // Print a VFP double precision register.
442 case 'q': // Print a NEON quad precision register.
443 printOperand(MI, OpNum, O);
445 case 'y': // Print a VFP single precision register as indexed double.
446 if (MI->getOperand(OpNum).isReg()) {
447 unsigned Reg = MI->getOperand(OpNum).getReg();
448 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
449 // Find the 'd' register that has this 's' register as a sub-register,
450 // and determine the lane number.
451 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
452 if (!ARM::DPRRegClass.contains(*SR))
454 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
455 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
460 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
461 if (!MI->getOperand(OpNum).isImm())
463 O << ~(MI->getOperand(OpNum).getImm());
465 case 'L': // The low 16 bits of an immediate constant.
466 if (!MI->getOperand(OpNum).isImm())
468 O << (MI->getOperand(OpNum).getImm() & 0xffff);
470 case 'M': { // A register range suitable for LDM/STM.
471 if (!MI->getOperand(OpNum).isReg())
473 const MachineOperand &MO = MI->getOperand(OpNum);
474 unsigned RegBegin = MO.getReg();
475 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
476 // already got the operands in registers that are operands to the
477 // inline asm statement.
479 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
481 // FIXME: The register allocator not only may not have given us the
482 // registers in sequence, but may not be in ascending registers. This
483 // will require changes in the register allocator that'll need to be
484 // propagated down here if the operands change.
485 unsigned RegOps = OpNum + 1;
486 while (MI->getOperand(RegOps).isReg()) {
488 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
496 case 'R': // The most significant register of a pair.
497 case 'Q': { // The least significant register of a pair.
500 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
501 if (!FlagsOP.isImm())
503 unsigned Flags = FlagsOP.getImm();
504 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
507 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
508 if (RegOp >= MI->getNumOperands())
510 const MachineOperand &MO = MI->getOperand(RegOp);
513 unsigned Reg = MO.getReg();
514 O << ARMInstPrinter::getRegisterName(Reg);
518 case 'e': // The low doubleword register of a NEON quad register.
519 case 'f': { // The high doubleword register of a NEON quad register.
520 if (!MI->getOperand(OpNum).isReg())
522 unsigned Reg = MI->getOperand(OpNum).getReg();
523 if (!ARM::QPRRegClass.contains(Reg))
525 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
526 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
527 ARM::dsub_0 : ARM::dsub_1);
528 O << ARMInstPrinter::getRegisterName(SubReg);
532 // This modifier is not yet supported.
533 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
535 case 'H': // The highest-numbered register of a pair.
536 const MachineOperand &MO = MI->getOperand(OpNum);
539 const TargetRegisterClass &RC = ARM::GPRRegClass;
540 const MachineFunction &MF = *MI->getParent()->getParent();
541 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
543 unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
544 RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
546 unsigned Reg = RC.getRegister(RegIdx);
547 O << ARMInstPrinter::getRegisterName(Reg);
552 printOperand(MI, OpNum, O);
556 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
557 unsigned OpNum, unsigned AsmVariant,
558 const char *ExtraCode,
560 // Does this asm operand have a single letter operand modifier?
561 if (ExtraCode && ExtraCode[0]) {
562 if (ExtraCode[1] != 0) return true; // Unknown modifier.
564 switch (ExtraCode[0]) {
565 case 'A': // A memory operand for a VLD1/VST1 instruction.
566 default: return true; // Unknown modifier.
567 case 'm': // The base register of a memory operand.
568 if (!MI->getOperand(OpNum).isReg())
570 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
575 const MachineOperand &MO = MI->getOperand(OpNum);
576 assert(MO.isReg() && "unexpected inline asm memory operand");
577 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
581 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
582 if (Subtarget->isTargetDarwin()) {
583 Reloc::Model RelocM = TM.getRelocationModel();
584 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
585 // Declare all the text sections up front (before the DWARF sections
586 // emitted by AsmPrinter::doInitialization) so the assembler will keep
587 // them together at the beginning of the object file. This helps
588 // avoid out-of-range branches that are due a fundamental limitation of
589 // the way symbol offsets are encoded with the current Darwin ARM
591 const TargetLoweringObjectFileMachO &TLOFMacho =
592 static_cast<const TargetLoweringObjectFileMachO &>(
593 getObjFileLowering());
594 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
595 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
596 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
597 if (RelocM == Reloc::DynamicNoPIC) {
598 const MCSection *sect =
599 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
600 MCSectionMachO::S_SYMBOL_STUBS,
601 12, SectionKind::getText());
602 OutStreamer.SwitchSection(sect);
604 const MCSection *sect =
605 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
606 MCSectionMachO::S_SYMBOL_STUBS,
607 16, SectionKind::getText());
608 OutStreamer.SwitchSection(sect);
610 const MCSection *StaticInitSect =
611 OutContext.getMachOSection("__TEXT", "__StaticInit",
612 MCSectionMachO::S_REGULAR |
613 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
614 SectionKind::getText());
615 OutStreamer.SwitchSection(StaticInitSect);
619 // Use unified assembler syntax.
620 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
622 // Emit ARM Build Attributes
623 if (Subtarget->isTargetELF())
628 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
629 if (Subtarget->isTargetDarwin()) {
630 // All darwin targets use mach-o.
631 const TargetLoweringObjectFileMachO &TLOFMacho =
632 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
633 MachineModuleInfoMachO &MMIMacho =
634 MMI->getObjFileInfo<MachineModuleInfoMachO>();
636 // Output non-lazy-pointers for external and common global variables.
637 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
639 if (!Stubs.empty()) {
640 // Switch with ".non_lazy_symbol_pointer" directive.
641 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
643 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
645 OutStreamer.EmitLabel(Stubs[i].first);
646 // .indirect_symbol _foo
647 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
648 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
651 // External to current translation unit.
652 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
654 // Internal to current translation unit.
656 // When we place the LSDA into the TEXT section, the type info
657 // pointers need to be indirect and pc-rel. We accomplish this by
658 // using NLPs; however, sometimes the types are local to the file.
659 // We need to fill in the value for the NLP in those cases.
660 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
662 4/*size*/, 0/*addrspace*/);
666 OutStreamer.AddBlankLine();
669 Stubs = MMIMacho.GetHiddenGVStubList();
670 if (!Stubs.empty()) {
671 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
673 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
675 OutStreamer.EmitLabel(Stubs[i].first);
677 OutStreamer.EmitValue(MCSymbolRefExpr::
678 Create(Stubs[i].second.getPointer(),
680 4/*size*/, 0/*addrspace*/);
684 OutStreamer.AddBlankLine();
687 // Funny Darwin hack: This flag tells the linker that no global symbols
688 // contain code that falls through to other global symbols (e.g. the obvious
689 // implementation of multiple entry points). If this doesn't occur, the
690 // linker can safely perform dead code stripping. Since LLVM never
691 // generates code that does this, it is always safe to set.
692 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
696 //===----------------------------------------------------------------------===//
697 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
699 // The following seem like one-off assembler flags, but they actually need
700 // to appear in the .ARM.attributes section in ELF.
701 // Instead of subclassing the MCELFStreamer, we do the work here.
703 void ARMAsmPrinter::emitAttributes() {
705 emitARMAttributeSection();
707 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
708 bool emitFPU = false;
709 AttributeEmitter *AttrEmitter;
710 if (OutStreamer.hasRawTextSupport()) {
711 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
714 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
715 AttrEmitter = new ObjectAttributeEmitter(O);
718 AttrEmitter->MaybeSwitchVendor("aeabi");
720 std::string CPUString = Subtarget->getCPUString();
722 if (CPUString == "cortex-a8" ||
723 Subtarget->isCortexA8()) {
724 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
725 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
726 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
727 ARMBuildAttrs::ApplicationProfile);
728 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
729 ARMBuildAttrs::Allowed);
730 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
731 ARMBuildAttrs::AllowThumb32);
732 // Fixme: figure out when this is emitted.
733 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
734 // ARMBuildAttrs::AllowWMMXv1);
737 /// ADD additional Else-cases here!
738 } else if (CPUString == "xscale") {
739 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
740 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
741 ARMBuildAttrs::Allowed);
742 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
743 ARMBuildAttrs::Allowed);
744 } else if (CPUString == "generic") {
745 // FIXME: Why these defaults?
746 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
748 ARMBuildAttrs::Allowed);
749 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
750 ARMBuildAttrs::Allowed);
753 if (Subtarget->hasNEON() && emitFPU) {
754 /* NEON is not exactly a VFP architecture, but GAS emit one of
755 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
756 if (Subtarget->hasVFP4())
757 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
760 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
761 /* If emitted for NEON, omit from VFP below, since you can have both
762 * NEON and VFP in build attributes but only one .fpu */
767 if (Subtarget->hasVFP4()) {
768 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
769 ARMBuildAttrs::AllowFPv4A);
771 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
774 } else if (Subtarget->hasVFP3()) {
775 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
776 ARMBuildAttrs::AllowFPv3A);
778 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
781 } else if (Subtarget->hasVFP2()) {
782 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
783 ARMBuildAttrs::AllowFPv2);
785 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
788 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
789 * since NEON can have 1 (allowed) or 2 (MAC operations) */
790 if (Subtarget->hasNEON()) {
791 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
792 ARMBuildAttrs::Allowed);
795 // Signal various FP modes.
796 if (!TM.Options.UnsafeFPMath) {
797 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
798 ARMBuildAttrs::Allowed);
799 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
800 ARMBuildAttrs::Allowed);
803 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
804 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
805 ARMBuildAttrs::Allowed);
807 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
808 ARMBuildAttrs::AllowIEE754);
810 // FIXME: add more flags to ARMBuildAttrs.h
811 // 8-bytes alignment stuff.
812 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
813 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
815 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
816 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
817 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
818 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
820 // FIXME: Should we signal R9 usage?
822 if (Subtarget->hasDivide())
823 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
825 AttrEmitter->Finish();
829 void ARMAsmPrinter::emitARMAttributeSection() {
831 // [ <section-length> "vendor-name"
832 // [ <file-tag> <size> <attribute>*
833 // | <section-tag> <size> <section-number>* 0 <attribute>*
834 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
838 if (OutStreamer.hasRawTextSupport())
841 const ARMElfTargetObjectFile &TLOFELF =
842 static_cast<const ARMElfTargetObjectFile &>
843 (getObjFileLowering());
845 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
848 OutStreamer.EmitIntValue(0x41, 1);
851 //===----------------------------------------------------------------------===//
853 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
854 unsigned LabelId, MCContext &Ctx) {
856 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
857 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
861 static MCSymbolRefExpr::VariantKind
862 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
864 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
865 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
866 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
867 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
868 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
869 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
871 llvm_unreachable("Invalid ARMCPModifier!");
874 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
875 bool isIndirect = Subtarget->isTargetDarwin() &&
876 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
878 return Mang->getSymbol(GV);
880 // FIXME: Remove this when Darwin transition to @GOT like syntax.
881 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
882 MachineModuleInfoMachO &MMIMachO =
883 MMI->getObjFileInfo<MachineModuleInfoMachO>();
884 MachineModuleInfoImpl::StubValueTy &StubSym =
885 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
886 MMIMachO.getGVStubEntry(MCSym);
887 if (StubSym.getPointer() == 0)
888 StubSym = MachineModuleInfoImpl::
889 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
894 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
895 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
897 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
900 if (ACPV->isLSDA()) {
901 SmallString<128> Str;
902 raw_svector_ostream OS(Str);
903 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
904 MCSym = OutContext.GetOrCreateSymbol(OS.str());
905 } else if (ACPV->isBlockAddress()) {
906 const BlockAddress *BA =
907 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
908 MCSym = GetBlockAddressSymbol(BA);
909 } else if (ACPV->isGlobalValue()) {
910 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
911 MCSym = GetARMGVSymbol(GV);
912 } else if (ACPV->isMachineBasicBlock()) {
913 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
914 MCSym = MBB->getSymbol();
916 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
917 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
918 MCSym = GetExternalSymbolSymbol(Sym);
921 // Create an MCSymbol for the reference.
923 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
926 if (ACPV->getPCAdjustment()) {
927 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
931 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
933 MCBinaryExpr::CreateAdd(PCRelExpr,
934 MCConstantExpr::Create(ACPV->getPCAdjustment(),
937 if (ACPV->mustAddCurrentAddress()) {
938 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
939 // label, so just emit a local label end reference that instead.
940 MCSymbol *DotSym = OutContext.CreateTempSymbol();
941 OutStreamer.EmitLabel(DotSym);
942 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
943 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
945 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
947 OutStreamer.EmitValue(Expr, Size);
950 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
951 unsigned Opcode = MI->getOpcode();
953 if (Opcode == ARM::BR_JTadd)
955 else if (Opcode == ARM::BR_JTm)
958 const MachineOperand &MO1 = MI->getOperand(OpNum);
959 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
960 unsigned JTI = MO1.getIndex();
962 // Emit a label for the jump table.
963 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
964 OutStreamer.EmitLabel(JTISymbol);
966 // Mark the jump table as data-in-code.
967 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
969 // Emit each entry of the table.
970 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
971 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
972 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
974 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
975 MachineBasicBlock *MBB = JTBBs[i];
976 // Construct an MCExpr for the entry. We want a value of the form:
977 // (BasicBlockAddr - TableBeginAddr)
979 // For example, a table with entries jumping to basic blocks BB0 and BB1
982 // .word (LBB0 - LJTI_0_0)
983 // .word (LBB1 - LJTI_0_0)
984 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
986 if (TM.getRelocationModel() == Reloc::PIC_)
987 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
990 // If we're generating a table of Thumb addresses in static relocation
991 // model, we need to add one to keep interworking correctly.
992 else if (AFI->isThumbFunction())
993 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
995 OutStreamer.EmitValue(Expr, 4);
997 // Mark the end of jump table data-in-code region.
998 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1001 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1002 unsigned Opcode = MI->getOpcode();
1003 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1004 const MachineOperand &MO1 = MI->getOperand(OpNum);
1005 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1006 unsigned JTI = MO1.getIndex();
1008 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1009 OutStreamer.EmitLabel(JTISymbol);
1011 // Emit each entry of the table.
1012 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1013 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1014 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1015 unsigned OffsetWidth = 4;
1016 if (MI->getOpcode() == ARM::t2TBB_JT) {
1018 // Mark the jump table as data-in-code.
1019 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1020 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1022 // Mark the jump table as data-in-code.
1023 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1026 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1027 MachineBasicBlock *MBB = JTBBs[i];
1028 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1030 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1031 if (OffsetWidth == 4) {
1033 BrInst.setOpcode(ARM::t2B);
1034 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1035 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1036 BrInst.addOperand(MCOperand::CreateReg(0));
1037 OutStreamer.EmitInstruction(BrInst);
1040 // Otherwise it's an offset from the dispatch instruction. Construct an
1041 // MCExpr for the entry. We want a value of the form:
1042 // (BasicBlockAddr - TableBeginAddr) / 2
1044 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1047 // .byte (LBB0 - LJTI_0_0) / 2
1048 // .byte (LBB1 - LJTI_0_0) / 2
1049 const MCExpr *Expr =
1050 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1051 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1053 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1055 OutStreamer.EmitValue(Expr, OffsetWidth);
1057 // Mark the end of jump table data-in-code region. 32-bit offsets use
1058 // actual branch instructions here, so we don't mark those as a data-region
1060 if (OffsetWidth != 4)
1061 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1064 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1066 unsigned NOps = MI->getNumOperands();
1068 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1069 // cast away const; DIetc do not take const operands for some reason.
1070 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1073 // Frame address. Currently handles register +- offset only.
1074 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1075 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1078 printOperand(MI, NOps-2, OS);
1081 static void populateADROperands(MCInst &Inst, unsigned Dest,
1082 const MCSymbol *Label,
1083 unsigned pred, unsigned ccreg,
1085 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1086 Inst.addOperand(MCOperand::CreateReg(Dest));
1087 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1088 // Add predicate operands.
1089 Inst.addOperand(MCOperand::CreateImm(pred));
1090 Inst.addOperand(MCOperand::CreateReg(ccreg));
1093 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1097 // Emit the instruction as usual, just patch the opcode.
1098 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1099 TmpInst.setOpcode(Opcode);
1100 OutStreamer.EmitInstruction(TmpInst);
1103 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1104 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1105 "Only instruction which are involved into frame setup code are allowed");
1107 const MachineFunction &MF = *MI->getParent()->getParent();
1108 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1109 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1111 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1112 unsigned Opc = MI->getOpcode();
1113 unsigned SrcReg, DstReg;
1115 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1116 // Two special cases:
1117 // 1) tPUSH does not have src/dst regs.
1118 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1119 // load. Yes, this is pretty fragile, but for now I don't see better
1121 SrcReg = DstReg = ARM::SP;
1123 SrcReg = MI->getOperand(1).getReg();
1124 DstReg = MI->getOperand(0).getReg();
1127 // Try to figure out the unwinding opcode out of src / dst regs.
1128 if (MI->mayStore()) {
1130 assert(DstReg == ARM::SP &&
1131 "Only stack pointer as a destination reg is supported");
1133 SmallVector<unsigned, 4> RegList;
1134 // Skip src & dst reg, and pred ops.
1135 unsigned StartOp = 2 + 2;
1136 // Use all the operands.
1137 unsigned NumOffset = 0;
1142 llvm_unreachable("Unsupported opcode for unwinding information");
1144 // Special case here: no src & dst reg, but two extra imp ops.
1145 StartOp = 2; NumOffset = 2;
1146 case ARM::STMDB_UPD:
1147 case ARM::t2STMDB_UPD:
1148 case ARM::VSTMDDB_UPD:
1149 assert(SrcReg == ARM::SP &&
1150 "Only stack pointer as a source reg is supported");
1151 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1153 const MachineOperand &MO = MI->getOperand(i);
1154 // Actually, there should never be any impdef stuff here. Skip it
1155 // temporary to workaround PR11902.
1156 if (MO.isImplicit())
1158 RegList.push_back(MO.getReg());
1161 case ARM::STR_PRE_IMM:
1162 case ARM::STR_PRE_REG:
1163 case ARM::t2STR_PRE:
1164 assert(MI->getOperand(2).getReg() == ARM::SP &&
1165 "Only stack pointer as a source reg is supported");
1166 RegList.push_back(SrcReg);
1169 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1171 // Changes of stack / frame pointer.
1172 if (SrcReg == ARM::SP) {
1177 llvm_unreachable("Unsupported opcode for unwinding information");
1183 Offset = -MI->getOperand(2).getImm();
1187 Offset = MI->getOperand(2).getImm();
1190 Offset = MI->getOperand(2).getImm()*4;
1194 Offset = -MI->getOperand(2).getImm()*4;
1196 case ARM::tLDRpci: {
1197 // Grab the constpool index and check, whether it corresponds to
1198 // original or cloned constpool entry.
1199 unsigned CPI = MI->getOperand(1).getIndex();
1200 const MachineConstantPool *MCP = MF.getConstantPool();
1201 if (CPI >= MCP->getConstants().size())
1202 CPI = AFI.getOriginalCPIdx(CPI);
1203 assert(CPI != -1U && "Invalid constpool index");
1205 // Derive the actual offset.
1206 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1207 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1208 // FIXME: Check for user, it should be "add" instruction!
1209 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1214 if (DstReg == FramePtr && FramePtr != ARM::SP)
1215 // Set-up of the frame pointer. Positive values correspond to "add"
1217 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1218 else if (DstReg == ARM::SP) {
1219 // Change of SP by an offset. Positive values correspond to "sub"
1221 OutStreamer.EmitPad(Offset);
1224 llvm_unreachable("Unsupported opcode for unwinding information");
1226 } else if (DstReg == ARM::SP) {
1227 // FIXME: .movsp goes here
1229 llvm_unreachable("Unsupported opcode for unwinding information");
1233 llvm_unreachable("Unsupported opcode for unwinding information");
1238 extern cl::opt<bool> EnableARMEHABI;
1240 // Simple pseudo-instructions have their lowering (with expansion to real
1241 // instructions) auto-generated.
1242 #include "ARMGenMCPseudoLowering.inc"
1244 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1245 // If we just ended a constant pool, mark it as such.
1246 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1247 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1248 InConstantPool = false;
1251 // Emit unwinding stuff for frame-related instructions
1252 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1253 EmitUnwindingInstruction(MI);
1255 // Do any auto-generated pseudo lowerings.
1256 if (emitPseudoExpansionLowering(OutStreamer, MI))
1259 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1260 "Pseudo flag setting opcode should be expanded early");
1262 // Check for manual lowerings.
1263 unsigned Opc = MI->getOpcode();
1265 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1266 case ARM::DBG_VALUE: {
1267 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1268 SmallString<128> TmpStr;
1269 raw_svector_ostream OS(TmpStr);
1270 PrintDebugValueComment(MI, OS);
1271 OutStreamer.EmitRawText(StringRef(OS.str()));
1276 case ARM::tLEApcrel:
1277 case ARM::t2LEApcrel: {
1278 // FIXME: Need to also handle globals and externals
1280 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1281 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1283 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1284 GetCPISymbol(MI->getOperand(1).getIndex()),
1285 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1287 OutStreamer.EmitInstruction(TmpInst);
1290 case ARM::LEApcrelJT:
1291 case ARM::tLEApcrelJT:
1292 case ARM::t2LEApcrelJT: {
1294 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1295 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1297 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1298 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1299 MI->getOperand(2).getImm()),
1300 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1302 OutStreamer.EmitInstruction(TmpInst);
1305 // Darwin call instructions are just normal call instructions with different
1306 // clobber semantics (they clobber R9).
1307 case ARM::BX_CALL: {
1310 TmpInst.setOpcode(ARM::MOVr);
1311 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1312 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1313 // Add predicate operands.
1314 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1315 TmpInst.addOperand(MCOperand::CreateReg(0));
1316 // Add 's' bit operand (always reg0 for this)
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
1318 OutStreamer.EmitInstruction(TmpInst);
1322 TmpInst.setOpcode(ARM::BX);
1323 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1324 OutStreamer.EmitInstruction(TmpInst);
1328 case ARM::tBX_CALL: {
1331 TmpInst.setOpcode(ARM::tMOVr);
1332 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1333 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1334 // Add predicate operands.
1335 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1336 TmpInst.addOperand(MCOperand::CreateReg(0));
1337 OutStreamer.EmitInstruction(TmpInst);
1341 TmpInst.setOpcode(ARM::tBX);
1342 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1343 // Add predicate operands.
1344 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1345 TmpInst.addOperand(MCOperand::CreateReg(0));
1346 OutStreamer.EmitInstruction(TmpInst);
1350 case ARM::BMOVPCRX_CALL: {
1353 TmpInst.setOpcode(ARM::MOVr);
1354 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1355 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1356 // Add predicate operands.
1357 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1358 TmpInst.addOperand(MCOperand::CreateReg(0));
1359 // Add 's' bit operand (always reg0 for this)
1360 TmpInst.addOperand(MCOperand::CreateReg(0));
1361 OutStreamer.EmitInstruction(TmpInst);
1365 TmpInst.setOpcode(ARM::MOVr);
1366 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1367 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1368 // Add predicate operands.
1369 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1370 TmpInst.addOperand(MCOperand::CreateReg(0));
1371 // Add 's' bit operand (always reg0 for this)
1372 TmpInst.addOperand(MCOperand::CreateReg(0));
1373 OutStreamer.EmitInstruction(TmpInst);
1377 case ARM::BMOVPCB_CALL: {
1380 TmpInst.setOpcode(ARM::MOVr);
1381 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1382 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1383 // Add predicate operands.
1384 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1385 TmpInst.addOperand(MCOperand::CreateReg(0));
1386 // Add 's' bit operand (always reg0 for this)
1387 TmpInst.addOperand(MCOperand::CreateReg(0));
1388 OutStreamer.EmitInstruction(TmpInst);
1392 TmpInst.setOpcode(ARM::Bcc);
1393 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1394 MCSymbol *GVSym = Mang->getSymbol(GV);
1395 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1396 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1397 // Add predicate operands.
1398 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1399 TmpInst.addOperand(MCOperand::CreateReg(0));
1400 OutStreamer.EmitInstruction(TmpInst);
1404 case ARM::t2BMOVPCB_CALL: {
1407 TmpInst.setOpcode(ARM::tMOVr);
1408 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1409 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1410 // Add predicate operands.
1411 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1412 TmpInst.addOperand(MCOperand::CreateReg(0));
1413 OutStreamer.EmitInstruction(TmpInst);
1417 TmpInst.setOpcode(ARM::t2B);
1418 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1419 MCSymbol *GVSym = Mang->getSymbol(GV);
1420 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1421 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1422 // Add predicate operands.
1423 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1424 TmpInst.addOperand(MCOperand::CreateReg(0));
1425 OutStreamer.EmitInstruction(TmpInst);
1429 case ARM::MOVi16_ga_pcrel:
1430 case ARM::t2MOVi16_ga_pcrel: {
1432 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1433 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1435 unsigned TF = MI->getOperand(1).getTargetFlags();
1436 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1437 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1438 MCSymbol *GVSym = GetARMGVSymbol(GV);
1439 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1441 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1442 getFunctionNumber(),
1443 MI->getOperand(2).getImm(), OutContext);
1444 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1445 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1446 const MCExpr *PCRelExpr =
1447 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1448 MCBinaryExpr::CreateAdd(LabelSymExpr,
1449 MCConstantExpr::Create(PCAdj, OutContext),
1450 OutContext), OutContext), OutContext);
1451 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1453 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1454 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1457 // Add predicate operands.
1458 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1459 TmpInst.addOperand(MCOperand::CreateReg(0));
1460 // Add 's' bit operand (always reg0 for this)
1461 TmpInst.addOperand(MCOperand::CreateReg(0));
1462 OutStreamer.EmitInstruction(TmpInst);
1465 case ARM::MOVTi16_ga_pcrel:
1466 case ARM::t2MOVTi16_ga_pcrel: {
1468 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1469 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1470 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1471 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1473 unsigned TF = MI->getOperand(2).getTargetFlags();
1474 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1475 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1476 MCSymbol *GVSym = GetARMGVSymbol(GV);
1477 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1479 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1480 getFunctionNumber(),
1481 MI->getOperand(3).getImm(), OutContext);
1482 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1483 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1484 const MCExpr *PCRelExpr =
1485 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1486 MCBinaryExpr::CreateAdd(LabelSymExpr,
1487 MCConstantExpr::Create(PCAdj, OutContext),
1488 OutContext), OutContext), OutContext);
1489 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1491 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1492 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1494 // Add predicate operands.
1495 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1496 TmpInst.addOperand(MCOperand::CreateReg(0));
1497 // Add 's' bit operand (always reg0 for this)
1498 TmpInst.addOperand(MCOperand::CreateReg(0));
1499 OutStreamer.EmitInstruction(TmpInst);
1502 case ARM::tPICADD: {
1503 // This is a pseudo op for a label + instruction sequence, which looks like:
1506 // This adds the address of LPC0 to r0.
1509 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1510 getFunctionNumber(), MI->getOperand(2).getImm(),
1513 // Form and emit the add.
1515 AddInst.setOpcode(ARM::tADDhirr);
1516 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1517 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1518 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1519 // Add predicate operands.
1520 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1521 AddInst.addOperand(MCOperand::CreateReg(0));
1522 OutStreamer.EmitInstruction(AddInst);
1526 // This is a pseudo op for a label + instruction sequence, which looks like:
1529 // This adds the address of LPC0 to r0.
1532 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1533 getFunctionNumber(), MI->getOperand(2).getImm(),
1536 // Form and emit the add.
1538 AddInst.setOpcode(ARM::ADDrr);
1539 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1540 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1541 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1542 // Add predicate operands.
1543 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1544 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1545 // Add 's' bit operand (always reg0 for this)
1546 AddInst.addOperand(MCOperand::CreateReg(0));
1547 OutStreamer.EmitInstruction(AddInst);
1557 case ARM::PICLDRSH: {
1558 // This is a pseudo op for a label + instruction sequence, which looks like:
1561 // The LCP0 label is referenced by a constant pool entry in order to get
1562 // a PC-relative address at the ldr instruction.
1565 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1566 getFunctionNumber(), MI->getOperand(2).getImm(),
1569 // Form and emit the load
1571 switch (MI->getOpcode()) {
1573 llvm_unreachable("Unexpected opcode!");
1574 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1575 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1576 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1577 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1578 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1579 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1580 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1581 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1584 LdStInst.setOpcode(Opcode);
1585 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1586 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1587 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1588 LdStInst.addOperand(MCOperand::CreateImm(0));
1589 // Add predicate operands.
1590 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1591 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1592 OutStreamer.EmitInstruction(LdStInst);
1596 case ARM::CONSTPOOL_ENTRY: {
1597 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1598 /// in the function. The first operand is the ID# for this instruction, the
1599 /// second is the index into the MachineConstantPool that this is, the third
1600 /// is the size in bytes of this constant pool entry.
1601 /// The required alignment is specified on the basic block holding this MI.
1602 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1603 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1605 // If this is the first entry of the pool, mark it.
1606 if (!InConstantPool) {
1607 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1608 InConstantPool = true;
1611 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1613 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1614 if (MCPE.isMachineConstantPoolEntry())
1615 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1617 EmitGlobalConstant(MCPE.Val.ConstVal);
1620 case ARM::t2BR_JT: {
1621 // Lower and emit the instruction itself, then the jump table following it.
1623 TmpInst.setOpcode(ARM::tMOVr);
1624 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1625 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1626 // Add predicate operands.
1627 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1628 TmpInst.addOperand(MCOperand::CreateReg(0));
1629 OutStreamer.EmitInstruction(TmpInst);
1630 // Output the data for the jump table itself
1634 case ARM::t2TBB_JT: {
1635 // Lower and emit the instruction itself, then the jump table following it.
1638 TmpInst.setOpcode(ARM::t2TBB);
1639 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1640 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1641 // Add predicate operands.
1642 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1643 TmpInst.addOperand(MCOperand::CreateReg(0));
1644 OutStreamer.EmitInstruction(TmpInst);
1645 // Output the data for the jump table itself
1647 // Make sure the next instruction is 2-byte aligned.
1651 case ARM::t2TBH_JT: {
1652 // Lower and emit the instruction itself, then the jump table following it.
1655 TmpInst.setOpcode(ARM::t2TBH);
1656 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1657 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1658 // Add predicate operands.
1659 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1660 TmpInst.addOperand(MCOperand::CreateReg(0));
1661 OutStreamer.EmitInstruction(TmpInst);
1662 // Output the data for the jump table itself
1668 // Lower and emit the instruction itself, then the jump table following it.
1671 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1672 ARM::MOVr : ARM::tMOVr;
1673 TmpInst.setOpcode(Opc);
1674 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1675 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1676 // Add predicate operands.
1677 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1678 TmpInst.addOperand(MCOperand::CreateReg(0));
1679 // Add 's' bit operand (always reg0 for this)
1680 if (Opc == ARM::MOVr)
1681 TmpInst.addOperand(MCOperand::CreateReg(0));
1682 OutStreamer.EmitInstruction(TmpInst);
1684 // Make sure the Thumb jump table is 4-byte aligned.
1685 if (Opc == ARM::tMOVr)
1688 // Output the data for the jump table itself
1693 // Lower and emit the instruction itself, then the jump table following it.
1696 if (MI->getOperand(1).getReg() == 0) {
1698 TmpInst.setOpcode(ARM::LDRi12);
1699 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1700 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1701 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1703 TmpInst.setOpcode(ARM::LDRrs);
1704 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1705 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1706 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1707 TmpInst.addOperand(MCOperand::CreateImm(0));
1709 // Add predicate operands.
1710 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1711 TmpInst.addOperand(MCOperand::CreateReg(0));
1712 OutStreamer.EmitInstruction(TmpInst);
1714 // Output the data for the jump table itself
1718 case ARM::BR_JTadd: {
1719 // Lower and emit the instruction itself, then the jump table following it.
1720 // add pc, target, idx
1722 TmpInst.setOpcode(ARM::ADDrr);
1723 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1724 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1725 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1726 // Add predicate operands.
1727 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1728 TmpInst.addOperand(MCOperand::CreateReg(0));
1729 // Add 's' bit operand (always reg0 for this)
1730 TmpInst.addOperand(MCOperand::CreateReg(0));
1731 OutStreamer.EmitInstruction(TmpInst);
1733 // Output the data for the jump table itself
1738 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1739 // FIXME: Remove this special case when they do.
1740 if (!Subtarget->isTargetDarwin()) {
1741 //.long 0xe7ffdefe @ trap
1742 uint32_t Val = 0xe7ffdefeUL;
1743 OutStreamer.AddComment("trap");
1744 OutStreamer.EmitIntValue(Val, 4);
1750 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1751 // FIXME: Remove this special case when they do.
1752 if (!Subtarget->isTargetDarwin()) {
1753 //.short 57086 @ trap
1754 uint16_t Val = 0xdefe;
1755 OutStreamer.AddComment("trap");
1756 OutStreamer.EmitIntValue(Val, 2);
1761 case ARM::t2Int_eh_sjlj_setjmp:
1762 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1763 case ARM::tInt_eh_sjlj_setjmp: {
1764 // Two incoming args: GPR:$src, GPR:$val
1767 // str $val, [$src, #4]
1772 unsigned SrcReg = MI->getOperand(0).getReg();
1773 unsigned ValReg = MI->getOperand(1).getReg();
1774 MCSymbol *Label = GetARMSJLJEHLabel();
1777 TmpInst.setOpcode(ARM::tMOVr);
1778 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1779 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1781 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1782 TmpInst.addOperand(MCOperand::CreateReg(0));
1783 OutStreamer.AddComment("eh_setjmp begin");
1784 OutStreamer.EmitInstruction(TmpInst);
1788 TmpInst.setOpcode(ARM::tADDi3);
1789 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1791 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1792 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1793 TmpInst.addOperand(MCOperand::CreateImm(7));
1795 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1796 TmpInst.addOperand(MCOperand::CreateReg(0));
1797 OutStreamer.EmitInstruction(TmpInst);
1801 TmpInst.setOpcode(ARM::tSTRi);
1802 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1803 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1804 // The offset immediate is #4. The operand value is scaled by 4 for the
1805 // tSTR instruction.
1806 TmpInst.addOperand(MCOperand::CreateImm(1));
1808 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1809 TmpInst.addOperand(MCOperand::CreateReg(0));
1810 OutStreamer.EmitInstruction(TmpInst);
1814 TmpInst.setOpcode(ARM::tMOVi8);
1815 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1816 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1817 TmpInst.addOperand(MCOperand::CreateImm(0));
1819 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1820 TmpInst.addOperand(MCOperand::CreateReg(0));
1821 OutStreamer.EmitInstruction(TmpInst);
1824 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1826 TmpInst.setOpcode(ARM::tB);
1827 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1828 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1829 TmpInst.addOperand(MCOperand::CreateReg(0));
1830 OutStreamer.EmitInstruction(TmpInst);
1834 TmpInst.setOpcode(ARM::tMOVi8);
1835 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1836 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1837 TmpInst.addOperand(MCOperand::CreateImm(1));
1839 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1840 TmpInst.addOperand(MCOperand::CreateReg(0));
1841 OutStreamer.AddComment("eh_setjmp end");
1842 OutStreamer.EmitInstruction(TmpInst);
1844 OutStreamer.EmitLabel(Label);
1848 case ARM::Int_eh_sjlj_setjmp_nofp:
1849 case ARM::Int_eh_sjlj_setjmp: {
1850 // Two incoming args: GPR:$src, GPR:$val
1852 // str $val, [$src, #+4]
1856 unsigned SrcReg = MI->getOperand(0).getReg();
1857 unsigned ValReg = MI->getOperand(1).getReg();
1861 TmpInst.setOpcode(ARM::ADDri);
1862 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1863 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1864 TmpInst.addOperand(MCOperand::CreateImm(8));
1866 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1867 TmpInst.addOperand(MCOperand::CreateReg(0));
1868 // 's' bit operand (always reg0 for this).
1869 TmpInst.addOperand(MCOperand::CreateReg(0));
1870 OutStreamer.AddComment("eh_setjmp begin");
1871 OutStreamer.EmitInstruction(TmpInst);
1875 TmpInst.setOpcode(ARM::STRi12);
1876 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1877 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1878 TmpInst.addOperand(MCOperand::CreateImm(4));
1880 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1881 TmpInst.addOperand(MCOperand::CreateReg(0));
1882 OutStreamer.EmitInstruction(TmpInst);
1886 TmpInst.setOpcode(ARM::MOVi);
1887 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1888 TmpInst.addOperand(MCOperand::CreateImm(0));
1890 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1891 TmpInst.addOperand(MCOperand::CreateReg(0));
1892 // 's' bit operand (always reg0 for this).
1893 TmpInst.addOperand(MCOperand::CreateReg(0));
1894 OutStreamer.EmitInstruction(TmpInst);
1898 TmpInst.setOpcode(ARM::ADDri);
1899 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1900 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1901 TmpInst.addOperand(MCOperand::CreateImm(0));
1903 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1904 TmpInst.addOperand(MCOperand::CreateReg(0));
1905 // 's' bit operand (always reg0 for this).
1906 TmpInst.addOperand(MCOperand::CreateReg(0));
1907 OutStreamer.EmitInstruction(TmpInst);
1911 TmpInst.setOpcode(ARM::MOVi);
1912 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1913 TmpInst.addOperand(MCOperand::CreateImm(1));
1915 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1916 TmpInst.addOperand(MCOperand::CreateReg(0));
1917 // 's' bit operand (always reg0 for this).
1918 TmpInst.addOperand(MCOperand::CreateReg(0));
1919 OutStreamer.AddComment("eh_setjmp end");
1920 OutStreamer.EmitInstruction(TmpInst);
1924 case ARM::Int_eh_sjlj_longjmp: {
1925 // ldr sp, [$src, #8]
1926 // ldr $scratch, [$src, #4]
1929 unsigned SrcReg = MI->getOperand(0).getReg();
1930 unsigned ScratchReg = MI->getOperand(1).getReg();
1933 TmpInst.setOpcode(ARM::LDRi12);
1934 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1935 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1936 TmpInst.addOperand(MCOperand::CreateImm(8));
1938 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1939 TmpInst.addOperand(MCOperand::CreateReg(0));
1940 OutStreamer.EmitInstruction(TmpInst);
1944 TmpInst.setOpcode(ARM::LDRi12);
1945 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1946 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1947 TmpInst.addOperand(MCOperand::CreateImm(4));
1949 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1950 TmpInst.addOperand(MCOperand::CreateReg(0));
1951 OutStreamer.EmitInstruction(TmpInst);
1955 TmpInst.setOpcode(ARM::LDRi12);
1956 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1957 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1958 TmpInst.addOperand(MCOperand::CreateImm(0));
1960 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1961 TmpInst.addOperand(MCOperand::CreateReg(0));
1962 OutStreamer.EmitInstruction(TmpInst);
1966 TmpInst.setOpcode(ARM::BX);
1967 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1969 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1970 TmpInst.addOperand(MCOperand::CreateReg(0));
1971 OutStreamer.EmitInstruction(TmpInst);
1975 case ARM::tInt_eh_sjlj_longjmp: {
1976 // ldr $scratch, [$src, #8]
1978 // ldr $scratch, [$src, #4]
1981 unsigned SrcReg = MI->getOperand(0).getReg();
1982 unsigned ScratchReg = MI->getOperand(1).getReg();
1985 TmpInst.setOpcode(ARM::tLDRi);
1986 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1987 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1988 // The offset immediate is #8. The operand value is scaled by 4 for the
1989 // tLDR instruction.
1990 TmpInst.addOperand(MCOperand::CreateImm(2));
1992 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1993 TmpInst.addOperand(MCOperand::CreateReg(0));
1994 OutStreamer.EmitInstruction(TmpInst);
1998 TmpInst.setOpcode(ARM::tMOVr);
1999 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
2000 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2002 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2003 TmpInst.addOperand(MCOperand::CreateReg(0));
2004 OutStreamer.EmitInstruction(TmpInst);
2008 TmpInst.setOpcode(ARM::tLDRi);
2009 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2010 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2011 TmpInst.addOperand(MCOperand::CreateImm(1));
2013 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2014 TmpInst.addOperand(MCOperand::CreateReg(0));
2015 OutStreamer.EmitInstruction(TmpInst);
2019 TmpInst.setOpcode(ARM::tLDRi);
2020 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2021 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2022 TmpInst.addOperand(MCOperand::CreateImm(0));
2024 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2025 TmpInst.addOperand(MCOperand::CreateReg(0));
2026 OutStreamer.EmitInstruction(TmpInst);
2030 TmpInst.setOpcode(ARM::tBX);
2031 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2033 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2034 TmpInst.addOperand(MCOperand::CreateReg(0));
2035 OutStreamer.EmitInstruction(TmpInst);
2042 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2044 OutStreamer.EmitInstruction(TmpInst);
2047 //===----------------------------------------------------------------------===//
2048 // Target Registry Stuff
2049 //===----------------------------------------------------------------------===//
2051 // Force static initialization.
2052 extern "C" void LLVMInitializeARMAsmPrinter() {
2053 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2054 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);