1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionEntryLabel() {
287 OutStreamer.ForceCodeRegion();
289 if (AFI->isThumbFunction()) {
290 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
291 OutStreamer.EmitThumbFunc(CurrentFnSym);
294 OutStreamer.EmitLabel(CurrentFnSym);
297 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
298 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
299 assert(Size && "C++ constructor pointer had zero size!");
301 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
302 assert(GV && "C++ constructor pointer was not a GlobalValue!");
304 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
305 (Subtarget->isTargetDarwin()
306 ? MCSymbolRefExpr::VK_None
307 : MCSymbolRefExpr::VK_ARM_TARGET1),
310 OutStreamer.EmitValue(E, Size);
313 /// runOnMachineFunction - This uses the EmitInstruction()
314 /// method to print assembly for each instruction.
316 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
317 AFI = MF.getInfo<ARMFunctionInfo>();
318 MCP = MF.getConstantPool();
320 return AsmPrinter::runOnMachineFunction(MF);
323 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
324 raw_ostream &O, const char *Modifier) {
325 const MachineOperand &MO = MI->getOperand(OpNum);
326 unsigned TF = MO.getTargetFlags();
328 switch (MO.getType()) {
329 default: llvm_unreachable("<unknown operand type>");
330 case MachineOperand::MO_Register: {
331 unsigned Reg = MO.getReg();
332 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
333 assert(!MO.getSubReg() && "Subregs should be eliminated!");
334 O << ARMInstPrinter::getRegisterName(Reg);
337 case MachineOperand::MO_Immediate: {
338 int64_t Imm = MO.getImm();
340 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
341 (TF == ARMII::MO_LO16))
343 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
344 (TF == ARMII::MO_HI16))
349 case MachineOperand::MO_MachineBasicBlock:
350 O << *MO.getMBB()->getSymbol();
352 case MachineOperand::MO_GlobalAddress: {
353 const GlobalValue *GV = MO.getGlobal();
354 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
355 (TF & ARMII::MO_LO16))
357 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
358 (TF & ARMII::MO_HI16))
360 O << *Mang->getSymbol(GV);
362 printOffset(MO.getOffset(), O);
363 if (TF == ARMII::MO_PLT)
367 case MachineOperand::MO_ExternalSymbol: {
368 O << *GetExternalSymbolSymbol(MO.getSymbolName());
369 if (TF == ARMII::MO_PLT)
373 case MachineOperand::MO_ConstantPoolIndex:
374 O << *GetCPISymbol(MO.getIndex());
376 case MachineOperand::MO_JumpTableIndex:
377 O << *GetJTISymbol(MO.getIndex());
382 //===--------------------------------------------------------------------===//
384 MCSymbol *ARMAsmPrinter::
385 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
386 const MachineBasicBlock *MBB) const {
387 SmallString<60> Name;
388 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
389 << getFunctionNumber() << '_' << uid << '_' << uid2
390 << "_set_" << MBB->getNumber();
391 return OutContext.GetOrCreateSymbol(Name.str());
394 MCSymbol *ARMAsmPrinter::
395 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
396 SmallString<60> Name;
397 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
398 << getFunctionNumber() << '_' << uid << '_' << uid2;
399 return OutContext.GetOrCreateSymbol(Name.str());
403 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
404 SmallString<60> Name;
405 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
406 << getFunctionNumber();
407 return OutContext.GetOrCreateSymbol(Name.str());
410 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
411 unsigned AsmVariant, const char *ExtraCode,
413 // Does this asm operand have a single letter operand modifier?
414 if (ExtraCode && ExtraCode[0]) {
415 if (ExtraCode[1] != 0) return true; // Unknown modifier.
417 switch (ExtraCode[0]) {
418 default: return true; // Unknown modifier.
419 case 'a': // Print as a memory address.
420 if (MI->getOperand(OpNum).isReg()) {
422 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
427 case 'c': // Don't print "#" before an immediate operand.
428 if (!MI->getOperand(OpNum).isImm())
430 O << MI->getOperand(OpNum).getImm();
432 case 'P': // Print a VFP double precision register.
433 case 'q': // Print a NEON quad precision register.
434 printOperand(MI, OpNum, O);
436 case 'y': // Print a VFP single precision register as indexed double.
437 // This uses the ordering of the alias table to get the first 'd' register
438 // that overlaps the 's' register. Also, s0 is an odd register, hence the
439 // odd modulus check below.
440 if (MI->getOperand(OpNum).isReg()) {
441 unsigned Reg = MI->getOperand(OpNum).getReg();
442 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
443 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
444 (((Reg % 2) == 1) ? "[0]" : "[1]");
448 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
449 if (!MI->getOperand(OpNum).isImm())
451 O << ~(MI->getOperand(OpNum).getImm());
453 case 'L': // The low 16 bits of an immediate constant.
454 if (!MI->getOperand(OpNum).isImm())
456 O << (MI->getOperand(OpNum).getImm() & 0xffff);
458 case 'M': { // A register range suitable for LDM/STM.
459 if (!MI->getOperand(OpNum).isReg())
461 const MachineOperand &MO = MI->getOperand(OpNum);
462 unsigned RegBegin = MO.getReg();
463 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
464 // already got the operands in registers that are operands to the
465 // inline asm statement.
467 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
469 // FIXME: The register allocator not only may not have given us the
470 // registers in sequence, but may not be in ascending registers. This
471 // will require changes in the register allocator that'll need to be
472 // propagated down here if the operands change.
473 unsigned RegOps = OpNum + 1;
474 while (MI->getOperand(RegOps).isReg()) {
476 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
484 case 'R': // The most significant register of a pair.
485 case 'Q': { // The least significant register of a pair.
488 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
489 if (!FlagsOP.isImm())
491 unsigned Flags = FlagsOP.getImm();
492 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
495 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
496 if (RegOp >= MI->getNumOperands())
498 const MachineOperand &MO = MI->getOperand(RegOp);
501 unsigned Reg = MO.getReg();
502 O << ARMInstPrinter::getRegisterName(Reg);
506 case 'e': // The low doubleword register of a NEON quad register.
507 case 'f': { // The high doubleword register of a NEON quad register.
508 if (!MI->getOperand(OpNum).isReg())
510 unsigned Reg = MI->getOperand(OpNum).getReg();
511 if (!ARM::QPRRegClass.contains(Reg))
513 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
514 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
515 ARM::dsub_0 : ARM::dsub_1);
516 O << ARMInstPrinter::getRegisterName(SubReg);
520 // These modifiers are not yet supported.
521 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
522 case 'H': // The highest-numbered register of a pair.
527 printOperand(MI, OpNum, O);
531 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
532 unsigned OpNum, unsigned AsmVariant,
533 const char *ExtraCode,
535 // Does this asm operand have a single letter operand modifier?
536 if (ExtraCode && ExtraCode[0]) {
537 if (ExtraCode[1] != 0) return true; // Unknown modifier.
539 switch (ExtraCode[0]) {
540 case 'A': // A memory operand for a VLD1/VST1 instruction.
541 default: return true; // Unknown modifier.
542 case 'm': // The base register of a memory operand.
543 if (!MI->getOperand(OpNum).isReg())
545 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
550 const MachineOperand &MO = MI->getOperand(OpNum);
551 assert(MO.isReg() && "unexpected inline asm memory operand");
552 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
556 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
557 if (Subtarget->isTargetDarwin()) {
558 Reloc::Model RelocM = TM.getRelocationModel();
559 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
560 // Declare all the text sections up front (before the DWARF sections
561 // emitted by AsmPrinter::doInitialization) so the assembler will keep
562 // them together at the beginning of the object file. This helps
563 // avoid out-of-range branches that are due a fundamental limitation of
564 // the way symbol offsets are encoded with the current Darwin ARM
566 const TargetLoweringObjectFileMachO &TLOFMacho =
567 static_cast<const TargetLoweringObjectFileMachO &>(
568 getObjFileLowering());
569 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
570 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
571 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
572 if (RelocM == Reloc::DynamicNoPIC) {
573 const MCSection *sect =
574 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
575 MCSectionMachO::S_SYMBOL_STUBS,
576 12, SectionKind::getText());
577 OutStreamer.SwitchSection(sect);
579 const MCSection *sect =
580 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
581 MCSectionMachO::S_SYMBOL_STUBS,
582 16, SectionKind::getText());
583 OutStreamer.SwitchSection(sect);
585 const MCSection *StaticInitSect =
586 OutContext.getMachOSection("__TEXT", "__StaticInit",
587 MCSectionMachO::S_REGULAR |
588 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
589 SectionKind::getText());
590 OutStreamer.SwitchSection(StaticInitSect);
594 // Use unified assembler syntax.
595 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
597 // Emit ARM Build Attributes
598 if (Subtarget->isTargetELF())
603 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
604 if (Subtarget->isTargetDarwin()) {
605 // All darwin targets use mach-o.
606 const TargetLoweringObjectFileMachO &TLOFMacho =
607 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
608 MachineModuleInfoMachO &MMIMacho =
609 MMI->getObjFileInfo<MachineModuleInfoMachO>();
611 // Output non-lazy-pointers for external and common global variables.
612 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
614 if (!Stubs.empty()) {
615 // Switch with ".non_lazy_symbol_pointer" directive.
616 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
618 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
620 OutStreamer.EmitLabel(Stubs[i].first);
621 // .indirect_symbol _foo
622 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
623 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
626 // External to current translation unit.
627 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
629 // Internal to current translation unit.
631 // When we place the LSDA into the TEXT section, the type info
632 // pointers need to be indirect and pc-rel. We accomplish this by
633 // using NLPs; however, sometimes the types are local to the file.
634 // We need to fill in the value for the NLP in those cases.
635 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
637 4/*size*/, 0/*addrspace*/);
641 OutStreamer.AddBlankLine();
644 Stubs = MMIMacho.GetHiddenGVStubList();
645 if (!Stubs.empty()) {
646 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
648 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
650 OutStreamer.EmitLabel(Stubs[i].first);
652 OutStreamer.EmitValue(MCSymbolRefExpr::
653 Create(Stubs[i].second.getPointer(),
655 4/*size*/, 0/*addrspace*/);
659 OutStreamer.AddBlankLine();
662 // Funny Darwin hack: This flag tells the linker that no global symbols
663 // contain code that falls through to other global symbols (e.g. the obvious
664 // implementation of multiple entry points). If this doesn't occur, the
665 // linker can safely perform dead code stripping. Since LLVM never
666 // generates code that does this, it is always safe to set.
667 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
671 //===----------------------------------------------------------------------===//
672 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
674 // The following seem like one-off assembler flags, but they actually need
675 // to appear in the .ARM.attributes section in ELF.
676 // Instead of subclassing the MCELFStreamer, we do the work here.
678 void ARMAsmPrinter::emitAttributes() {
680 emitARMAttributeSection();
682 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
683 bool emitFPU = false;
684 AttributeEmitter *AttrEmitter;
685 if (OutStreamer.hasRawTextSupport()) {
686 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
689 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
690 AttrEmitter = new ObjectAttributeEmitter(O);
693 AttrEmitter->MaybeSwitchVendor("aeabi");
695 std::string CPUString = Subtarget->getCPUString();
697 if (CPUString == "cortex-a8" ||
698 Subtarget->isCortexA8()) {
699 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
700 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
701 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
702 ARMBuildAttrs::ApplicationProfile);
703 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
704 ARMBuildAttrs::Allowed);
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
706 ARMBuildAttrs::AllowThumb32);
707 // Fixme: figure out when this is emitted.
708 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
709 // ARMBuildAttrs::AllowWMMXv1);
712 /// ADD additional Else-cases here!
713 } else if (CPUString == "xscale") {
714 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
715 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
716 ARMBuildAttrs::Allowed);
717 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
718 ARMBuildAttrs::Allowed);
719 } else if (CPUString == "generic") {
720 // FIXME: Why these defaults?
721 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
722 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
723 ARMBuildAttrs::Allowed);
724 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
725 ARMBuildAttrs::Allowed);
728 if (Subtarget->hasNEON() && emitFPU) {
729 /* NEON is not exactly a VFP architecture, but GAS emit one of
730 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
731 if (Subtarget->hasNEON2())
732 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon-vfpv4");
734 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
735 /* If emitted for NEON, omit from VFP below, since you can have both
736 * NEON and VFP in build attributes but only one .fpu */
741 if (Subtarget->hasVFP4()) {
742 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
743 ARMBuildAttrs::AllowFPv4A);
745 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
748 } else if (Subtarget->hasVFP3()) {
749 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
750 ARMBuildAttrs::AllowFPv3A);
752 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
755 } else if (Subtarget->hasVFP2()) {
756 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
757 ARMBuildAttrs::AllowFPv2);
759 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
762 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
763 * since NEON can have 1 (allowed) or 2 (MAC operations) */
764 if (Subtarget->hasNEON()) {
765 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
766 ARMBuildAttrs::Allowed);
769 // Signal various FP modes.
770 if (!TM.Options.UnsafeFPMath) {
771 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
772 ARMBuildAttrs::Allowed);
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
774 ARMBuildAttrs::Allowed);
777 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
778 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
779 ARMBuildAttrs::Allowed);
781 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
782 ARMBuildAttrs::AllowIEE754);
784 // FIXME: add more flags to ARMBuildAttrs.h
785 // 8-bytes alignment stuff.
786 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
787 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
789 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
790 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
791 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
792 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
794 // FIXME: Should we signal R9 usage?
796 if (Subtarget->hasDivide())
797 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
799 AttrEmitter->Finish();
803 void ARMAsmPrinter::emitARMAttributeSection() {
805 // [ <section-length> "vendor-name"
806 // [ <file-tag> <size> <attribute>*
807 // | <section-tag> <size> <section-number>* 0 <attribute>*
808 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
812 if (OutStreamer.hasRawTextSupport())
815 const ARMElfTargetObjectFile &TLOFELF =
816 static_cast<const ARMElfTargetObjectFile &>
817 (getObjFileLowering());
819 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
822 OutStreamer.EmitIntValue(0x41, 1);
825 //===----------------------------------------------------------------------===//
827 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
828 unsigned LabelId, MCContext &Ctx) {
830 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
831 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
835 static MCSymbolRefExpr::VariantKind
836 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
838 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
839 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
840 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
841 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
842 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
843 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
845 llvm_unreachable("Invalid ARMCPModifier!");
848 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
849 bool isIndirect = Subtarget->isTargetDarwin() &&
850 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
852 return Mang->getSymbol(GV);
854 // FIXME: Remove this when Darwin transition to @GOT like syntax.
855 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
856 MachineModuleInfoMachO &MMIMachO =
857 MMI->getObjFileInfo<MachineModuleInfoMachO>();
858 MachineModuleInfoImpl::StubValueTy &StubSym =
859 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
860 MMIMachO.getGVStubEntry(MCSym);
861 if (StubSym.getPointer() == 0)
862 StubSym = MachineModuleInfoImpl::
863 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
868 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
869 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
871 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
874 if (ACPV->isLSDA()) {
875 SmallString<128> Str;
876 raw_svector_ostream OS(Str);
877 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
878 MCSym = OutContext.GetOrCreateSymbol(OS.str());
879 } else if (ACPV->isBlockAddress()) {
880 const BlockAddress *BA =
881 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
882 MCSym = GetBlockAddressSymbol(BA);
883 } else if (ACPV->isGlobalValue()) {
884 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
885 MCSym = GetARMGVSymbol(GV);
886 } else if (ACPV->isMachineBasicBlock()) {
887 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
888 MCSym = MBB->getSymbol();
890 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
891 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
892 MCSym = GetExternalSymbolSymbol(Sym);
895 // Create an MCSymbol for the reference.
897 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
900 if (ACPV->getPCAdjustment()) {
901 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
905 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
907 MCBinaryExpr::CreateAdd(PCRelExpr,
908 MCConstantExpr::Create(ACPV->getPCAdjustment(),
911 if (ACPV->mustAddCurrentAddress()) {
912 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
913 // label, so just emit a local label end reference that instead.
914 MCSymbol *DotSym = OutContext.CreateTempSymbol();
915 OutStreamer.EmitLabel(DotSym);
916 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
917 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
919 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
921 OutStreamer.EmitValue(Expr, Size);
924 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
925 unsigned Opcode = MI->getOpcode();
927 if (Opcode == ARM::BR_JTadd)
929 else if (Opcode == ARM::BR_JTm)
932 const MachineOperand &MO1 = MI->getOperand(OpNum);
933 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
934 unsigned JTI = MO1.getIndex();
936 // Tag the jump table appropriately for precise disassembly.
937 OutStreamer.EmitJumpTable32Region();
939 // Emit a label for the jump table.
940 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
941 OutStreamer.EmitLabel(JTISymbol);
943 // Emit each entry of the table.
944 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
945 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
946 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
948 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
949 MachineBasicBlock *MBB = JTBBs[i];
950 // Construct an MCExpr for the entry. We want a value of the form:
951 // (BasicBlockAddr - TableBeginAddr)
953 // For example, a table with entries jumping to basic blocks BB0 and BB1
956 // .word (LBB0 - LJTI_0_0)
957 // .word (LBB1 - LJTI_0_0)
958 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
960 if (TM.getRelocationModel() == Reloc::PIC_)
961 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
964 // If we're generating a table of Thumb addresses in static relocation
965 // model, we need to add one to keep interworking correctly.
966 else if (AFI->isThumbFunction())
967 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
969 OutStreamer.EmitValue(Expr, 4);
973 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
974 unsigned Opcode = MI->getOpcode();
975 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
976 const MachineOperand &MO1 = MI->getOperand(OpNum);
977 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
978 unsigned JTI = MO1.getIndex();
980 // Emit a label for the jump table.
981 if (MI->getOpcode() == ARM::t2TBB_JT) {
982 OutStreamer.EmitJumpTable8Region();
983 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
984 OutStreamer.EmitJumpTable16Region();
986 OutStreamer.EmitJumpTable32Region();
989 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
990 OutStreamer.EmitLabel(JTISymbol);
992 // Emit each entry of the table.
993 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
994 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
995 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
996 unsigned OffsetWidth = 4;
997 if (MI->getOpcode() == ARM::t2TBB_JT)
999 else if (MI->getOpcode() == ARM::t2TBH_JT)
1002 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1003 MachineBasicBlock *MBB = JTBBs[i];
1004 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1006 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1007 if (OffsetWidth == 4) {
1009 BrInst.setOpcode(ARM::t2B);
1010 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1011 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1012 BrInst.addOperand(MCOperand::CreateReg(0));
1013 OutStreamer.EmitInstruction(BrInst);
1016 // Otherwise it's an offset from the dispatch instruction. Construct an
1017 // MCExpr for the entry. We want a value of the form:
1018 // (BasicBlockAddr - TableBeginAddr) / 2
1020 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1023 // .byte (LBB0 - LJTI_0_0) / 2
1024 // .byte (LBB1 - LJTI_0_0) / 2
1025 const MCExpr *Expr =
1026 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1027 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1029 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1031 OutStreamer.EmitValue(Expr, OffsetWidth);
1035 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1037 unsigned NOps = MI->getNumOperands();
1039 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1040 // cast away const; DIetc do not take const operands for some reason.
1041 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1044 // Frame address. Currently handles register +- offset only.
1045 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1046 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1049 printOperand(MI, NOps-2, OS);
1052 static void populateADROperands(MCInst &Inst, unsigned Dest,
1053 const MCSymbol *Label,
1054 unsigned pred, unsigned ccreg,
1056 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1057 Inst.addOperand(MCOperand::CreateReg(Dest));
1058 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1059 // Add predicate operands.
1060 Inst.addOperand(MCOperand::CreateImm(pred));
1061 Inst.addOperand(MCOperand::CreateReg(ccreg));
1064 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1068 // Emit the instruction as usual, just patch the opcode.
1069 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1070 TmpInst.setOpcode(Opcode);
1071 OutStreamer.EmitInstruction(TmpInst);
1074 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1075 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1076 "Only instruction which are involved into frame setup code are allowed");
1078 const MachineFunction &MF = *MI->getParent()->getParent();
1079 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1080 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1082 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1083 unsigned Opc = MI->getOpcode();
1084 unsigned SrcReg, DstReg;
1086 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1087 // Two special cases:
1088 // 1) tPUSH does not have src/dst regs.
1089 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1090 // load. Yes, this is pretty fragile, but for now I don't see better
1092 SrcReg = DstReg = ARM::SP;
1094 SrcReg = MI->getOperand(1).getReg();
1095 DstReg = MI->getOperand(0).getReg();
1098 // Try to figure out the unwinding opcode out of src / dst regs.
1099 if (MI->mayStore()) {
1101 assert(DstReg == ARM::SP &&
1102 "Only stack pointer as a destination reg is supported");
1104 SmallVector<unsigned, 4> RegList;
1105 // Skip src & dst reg, and pred ops.
1106 unsigned StartOp = 2 + 2;
1107 // Use all the operands.
1108 unsigned NumOffset = 0;
1113 llvm_unreachable("Unsupported opcode for unwinding information");
1115 // Special case here: no src & dst reg, but two extra imp ops.
1116 StartOp = 2; NumOffset = 2;
1117 case ARM::STMDB_UPD:
1118 case ARM::t2STMDB_UPD:
1119 case ARM::VSTMDDB_UPD:
1120 assert(SrcReg == ARM::SP &&
1121 "Only stack pointer as a source reg is supported");
1122 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1124 RegList.push_back(MI->getOperand(i).getReg());
1126 case ARM::STR_PRE_IMM:
1127 case ARM::STR_PRE_REG:
1128 case ARM::t2STR_PRE:
1129 assert(MI->getOperand(2).getReg() == ARM::SP &&
1130 "Only stack pointer as a source reg is supported");
1131 RegList.push_back(SrcReg);
1134 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1136 // Changes of stack / frame pointer.
1137 if (SrcReg == ARM::SP) {
1142 llvm_unreachable("Unsupported opcode for unwinding information");
1148 Offset = -MI->getOperand(2).getImm();
1152 Offset = MI->getOperand(2).getImm();
1155 Offset = MI->getOperand(2).getImm()*4;
1159 Offset = -MI->getOperand(2).getImm()*4;
1161 case ARM::tLDRpci: {
1162 // Grab the constpool index and check, whether it corresponds to
1163 // original or cloned constpool entry.
1164 unsigned CPI = MI->getOperand(1).getIndex();
1165 const MachineConstantPool *MCP = MF.getConstantPool();
1166 if (CPI >= MCP->getConstants().size())
1167 CPI = AFI.getOriginalCPIdx(CPI);
1168 assert(CPI != -1U && "Invalid constpool index");
1170 // Derive the actual offset.
1171 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1172 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1173 // FIXME: Check for user, it should be "add" instruction!
1174 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1179 if (DstReg == FramePtr && FramePtr != ARM::SP)
1180 // Set-up of the frame pointer. Positive values correspond to "add"
1182 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1183 else if (DstReg == ARM::SP) {
1184 // Change of SP by an offset. Positive values correspond to "sub"
1186 OutStreamer.EmitPad(Offset);
1189 llvm_unreachable("Unsupported opcode for unwinding information");
1191 } else if (DstReg == ARM::SP) {
1192 // FIXME: .movsp goes here
1194 llvm_unreachable("Unsupported opcode for unwinding information");
1198 llvm_unreachable("Unsupported opcode for unwinding information");
1203 extern cl::opt<bool> EnableARMEHABI;
1205 // Simple pseudo-instructions have their lowering (with expansion to real
1206 // instructions) auto-generated.
1207 #include "ARMGenMCPseudoLowering.inc"
1209 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1210 if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1211 OutStreamer.EmitCodeRegion();
1213 // Emit unwinding stuff for frame-related instructions
1214 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1215 EmitUnwindingInstruction(MI);
1217 // Do any auto-generated pseudo lowerings.
1218 if (emitPseudoExpansionLowering(OutStreamer, MI))
1221 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1222 "Pseudo flag setting opcode should be expanded early");
1224 // Check for manual lowerings.
1225 unsigned Opc = MI->getOpcode();
1227 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1228 case ARM::DBG_VALUE: {
1229 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1230 SmallString<128> TmpStr;
1231 raw_svector_ostream OS(TmpStr);
1232 PrintDebugValueComment(MI, OS);
1233 OutStreamer.EmitRawText(StringRef(OS.str()));
1238 case ARM::tLEApcrel:
1239 case ARM::t2LEApcrel: {
1240 // FIXME: Need to also handle globals and externals
1242 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1243 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1245 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1246 GetCPISymbol(MI->getOperand(1).getIndex()),
1247 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1249 OutStreamer.EmitInstruction(TmpInst);
1252 case ARM::LEApcrelJT:
1253 case ARM::tLEApcrelJT:
1254 case ARM::t2LEApcrelJT: {
1256 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1257 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1259 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1260 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1261 MI->getOperand(2).getImm()),
1262 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1264 OutStreamer.EmitInstruction(TmpInst);
1267 // Darwin call instructions are just normal call instructions with different
1268 // clobber semantics (they clobber R9).
1269 case ARM::BXr9_CALL:
1270 case ARM::BX_CALL: {
1273 TmpInst.setOpcode(ARM::MOVr);
1274 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1275 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1276 // Add predicate operands.
1277 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1278 TmpInst.addOperand(MCOperand::CreateReg(0));
1279 // Add 's' bit operand (always reg0 for this)
1280 TmpInst.addOperand(MCOperand::CreateReg(0));
1281 OutStreamer.EmitInstruction(TmpInst);
1285 TmpInst.setOpcode(ARM::BX);
1286 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1287 OutStreamer.EmitInstruction(TmpInst);
1291 case ARM::tBXr9_CALL:
1292 case ARM::tBX_CALL: {
1295 TmpInst.setOpcode(ARM::tMOVr);
1296 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1297 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1298 // Add predicate operands.
1299 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1300 TmpInst.addOperand(MCOperand::CreateReg(0));
1301 OutStreamer.EmitInstruction(TmpInst);
1305 TmpInst.setOpcode(ARM::tBX);
1306 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1307 // Add predicate operands.
1308 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1309 TmpInst.addOperand(MCOperand::CreateReg(0));
1310 OutStreamer.EmitInstruction(TmpInst);
1314 case ARM::BMOVPCRXr9_CALL:
1315 case ARM::BMOVPCRX_CALL: {
1318 TmpInst.setOpcode(ARM::MOVr);
1319 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1320 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1321 // Add predicate operands.
1322 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1323 TmpInst.addOperand(MCOperand::CreateReg(0));
1324 // Add 's' bit operand (always reg0 for this)
1325 TmpInst.addOperand(MCOperand::CreateReg(0));
1326 OutStreamer.EmitInstruction(TmpInst);
1330 TmpInst.setOpcode(ARM::MOVr);
1331 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1332 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1333 // Add predicate operands.
1334 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 // Add 's' bit operand (always reg0 for this)
1337 TmpInst.addOperand(MCOperand::CreateReg(0));
1338 OutStreamer.EmitInstruction(TmpInst);
1342 case ARM::BMOVPCBr9_CALL:
1343 case ARM::BMOVPCB_CALL: {
1346 TmpInst.setOpcode(ARM::MOVr);
1347 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1348 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1349 // Add predicate operands.
1350 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1351 TmpInst.addOperand(MCOperand::CreateReg(0));
1352 // Add 's' bit operand (always reg0 for this)
1353 TmpInst.addOperand(MCOperand::CreateReg(0));
1354 OutStreamer.EmitInstruction(TmpInst);
1358 TmpInst.setOpcode(ARM::Bcc);
1359 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1360 MCSymbol *GVSym = Mang->getSymbol(GV);
1361 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1362 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1363 // Add predicate operands.
1364 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1365 TmpInst.addOperand(MCOperand::CreateReg(0));
1366 OutStreamer.EmitInstruction(TmpInst);
1370 case ARM::t2BMOVPCBr9_CALL:
1371 case ARM::t2BMOVPCB_CALL: {
1374 TmpInst.setOpcode(ARM::tMOVr);
1375 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1376 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1377 // Add predicate operands.
1378 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1379 TmpInst.addOperand(MCOperand::CreateReg(0));
1380 OutStreamer.EmitInstruction(TmpInst);
1384 TmpInst.setOpcode(ARM::t2B);
1385 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1386 MCSymbol *GVSym = Mang->getSymbol(GV);
1387 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1388 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1389 // Add predicate operands.
1390 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1391 TmpInst.addOperand(MCOperand::CreateReg(0));
1392 OutStreamer.EmitInstruction(TmpInst);
1396 case ARM::MOVi16_ga_pcrel:
1397 case ARM::t2MOVi16_ga_pcrel: {
1399 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1400 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1402 unsigned TF = MI->getOperand(1).getTargetFlags();
1403 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1404 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1405 MCSymbol *GVSym = GetARMGVSymbol(GV);
1406 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1408 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1409 getFunctionNumber(),
1410 MI->getOperand(2).getImm(), OutContext);
1411 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1412 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1413 const MCExpr *PCRelExpr =
1414 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1415 MCBinaryExpr::CreateAdd(LabelSymExpr,
1416 MCConstantExpr::Create(PCAdj, OutContext),
1417 OutContext), OutContext), OutContext);
1418 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1420 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1421 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1424 // Add predicate operands.
1425 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1426 TmpInst.addOperand(MCOperand::CreateReg(0));
1427 // Add 's' bit operand (always reg0 for this)
1428 TmpInst.addOperand(MCOperand::CreateReg(0));
1429 OutStreamer.EmitInstruction(TmpInst);
1432 case ARM::MOVTi16_ga_pcrel:
1433 case ARM::t2MOVTi16_ga_pcrel: {
1435 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1436 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1437 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1438 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1440 unsigned TF = MI->getOperand(2).getTargetFlags();
1441 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1442 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1443 MCSymbol *GVSym = GetARMGVSymbol(GV);
1444 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1446 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1447 getFunctionNumber(),
1448 MI->getOperand(3).getImm(), OutContext);
1449 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1450 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1451 const MCExpr *PCRelExpr =
1452 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1453 MCBinaryExpr::CreateAdd(LabelSymExpr,
1454 MCConstantExpr::Create(PCAdj, OutContext),
1455 OutContext), OutContext), OutContext);
1456 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1458 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1459 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1461 // Add predicate operands.
1462 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1463 TmpInst.addOperand(MCOperand::CreateReg(0));
1464 // Add 's' bit operand (always reg0 for this)
1465 TmpInst.addOperand(MCOperand::CreateReg(0));
1466 OutStreamer.EmitInstruction(TmpInst);
1469 case ARM::tPICADD: {
1470 // This is a pseudo op for a label + instruction sequence, which looks like:
1473 // This adds the address of LPC0 to r0.
1476 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1477 getFunctionNumber(), MI->getOperand(2).getImm(),
1480 // Form and emit the add.
1482 AddInst.setOpcode(ARM::tADDhirr);
1483 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1484 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1485 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1486 // Add predicate operands.
1487 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1488 AddInst.addOperand(MCOperand::CreateReg(0));
1489 OutStreamer.EmitInstruction(AddInst);
1493 // This is a pseudo op for a label + instruction sequence, which looks like:
1496 // This adds the address of LPC0 to r0.
1499 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1500 getFunctionNumber(), MI->getOperand(2).getImm(),
1503 // Form and emit the add.
1505 AddInst.setOpcode(ARM::ADDrr);
1506 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1507 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1508 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1509 // Add predicate operands.
1510 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1511 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1512 // Add 's' bit operand (always reg0 for this)
1513 AddInst.addOperand(MCOperand::CreateReg(0));
1514 OutStreamer.EmitInstruction(AddInst);
1524 case ARM::PICLDRSH: {
1525 // This is a pseudo op for a label + instruction sequence, which looks like:
1528 // The LCP0 label is referenced by a constant pool entry in order to get
1529 // a PC-relative address at the ldr instruction.
1532 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1533 getFunctionNumber(), MI->getOperand(2).getImm(),
1536 // Form and emit the load
1538 switch (MI->getOpcode()) {
1540 llvm_unreachable("Unexpected opcode!");
1541 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1542 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1543 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1544 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1545 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1546 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1547 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1548 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1551 LdStInst.setOpcode(Opcode);
1552 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1553 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1554 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1555 LdStInst.addOperand(MCOperand::CreateImm(0));
1556 // Add predicate operands.
1557 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1558 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1559 OutStreamer.EmitInstruction(LdStInst);
1563 case ARM::CONSTPOOL_ENTRY: {
1564 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1565 /// in the function. The first operand is the ID# for this instruction, the
1566 /// second is the index into the MachineConstantPool that this is, the third
1567 /// is the size in bytes of this constant pool entry.
1568 /// The required alignment is specified on the basic block holding this MI.
1569 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1570 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1572 // Mark the constant pool entry as data if we're not already in a data
1574 OutStreamer.EmitDataRegion();
1575 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1577 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1578 if (MCPE.isMachineConstantPoolEntry())
1579 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1581 EmitGlobalConstant(MCPE.Val.ConstVal);
1584 case ARM::t2BR_JT: {
1585 // Lower and emit the instruction itself, then the jump table following it.
1587 TmpInst.setOpcode(ARM::tMOVr);
1588 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1589 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1590 // Add predicate operands.
1591 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1592 TmpInst.addOperand(MCOperand::CreateReg(0));
1593 OutStreamer.EmitInstruction(TmpInst);
1594 // Output the data for the jump table itself
1598 case ARM::t2TBB_JT: {
1599 // Lower and emit the instruction itself, then the jump table following it.
1602 TmpInst.setOpcode(ARM::t2TBB);
1603 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1604 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1605 // Add predicate operands.
1606 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1607 TmpInst.addOperand(MCOperand::CreateReg(0));
1608 OutStreamer.EmitInstruction(TmpInst);
1609 // Output the data for the jump table itself
1611 // Make sure the next instruction is 2-byte aligned.
1615 case ARM::t2TBH_JT: {
1616 // Lower and emit the instruction itself, then the jump table following it.
1619 TmpInst.setOpcode(ARM::t2TBH);
1620 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1621 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1622 // Add predicate operands.
1623 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1624 TmpInst.addOperand(MCOperand::CreateReg(0));
1625 OutStreamer.EmitInstruction(TmpInst);
1626 // Output the data for the jump table itself
1632 // Lower and emit the instruction itself, then the jump table following it.
1635 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1636 ARM::MOVr : ARM::tMOVr;
1637 TmpInst.setOpcode(Opc);
1638 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1639 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1640 // Add predicate operands.
1641 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1642 TmpInst.addOperand(MCOperand::CreateReg(0));
1643 // Add 's' bit operand (always reg0 for this)
1644 if (Opc == ARM::MOVr)
1645 TmpInst.addOperand(MCOperand::CreateReg(0));
1646 OutStreamer.EmitInstruction(TmpInst);
1648 // Make sure the Thumb jump table is 4-byte aligned.
1649 if (Opc == ARM::tMOVr)
1652 // Output the data for the jump table itself
1657 // Lower and emit the instruction itself, then the jump table following it.
1660 if (MI->getOperand(1).getReg() == 0) {
1662 TmpInst.setOpcode(ARM::LDRi12);
1663 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1664 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1665 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1667 TmpInst.setOpcode(ARM::LDRrs);
1668 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1669 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1670 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1671 TmpInst.addOperand(MCOperand::CreateImm(0));
1673 // Add predicate operands.
1674 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1675 TmpInst.addOperand(MCOperand::CreateReg(0));
1676 OutStreamer.EmitInstruction(TmpInst);
1678 // Output the data for the jump table itself
1682 case ARM::BR_JTadd: {
1683 // Lower and emit the instruction itself, then the jump table following it.
1684 // add pc, target, idx
1686 TmpInst.setOpcode(ARM::ADDrr);
1687 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1688 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1689 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1690 // Add predicate operands.
1691 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1692 TmpInst.addOperand(MCOperand::CreateReg(0));
1693 // Add 's' bit operand (always reg0 for this)
1694 TmpInst.addOperand(MCOperand::CreateReg(0));
1695 OutStreamer.EmitInstruction(TmpInst);
1697 // Output the data for the jump table itself
1702 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1703 // FIXME: Remove this special case when they do.
1704 if (!Subtarget->isTargetDarwin()) {
1705 //.long 0xe7ffdefe @ trap
1706 uint32_t Val = 0xe7ffdefeUL;
1707 OutStreamer.AddComment("trap");
1708 OutStreamer.EmitIntValue(Val, 4);
1714 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1715 // FIXME: Remove this special case when they do.
1716 if (!Subtarget->isTargetDarwin()) {
1717 //.short 57086 @ trap
1718 uint16_t Val = 0xdefe;
1719 OutStreamer.AddComment("trap");
1720 OutStreamer.EmitIntValue(Val, 2);
1725 case ARM::t2Int_eh_sjlj_setjmp:
1726 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1727 case ARM::tInt_eh_sjlj_setjmp: {
1728 // Two incoming args: GPR:$src, GPR:$val
1731 // str $val, [$src, #4]
1736 unsigned SrcReg = MI->getOperand(0).getReg();
1737 unsigned ValReg = MI->getOperand(1).getReg();
1738 MCSymbol *Label = GetARMSJLJEHLabel();
1741 TmpInst.setOpcode(ARM::tMOVr);
1742 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1743 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1745 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1746 TmpInst.addOperand(MCOperand::CreateReg(0));
1747 OutStreamer.AddComment("eh_setjmp begin");
1748 OutStreamer.EmitInstruction(TmpInst);
1752 TmpInst.setOpcode(ARM::tADDi3);
1753 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1755 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1756 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1757 TmpInst.addOperand(MCOperand::CreateImm(7));
1759 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1760 TmpInst.addOperand(MCOperand::CreateReg(0));
1761 OutStreamer.EmitInstruction(TmpInst);
1765 TmpInst.setOpcode(ARM::tSTRi);
1766 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1767 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1768 // The offset immediate is #4. The operand value is scaled by 4 for the
1769 // tSTR instruction.
1770 TmpInst.addOperand(MCOperand::CreateImm(1));
1772 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1773 TmpInst.addOperand(MCOperand::CreateReg(0));
1774 OutStreamer.EmitInstruction(TmpInst);
1778 TmpInst.setOpcode(ARM::tMOVi8);
1779 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1780 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1781 TmpInst.addOperand(MCOperand::CreateImm(0));
1783 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1784 TmpInst.addOperand(MCOperand::CreateReg(0));
1785 OutStreamer.EmitInstruction(TmpInst);
1788 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1790 TmpInst.setOpcode(ARM::tB);
1791 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1792 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1793 TmpInst.addOperand(MCOperand::CreateReg(0));
1794 OutStreamer.EmitInstruction(TmpInst);
1798 TmpInst.setOpcode(ARM::tMOVi8);
1799 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1800 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1801 TmpInst.addOperand(MCOperand::CreateImm(1));
1803 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1804 TmpInst.addOperand(MCOperand::CreateReg(0));
1805 OutStreamer.AddComment("eh_setjmp end");
1806 OutStreamer.EmitInstruction(TmpInst);
1808 OutStreamer.EmitLabel(Label);
1812 case ARM::Int_eh_sjlj_setjmp_nofp:
1813 case ARM::Int_eh_sjlj_setjmp: {
1814 // Two incoming args: GPR:$src, GPR:$val
1816 // str $val, [$src, #+4]
1820 unsigned SrcReg = MI->getOperand(0).getReg();
1821 unsigned ValReg = MI->getOperand(1).getReg();
1825 TmpInst.setOpcode(ARM::ADDri);
1826 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1827 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1828 TmpInst.addOperand(MCOperand::CreateImm(8));
1830 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1831 TmpInst.addOperand(MCOperand::CreateReg(0));
1832 // 's' bit operand (always reg0 for this).
1833 TmpInst.addOperand(MCOperand::CreateReg(0));
1834 OutStreamer.AddComment("eh_setjmp begin");
1835 OutStreamer.EmitInstruction(TmpInst);
1839 TmpInst.setOpcode(ARM::STRi12);
1840 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1841 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1842 TmpInst.addOperand(MCOperand::CreateImm(4));
1844 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1845 TmpInst.addOperand(MCOperand::CreateReg(0));
1846 OutStreamer.EmitInstruction(TmpInst);
1850 TmpInst.setOpcode(ARM::MOVi);
1851 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1852 TmpInst.addOperand(MCOperand::CreateImm(0));
1854 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1855 TmpInst.addOperand(MCOperand::CreateReg(0));
1856 // 's' bit operand (always reg0 for this).
1857 TmpInst.addOperand(MCOperand::CreateReg(0));
1858 OutStreamer.EmitInstruction(TmpInst);
1862 TmpInst.setOpcode(ARM::ADDri);
1863 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1864 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1865 TmpInst.addOperand(MCOperand::CreateImm(0));
1867 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1868 TmpInst.addOperand(MCOperand::CreateReg(0));
1869 // 's' bit operand (always reg0 for this).
1870 TmpInst.addOperand(MCOperand::CreateReg(0));
1871 OutStreamer.EmitInstruction(TmpInst);
1875 TmpInst.setOpcode(ARM::MOVi);
1876 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1877 TmpInst.addOperand(MCOperand::CreateImm(1));
1879 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1880 TmpInst.addOperand(MCOperand::CreateReg(0));
1881 // 's' bit operand (always reg0 for this).
1882 TmpInst.addOperand(MCOperand::CreateReg(0));
1883 OutStreamer.AddComment("eh_setjmp end");
1884 OutStreamer.EmitInstruction(TmpInst);
1888 case ARM::Int_eh_sjlj_longjmp: {
1889 // ldr sp, [$src, #8]
1890 // ldr $scratch, [$src, #4]
1893 unsigned SrcReg = MI->getOperand(0).getReg();
1894 unsigned ScratchReg = MI->getOperand(1).getReg();
1897 TmpInst.setOpcode(ARM::LDRi12);
1898 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1899 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1900 TmpInst.addOperand(MCOperand::CreateImm(8));
1902 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1903 TmpInst.addOperand(MCOperand::CreateReg(0));
1904 OutStreamer.EmitInstruction(TmpInst);
1908 TmpInst.setOpcode(ARM::LDRi12);
1909 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1910 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1911 TmpInst.addOperand(MCOperand::CreateImm(4));
1913 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1914 TmpInst.addOperand(MCOperand::CreateReg(0));
1915 OutStreamer.EmitInstruction(TmpInst);
1919 TmpInst.setOpcode(ARM::LDRi12);
1920 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1921 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1922 TmpInst.addOperand(MCOperand::CreateImm(0));
1924 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1925 TmpInst.addOperand(MCOperand::CreateReg(0));
1926 OutStreamer.EmitInstruction(TmpInst);
1930 TmpInst.setOpcode(ARM::BX);
1931 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1933 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1934 TmpInst.addOperand(MCOperand::CreateReg(0));
1935 OutStreamer.EmitInstruction(TmpInst);
1939 case ARM::tInt_eh_sjlj_longjmp: {
1940 // ldr $scratch, [$src, #8]
1942 // ldr $scratch, [$src, #4]
1945 unsigned SrcReg = MI->getOperand(0).getReg();
1946 unsigned ScratchReg = MI->getOperand(1).getReg();
1949 TmpInst.setOpcode(ARM::tLDRi);
1950 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1951 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1952 // The offset immediate is #8. The operand value is scaled by 4 for the
1953 // tLDR instruction.
1954 TmpInst.addOperand(MCOperand::CreateImm(2));
1956 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1957 TmpInst.addOperand(MCOperand::CreateReg(0));
1958 OutStreamer.EmitInstruction(TmpInst);
1962 TmpInst.setOpcode(ARM::tMOVr);
1963 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1964 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1966 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1967 TmpInst.addOperand(MCOperand::CreateReg(0));
1968 OutStreamer.EmitInstruction(TmpInst);
1972 TmpInst.setOpcode(ARM::tLDRi);
1973 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1974 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1975 TmpInst.addOperand(MCOperand::CreateImm(1));
1977 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1978 TmpInst.addOperand(MCOperand::CreateReg(0));
1979 OutStreamer.EmitInstruction(TmpInst);
1983 TmpInst.setOpcode(ARM::tLDRr);
1984 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1985 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1986 TmpInst.addOperand(MCOperand::CreateReg(0));
1988 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1989 TmpInst.addOperand(MCOperand::CreateReg(0));
1990 OutStreamer.EmitInstruction(TmpInst);
1994 TmpInst.setOpcode(ARM::tBX);
1995 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1997 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1998 TmpInst.addOperand(MCOperand::CreateReg(0));
1999 OutStreamer.EmitInstruction(TmpInst);
2006 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2008 OutStreamer.EmitInstruction(TmpInst);
2011 //===----------------------------------------------------------------------===//
2012 // Target Registry Stuff
2013 //===----------------------------------------------------------------------===//
2015 // Force static initialization.
2016 extern "C" void LLVMInitializeARMAsmPrinter() {
2017 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2018 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);