1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMFPUName.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallString.h"
29 #include "llvm/Assembly/Writer.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/DebugInfo.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DataLayout.h"
36 #include "llvm/IR/Module.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCAssembler.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCELFStreamer.h"
42 #include "llvm/MC/MCInst.h"
43 #include "llvm/MC/MCInstBuilder.h"
44 #include "llvm/MC/MCObjectStreamer.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/MC/MCStreamer.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/Mangler.h"
55 #include "llvm/Target/TargetMachine.h"
59 /// EmitDwarfRegOp - Emit dwarf register operation.
60 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
61 bool Indirect) const {
62 const TargetRegisterInfo *RI = TM.getRegisterInfo();
63 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
64 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
67 assert(MLoc.isReg() && !Indirect &&
68 "This doesn't support offset/indirection - implement it if needed");
69 unsigned Reg = MLoc.getReg();
70 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
71 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
72 // S registers are described as bit-pieces of a register
73 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
74 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
76 unsigned SReg = Reg - ARM::S0;
77 bool odd = SReg & 0x1;
78 unsigned Rx = 256 + (SReg >> 1);
80 OutStreamer.AddComment("DW_OP_regx for S register");
81 EmitInt8(dwarf::DW_OP_regx);
83 OutStreamer.AddComment(Twine(SReg));
87 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
88 EmitInt8(dwarf::DW_OP_bit_piece);
92 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
93 EmitInt8(dwarf::DW_OP_bit_piece);
97 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
98 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
99 // Q registers Q0-Q15 are described by composing two D registers together.
100 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
103 unsigned QReg = Reg - ARM::Q0;
104 unsigned D1 = 256 + 2 * QReg;
105 unsigned D2 = D1 + 1;
107 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
108 EmitInt8(dwarf::DW_OP_regx);
110 OutStreamer.AddComment("DW_OP_piece 8");
111 EmitInt8(dwarf::DW_OP_piece);
114 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
115 EmitInt8(dwarf::DW_OP_regx);
117 OutStreamer.AddComment("DW_OP_piece 8");
118 EmitInt8(dwarf::DW_OP_piece);
123 void ARMAsmPrinter::EmitFunctionBodyEnd() {
124 // Make sure to terminate any constant pools that were at the end
128 InConstantPool = false;
129 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
132 void ARMAsmPrinter::EmitFunctionEntryLabel() {
133 if (AFI->isThumbFunction()) {
134 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
135 OutStreamer.EmitThumbFunc(CurrentFnSym);
138 OutStreamer.EmitLabel(CurrentFnSym);
141 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
142 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
143 assert(Size && "C++ constructor pointer had zero size!");
145 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
146 assert(GV && "C++ constructor pointer was not a GlobalValue!");
148 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
149 (Subtarget->isTargetDarwin()
150 ? MCSymbolRefExpr::VK_None
151 : MCSymbolRefExpr::VK_ARM_TARGET1),
154 OutStreamer.EmitValue(E, Size);
157 /// runOnMachineFunction - This uses the EmitInstruction()
158 /// method to print assembly for each instruction.
160 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
161 AFI = MF.getInfo<ARMFunctionInfo>();
162 MCP = MF.getConstantPool();
164 return AsmPrinter::runOnMachineFunction(MF);
167 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
168 raw_ostream &O, const char *Modifier) {
169 const MachineOperand &MO = MI->getOperand(OpNum);
170 unsigned TF = MO.getTargetFlags();
172 switch (MO.getType()) {
173 default: llvm_unreachable("<unknown operand type>");
174 case MachineOperand::MO_Register: {
175 unsigned Reg = MO.getReg();
176 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
177 assert(!MO.getSubReg() && "Subregs should be eliminated!");
178 if(ARM::GPRPairRegClass.contains(Reg)) {
179 const MachineFunction &MF = *MI->getParent()->getParent();
180 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
181 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
183 O << ARMInstPrinter::getRegisterName(Reg);
186 case MachineOperand::MO_Immediate: {
187 int64_t Imm = MO.getImm();
189 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
190 (TF == ARMII::MO_LO16))
192 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
193 (TF == ARMII::MO_HI16))
198 case MachineOperand::MO_MachineBasicBlock:
199 O << *MO.getMBB()->getSymbol();
201 case MachineOperand::MO_GlobalAddress: {
202 const GlobalValue *GV = MO.getGlobal();
203 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
204 (TF & ARMII::MO_LO16))
206 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
207 (TF & ARMII::MO_HI16))
211 printOffset(MO.getOffset(), O);
212 if (TF == ARMII::MO_PLT)
216 case MachineOperand::MO_ConstantPoolIndex:
217 O << *GetCPISymbol(MO.getIndex());
222 //===--------------------------------------------------------------------===//
224 MCSymbol *ARMAsmPrinter::
225 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
226 SmallString<60> Name;
227 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
228 << getFunctionNumber() << '_' << uid << '_' << uid2;
229 return OutContext.GetOrCreateSymbol(Name.str());
233 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
234 SmallString<60> Name;
235 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
236 << getFunctionNumber();
237 return OutContext.GetOrCreateSymbol(Name.str());
240 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
241 unsigned AsmVariant, const char *ExtraCode,
243 // Does this asm operand have a single letter operand modifier?
244 if (ExtraCode && ExtraCode[0]) {
245 if (ExtraCode[1] != 0) return true; // Unknown modifier.
247 switch (ExtraCode[0]) {
249 // See if this is a generic print operand
250 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
251 case 'a': // Print as a memory address.
252 if (MI->getOperand(OpNum).isReg()) {
254 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
259 case 'c': // Don't print "#" before an immediate operand.
260 if (!MI->getOperand(OpNum).isImm())
262 O << MI->getOperand(OpNum).getImm();
264 case 'P': // Print a VFP double precision register.
265 case 'q': // Print a NEON quad precision register.
266 printOperand(MI, OpNum, O);
268 case 'y': // Print a VFP single precision register as indexed double.
269 if (MI->getOperand(OpNum).isReg()) {
270 unsigned Reg = MI->getOperand(OpNum).getReg();
271 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
272 // Find the 'd' register that has this 's' register as a sub-register,
273 // and determine the lane number.
274 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
275 if (!ARM::DPRRegClass.contains(*SR))
277 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
278 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
283 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
284 if (!MI->getOperand(OpNum).isImm())
286 O << ~(MI->getOperand(OpNum).getImm());
288 case 'L': // The low 16 bits of an immediate constant.
289 if (!MI->getOperand(OpNum).isImm())
291 O << (MI->getOperand(OpNum).getImm() & 0xffff);
293 case 'M': { // A register range suitable for LDM/STM.
294 if (!MI->getOperand(OpNum).isReg())
296 const MachineOperand &MO = MI->getOperand(OpNum);
297 unsigned RegBegin = MO.getReg();
298 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
299 // already got the operands in registers that are operands to the
300 // inline asm statement.
302 if (ARM::GPRPairRegClass.contains(RegBegin)) {
303 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
304 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
305 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
306 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
308 O << ARMInstPrinter::getRegisterName(RegBegin);
310 // FIXME: The register allocator not only may not have given us the
311 // registers in sequence, but may not be in ascending registers. This
312 // will require changes in the register allocator that'll need to be
313 // propagated down here if the operands change.
314 unsigned RegOps = OpNum + 1;
315 while (MI->getOperand(RegOps).isReg()) {
317 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
325 case 'R': // The most significant register of a pair.
326 case 'Q': { // The least significant register of a pair.
329 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
330 if (!FlagsOP.isImm())
332 unsigned Flags = FlagsOP.getImm();
334 // This operand may not be the one that actually provides the register. If
335 // it's tied to a previous one then we should refer instead to that one
336 // for registers and their classes.
338 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
339 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
340 unsigned OpFlags = MI->getOperand(OpNum).getImm();
341 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
343 Flags = MI->getOperand(OpNum).getImm();
345 // Later code expects OpNum to be pointing at the register rather than
350 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
352 InlineAsm::hasRegClassConstraint(Flags, RC);
353 if (RC == ARM::GPRPairRegClassID) {
356 const MachineOperand &MO = MI->getOperand(OpNum);
359 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
360 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
361 ARM::gsub_0 : ARM::gsub_1);
362 O << ARMInstPrinter::getRegisterName(Reg);
367 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
368 if (RegOp >= MI->getNumOperands())
370 const MachineOperand &MO = MI->getOperand(RegOp);
373 unsigned Reg = MO.getReg();
374 O << ARMInstPrinter::getRegisterName(Reg);
378 case 'e': // The low doubleword register of a NEON quad register.
379 case 'f': { // The high doubleword register of a NEON quad register.
380 if (!MI->getOperand(OpNum).isReg())
382 unsigned Reg = MI->getOperand(OpNum).getReg();
383 if (!ARM::QPRRegClass.contains(Reg))
385 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
386 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
387 ARM::dsub_0 : ARM::dsub_1);
388 O << ARMInstPrinter::getRegisterName(SubReg);
392 // This modifier is not yet supported.
393 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
395 case 'H': { // The highest-numbered register of a pair.
396 const MachineOperand &MO = MI->getOperand(OpNum);
399 const MachineFunction &MF = *MI->getParent()->getParent();
400 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
401 unsigned Reg = MO.getReg();
402 if(!ARM::GPRPairRegClass.contains(Reg))
404 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
405 O << ARMInstPrinter::getRegisterName(Reg);
411 printOperand(MI, OpNum, O);
415 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
416 unsigned OpNum, unsigned AsmVariant,
417 const char *ExtraCode,
419 // Does this asm operand have a single letter operand modifier?
420 if (ExtraCode && ExtraCode[0]) {
421 if (ExtraCode[1] != 0) return true; // Unknown modifier.
423 switch (ExtraCode[0]) {
424 case 'A': // A memory operand for a VLD1/VST1 instruction.
425 default: return true; // Unknown modifier.
426 case 'm': // The base register of a memory operand.
427 if (!MI->getOperand(OpNum).isReg())
429 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
434 const MachineOperand &MO = MI->getOperand(OpNum);
435 assert(MO.isReg() && "unexpected inline asm memory operand");
436 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
440 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
441 if (Subtarget->isTargetDarwin()) {
442 Reloc::Model RelocM = TM.getRelocationModel();
443 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
444 // Declare all the text sections up front (before the DWARF sections
445 // emitted by AsmPrinter::doInitialization) so the assembler will keep
446 // them together at the beginning of the object file. This helps
447 // avoid out-of-range branches that are due a fundamental limitation of
448 // the way symbol offsets are encoded with the current Darwin ARM
450 const TargetLoweringObjectFileMachO &TLOFMacho =
451 static_cast<const TargetLoweringObjectFileMachO &>(
452 getObjFileLowering());
454 // Collect the set of sections our functions will go into.
455 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
456 SmallPtrSet<const MCSection *, 8> > TextSections;
457 // Default text section comes first.
458 TextSections.insert(TLOFMacho.getTextSection());
459 // Now any user defined text sections from function attributes.
460 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
461 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
462 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
463 // Now the coalescable sections.
464 TextSections.insert(TLOFMacho.getTextCoalSection());
465 TextSections.insert(TLOFMacho.getConstTextCoalSection());
467 // Emit the sections in the .s file header to fix the order.
468 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
469 OutStreamer.SwitchSection(TextSections[i]);
471 if (RelocM == Reloc::DynamicNoPIC) {
472 const MCSection *sect =
473 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
474 MCSectionMachO::S_SYMBOL_STUBS,
475 12, SectionKind::getText());
476 OutStreamer.SwitchSection(sect);
478 const MCSection *sect =
479 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
480 MCSectionMachO::S_SYMBOL_STUBS,
481 16, SectionKind::getText());
482 OutStreamer.SwitchSection(sect);
484 const MCSection *StaticInitSect =
485 OutContext.getMachOSection("__TEXT", "__StaticInit",
486 MCSectionMachO::S_REGULAR |
487 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
488 SectionKind::getText());
489 OutStreamer.SwitchSection(StaticInitSect);
493 // Use unified assembler syntax.
494 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
496 // Emit ARM Build Attributes
497 if (Subtarget->isTargetELF())
502 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
503 if (Subtarget->isTargetDarwin()) {
504 // All darwin targets use mach-o.
505 const TargetLoweringObjectFileMachO &TLOFMacho =
506 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
507 MachineModuleInfoMachO &MMIMacho =
508 MMI->getObjFileInfo<MachineModuleInfoMachO>();
510 // Output non-lazy-pointers for external and common global variables.
511 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
513 if (!Stubs.empty()) {
514 // Switch with ".non_lazy_symbol_pointer" directive.
515 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
517 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
519 OutStreamer.EmitLabel(Stubs[i].first);
520 // .indirect_symbol _foo
521 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
522 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
525 // External to current translation unit.
526 OutStreamer.EmitIntValue(0, 4/*size*/);
528 // Internal to current translation unit.
530 // When we place the LSDA into the TEXT section, the type info
531 // pointers need to be indirect and pc-rel. We accomplish this by
532 // using NLPs; however, sometimes the types are local to the file.
533 // We need to fill in the value for the NLP in those cases.
534 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
540 OutStreamer.AddBlankLine();
543 Stubs = MMIMacho.GetHiddenGVStubList();
544 if (!Stubs.empty()) {
545 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
547 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
549 OutStreamer.EmitLabel(Stubs[i].first);
551 OutStreamer.EmitValue(MCSymbolRefExpr::
552 Create(Stubs[i].second.getPointer(),
558 OutStreamer.AddBlankLine();
561 // Funny Darwin hack: This flag tells the linker that no global symbols
562 // contain code that falls through to other global symbols (e.g. the obvious
563 // implementation of multiple entry points). If this doesn't occur, the
564 // linker can safely perform dead code stripping. Since LLVM never
565 // generates code that does this, it is always safe to set.
566 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
570 //===----------------------------------------------------------------------===//
571 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
573 // The following seem like one-off assembler flags, but they actually need
574 // to appear in the .ARM.attributes section in ELF.
575 // Instead of subclassing the MCELFStreamer, we do the work here.
577 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
578 const ARMSubtarget *Subtarget) {
580 return ARMBuildAttrs::v5TEJ;
582 if (Subtarget->hasV8Ops())
583 return ARMBuildAttrs::v8;
584 else if (Subtarget->hasV7Ops()) {
585 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
586 return ARMBuildAttrs::v7E_M;
587 return ARMBuildAttrs::v7;
588 } else if (Subtarget->hasV6T2Ops())
589 return ARMBuildAttrs::v6T2;
590 else if (Subtarget->hasV6MOps())
591 return ARMBuildAttrs::v6S_M;
592 else if (Subtarget->hasV6Ops())
593 return ARMBuildAttrs::v6;
594 else if (Subtarget->hasV5TEOps())
595 return ARMBuildAttrs::v5TE;
596 else if (Subtarget->hasV5TOps())
597 return ARMBuildAttrs::v5T;
598 else if (Subtarget->hasV4TOps())
599 return ARMBuildAttrs::v4T;
601 return ARMBuildAttrs::v4;
604 void ARMAsmPrinter::emitAttributes() {
605 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
606 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
608 ATS.switchVendor("aeabi");
610 std::string CPUString = Subtarget->getCPUString();
612 if (CPUString != "generic")
613 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
615 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
616 getArchForCPU(CPUString, Subtarget));
618 if (Subtarget->isAClass()) {
619 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
620 ARMBuildAttrs::ApplicationProfile);
621 } else if (Subtarget->isRClass()) {
622 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
623 ARMBuildAttrs::RealTimeProfile);
624 } else if (Subtarget->isMClass()){
625 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
626 ARMBuildAttrs::MicroControllerProfile);
629 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
630 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
631 if (Subtarget->isThumb1Only()) {
632 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
633 ARMBuildAttrs::Allowed);
634 } else if (Subtarget->hasThumb2()) {
635 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
636 ARMBuildAttrs::AllowThumb32);
639 if (Subtarget->hasNEON()) {
640 /* NEON is not exactly a VFP architecture, but GAS emit one of
641 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
642 if (Subtarget->hasFPARMv8()) {
643 if (Subtarget->hasCrypto())
644 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
646 ATS.emitFPU(ARM::NEON_FP_ARMV8);
648 else if (Subtarget->hasVFP4())
649 ATS.emitFPU(ARM::NEON_VFPV4);
651 ATS.emitFPU(ARM::NEON);
652 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
653 if (Subtarget->hasV8Ops())
654 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
655 ARMBuildAttrs::AllowNeonARMv8);
657 if (Subtarget->hasFPARMv8())
658 ATS.emitFPU(ARM::FP_ARMV8);
659 else if (Subtarget->hasVFP4())
660 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
661 else if (Subtarget->hasVFP3())
662 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
663 else if (Subtarget->hasVFP2())
664 ATS.emitFPU(ARM::VFPV2);
667 // Signal various FP modes.
668 if (!TM.Options.UnsafeFPMath) {
669 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
670 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
671 ARMBuildAttrs::Allowed);
674 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
675 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
676 ARMBuildAttrs::Allowed);
678 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
679 ARMBuildAttrs::AllowIEE754);
681 // FIXME: add more flags to ARMBuildAttrs.h
682 // 8-bytes alignment stuff.
683 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
684 ATS.emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
686 // ABI_HardFP_use attribute to indicate single precision FP.
687 if (Subtarget->isFPOnlySP())
688 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
689 ARMBuildAttrs::HardFPSinglePrecision);
691 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
692 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
693 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
695 // FIXME: Should we signal R9 usage?
697 if (Subtarget->hasFP16())
698 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
700 if (Subtarget->hasMPExtension())
701 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
703 if (Subtarget->hasDivide()) {
704 // Check if hardware divide is only available in thumb2 or ARM as well.
705 ATS.emitAttribute(ARMBuildAttrs::DIV_use,
706 Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
707 ARMBuildAttrs::AllowDIVIfExists);
710 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
711 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
712 ARMBuildAttrs::AllowTZVirtualization);
713 else if (Subtarget->hasTrustZone())
714 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
715 ARMBuildAttrs::AllowTZ);
716 else if (Subtarget->hasVirtualization())
717 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
718 ARMBuildAttrs::AllowVirtualization);
720 ATS.finishAttributeSection();
723 void ARMAsmPrinter::emitARMAttributeSection() {
725 // [ <section-length> "vendor-name"
726 // [ <file-tag> <size> <attribute>*
727 // | <section-tag> <size> <section-number>* 0 <attribute>*
728 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
732 if (OutStreamer.hasRawTextSupport())
735 const ARMElfTargetObjectFile &TLOFELF =
736 static_cast<const ARMElfTargetObjectFile &>
737 (getObjFileLowering());
739 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
742 OutStreamer.EmitIntValue(0x41, 1);
745 //===----------------------------------------------------------------------===//
747 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
748 unsigned LabelId, MCContext &Ctx) {
750 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
751 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
755 static MCSymbolRefExpr::VariantKind
756 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
758 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
759 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
760 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
761 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
762 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
763 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
765 llvm_unreachable("Invalid ARMCPModifier!");
768 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
769 unsigned char TargetFlags) {
770 bool isIndirect = Subtarget->isTargetDarwin() &&
771 (TargetFlags & ARMII::MO_NONLAZY) &&
772 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
774 return getSymbol(GV);
776 // FIXME: Remove this when Darwin transition to @GOT like syntax.
777 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
778 MachineModuleInfoMachO &MMIMachO =
779 MMI->getObjFileInfo<MachineModuleInfoMachO>();
780 MachineModuleInfoImpl::StubValueTy &StubSym =
781 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
782 MMIMachO.getGVStubEntry(MCSym);
783 if (StubSym.getPointer() == 0)
784 StubSym = MachineModuleInfoImpl::
785 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
790 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
791 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
793 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
796 if (ACPV->isLSDA()) {
797 SmallString<128> Str;
798 raw_svector_ostream OS(Str);
799 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
800 MCSym = OutContext.GetOrCreateSymbol(OS.str());
801 } else if (ACPV->isBlockAddress()) {
802 const BlockAddress *BA =
803 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
804 MCSym = GetBlockAddressSymbol(BA);
805 } else if (ACPV->isGlobalValue()) {
806 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
808 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
809 // flag the global as MO_NONLAZY.
810 unsigned char TF = Subtarget->isTargetDarwin() ? ARMII::MO_NONLAZY : 0;
811 MCSym = GetARMGVSymbol(GV, TF);
812 } else if (ACPV->isMachineBasicBlock()) {
813 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
814 MCSym = MBB->getSymbol();
816 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
817 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
818 MCSym = GetExternalSymbolSymbol(Sym);
821 // Create an MCSymbol for the reference.
823 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
826 if (ACPV->getPCAdjustment()) {
827 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
831 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
833 MCBinaryExpr::CreateAdd(PCRelExpr,
834 MCConstantExpr::Create(ACPV->getPCAdjustment(),
837 if (ACPV->mustAddCurrentAddress()) {
838 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
839 // label, so just emit a local label end reference that instead.
840 MCSymbol *DotSym = OutContext.CreateTempSymbol();
841 OutStreamer.EmitLabel(DotSym);
842 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
843 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
845 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
847 OutStreamer.EmitValue(Expr, Size);
850 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
851 unsigned Opcode = MI->getOpcode();
853 if (Opcode == ARM::BR_JTadd)
855 else if (Opcode == ARM::BR_JTm)
858 const MachineOperand &MO1 = MI->getOperand(OpNum);
859 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
860 unsigned JTI = MO1.getIndex();
862 // Emit a label for the jump table.
863 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
864 OutStreamer.EmitLabel(JTISymbol);
866 // Mark the jump table as data-in-code.
867 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
869 // Emit each entry of the table.
870 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
871 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
872 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
874 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
875 MachineBasicBlock *MBB = JTBBs[i];
876 // Construct an MCExpr for the entry. We want a value of the form:
877 // (BasicBlockAddr - TableBeginAddr)
879 // For example, a table with entries jumping to basic blocks BB0 and BB1
882 // .word (LBB0 - LJTI_0_0)
883 // .word (LBB1 - LJTI_0_0)
884 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
886 if (TM.getRelocationModel() == Reloc::PIC_)
887 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
890 // If we're generating a table of Thumb addresses in static relocation
891 // model, we need to add one to keep interworking correctly.
892 else if (AFI->isThumbFunction())
893 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
895 OutStreamer.EmitValue(Expr, 4);
897 // Mark the end of jump table data-in-code region.
898 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
901 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
902 unsigned Opcode = MI->getOpcode();
903 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
904 const MachineOperand &MO1 = MI->getOperand(OpNum);
905 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
906 unsigned JTI = MO1.getIndex();
908 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
909 OutStreamer.EmitLabel(JTISymbol);
911 // Emit each entry of the table.
912 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
913 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
914 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
915 unsigned OffsetWidth = 4;
916 if (MI->getOpcode() == ARM::t2TBB_JT) {
918 // Mark the jump table as data-in-code.
919 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
920 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
922 // Mark the jump table as data-in-code.
923 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
926 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
927 MachineBasicBlock *MBB = JTBBs[i];
928 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
930 // If this isn't a TBB or TBH, the entries are direct branch instructions.
931 if (OffsetWidth == 4) {
932 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
933 .addExpr(MBBSymbolExpr)
938 // Otherwise it's an offset from the dispatch instruction. Construct an
939 // MCExpr for the entry. We want a value of the form:
940 // (BasicBlockAddr - TableBeginAddr) / 2
942 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
945 // .byte (LBB0 - LJTI_0_0) / 2
946 // .byte (LBB1 - LJTI_0_0) / 2
948 MCBinaryExpr::CreateSub(MBBSymbolExpr,
949 MCSymbolRefExpr::Create(JTISymbol, OutContext),
951 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
953 OutStreamer.EmitValue(Expr, OffsetWidth);
955 // Mark the end of jump table data-in-code region. 32-bit offsets use
956 // actual branch instructions here, so we don't mark those as a data-region
958 if (OffsetWidth != 4)
959 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
962 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
963 assert(MI->getFlag(MachineInstr::FrameSetup) &&
964 "Only instruction which are involved into frame setup code are allowed");
966 MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
967 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
968 const MachineFunction &MF = *MI->getParent()->getParent();
969 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
970 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
972 unsigned FramePtr = RegInfo->getFrameRegister(MF);
973 unsigned Opc = MI->getOpcode();
974 unsigned SrcReg, DstReg;
976 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
977 // Two special cases:
978 // 1) tPUSH does not have src/dst regs.
979 // 2) for Thumb1 code we sometimes materialize the constant via constpool
980 // load. Yes, this is pretty fragile, but for now I don't see better
982 SrcReg = DstReg = ARM::SP;
984 SrcReg = MI->getOperand(1).getReg();
985 DstReg = MI->getOperand(0).getReg();
988 // Try to figure out the unwinding opcode out of src / dst regs.
989 if (MI->mayStore()) {
991 assert(DstReg == ARM::SP &&
992 "Only stack pointer as a destination reg is supported");
994 SmallVector<unsigned, 4> RegList;
995 // Skip src & dst reg, and pred ops.
996 unsigned StartOp = 2 + 2;
997 // Use all the operands.
998 unsigned NumOffset = 0;
1003 llvm_unreachable("Unsupported opcode for unwinding information");
1005 // Special case here: no src & dst reg, but two extra imp ops.
1006 StartOp = 2; NumOffset = 2;
1007 case ARM::STMDB_UPD:
1008 case ARM::t2STMDB_UPD:
1009 case ARM::VSTMDDB_UPD:
1010 assert(SrcReg == ARM::SP &&
1011 "Only stack pointer as a source reg is supported");
1012 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1014 const MachineOperand &MO = MI->getOperand(i);
1015 // Actually, there should never be any impdef stuff here. Skip it
1016 // temporary to workaround PR11902.
1017 if (MO.isImplicit())
1019 RegList.push_back(MO.getReg());
1022 case ARM::STR_PRE_IMM:
1023 case ARM::STR_PRE_REG:
1024 case ARM::t2STR_PRE:
1025 assert(MI->getOperand(2).getReg() == ARM::SP &&
1026 "Only stack pointer as a source reg is supported");
1027 RegList.push_back(SrcReg);
1030 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1032 // Changes of stack / frame pointer.
1033 if (SrcReg == ARM::SP) {
1038 llvm_unreachable("Unsupported opcode for unwinding information");
1044 Offset = -MI->getOperand(2).getImm();
1048 Offset = MI->getOperand(2).getImm();
1051 Offset = MI->getOperand(2).getImm()*4;
1055 Offset = -MI->getOperand(2).getImm()*4;
1057 case ARM::tLDRpci: {
1058 // Grab the constpool index and check, whether it corresponds to
1059 // original or cloned constpool entry.
1060 unsigned CPI = MI->getOperand(1).getIndex();
1061 const MachineConstantPool *MCP = MF.getConstantPool();
1062 if (CPI >= MCP->getConstants().size())
1063 CPI = AFI.getOriginalCPIdx(CPI);
1064 assert(CPI != -1U && "Invalid constpool index");
1066 // Derive the actual offset.
1067 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1068 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1069 // FIXME: Check for user, it should be "add" instruction!
1070 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1075 if (DstReg == FramePtr && FramePtr != ARM::SP)
1076 // Set-up of the frame pointer. Positive values correspond to "add"
1078 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1079 else if (DstReg == ARM::SP) {
1080 // Change of SP by an offset. Positive values correspond to "sub"
1082 ATS.emitPad(Offset);
1085 llvm_unreachable("Unsupported opcode for unwinding information");
1087 } else if (DstReg == ARM::SP) {
1088 // FIXME: .movsp goes here
1090 llvm_unreachable("Unsupported opcode for unwinding information");
1094 llvm_unreachable("Unsupported opcode for unwinding information");
1099 extern cl::opt<bool> EnableARMEHABI;
1101 // Simple pseudo-instructions have their lowering (with expansion to real
1102 // instructions) auto-generated.
1103 #include "ARMGenMCPseudoLowering.inc"
1105 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1106 // If we just ended a constant pool, mark it as such.
1107 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1108 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1109 InConstantPool = false;
1112 // Emit unwinding stuff for frame-related instructions
1113 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1114 EmitUnwindingInstruction(MI);
1116 // Do any auto-generated pseudo lowerings.
1117 if (emitPseudoExpansionLowering(OutStreamer, MI))
1120 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1121 "Pseudo flag setting opcode should be expanded early");
1123 // Check for manual lowerings.
1124 unsigned Opc = MI->getOpcode();
1126 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1127 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1129 case ARM::tLEApcrel:
1130 case ARM::t2LEApcrel: {
1131 // FIXME: Need to also handle globals and externals
1132 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1133 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1134 ARM::t2LEApcrel ? ARM::t2ADR
1135 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1137 .addReg(MI->getOperand(0).getReg())
1138 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1139 // Add predicate operands.
1140 .addImm(MI->getOperand(2).getImm())
1141 .addReg(MI->getOperand(3).getReg()));
1144 case ARM::LEApcrelJT:
1145 case ARM::tLEApcrelJT:
1146 case ARM::t2LEApcrelJT: {
1147 MCSymbol *JTIPICSymbol =
1148 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1149 MI->getOperand(2).getImm());
1150 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1151 ARM::t2LEApcrelJT ? ARM::t2ADR
1152 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1154 .addReg(MI->getOperand(0).getReg())
1155 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1156 // Add predicate operands.
1157 .addImm(MI->getOperand(3).getImm())
1158 .addReg(MI->getOperand(4).getReg()));
1161 // Darwin call instructions are just normal call instructions with different
1162 // clobber semantics (they clobber R9).
1163 case ARM::BX_CALL: {
1164 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1167 // Add predicate operands.
1170 // Add 's' bit operand (always reg0 for this)
1173 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1174 .addReg(MI->getOperand(0).getReg()));
1177 case ARM::tBX_CALL: {
1178 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1181 // Add predicate operands.
1185 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1186 .addReg(MI->getOperand(0).getReg())
1187 // Add predicate operands.
1192 case ARM::BMOVPCRX_CALL: {
1193 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1196 // Add predicate operands.
1199 // Add 's' bit operand (always reg0 for this)
1202 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1204 .addReg(MI->getOperand(0).getReg())
1205 // Add predicate operands.
1208 // Add 's' bit operand (always reg0 for this)
1212 case ARM::BMOVPCB_CALL: {
1213 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1216 // Add predicate operands.
1219 // Add 's' bit operand (always reg0 for this)
1222 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1223 MCSymbol *GVSym = getSymbol(GV);
1224 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1225 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1227 // Add predicate operands.
1232 case ARM::MOVi16_ga_pcrel:
1233 case ARM::t2MOVi16_ga_pcrel: {
1235 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1236 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1238 unsigned TF = MI->getOperand(1).getTargetFlags();
1239 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1240 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1241 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1243 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1244 getFunctionNumber(),
1245 MI->getOperand(2).getImm(), OutContext);
1246 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1247 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1248 const MCExpr *PCRelExpr =
1249 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1250 MCBinaryExpr::CreateAdd(LabelSymExpr,
1251 MCConstantExpr::Create(PCAdj, OutContext),
1252 OutContext), OutContext), OutContext);
1253 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1255 // Add predicate operands.
1256 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1257 TmpInst.addOperand(MCOperand::CreateReg(0));
1258 // Add 's' bit operand (always reg0 for this)
1259 TmpInst.addOperand(MCOperand::CreateReg(0));
1260 OutStreamer.EmitInstruction(TmpInst);
1263 case ARM::MOVTi16_ga_pcrel:
1264 case ARM::t2MOVTi16_ga_pcrel: {
1266 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1267 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1268 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1269 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1271 unsigned TF = MI->getOperand(2).getTargetFlags();
1272 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1273 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1274 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1276 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1277 getFunctionNumber(),
1278 MI->getOperand(3).getImm(), OutContext);
1279 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1280 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1281 const MCExpr *PCRelExpr =
1282 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1283 MCBinaryExpr::CreateAdd(LabelSymExpr,
1284 MCConstantExpr::Create(PCAdj, OutContext),
1285 OutContext), OutContext), OutContext);
1286 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1287 // Add predicate operands.
1288 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1289 TmpInst.addOperand(MCOperand::CreateReg(0));
1290 // Add 's' bit operand (always reg0 for this)
1291 TmpInst.addOperand(MCOperand::CreateReg(0));
1292 OutStreamer.EmitInstruction(TmpInst);
1295 case ARM::tPICADD: {
1296 // This is a pseudo op for a label + instruction sequence, which looks like:
1299 // This adds the address of LPC0 to r0.
1302 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1303 getFunctionNumber(), MI->getOperand(2).getImm(),
1306 // Form and emit the add.
1307 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1308 .addReg(MI->getOperand(0).getReg())
1309 .addReg(MI->getOperand(0).getReg())
1311 // Add predicate operands.
1317 // This is a pseudo op for a label + instruction sequence, which looks like:
1320 // This adds the address of LPC0 to r0.
1323 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1324 getFunctionNumber(), MI->getOperand(2).getImm(),
1327 // Form and emit the add.
1328 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1329 .addReg(MI->getOperand(0).getReg())
1331 .addReg(MI->getOperand(1).getReg())
1332 // Add predicate operands.
1333 .addImm(MI->getOperand(3).getImm())
1334 .addReg(MI->getOperand(4).getReg())
1335 // Add 's' bit operand (always reg0 for this)
1346 case ARM::PICLDRSH: {
1347 // This is a pseudo op for a label + instruction sequence, which looks like:
1350 // The LCP0 label is referenced by a constant pool entry in order to get
1351 // a PC-relative address at the ldr instruction.
1354 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1355 getFunctionNumber(), MI->getOperand(2).getImm(),
1358 // Form and emit the load
1360 switch (MI->getOpcode()) {
1362 llvm_unreachable("Unexpected opcode!");
1363 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1364 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1365 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1366 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1367 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1368 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1369 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1370 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1372 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1373 .addReg(MI->getOperand(0).getReg())
1375 .addReg(MI->getOperand(1).getReg())
1377 // Add predicate operands.
1378 .addImm(MI->getOperand(3).getImm())
1379 .addReg(MI->getOperand(4).getReg()));
1383 case ARM::CONSTPOOL_ENTRY: {
1384 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1385 /// in the function. The first operand is the ID# for this instruction, the
1386 /// second is the index into the MachineConstantPool that this is, the third
1387 /// is the size in bytes of this constant pool entry.
1388 /// The required alignment is specified on the basic block holding this MI.
1389 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1390 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1392 // If this is the first entry of the pool, mark it.
1393 if (!InConstantPool) {
1394 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1395 InConstantPool = true;
1398 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1400 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1401 if (MCPE.isMachineConstantPoolEntry())
1402 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1404 EmitGlobalConstant(MCPE.Val.ConstVal);
1407 case ARM::t2BR_JT: {
1408 // Lower and emit the instruction itself, then the jump table following it.
1409 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1411 .addReg(MI->getOperand(0).getReg())
1412 // Add predicate operands.
1416 // Output the data for the jump table itself
1420 case ARM::t2TBB_JT: {
1421 // Lower and emit the instruction itself, then the jump table following it.
1422 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1424 .addReg(MI->getOperand(0).getReg())
1425 // Add predicate operands.
1429 // Output the data for the jump table itself
1431 // Make sure the next instruction is 2-byte aligned.
1435 case ARM::t2TBH_JT: {
1436 // Lower and emit the instruction itself, then the jump table following it.
1437 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1439 .addReg(MI->getOperand(0).getReg())
1440 // Add predicate operands.
1444 // Output the data for the jump table itself
1450 // Lower and emit the instruction itself, then the jump table following it.
1453 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1454 ARM::MOVr : ARM::tMOVr;
1455 TmpInst.setOpcode(Opc);
1456 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1457 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1458 // Add predicate operands.
1459 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1460 TmpInst.addOperand(MCOperand::CreateReg(0));
1461 // Add 's' bit operand (always reg0 for this)
1462 if (Opc == ARM::MOVr)
1463 TmpInst.addOperand(MCOperand::CreateReg(0));
1464 OutStreamer.EmitInstruction(TmpInst);
1466 // Make sure the Thumb jump table is 4-byte aligned.
1467 if (Opc == ARM::tMOVr)
1470 // Output the data for the jump table itself
1475 // Lower and emit the instruction itself, then the jump table following it.
1478 if (MI->getOperand(1).getReg() == 0) {
1480 TmpInst.setOpcode(ARM::LDRi12);
1481 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1482 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1483 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1485 TmpInst.setOpcode(ARM::LDRrs);
1486 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1487 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1488 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1489 TmpInst.addOperand(MCOperand::CreateImm(0));
1491 // Add predicate operands.
1492 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1493 TmpInst.addOperand(MCOperand::CreateReg(0));
1494 OutStreamer.EmitInstruction(TmpInst);
1496 // Output the data for the jump table itself
1500 case ARM::BR_JTadd: {
1501 // Lower and emit the instruction itself, then the jump table following it.
1502 // add pc, target, idx
1503 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1505 .addReg(MI->getOperand(0).getReg())
1506 .addReg(MI->getOperand(1).getReg())
1507 // Add predicate operands.
1510 // Add 's' bit operand (always reg0 for this)
1513 // Output the data for the jump table itself
1518 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1519 // FIXME: Remove this special case when they do.
1520 if (!Subtarget->isTargetDarwin()) {
1521 //.long 0xe7ffdefe @ trap
1522 uint32_t Val = 0xe7ffdefeUL;
1523 OutStreamer.AddComment("trap");
1524 OutStreamer.EmitIntValue(Val, 4);
1529 case ARM::TRAPNaCl: {
1530 //.long 0xe7fedef0 @ trap
1531 uint32_t Val = 0xe7fedef0UL;
1532 OutStreamer.AddComment("trap");
1533 OutStreamer.EmitIntValue(Val, 4);
1537 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1538 // FIXME: Remove this special case when they do.
1539 if (!Subtarget->isTargetDarwin()) {
1540 //.short 57086 @ trap
1541 uint16_t Val = 0xdefe;
1542 OutStreamer.AddComment("trap");
1543 OutStreamer.EmitIntValue(Val, 2);
1548 case ARM::t2Int_eh_sjlj_setjmp:
1549 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1550 case ARM::tInt_eh_sjlj_setjmp: {
1551 // Two incoming args: GPR:$src, GPR:$val
1554 // str $val, [$src, #4]
1559 unsigned SrcReg = MI->getOperand(0).getReg();
1560 unsigned ValReg = MI->getOperand(1).getReg();
1561 MCSymbol *Label = GetARMSJLJEHLabel();
1562 OutStreamer.AddComment("eh_setjmp begin");
1563 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1570 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1580 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1583 // The offset immediate is #4. The operand value is scaled by 4 for the
1584 // tSTR instruction.
1590 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1598 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1599 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1600 .addExpr(SymbolExpr)
1604 OutStreamer.AddComment("eh_setjmp end");
1605 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1613 OutStreamer.EmitLabel(Label);
1617 case ARM::Int_eh_sjlj_setjmp_nofp:
1618 case ARM::Int_eh_sjlj_setjmp: {
1619 // Two incoming args: GPR:$src, GPR:$val
1621 // str $val, [$src, #+4]
1625 unsigned SrcReg = MI->getOperand(0).getReg();
1626 unsigned ValReg = MI->getOperand(1).getReg();
1628 OutStreamer.AddComment("eh_setjmp begin");
1629 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1636 // 's' bit operand (always reg0 for this).
1639 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1647 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1653 // 's' bit operand (always reg0 for this).
1656 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1663 // 's' bit operand (always reg0 for this).
1666 OutStreamer.AddComment("eh_setjmp end");
1667 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1673 // 's' bit operand (always reg0 for this).
1677 case ARM::Int_eh_sjlj_longjmp: {
1678 // ldr sp, [$src, #8]
1679 // ldr $scratch, [$src, #4]
1682 unsigned SrcReg = MI->getOperand(0).getReg();
1683 unsigned ScratchReg = MI->getOperand(1).getReg();
1684 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1692 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1700 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1708 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1715 case ARM::tInt_eh_sjlj_longjmp: {
1716 // ldr $scratch, [$src, #8]
1718 // ldr $scratch, [$src, #4]
1721 unsigned SrcReg = MI->getOperand(0).getReg();
1722 unsigned ScratchReg = MI->getOperand(1).getReg();
1723 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1726 // The offset immediate is #8. The operand value is scaled by 4 for the
1727 // tLDR instruction.
1733 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1740 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1748 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1756 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1766 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1768 OutStreamer.EmitInstruction(TmpInst);
1771 //===----------------------------------------------------------------------===//
1772 // Target Registry Stuff
1773 //===----------------------------------------------------------------------===//
1775 // Force static initialization.
1776 extern "C" void LLVMInitializeARMAsmPrinter() {
1777 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1778 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);