1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/DebugInfo.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ELF.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/TargetRegistry.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/Mangler.h"
54 #include "llvm/Target/TargetMachine.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
73 class AsmAttributeEmitter : public AttributeEmitter {
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
113 StringRef StringValue;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
129 Size += sizeof(int8_t); // Is this really necessary?
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
172 ContentsSize += getULEBSize(Attribute);
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag);
199 default: llvm_unreachable("Invalid attribute type");
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(item.StringValue.upper());
205 Streamer.EmitIntValue(0, 1); // '\0'
214 } // end of anonymous namespace
216 MachineLocation ARMAsmPrinter::
217 getDebugValueLocation(const MachineInstr *MI) const {
218 MachineLocation Location;
219 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
220 // Frame address. Currently handles register +- offset only.
221 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
222 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
224 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
229 /// EmitDwarfRegOp - Emit dwarf register operation.
230 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
231 const TargetRegisterInfo *RI = TM.getRegisterInfo();
232 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
233 AsmPrinter::EmitDwarfRegOp(MLoc);
235 unsigned Reg = MLoc.getReg();
236 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
237 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
238 // S registers are described as bit-pieces of a register
239 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
240 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
242 unsigned SReg = Reg - ARM::S0;
243 bool odd = SReg & 0x1;
244 unsigned Rx = 256 + (SReg >> 1);
246 OutStreamer.AddComment("DW_OP_regx for S register");
247 EmitInt8(dwarf::DW_OP_regx);
249 OutStreamer.AddComment(Twine(SReg));
253 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
254 EmitInt8(dwarf::DW_OP_bit_piece);
258 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
259 EmitInt8(dwarf::DW_OP_bit_piece);
263 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
264 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
265 // Q registers Q0-Q15 are described by composing two D registers together.
266 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
269 unsigned QReg = Reg - ARM::Q0;
270 unsigned D1 = 256 + 2 * QReg;
271 unsigned D2 = D1 + 1;
273 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
274 EmitInt8(dwarf::DW_OP_regx);
276 OutStreamer.AddComment("DW_OP_piece 8");
277 EmitInt8(dwarf::DW_OP_piece);
280 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
281 EmitInt8(dwarf::DW_OP_regx);
283 OutStreamer.AddComment("DW_OP_piece 8");
284 EmitInt8(dwarf::DW_OP_piece);
290 void ARMAsmPrinter::EmitFunctionBodyEnd() {
291 // Make sure to terminate any constant pools that were at the end
295 InConstantPool = false;
296 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
299 void ARMAsmPrinter::EmitFunctionEntryLabel() {
300 if (AFI->isThumbFunction()) {
301 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
302 OutStreamer.EmitThumbFunc(CurrentFnSym);
305 OutStreamer.EmitLabel(CurrentFnSym);
308 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
309 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
310 assert(Size && "C++ constructor pointer had zero size!");
312 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
313 assert(GV && "C++ constructor pointer was not a GlobalValue!");
315 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
316 (Subtarget->isTargetDarwin()
317 ? MCSymbolRefExpr::VK_None
318 : MCSymbolRefExpr::VK_ARM_TARGET1),
321 OutStreamer.EmitValue(E, Size);
324 /// runOnMachineFunction - This uses the EmitInstruction()
325 /// method to print assembly for each instruction.
327 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
328 AFI = MF.getInfo<ARMFunctionInfo>();
329 MCP = MF.getConstantPool();
331 return AsmPrinter::runOnMachineFunction(MF);
334 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
335 raw_ostream &O, const char *Modifier) {
336 const MachineOperand &MO = MI->getOperand(OpNum);
337 unsigned TF = MO.getTargetFlags();
339 switch (MO.getType()) {
340 default: llvm_unreachable("<unknown operand type>");
341 case MachineOperand::MO_Register: {
342 unsigned Reg = MO.getReg();
343 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
344 assert(!MO.getSubReg() && "Subregs should be eliminated!");
345 if(ARM::GPRPairRegClass.contains(Reg)) {
346 const MachineFunction &MF = *MI->getParent()->getParent();
347 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
348 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
350 O << ARMInstPrinter::getRegisterName(Reg);
353 case MachineOperand::MO_Immediate: {
354 int64_t Imm = MO.getImm();
356 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
357 (TF == ARMII::MO_LO16))
359 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
360 (TF == ARMII::MO_HI16))
365 case MachineOperand::MO_MachineBasicBlock:
366 O << *MO.getMBB()->getSymbol();
368 case MachineOperand::MO_GlobalAddress: {
369 const GlobalValue *GV = MO.getGlobal();
370 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
371 (TF & ARMII::MO_LO16))
373 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
374 (TF & ARMII::MO_HI16))
376 O << *Mang->getSymbol(GV);
378 printOffset(MO.getOffset(), O);
379 if (TF == ARMII::MO_PLT)
383 case MachineOperand::MO_ExternalSymbol: {
384 O << *GetExternalSymbolSymbol(MO.getSymbolName());
385 if (TF == ARMII::MO_PLT)
389 case MachineOperand::MO_ConstantPoolIndex:
390 O << *GetCPISymbol(MO.getIndex());
392 case MachineOperand::MO_JumpTableIndex:
393 O << *GetJTISymbol(MO.getIndex());
398 //===--------------------------------------------------------------------===//
400 MCSymbol *ARMAsmPrinter::
401 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
402 SmallString<60> Name;
403 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
404 << getFunctionNumber() << '_' << uid << '_' << uid2;
405 return OutContext.GetOrCreateSymbol(Name.str());
409 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
410 SmallString<60> Name;
411 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
412 << getFunctionNumber();
413 return OutContext.GetOrCreateSymbol(Name.str());
416 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
417 unsigned AsmVariant, const char *ExtraCode,
419 // Does this asm operand have a single letter operand modifier?
420 if (ExtraCode && ExtraCode[0]) {
421 if (ExtraCode[1] != 0) return true; // Unknown modifier.
423 switch (ExtraCode[0]) {
425 // See if this is a generic print operand
426 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
427 case 'a': // Print as a memory address.
428 if (MI->getOperand(OpNum).isReg()) {
430 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
435 case 'c': // Don't print "#" before an immediate operand.
436 if (!MI->getOperand(OpNum).isImm())
438 O << MI->getOperand(OpNum).getImm();
440 case 'P': // Print a VFP double precision register.
441 case 'q': // Print a NEON quad precision register.
442 printOperand(MI, OpNum, O);
444 case 'y': // Print a VFP single precision register as indexed double.
445 if (MI->getOperand(OpNum).isReg()) {
446 unsigned Reg = MI->getOperand(OpNum).getReg();
447 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
448 // Find the 'd' register that has this 's' register as a sub-register,
449 // and determine the lane number.
450 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
451 if (!ARM::DPRRegClass.contains(*SR))
453 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
454 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
459 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
460 if (!MI->getOperand(OpNum).isImm())
462 O << ~(MI->getOperand(OpNum).getImm());
464 case 'L': // The low 16 bits of an immediate constant.
465 if (!MI->getOperand(OpNum).isImm())
467 O << (MI->getOperand(OpNum).getImm() & 0xffff);
469 case 'M': { // A register range suitable for LDM/STM.
470 if (!MI->getOperand(OpNum).isReg())
472 const MachineOperand &MO = MI->getOperand(OpNum);
473 unsigned RegBegin = MO.getReg();
474 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
475 // already got the operands in registers that are operands to the
476 // inline asm statement.
478 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
480 // FIXME: The register allocator not only may not have given us the
481 // registers in sequence, but may not be in ascending registers. This
482 // will require changes in the register allocator that'll need to be
483 // propagated down here if the operands change.
484 unsigned RegOps = OpNum + 1;
485 while (MI->getOperand(RegOps).isReg()) {
487 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
495 case 'R': // The most significant register of a pair.
496 case 'Q': { // The least significant register of a pair.
499 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
500 if (!FlagsOP.isImm())
502 unsigned Flags = FlagsOP.getImm();
503 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
506 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
507 if (RegOp >= MI->getNumOperands())
509 const MachineOperand &MO = MI->getOperand(RegOp);
512 unsigned Reg = MO.getReg();
513 O << ARMInstPrinter::getRegisterName(Reg);
517 case 'e': // The low doubleword register of a NEON quad register.
518 case 'f': { // The high doubleword register of a NEON quad register.
519 if (!MI->getOperand(OpNum).isReg())
521 unsigned Reg = MI->getOperand(OpNum).getReg();
522 if (!ARM::QPRRegClass.contains(Reg))
524 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
525 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
526 ARM::dsub_0 : ARM::dsub_1);
527 O << ARMInstPrinter::getRegisterName(SubReg);
531 // This modifier is not yet supported.
532 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
534 case 'H': { // The highest-numbered register of a pair.
535 const MachineOperand &MO = MI->getOperand(OpNum);
538 const MachineFunction &MF = *MI->getParent()->getParent();
539 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
540 unsigned Reg = MO.getReg();
541 if(!ARM::GPRPairRegClass.contains(Reg))
543 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
544 O << ARMInstPrinter::getRegisterName(Reg);
550 printOperand(MI, OpNum, O);
554 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
555 unsigned OpNum, unsigned AsmVariant,
556 const char *ExtraCode,
558 // Does this asm operand have a single letter operand modifier?
559 if (ExtraCode && ExtraCode[0]) {
560 if (ExtraCode[1] != 0) return true; // Unknown modifier.
562 switch (ExtraCode[0]) {
563 case 'A': // A memory operand for a VLD1/VST1 instruction.
564 default: return true; // Unknown modifier.
565 case 'm': // The base register of a memory operand.
566 if (!MI->getOperand(OpNum).isReg())
568 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
573 const MachineOperand &MO = MI->getOperand(OpNum);
574 assert(MO.isReg() && "unexpected inline asm memory operand");
575 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
579 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
580 if (Subtarget->isTargetDarwin()) {
581 Reloc::Model RelocM = TM.getRelocationModel();
582 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
583 // Declare all the text sections up front (before the DWARF sections
584 // emitted by AsmPrinter::doInitialization) so the assembler will keep
585 // them together at the beginning of the object file. This helps
586 // avoid out-of-range branches that are due a fundamental limitation of
587 // the way symbol offsets are encoded with the current Darwin ARM
589 const TargetLoweringObjectFileMachO &TLOFMacho =
590 static_cast<const TargetLoweringObjectFileMachO &>(
591 getObjFileLowering());
593 // Collect the set of sections our functions will go into.
594 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
595 SmallPtrSet<const MCSection *, 8> > TextSections;
596 // Default text section comes first.
597 TextSections.insert(TLOFMacho.getTextSection());
598 // Now any user defined text sections from function attributes.
599 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
600 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
601 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
602 // Now the coalescable sections.
603 TextSections.insert(TLOFMacho.getTextCoalSection());
604 TextSections.insert(TLOFMacho.getConstTextCoalSection());
606 // Emit the sections in the .s file header to fix the order.
607 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
608 OutStreamer.SwitchSection(TextSections[i]);
610 if (RelocM == Reloc::DynamicNoPIC) {
611 const MCSection *sect =
612 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
613 MCSectionMachO::S_SYMBOL_STUBS,
614 12, SectionKind::getText());
615 OutStreamer.SwitchSection(sect);
617 const MCSection *sect =
618 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
619 MCSectionMachO::S_SYMBOL_STUBS,
620 16, SectionKind::getText());
621 OutStreamer.SwitchSection(sect);
623 const MCSection *StaticInitSect =
624 OutContext.getMachOSection("__TEXT", "__StaticInit",
625 MCSectionMachO::S_REGULAR |
626 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
627 SectionKind::getText());
628 OutStreamer.SwitchSection(StaticInitSect);
632 // Use unified assembler syntax.
633 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
635 // Emit ARM Build Attributes
636 if (Subtarget->isTargetELF())
641 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
642 if (Subtarget->isTargetDarwin()) {
643 // All darwin targets use mach-o.
644 const TargetLoweringObjectFileMachO &TLOFMacho =
645 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
646 MachineModuleInfoMachO &MMIMacho =
647 MMI->getObjFileInfo<MachineModuleInfoMachO>();
649 // Output non-lazy-pointers for external and common global variables.
650 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
652 if (!Stubs.empty()) {
653 // Switch with ".non_lazy_symbol_pointer" directive.
654 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
656 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
658 OutStreamer.EmitLabel(Stubs[i].first);
659 // .indirect_symbol _foo
660 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
661 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
664 // External to current translation unit.
665 OutStreamer.EmitIntValue(0, 4/*size*/);
667 // Internal to current translation unit.
669 // When we place the LSDA into the TEXT section, the type info
670 // pointers need to be indirect and pc-rel. We accomplish this by
671 // using NLPs; however, sometimes the types are local to the file.
672 // We need to fill in the value for the NLP in those cases.
673 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
679 OutStreamer.AddBlankLine();
682 Stubs = MMIMacho.GetHiddenGVStubList();
683 if (!Stubs.empty()) {
684 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
686 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
688 OutStreamer.EmitLabel(Stubs[i].first);
690 OutStreamer.EmitValue(MCSymbolRefExpr::
691 Create(Stubs[i].second.getPointer(),
697 OutStreamer.AddBlankLine();
700 // Funny Darwin hack: This flag tells the linker that no global symbols
701 // contain code that falls through to other global symbols (e.g. the obvious
702 // implementation of multiple entry points). If this doesn't occur, the
703 // linker can safely perform dead code stripping. Since LLVM never
704 // generates code that does this, it is always safe to set.
705 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
707 // FIXME: This should eventually end up somewhere else where more
708 // intelligent flag decisions can be made. For now we are just maintaining
709 // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
710 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&OutStreamer))
711 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
714 //===----------------------------------------------------------------------===//
715 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
717 // The following seem like one-off assembler flags, but they actually need
718 // to appear in the .ARM.attributes section in ELF.
719 // Instead of subclassing the MCELFStreamer, we do the work here.
721 void ARMAsmPrinter::emitAttributes() {
723 emitARMAttributeSection();
725 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
726 bool emitFPU = false;
727 AttributeEmitter *AttrEmitter;
728 if (OutStreamer.hasRawTextSupport()) {
729 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
732 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
733 AttrEmitter = new ObjectAttributeEmitter(O);
736 AttrEmitter->MaybeSwitchVendor("aeabi");
738 std::string CPUString = Subtarget->getCPUString();
740 if (CPUString == "cortex-a8" ||
741 Subtarget->isCortexA8()) {
742 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
743 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
744 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
745 ARMBuildAttrs::ApplicationProfile);
746 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
747 ARMBuildAttrs::Allowed);
748 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
749 ARMBuildAttrs::AllowThumb32);
750 // Fixme: figure out when this is emitted.
751 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
752 // ARMBuildAttrs::AllowWMMXv1);
755 /// ADD additional Else-cases here!
756 } else if (CPUString == "xscale") {
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
758 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
759 ARMBuildAttrs::Allowed);
760 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
761 ARMBuildAttrs::Allowed);
762 } else if (CPUString == "generic") {
763 // For a generic CPU, we assume a standard v7a architecture in Subtarget.
764 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
765 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
766 ARMBuildAttrs::ApplicationProfile);
767 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
768 ARMBuildAttrs::Allowed);
769 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
770 ARMBuildAttrs::AllowThumb32);
771 } else if (Subtarget->hasV7Ops()) {
772 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
774 ARMBuildAttrs::AllowThumb32);
775 } else if (Subtarget->hasV6T2Ops())
776 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2);
777 else if (Subtarget->hasV6Ops())
778 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6);
779 else if (Subtarget->hasV5TEOps())
780 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE);
781 else if (Subtarget->hasV5TOps())
782 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T);
783 else if (Subtarget->hasV4TOps())
784 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
786 if (Subtarget->hasNEON() && emitFPU) {
787 /* NEON is not exactly a VFP architecture, but GAS emit one of
788 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
789 if (Subtarget->hasVFP4())
790 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
793 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
794 /* If emitted for NEON, omit from VFP below, since you can have both
795 * NEON and VFP in build attributes but only one .fpu */
800 if (Subtarget->hasVFP4()) {
801 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
802 ARMBuildAttrs::AllowFPv4A);
804 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
807 } else if (Subtarget->hasVFP3()) {
808 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
809 ARMBuildAttrs::AllowFPv3A);
811 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
814 } else if (Subtarget->hasVFP2()) {
815 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
816 ARMBuildAttrs::AllowFPv2);
818 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
821 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
822 * since NEON can have 1 (allowed) or 2 (MAC operations) */
823 if (Subtarget->hasNEON()) {
824 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
825 ARMBuildAttrs::Allowed);
828 // Signal various FP modes.
829 if (!TM.Options.UnsafeFPMath) {
830 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
831 ARMBuildAttrs::Allowed);
832 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
833 ARMBuildAttrs::Allowed);
836 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
837 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
838 ARMBuildAttrs::Allowed);
840 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
841 ARMBuildAttrs::AllowIEE754);
843 // FIXME: add more flags to ARMBuildAttrs.h
844 // 8-bytes alignment stuff.
845 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
846 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
848 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
849 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
850 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
851 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
853 // FIXME: Should we signal R9 usage?
855 if (Subtarget->hasDivide())
856 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
858 AttrEmitter->Finish();
862 void ARMAsmPrinter::emitARMAttributeSection() {
864 // [ <section-length> "vendor-name"
865 // [ <file-tag> <size> <attribute>*
866 // | <section-tag> <size> <section-number>* 0 <attribute>*
867 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
871 if (OutStreamer.hasRawTextSupport())
874 const ARMElfTargetObjectFile &TLOFELF =
875 static_cast<const ARMElfTargetObjectFile &>
876 (getObjFileLowering());
878 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
881 OutStreamer.EmitIntValue(0x41, 1);
884 //===----------------------------------------------------------------------===//
886 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
887 unsigned LabelId, MCContext &Ctx) {
889 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
890 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
894 static MCSymbolRefExpr::VariantKind
895 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
897 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
898 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
899 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
900 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
901 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
902 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
904 llvm_unreachable("Invalid ARMCPModifier!");
907 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
908 bool isIndirect = Subtarget->isTargetDarwin() &&
909 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
911 return Mang->getSymbol(GV);
913 // FIXME: Remove this when Darwin transition to @GOT like syntax.
914 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
915 MachineModuleInfoMachO &MMIMachO =
916 MMI->getObjFileInfo<MachineModuleInfoMachO>();
917 MachineModuleInfoImpl::StubValueTy &StubSym =
918 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
919 MMIMachO.getGVStubEntry(MCSym);
920 if (StubSym.getPointer() == 0)
921 StubSym = MachineModuleInfoImpl::
922 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
927 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
928 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
930 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
933 if (ACPV->isLSDA()) {
934 SmallString<128> Str;
935 raw_svector_ostream OS(Str);
936 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
937 MCSym = OutContext.GetOrCreateSymbol(OS.str());
938 } else if (ACPV->isBlockAddress()) {
939 const BlockAddress *BA =
940 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
941 MCSym = GetBlockAddressSymbol(BA);
942 } else if (ACPV->isGlobalValue()) {
943 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
944 MCSym = GetARMGVSymbol(GV);
945 } else if (ACPV->isMachineBasicBlock()) {
946 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
947 MCSym = MBB->getSymbol();
949 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
950 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
951 MCSym = GetExternalSymbolSymbol(Sym);
954 // Create an MCSymbol for the reference.
956 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
959 if (ACPV->getPCAdjustment()) {
960 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
964 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
966 MCBinaryExpr::CreateAdd(PCRelExpr,
967 MCConstantExpr::Create(ACPV->getPCAdjustment(),
970 if (ACPV->mustAddCurrentAddress()) {
971 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
972 // label, so just emit a local label end reference that instead.
973 MCSymbol *DotSym = OutContext.CreateTempSymbol();
974 OutStreamer.EmitLabel(DotSym);
975 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
976 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
978 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
980 OutStreamer.EmitValue(Expr, Size);
983 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
984 unsigned Opcode = MI->getOpcode();
986 if (Opcode == ARM::BR_JTadd)
988 else if (Opcode == ARM::BR_JTm)
991 const MachineOperand &MO1 = MI->getOperand(OpNum);
992 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
993 unsigned JTI = MO1.getIndex();
995 // Emit a label for the jump table.
996 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
997 OutStreamer.EmitLabel(JTISymbol);
999 // Mark the jump table as data-in-code.
1000 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
1002 // Emit each entry of the table.
1003 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1004 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1005 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1007 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1008 MachineBasicBlock *MBB = JTBBs[i];
1009 // Construct an MCExpr for the entry. We want a value of the form:
1010 // (BasicBlockAddr - TableBeginAddr)
1012 // For example, a table with entries jumping to basic blocks BB0 and BB1
1015 // .word (LBB0 - LJTI_0_0)
1016 // .word (LBB1 - LJTI_0_0)
1017 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1019 if (TM.getRelocationModel() == Reloc::PIC_)
1020 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1023 // If we're generating a table of Thumb addresses in static relocation
1024 // model, we need to add one to keep interworking correctly.
1025 else if (AFI->isThumbFunction())
1026 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1028 OutStreamer.EmitValue(Expr, 4);
1030 // Mark the end of jump table data-in-code region.
1031 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1034 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1035 unsigned Opcode = MI->getOpcode();
1036 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1037 const MachineOperand &MO1 = MI->getOperand(OpNum);
1038 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1039 unsigned JTI = MO1.getIndex();
1041 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1042 OutStreamer.EmitLabel(JTISymbol);
1044 // Emit each entry of the table.
1045 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1046 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1047 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1048 unsigned OffsetWidth = 4;
1049 if (MI->getOpcode() == ARM::t2TBB_JT) {
1051 // Mark the jump table as data-in-code.
1052 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1053 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1055 // Mark the jump table as data-in-code.
1056 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1059 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1060 MachineBasicBlock *MBB = JTBBs[i];
1061 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1063 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1064 if (OffsetWidth == 4) {
1065 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
1066 .addExpr(MBBSymbolExpr)
1071 // Otherwise it's an offset from the dispatch instruction. Construct an
1072 // MCExpr for the entry. We want a value of the form:
1073 // (BasicBlockAddr - TableBeginAddr) / 2
1075 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1078 // .byte (LBB0 - LJTI_0_0) / 2
1079 // .byte (LBB1 - LJTI_0_0) / 2
1080 const MCExpr *Expr =
1081 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1082 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1084 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1086 OutStreamer.EmitValue(Expr, OffsetWidth);
1088 // Mark the end of jump table data-in-code region. 32-bit offsets use
1089 // actual branch instructions here, so we don't mark those as a data-region
1091 if (OffsetWidth != 4)
1092 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1095 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1097 unsigned NOps = MI->getNumOperands();
1099 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1100 // cast away const; DIetc do not take const operands for some reason.
1101 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1104 // Frame address. Currently handles register +- offset only.
1105 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1106 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1109 printOperand(MI, NOps-2, OS);
1112 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1113 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1114 "Only instruction which are involved into frame setup code are allowed");
1116 const MachineFunction &MF = *MI->getParent()->getParent();
1117 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1118 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1120 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1121 unsigned Opc = MI->getOpcode();
1122 unsigned SrcReg, DstReg;
1124 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1125 // Two special cases:
1126 // 1) tPUSH does not have src/dst regs.
1127 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1128 // load. Yes, this is pretty fragile, but for now I don't see better
1130 SrcReg = DstReg = ARM::SP;
1132 SrcReg = MI->getOperand(1).getReg();
1133 DstReg = MI->getOperand(0).getReg();
1136 // Try to figure out the unwinding opcode out of src / dst regs.
1137 if (MI->mayStore()) {
1139 assert(DstReg == ARM::SP &&
1140 "Only stack pointer as a destination reg is supported");
1142 SmallVector<unsigned, 4> RegList;
1143 // Skip src & dst reg, and pred ops.
1144 unsigned StartOp = 2 + 2;
1145 // Use all the operands.
1146 unsigned NumOffset = 0;
1151 llvm_unreachable("Unsupported opcode for unwinding information");
1153 // Special case here: no src & dst reg, but two extra imp ops.
1154 StartOp = 2; NumOffset = 2;
1155 case ARM::STMDB_UPD:
1156 case ARM::t2STMDB_UPD:
1157 case ARM::VSTMDDB_UPD:
1158 assert(SrcReg == ARM::SP &&
1159 "Only stack pointer as a source reg is supported");
1160 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1162 const MachineOperand &MO = MI->getOperand(i);
1163 // Actually, there should never be any impdef stuff here. Skip it
1164 // temporary to workaround PR11902.
1165 if (MO.isImplicit())
1167 RegList.push_back(MO.getReg());
1170 case ARM::STR_PRE_IMM:
1171 case ARM::STR_PRE_REG:
1172 case ARM::t2STR_PRE:
1173 assert(MI->getOperand(2).getReg() == ARM::SP &&
1174 "Only stack pointer as a source reg is supported");
1175 RegList.push_back(SrcReg);
1178 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1180 // Changes of stack / frame pointer.
1181 if (SrcReg == ARM::SP) {
1186 llvm_unreachable("Unsupported opcode for unwinding information");
1192 Offset = -MI->getOperand(2).getImm();
1196 Offset = MI->getOperand(2).getImm();
1199 Offset = MI->getOperand(2).getImm()*4;
1203 Offset = -MI->getOperand(2).getImm()*4;
1205 case ARM::tLDRpci: {
1206 // Grab the constpool index and check, whether it corresponds to
1207 // original or cloned constpool entry.
1208 unsigned CPI = MI->getOperand(1).getIndex();
1209 const MachineConstantPool *MCP = MF.getConstantPool();
1210 if (CPI >= MCP->getConstants().size())
1211 CPI = AFI.getOriginalCPIdx(CPI);
1212 assert(CPI != -1U && "Invalid constpool index");
1214 // Derive the actual offset.
1215 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1216 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1217 // FIXME: Check for user, it should be "add" instruction!
1218 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1223 if (DstReg == FramePtr && FramePtr != ARM::SP)
1224 // Set-up of the frame pointer. Positive values correspond to "add"
1226 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1227 else if (DstReg == ARM::SP) {
1228 // Change of SP by an offset. Positive values correspond to "sub"
1230 OutStreamer.EmitPad(Offset);
1233 llvm_unreachable("Unsupported opcode for unwinding information");
1235 } else if (DstReg == ARM::SP) {
1236 // FIXME: .movsp goes here
1238 llvm_unreachable("Unsupported opcode for unwinding information");
1242 llvm_unreachable("Unsupported opcode for unwinding information");
1247 extern cl::opt<bool> EnableARMEHABI;
1249 // Simple pseudo-instructions have their lowering (with expansion to real
1250 // instructions) auto-generated.
1251 #include "ARMGenMCPseudoLowering.inc"
1253 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1254 // If we just ended a constant pool, mark it as such.
1255 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1256 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1257 InConstantPool = false;
1260 // Emit unwinding stuff for frame-related instructions
1261 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1262 EmitUnwindingInstruction(MI);
1264 // Do any auto-generated pseudo lowerings.
1265 if (emitPseudoExpansionLowering(OutStreamer, MI))
1268 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1269 "Pseudo flag setting opcode should be expanded early");
1271 // Check for manual lowerings.
1272 unsigned Opc = MI->getOpcode();
1274 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1275 case ARM::DBG_VALUE: {
1276 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1277 SmallString<128> TmpStr;
1278 raw_svector_ostream OS(TmpStr);
1279 PrintDebugValueComment(MI, OS);
1280 OutStreamer.EmitRawText(StringRef(OS.str()));
1285 case ARM::tLEApcrel:
1286 case ARM::t2LEApcrel: {
1287 // FIXME: Need to also handle globals and externals
1288 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1289 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1290 ARM::t2LEApcrel ? ARM::t2ADR
1291 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1293 .addReg(MI->getOperand(0).getReg())
1294 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1295 // Add predicate operands.
1296 .addImm(MI->getOperand(2).getImm())
1297 .addReg(MI->getOperand(3).getReg()));
1300 case ARM::LEApcrelJT:
1301 case ARM::tLEApcrelJT:
1302 case ARM::t2LEApcrelJT: {
1303 MCSymbol *JTIPICSymbol =
1304 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1305 MI->getOperand(2).getImm());
1306 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1307 ARM::t2LEApcrelJT ? ARM::t2ADR
1308 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1310 .addReg(MI->getOperand(0).getReg())
1311 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1312 // Add predicate operands.
1313 .addImm(MI->getOperand(3).getImm())
1314 .addReg(MI->getOperand(4).getReg()));
1317 // Darwin call instructions are just normal call instructions with different
1318 // clobber semantics (they clobber R9).
1319 case ARM::BX_CALL: {
1320 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1323 // Add predicate operands.
1326 // Add 's' bit operand (always reg0 for this)
1329 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1330 .addReg(MI->getOperand(0).getReg()));
1333 case ARM::tBX_CALL: {
1334 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1337 // Add predicate operands.
1341 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1342 .addReg(MI->getOperand(0).getReg())
1343 // Add predicate operands.
1348 case ARM::BMOVPCRX_CALL: {
1349 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1352 // Add predicate operands.
1355 // Add 's' bit operand (always reg0 for this)
1358 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1360 .addReg(MI->getOperand(0).getReg())
1361 // Add predicate operands.
1364 // Add 's' bit operand (always reg0 for this)
1368 case ARM::BMOVPCB_CALL: {
1369 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1372 // Add predicate operands.
1375 // Add 's' bit operand (always reg0 for this)
1378 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1379 MCSymbol *GVSym = Mang->getSymbol(GV);
1380 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1381 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1383 // Add predicate operands.
1388 case ARM::MOVi16_ga_pcrel:
1389 case ARM::t2MOVi16_ga_pcrel: {
1391 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1392 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1394 unsigned TF = MI->getOperand(1).getTargetFlags();
1395 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1396 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1397 MCSymbol *GVSym = GetARMGVSymbol(GV);
1398 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1400 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1401 getFunctionNumber(),
1402 MI->getOperand(2).getImm(), OutContext);
1403 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1404 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1405 const MCExpr *PCRelExpr =
1406 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1407 MCBinaryExpr::CreateAdd(LabelSymExpr,
1408 MCConstantExpr::Create(PCAdj, OutContext),
1409 OutContext), OutContext), OutContext);
1410 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1412 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1413 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1416 // Add predicate operands.
1417 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1418 TmpInst.addOperand(MCOperand::CreateReg(0));
1419 // Add 's' bit operand (always reg0 for this)
1420 TmpInst.addOperand(MCOperand::CreateReg(0));
1421 OutStreamer.EmitInstruction(TmpInst);
1424 case ARM::MOVTi16_ga_pcrel:
1425 case ARM::t2MOVTi16_ga_pcrel: {
1427 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1428 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1429 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1430 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1432 unsigned TF = MI->getOperand(2).getTargetFlags();
1433 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1434 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1435 MCSymbol *GVSym = GetARMGVSymbol(GV);
1436 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1438 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1439 getFunctionNumber(),
1440 MI->getOperand(3).getImm(), OutContext);
1441 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1442 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1443 const MCExpr *PCRelExpr =
1444 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1445 MCBinaryExpr::CreateAdd(LabelSymExpr,
1446 MCConstantExpr::Create(PCAdj, OutContext),
1447 OutContext), OutContext), OutContext);
1448 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1450 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1451 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1453 // Add predicate operands.
1454 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1455 TmpInst.addOperand(MCOperand::CreateReg(0));
1456 // Add 's' bit operand (always reg0 for this)
1457 TmpInst.addOperand(MCOperand::CreateReg(0));
1458 OutStreamer.EmitInstruction(TmpInst);
1461 case ARM::tPICADD: {
1462 // This is a pseudo op for a label + instruction sequence, which looks like:
1465 // This adds the address of LPC0 to r0.
1468 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1469 getFunctionNumber(), MI->getOperand(2).getImm(),
1472 // Form and emit the add.
1473 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1474 .addReg(MI->getOperand(0).getReg())
1475 .addReg(MI->getOperand(0).getReg())
1477 // Add predicate operands.
1483 // This is a pseudo op for a label + instruction sequence, which looks like:
1486 // This adds the address of LPC0 to r0.
1489 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1490 getFunctionNumber(), MI->getOperand(2).getImm(),
1493 // Form and emit the add.
1494 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1495 .addReg(MI->getOperand(0).getReg())
1497 .addReg(MI->getOperand(1).getReg())
1498 // Add predicate operands.
1499 .addImm(MI->getOperand(3).getImm())
1500 .addReg(MI->getOperand(4).getReg())
1501 // Add 's' bit operand (always reg0 for this)
1512 case ARM::PICLDRSH: {
1513 // This is a pseudo op for a label + instruction sequence, which looks like:
1516 // The LCP0 label is referenced by a constant pool entry in order to get
1517 // a PC-relative address at the ldr instruction.
1520 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1521 getFunctionNumber(), MI->getOperand(2).getImm(),
1524 // Form and emit the load
1526 switch (MI->getOpcode()) {
1528 llvm_unreachable("Unexpected opcode!");
1529 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1530 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1531 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1532 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1533 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1534 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1535 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1536 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1538 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1539 .addReg(MI->getOperand(0).getReg())
1541 .addReg(MI->getOperand(1).getReg())
1543 // Add predicate operands.
1544 .addImm(MI->getOperand(3).getImm())
1545 .addReg(MI->getOperand(4).getReg()));
1549 case ARM::CONSTPOOL_ENTRY: {
1550 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1551 /// in the function. The first operand is the ID# for this instruction, the
1552 /// second is the index into the MachineConstantPool that this is, the third
1553 /// is the size in bytes of this constant pool entry.
1554 /// The required alignment is specified on the basic block holding this MI.
1555 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1556 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1558 // If this is the first entry of the pool, mark it.
1559 if (!InConstantPool) {
1560 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1561 InConstantPool = true;
1564 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1566 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1567 if (MCPE.isMachineConstantPoolEntry())
1568 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1570 EmitGlobalConstant(MCPE.Val.ConstVal);
1573 case ARM::t2BR_JT: {
1574 // Lower and emit the instruction itself, then the jump table following it.
1575 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1577 .addReg(MI->getOperand(0).getReg())
1578 // Add predicate operands.
1582 // Output the data for the jump table itself
1586 case ARM::t2TBB_JT: {
1587 // Lower and emit the instruction itself, then the jump table following it.
1588 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1590 .addReg(MI->getOperand(0).getReg())
1591 // Add predicate operands.
1595 // Output the data for the jump table itself
1597 // Make sure the next instruction is 2-byte aligned.
1601 case ARM::t2TBH_JT: {
1602 // Lower and emit the instruction itself, then the jump table following it.
1603 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1605 .addReg(MI->getOperand(0).getReg())
1606 // Add predicate operands.
1610 // Output the data for the jump table itself
1616 // Lower and emit the instruction itself, then the jump table following it.
1619 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1620 ARM::MOVr : ARM::tMOVr;
1621 TmpInst.setOpcode(Opc);
1622 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1623 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1624 // Add predicate operands.
1625 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1626 TmpInst.addOperand(MCOperand::CreateReg(0));
1627 // Add 's' bit operand (always reg0 for this)
1628 if (Opc == ARM::MOVr)
1629 TmpInst.addOperand(MCOperand::CreateReg(0));
1630 OutStreamer.EmitInstruction(TmpInst);
1632 // Make sure the Thumb jump table is 4-byte aligned.
1633 if (Opc == ARM::tMOVr)
1636 // Output the data for the jump table itself
1641 // Lower and emit the instruction itself, then the jump table following it.
1644 if (MI->getOperand(1).getReg() == 0) {
1646 TmpInst.setOpcode(ARM::LDRi12);
1647 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1648 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1649 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1651 TmpInst.setOpcode(ARM::LDRrs);
1652 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1653 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1654 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1655 TmpInst.addOperand(MCOperand::CreateImm(0));
1657 // Add predicate operands.
1658 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1659 TmpInst.addOperand(MCOperand::CreateReg(0));
1660 OutStreamer.EmitInstruction(TmpInst);
1662 // Output the data for the jump table itself
1666 case ARM::BR_JTadd: {
1667 // Lower and emit the instruction itself, then the jump table following it.
1668 // add pc, target, idx
1669 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1671 .addReg(MI->getOperand(0).getReg())
1672 .addReg(MI->getOperand(1).getReg())
1673 // Add predicate operands.
1676 // Add 's' bit operand (always reg0 for this)
1679 // Output the data for the jump table itself
1684 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1685 // FIXME: Remove this special case when they do.
1686 if (!Subtarget->isTargetDarwin()) {
1687 //.long 0xe7ffdefe @ trap
1688 uint32_t Val = 0xe7ffdefeUL;
1689 OutStreamer.AddComment("trap");
1690 OutStreamer.EmitIntValue(Val, 4);
1695 case ARM::TRAPNaCl: {
1696 //.long 0xe7fedef0 @ trap
1697 uint32_t Val = 0xe7fedef0UL;
1698 OutStreamer.AddComment("trap");
1699 OutStreamer.EmitIntValue(Val, 4);
1703 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1704 // FIXME: Remove this special case when they do.
1705 if (!Subtarget->isTargetDarwin()) {
1706 //.short 57086 @ trap
1707 uint16_t Val = 0xdefe;
1708 OutStreamer.AddComment("trap");
1709 OutStreamer.EmitIntValue(Val, 2);
1714 case ARM::t2Int_eh_sjlj_setjmp:
1715 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1716 case ARM::tInt_eh_sjlj_setjmp: {
1717 // Two incoming args: GPR:$src, GPR:$val
1720 // str $val, [$src, #4]
1725 unsigned SrcReg = MI->getOperand(0).getReg();
1726 unsigned ValReg = MI->getOperand(1).getReg();
1727 MCSymbol *Label = GetARMSJLJEHLabel();
1728 OutStreamer.AddComment("eh_setjmp begin");
1729 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1746 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1749 // The offset immediate is #4. The operand value is scaled by 4 for the
1750 // tSTR instruction.
1756 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1764 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1765 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1766 .addExpr(SymbolExpr)
1770 OutStreamer.AddComment("eh_setjmp end");
1771 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1779 OutStreamer.EmitLabel(Label);
1783 case ARM::Int_eh_sjlj_setjmp_nofp:
1784 case ARM::Int_eh_sjlj_setjmp: {
1785 // Two incoming args: GPR:$src, GPR:$val
1787 // str $val, [$src, #+4]
1791 unsigned SrcReg = MI->getOperand(0).getReg();
1792 unsigned ValReg = MI->getOperand(1).getReg();
1794 OutStreamer.AddComment("eh_setjmp begin");
1795 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1802 // 's' bit operand (always reg0 for this).
1805 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1813 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1819 // 's' bit operand (always reg0 for this).
1822 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1829 // 's' bit operand (always reg0 for this).
1832 OutStreamer.AddComment("eh_setjmp end");
1833 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1839 // 's' bit operand (always reg0 for this).
1843 case ARM::Int_eh_sjlj_longjmp: {
1844 // ldr sp, [$src, #8]
1845 // ldr $scratch, [$src, #4]
1848 unsigned SrcReg = MI->getOperand(0).getReg();
1849 unsigned ScratchReg = MI->getOperand(1).getReg();
1850 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1858 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1866 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1874 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1881 case ARM::tInt_eh_sjlj_longjmp: {
1882 // ldr $scratch, [$src, #8]
1884 // ldr $scratch, [$src, #4]
1887 unsigned SrcReg = MI->getOperand(0).getReg();
1888 unsigned ScratchReg = MI->getOperand(1).getReg();
1889 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1892 // The offset immediate is #8. The operand value is scaled by 4 for the
1893 // tLDR instruction.
1899 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1906 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1914 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1922 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1932 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1934 OutStreamer.EmitInstruction(TmpInst);
1937 //===----------------------------------------------------------------------===//
1938 // Target Registry Stuff
1939 //===----------------------------------------------------------------------===//
1941 // Force static initialization.
1942 extern "C" void LLVMInitializeARMAsmPrinter() {
1943 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1944 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);