1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/DebugInfo.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DataLayout.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ELF.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/TargetRegistry.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/Mangler.h"
54 #include "llvm/Target/TargetMachine.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
73 class AsmAttributeEmitter : public AttributeEmitter {
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
113 StringRef StringValue;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
129 Size += sizeof(int8_t); // Is this really necessary?
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
172 ContentsSize += getULEBSize(Attribute);
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag);
199 default: llvm_unreachable("Invalid attribute type");
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(item.StringValue.upper());
205 Streamer.EmitIntValue(0, 1); // '\0'
214 } // end of anonymous namespace
216 /// EmitDwarfRegOp - Emit dwarf register operation.
217 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
218 const TargetRegisterInfo *RI = TM.getRegisterInfo();
219 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
220 AsmPrinter::EmitDwarfRegOp(MLoc);
223 assert(MLoc.isReg() &&
224 "This doesn't support offset/indirection - implement it if needed");
225 unsigned Reg = MLoc.getReg();
226 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
227 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
228 // S registers are described as bit-pieces of a register
229 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
230 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
232 unsigned SReg = Reg - ARM::S0;
233 bool odd = SReg & 0x1;
234 unsigned Rx = 256 + (SReg >> 1);
236 OutStreamer.AddComment("DW_OP_regx for S register");
237 EmitInt8(dwarf::DW_OP_regx);
239 OutStreamer.AddComment(Twine(SReg));
243 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
244 EmitInt8(dwarf::DW_OP_bit_piece);
248 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
249 EmitInt8(dwarf::DW_OP_bit_piece);
253 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
254 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
255 // Q registers Q0-Q15 are described by composing two D registers together.
256 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
259 unsigned QReg = Reg - ARM::Q0;
260 unsigned D1 = 256 + 2 * QReg;
261 unsigned D2 = D1 + 1;
263 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
264 EmitInt8(dwarf::DW_OP_regx);
266 OutStreamer.AddComment("DW_OP_piece 8");
267 EmitInt8(dwarf::DW_OP_piece);
270 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
271 EmitInt8(dwarf::DW_OP_regx);
273 OutStreamer.AddComment("DW_OP_piece 8");
274 EmitInt8(dwarf::DW_OP_piece);
279 void ARMAsmPrinter::EmitFunctionBodyEnd() {
280 // Make sure to terminate any constant pools that were at the end
284 InConstantPool = false;
285 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
288 void ARMAsmPrinter::EmitFunctionEntryLabel() {
289 if (AFI->isThumbFunction()) {
290 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
291 OutStreamer.EmitThumbFunc(CurrentFnSym);
294 OutStreamer.EmitLabel(CurrentFnSym);
297 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
298 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
299 assert(Size && "C++ constructor pointer had zero size!");
301 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
302 assert(GV && "C++ constructor pointer was not a GlobalValue!");
304 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
305 (Subtarget->isTargetDarwin()
306 ? MCSymbolRefExpr::VK_None
307 : MCSymbolRefExpr::VK_ARM_TARGET1),
310 OutStreamer.EmitValue(E, Size);
313 /// runOnMachineFunction - This uses the EmitInstruction()
314 /// method to print assembly for each instruction.
316 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
317 AFI = MF.getInfo<ARMFunctionInfo>();
318 MCP = MF.getConstantPool();
320 return AsmPrinter::runOnMachineFunction(MF);
323 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
324 raw_ostream &O, const char *Modifier) {
325 const MachineOperand &MO = MI->getOperand(OpNum);
326 unsigned TF = MO.getTargetFlags();
328 switch (MO.getType()) {
329 default: llvm_unreachable("<unknown operand type>");
330 case MachineOperand::MO_Register: {
331 unsigned Reg = MO.getReg();
332 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
333 assert(!MO.getSubReg() && "Subregs should be eliminated!");
334 if(ARM::GPRPairRegClass.contains(Reg)) {
335 const MachineFunction &MF = *MI->getParent()->getParent();
336 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
337 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
339 O << ARMInstPrinter::getRegisterName(Reg);
342 case MachineOperand::MO_Immediate: {
343 int64_t Imm = MO.getImm();
345 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
346 (TF == ARMII::MO_LO16))
348 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
349 (TF == ARMII::MO_HI16))
354 case MachineOperand::MO_MachineBasicBlock:
355 O << *MO.getMBB()->getSymbol();
357 case MachineOperand::MO_GlobalAddress: {
358 const GlobalValue *GV = MO.getGlobal();
359 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
360 (TF & ARMII::MO_LO16))
362 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
363 (TF & ARMII::MO_HI16))
365 O << *Mang->getSymbol(GV);
367 printOffset(MO.getOffset(), O);
368 if (TF == ARMII::MO_PLT)
372 case MachineOperand::MO_ExternalSymbol: {
373 O << *GetExternalSymbolSymbol(MO.getSymbolName());
374 if (TF == ARMII::MO_PLT)
378 case MachineOperand::MO_ConstantPoolIndex:
379 O << *GetCPISymbol(MO.getIndex());
381 case MachineOperand::MO_JumpTableIndex:
382 O << *GetJTISymbol(MO.getIndex());
387 //===--------------------------------------------------------------------===//
389 MCSymbol *ARMAsmPrinter::
390 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
391 SmallString<60> Name;
392 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
393 << getFunctionNumber() << '_' << uid << '_' << uid2;
394 return OutContext.GetOrCreateSymbol(Name.str());
398 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
399 SmallString<60> Name;
400 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
401 << getFunctionNumber();
402 return OutContext.GetOrCreateSymbol(Name.str());
405 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
406 unsigned AsmVariant, const char *ExtraCode,
408 // Does this asm operand have a single letter operand modifier?
409 if (ExtraCode && ExtraCode[0]) {
410 if (ExtraCode[1] != 0) return true; // Unknown modifier.
412 switch (ExtraCode[0]) {
414 // See if this is a generic print operand
415 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
416 case 'a': // Print as a memory address.
417 if (MI->getOperand(OpNum).isReg()) {
419 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
424 case 'c': // Don't print "#" before an immediate operand.
425 if (!MI->getOperand(OpNum).isImm())
427 O << MI->getOperand(OpNum).getImm();
429 case 'P': // Print a VFP double precision register.
430 case 'q': // Print a NEON quad precision register.
431 printOperand(MI, OpNum, O);
433 case 'y': // Print a VFP single precision register as indexed double.
434 if (MI->getOperand(OpNum).isReg()) {
435 unsigned Reg = MI->getOperand(OpNum).getReg();
436 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
437 // Find the 'd' register that has this 's' register as a sub-register,
438 // and determine the lane number.
439 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
440 if (!ARM::DPRRegClass.contains(*SR))
442 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
443 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
448 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
449 if (!MI->getOperand(OpNum).isImm())
451 O << ~(MI->getOperand(OpNum).getImm());
453 case 'L': // The low 16 bits of an immediate constant.
454 if (!MI->getOperand(OpNum).isImm())
456 O << (MI->getOperand(OpNum).getImm() & 0xffff);
458 case 'M': { // A register range suitable for LDM/STM.
459 if (!MI->getOperand(OpNum).isReg())
461 const MachineOperand &MO = MI->getOperand(OpNum);
462 unsigned RegBegin = MO.getReg();
463 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
464 // already got the operands in registers that are operands to the
465 // inline asm statement.
467 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
469 // FIXME: The register allocator not only may not have given us the
470 // registers in sequence, but may not be in ascending registers. This
471 // will require changes in the register allocator that'll need to be
472 // propagated down here if the operands change.
473 unsigned RegOps = OpNum + 1;
474 while (MI->getOperand(RegOps).isReg()) {
476 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
484 case 'R': // The most significant register of a pair.
485 case 'Q': { // The least significant register of a pair.
488 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
489 if (!FlagsOP.isImm())
491 unsigned Flags = FlagsOP.getImm();
492 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
495 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
496 if (RegOp >= MI->getNumOperands())
498 const MachineOperand &MO = MI->getOperand(RegOp);
501 unsigned Reg = MO.getReg();
502 O << ARMInstPrinter::getRegisterName(Reg);
506 case 'e': // The low doubleword register of a NEON quad register.
507 case 'f': { // The high doubleword register of a NEON quad register.
508 if (!MI->getOperand(OpNum).isReg())
510 unsigned Reg = MI->getOperand(OpNum).getReg();
511 if (!ARM::QPRRegClass.contains(Reg))
513 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
514 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
515 ARM::dsub_0 : ARM::dsub_1);
516 O << ARMInstPrinter::getRegisterName(SubReg);
520 // This modifier is not yet supported.
521 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
523 case 'H': { // The highest-numbered register of a pair.
524 const MachineOperand &MO = MI->getOperand(OpNum);
527 const MachineFunction &MF = *MI->getParent()->getParent();
528 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
529 unsigned Reg = MO.getReg();
530 if(!ARM::GPRPairRegClass.contains(Reg))
532 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
533 O << ARMInstPrinter::getRegisterName(Reg);
539 printOperand(MI, OpNum, O);
543 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
544 unsigned OpNum, unsigned AsmVariant,
545 const char *ExtraCode,
547 // Does this asm operand have a single letter operand modifier?
548 if (ExtraCode && ExtraCode[0]) {
549 if (ExtraCode[1] != 0) return true; // Unknown modifier.
551 switch (ExtraCode[0]) {
552 case 'A': // A memory operand for a VLD1/VST1 instruction.
553 default: return true; // Unknown modifier.
554 case 'm': // The base register of a memory operand.
555 if (!MI->getOperand(OpNum).isReg())
557 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
562 const MachineOperand &MO = MI->getOperand(OpNum);
563 assert(MO.isReg() && "unexpected inline asm memory operand");
564 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
568 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
569 if (Subtarget->isTargetDarwin()) {
570 Reloc::Model RelocM = TM.getRelocationModel();
571 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
572 // Declare all the text sections up front (before the DWARF sections
573 // emitted by AsmPrinter::doInitialization) so the assembler will keep
574 // them together at the beginning of the object file. This helps
575 // avoid out-of-range branches that are due a fundamental limitation of
576 // the way symbol offsets are encoded with the current Darwin ARM
578 const TargetLoweringObjectFileMachO &TLOFMacho =
579 static_cast<const TargetLoweringObjectFileMachO &>(
580 getObjFileLowering());
582 // Collect the set of sections our functions will go into.
583 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
584 SmallPtrSet<const MCSection *, 8> > TextSections;
585 // Default text section comes first.
586 TextSections.insert(TLOFMacho.getTextSection());
587 // Now any user defined text sections from function attributes.
588 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
589 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
590 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
591 // Now the coalescable sections.
592 TextSections.insert(TLOFMacho.getTextCoalSection());
593 TextSections.insert(TLOFMacho.getConstTextCoalSection());
595 // Emit the sections in the .s file header to fix the order.
596 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
597 OutStreamer.SwitchSection(TextSections[i]);
599 if (RelocM == Reloc::DynamicNoPIC) {
600 const MCSection *sect =
601 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
602 MCSectionMachO::S_SYMBOL_STUBS,
603 12, SectionKind::getText());
604 OutStreamer.SwitchSection(sect);
606 const MCSection *sect =
607 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
608 MCSectionMachO::S_SYMBOL_STUBS,
609 16, SectionKind::getText());
610 OutStreamer.SwitchSection(sect);
612 const MCSection *StaticInitSect =
613 OutContext.getMachOSection("__TEXT", "__StaticInit",
614 MCSectionMachO::S_REGULAR |
615 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
616 SectionKind::getText());
617 OutStreamer.SwitchSection(StaticInitSect);
621 // Use unified assembler syntax.
622 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
624 // Emit ARM Build Attributes
625 if (Subtarget->isTargetELF())
630 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
631 if (Subtarget->isTargetDarwin()) {
632 // All darwin targets use mach-o.
633 const TargetLoweringObjectFileMachO &TLOFMacho =
634 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
635 MachineModuleInfoMachO &MMIMacho =
636 MMI->getObjFileInfo<MachineModuleInfoMachO>();
638 // Output non-lazy-pointers for external and common global variables.
639 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
641 if (!Stubs.empty()) {
642 // Switch with ".non_lazy_symbol_pointer" directive.
643 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
645 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
647 OutStreamer.EmitLabel(Stubs[i].first);
648 // .indirect_symbol _foo
649 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
650 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
653 // External to current translation unit.
654 OutStreamer.EmitIntValue(0, 4/*size*/);
656 // Internal to current translation unit.
658 // When we place the LSDA into the TEXT section, the type info
659 // pointers need to be indirect and pc-rel. We accomplish this by
660 // using NLPs; however, sometimes the types are local to the file.
661 // We need to fill in the value for the NLP in those cases.
662 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
668 OutStreamer.AddBlankLine();
671 Stubs = MMIMacho.GetHiddenGVStubList();
672 if (!Stubs.empty()) {
673 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
675 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
677 OutStreamer.EmitLabel(Stubs[i].first);
679 OutStreamer.EmitValue(MCSymbolRefExpr::
680 Create(Stubs[i].second.getPointer(),
686 OutStreamer.AddBlankLine();
689 // Funny Darwin hack: This flag tells the linker that no global symbols
690 // contain code that falls through to other global symbols (e.g. the obvious
691 // implementation of multiple entry points). If this doesn't occur, the
692 // linker can safely perform dead code stripping. Since LLVM never
693 // generates code that does this, it is always safe to set.
694 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
696 // FIXME: This should eventually end up somewhere else where more
697 // intelligent flag decisions can be made. For now we are just maintaining
698 // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
699 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&OutStreamer))
700 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
703 //===----------------------------------------------------------------------===//
704 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
706 // The following seem like one-off assembler flags, but they actually need
707 // to appear in the .ARM.attributes section in ELF.
708 // Instead of subclassing the MCELFStreamer, we do the work here.
710 void ARMAsmPrinter::emitAttributes() {
712 emitARMAttributeSection();
714 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
715 bool emitFPU = false;
716 AttributeEmitter *AttrEmitter;
717 if (OutStreamer.hasRawTextSupport()) {
718 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
721 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
722 AttrEmitter = new ObjectAttributeEmitter(O);
725 AttrEmitter->MaybeSwitchVendor("aeabi");
727 std::string CPUString = Subtarget->getCPUString();
729 if (CPUString == "cortex-a8" ||
730 Subtarget->isCortexA8()) {
731 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
732 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
733 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
734 ARMBuildAttrs::ApplicationProfile);
735 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
736 ARMBuildAttrs::Allowed);
737 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
738 ARMBuildAttrs::AllowThumb32);
739 // Fixme: figure out when this is emitted.
740 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
741 // ARMBuildAttrs::AllowWMMXv1);
744 /// ADD additional Else-cases here!
745 } else if (CPUString == "xscale") {
746 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
748 ARMBuildAttrs::Allowed);
749 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
750 ARMBuildAttrs::Allowed);
751 } else if (CPUString == "generic") {
752 // For a generic CPU, we assume a standard v7a architecture in Subtarget.
753 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
754 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
755 ARMBuildAttrs::ApplicationProfile);
756 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
757 ARMBuildAttrs::Allowed);
758 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
759 ARMBuildAttrs::AllowThumb32);
760 } else if (Subtarget->hasV7Ops()) {
761 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
762 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
763 ARMBuildAttrs::AllowThumb32);
764 } else if (Subtarget->hasV6T2Ops())
765 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2);
766 else if (Subtarget->hasV6Ops())
767 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6);
768 else if (Subtarget->hasV5TEOps())
769 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE);
770 else if (Subtarget->hasV5TOps())
771 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T);
772 else if (Subtarget->hasV4TOps())
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
775 if (Subtarget->hasNEON() && emitFPU) {
776 /* NEON is not exactly a VFP architecture, but GAS emit one of
777 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
778 if (Subtarget->hasVFP4())
779 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
782 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
783 /* If emitted for NEON, omit from VFP below, since you can have both
784 * NEON and VFP in build attributes but only one .fpu */
789 if (Subtarget->hasVFP4()) {
790 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
791 ARMBuildAttrs::AllowFPv4A);
793 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
796 } else if (Subtarget->hasVFP3()) {
797 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
798 ARMBuildAttrs::AllowFPv3A);
800 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
803 } else if (Subtarget->hasVFP2()) {
804 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
805 ARMBuildAttrs::AllowFPv2);
807 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
810 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
811 * since NEON can have 1 (allowed) or 2 (MAC operations) */
812 if (Subtarget->hasNEON()) {
813 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
814 ARMBuildAttrs::Allowed);
817 // Signal various FP modes.
818 if (!TM.Options.UnsafeFPMath) {
819 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
820 ARMBuildAttrs::Allowed);
821 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
822 ARMBuildAttrs::Allowed);
825 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
826 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
827 ARMBuildAttrs::Allowed);
829 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
830 ARMBuildAttrs::AllowIEE754);
832 // FIXME: add more flags to ARMBuildAttrs.h
833 // 8-bytes alignment stuff.
834 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
835 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
837 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
838 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
839 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
840 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
842 // FIXME: Should we signal R9 usage?
844 if (Subtarget->hasDivide())
845 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
847 AttrEmitter->Finish();
851 void ARMAsmPrinter::emitARMAttributeSection() {
853 // [ <section-length> "vendor-name"
854 // [ <file-tag> <size> <attribute>*
855 // | <section-tag> <size> <section-number>* 0 <attribute>*
856 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
860 if (OutStreamer.hasRawTextSupport())
863 const ARMElfTargetObjectFile &TLOFELF =
864 static_cast<const ARMElfTargetObjectFile &>
865 (getObjFileLowering());
867 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
870 OutStreamer.EmitIntValue(0x41, 1);
873 //===----------------------------------------------------------------------===//
875 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
876 unsigned LabelId, MCContext &Ctx) {
878 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
879 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
883 static MCSymbolRefExpr::VariantKind
884 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
886 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
887 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
888 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
889 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
890 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
891 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
893 llvm_unreachable("Invalid ARMCPModifier!");
896 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
897 bool isIndirect = Subtarget->isTargetDarwin() &&
898 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
900 return Mang->getSymbol(GV);
902 // FIXME: Remove this when Darwin transition to @GOT like syntax.
903 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
904 MachineModuleInfoMachO &MMIMachO =
905 MMI->getObjFileInfo<MachineModuleInfoMachO>();
906 MachineModuleInfoImpl::StubValueTy &StubSym =
907 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
908 MMIMachO.getGVStubEntry(MCSym);
909 if (StubSym.getPointer() == 0)
910 StubSym = MachineModuleInfoImpl::
911 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
916 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
917 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
919 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
922 if (ACPV->isLSDA()) {
923 SmallString<128> Str;
924 raw_svector_ostream OS(Str);
925 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
926 MCSym = OutContext.GetOrCreateSymbol(OS.str());
927 } else if (ACPV->isBlockAddress()) {
928 const BlockAddress *BA =
929 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
930 MCSym = GetBlockAddressSymbol(BA);
931 } else if (ACPV->isGlobalValue()) {
932 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
933 MCSym = GetARMGVSymbol(GV);
934 } else if (ACPV->isMachineBasicBlock()) {
935 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
936 MCSym = MBB->getSymbol();
938 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
939 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
940 MCSym = GetExternalSymbolSymbol(Sym);
943 // Create an MCSymbol for the reference.
945 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
948 if (ACPV->getPCAdjustment()) {
949 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
953 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
955 MCBinaryExpr::CreateAdd(PCRelExpr,
956 MCConstantExpr::Create(ACPV->getPCAdjustment(),
959 if (ACPV->mustAddCurrentAddress()) {
960 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
961 // label, so just emit a local label end reference that instead.
962 MCSymbol *DotSym = OutContext.CreateTempSymbol();
963 OutStreamer.EmitLabel(DotSym);
964 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
965 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
967 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
969 OutStreamer.EmitValue(Expr, Size);
972 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
973 unsigned Opcode = MI->getOpcode();
975 if (Opcode == ARM::BR_JTadd)
977 else if (Opcode == ARM::BR_JTm)
980 const MachineOperand &MO1 = MI->getOperand(OpNum);
981 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
982 unsigned JTI = MO1.getIndex();
984 // Emit a label for the jump table.
985 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
986 OutStreamer.EmitLabel(JTISymbol);
988 // Mark the jump table as data-in-code.
989 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
991 // Emit each entry of the table.
992 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
993 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
994 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
996 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
997 MachineBasicBlock *MBB = JTBBs[i];
998 // Construct an MCExpr for the entry. We want a value of the form:
999 // (BasicBlockAddr - TableBeginAddr)
1001 // For example, a table with entries jumping to basic blocks BB0 and BB1
1004 // .word (LBB0 - LJTI_0_0)
1005 // .word (LBB1 - LJTI_0_0)
1006 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1008 if (TM.getRelocationModel() == Reloc::PIC_)
1009 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1012 // If we're generating a table of Thumb addresses in static relocation
1013 // model, we need to add one to keep interworking correctly.
1014 else if (AFI->isThumbFunction())
1015 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1017 OutStreamer.EmitValue(Expr, 4);
1019 // Mark the end of jump table data-in-code region.
1020 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1023 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1024 unsigned Opcode = MI->getOpcode();
1025 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1026 const MachineOperand &MO1 = MI->getOperand(OpNum);
1027 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1028 unsigned JTI = MO1.getIndex();
1030 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1031 OutStreamer.EmitLabel(JTISymbol);
1033 // Emit each entry of the table.
1034 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1035 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1036 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1037 unsigned OffsetWidth = 4;
1038 if (MI->getOpcode() == ARM::t2TBB_JT) {
1040 // Mark the jump table as data-in-code.
1041 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1042 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1044 // Mark the jump table as data-in-code.
1045 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1048 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1049 MachineBasicBlock *MBB = JTBBs[i];
1050 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1052 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1053 if (OffsetWidth == 4) {
1054 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
1055 .addExpr(MBBSymbolExpr)
1060 // Otherwise it's an offset from the dispatch instruction. Construct an
1061 // MCExpr for the entry. We want a value of the form:
1062 // (BasicBlockAddr - TableBeginAddr) / 2
1064 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1067 // .byte (LBB0 - LJTI_0_0) / 2
1068 // .byte (LBB1 - LJTI_0_0) / 2
1069 const MCExpr *Expr =
1070 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1071 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1073 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1075 OutStreamer.EmitValue(Expr, OffsetWidth);
1077 // Mark the end of jump table data-in-code region. 32-bit offsets use
1078 // actual branch instructions here, so we don't mark those as a data-region
1080 if (OffsetWidth != 4)
1081 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1084 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1085 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1086 "Only instruction which are involved into frame setup code are allowed");
1088 const MachineFunction &MF = *MI->getParent()->getParent();
1089 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1090 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1092 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1093 unsigned Opc = MI->getOpcode();
1094 unsigned SrcReg, DstReg;
1096 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1097 // Two special cases:
1098 // 1) tPUSH does not have src/dst regs.
1099 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1100 // load. Yes, this is pretty fragile, but for now I don't see better
1102 SrcReg = DstReg = ARM::SP;
1104 SrcReg = MI->getOperand(1).getReg();
1105 DstReg = MI->getOperand(0).getReg();
1108 // Try to figure out the unwinding opcode out of src / dst regs.
1109 if (MI->mayStore()) {
1111 assert(DstReg == ARM::SP &&
1112 "Only stack pointer as a destination reg is supported");
1114 SmallVector<unsigned, 4> RegList;
1115 // Skip src & dst reg, and pred ops.
1116 unsigned StartOp = 2 + 2;
1117 // Use all the operands.
1118 unsigned NumOffset = 0;
1123 llvm_unreachable("Unsupported opcode for unwinding information");
1125 // Special case here: no src & dst reg, but two extra imp ops.
1126 StartOp = 2; NumOffset = 2;
1127 case ARM::STMDB_UPD:
1128 case ARM::t2STMDB_UPD:
1129 case ARM::VSTMDDB_UPD:
1130 assert(SrcReg == ARM::SP &&
1131 "Only stack pointer as a source reg is supported");
1132 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1134 const MachineOperand &MO = MI->getOperand(i);
1135 // Actually, there should never be any impdef stuff here. Skip it
1136 // temporary to workaround PR11902.
1137 if (MO.isImplicit())
1139 RegList.push_back(MO.getReg());
1142 case ARM::STR_PRE_IMM:
1143 case ARM::STR_PRE_REG:
1144 case ARM::t2STR_PRE:
1145 assert(MI->getOperand(2).getReg() == ARM::SP &&
1146 "Only stack pointer as a source reg is supported");
1147 RegList.push_back(SrcReg);
1150 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1152 // Changes of stack / frame pointer.
1153 if (SrcReg == ARM::SP) {
1158 llvm_unreachable("Unsupported opcode for unwinding information");
1164 Offset = -MI->getOperand(2).getImm();
1168 Offset = MI->getOperand(2).getImm();
1171 Offset = MI->getOperand(2).getImm()*4;
1175 Offset = -MI->getOperand(2).getImm()*4;
1177 case ARM::tLDRpci: {
1178 // Grab the constpool index and check, whether it corresponds to
1179 // original or cloned constpool entry.
1180 unsigned CPI = MI->getOperand(1).getIndex();
1181 const MachineConstantPool *MCP = MF.getConstantPool();
1182 if (CPI >= MCP->getConstants().size())
1183 CPI = AFI.getOriginalCPIdx(CPI);
1184 assert(CPI != -1U && "Invalid constpool index");
1186 // Derive the actual offset.
1187 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1188 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1189 // FIXME: Check for user, it should be "add" instruction!
1190 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1195 if (DstReg == FramePtr && FramePtr != ARM::SP)
1196 // Set-up of the frame pointer. Positive values correspond to "add"
1198 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1199 else if (DstReg == ARM::SP) {
1200 // Change of SP by an offset. Positive values correspond to "sub"
1202 OutStreamer.EmitPad(Offset);
1205 llvm_unreachable("Unsupported opcode for unwinding information");
1207 } else if (DstReg == ARM::SP) {
1208 // FIXME: .movsp goes here
1210 llvm_unreachable("Unsupported opcode for unwinding information");
1214 llvm_unreachable("Unsupported opcode for unwinding information");
1219 extern cl::opt<bool> EnableARMEHABI;
1221 // Simple pseudo-instructions have their lowering (with expansion to real
1222 // instructions) auto-generated.
1223 #include "ARMGenMCPseudoLowering.inc"
1225 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1226 // If we just ended a constant pool, mark it as such.
1227 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1228 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1229 InConstantPool = false;
1232 // Emit unwinding stuff for frame-related instructions
1233 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1234 EmitUnwindingInstruction(MI);
1236 // Do any auto-generated pseudo lowerings.
1237 if (emitPseudoExpansionLowering(OutStreamer, MI))
1240 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1241 "Pseudo flag setting opcode should be expanded early");
1243 // Check for manual lowerings.
1244 unsigned Opc = MI->getOpcode();
1246 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1247 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1249 case ARM::tLEApcrel:
1250 case ARM::t2LEApcrel: {
1251 // FIXME: Need to also handle globals and externals
1252 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1253 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1254 ARM::t2LEApcrel ? ARM::t2ADR
1255 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1257 .addReg(MI->getOperand(0).getReg())
1258 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1259 // Add predicate operands.
1260 .addImm(MI->getOperand(2).getImm())
1261 .addReg(MI->getOperand(3).getReg()));
1264 case ARM::LEApcrelJT:
1265 case ARM::tLEApcrelJT:
1266 case ARM::t2LEApcrelJT: {
1267 MCSymbol *JTIPICSymbol =
1268 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1269 MI->getOperand(2).getImm());
1270 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1271 ARM::t2LEApcrelJT ? ARM::t2ADR
1272 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1274 .addReg(MI->getOperand(0).getReg())
1275 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1276 // Add predicate operands.
1277 .addImm(MI->getOperand(3).getImm())
1278 .addReg(MI->getOperand(4).getReg()));
1281 // Darwin call instructions are just normal call instructions with different
1282 // clobber semantics (they clobber R9).
1283 case ARM::BX_CALL: {
1284 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1287 // Add predicate operands.
1290 // Add 's' bit operand (always reg0 for this)
1293 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1294 .addReg(MI->getOperand(0).getReg()));
1297 case ARM::tBX_CALL: {
1298 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1301 // Add predicate operands.
1305 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1306 .addReg(MI->getOperand(0).getReg())
1307 // Add predicate operands.
1312 case ARM::BMOVPCRX_CALL: {
1313 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1316 // Add predicate operands.
1319 // Add 's' bit operand (always reg0 for this)
1322 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1324 .addReg(MI->getOperand(0).getReg())
1325 // Add predicate operands.
1328 // Add 's' bit operand (always reg0 for this)
1332 case ARM::BMOVPCB_CALL: {
1333 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
1336 // Add predicate operands.
1339 // Add 's' bit operand (always reg0 for this)
1342 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1343 MCSymbol *GVSym = Mang->getSymbol(GV);
1344 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1345 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
1347 // Add predicate operands.
1352 case ARM::MOVi16_ga_pcrel:
1353 case ARM::t2MOVi16_ga_pcrel: {
1355 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1356 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1358 unsigned TF = MI->getOperand(1).getTargetFlags();
1359 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1360 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1361 MCSymbol *GVSym = GetARMGVSymbol(GV);
1362 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1364 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1365 getFunctionNumber(),
1366 MI->getOperand(2).getImm(), OutContext);
1367 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1368 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1369 const MCExpr *PCRelExpr =
1370 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1371 MCBinaryExpr::CreateAdd(LabelSymExpr,
1372 MCConstantExpr::Create(PCAdj, OutContext),
1373 OutContext), OutContext), OutContext);
1374 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1376 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1377 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1380 // Add predicate operands.
1381 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 // Add 's' bit operand (always reg0 for this)
1384 TmpInst.addOperand(MCOperand::CreateReg(0));
1385 OutStreamer.EmitInstruction(TmpInst);
1388 case ARM::MOVTi16_ga_pcrel:
1389 case ARM::t2MOVTi16_ga_pcrel: {
1391 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1392 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1393 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1394 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1396 unsigned TF = MI->getOperand(2).getTargetFlags();
1397 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1398 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1399 MCSymbol *GVSym = GetARMGVSymbol(GV);
1400 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1402 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1403 getFunctionNumber(),
1404 MI->getOperand(3).getImm(), OutContext);
1405 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1406 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1407 const MCExpr *PCRelExpr =
1408 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1409 MCBinaryExpr::CreateAdd(LabelSymExpr,
1410 MCConstantExpr::Create(PCAdj, OutContext),
1411 OutContext), OutContext), OutContext);
1412 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1414 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1415 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1417 // Add predicate operands.
1418 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1419 TmpInst.addOperand(MCOperand::CreateReg(0));
1420 // Add 's' bit operand (always reg0 for this)
1421 TmpInst.addOperand(MCOperand::CreateReg(0));
1422 OutStreamer.EmitInstruction(TmpInst);
1425 case ARM::tPICADD: {
1426 // This is a pseudo op for a label + instruction sequence, which looks like:
1429 // This adds the address of LPC0 to r0.
1432 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1433 getFunctionNumber(), MI->getOperand(2).getImm(),
1436 // Form and emit the add.
1437 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
1438 .addReg(MI->getOperand(0).getReg())
1439 .addReg(MI->getOperand(0).getReg())
1441 // Add predicate operands.
1447 // This is a pseudo op for a label + instruction sequence, which looks like:
1450 // This adds the address of LPC0 to r0.
1453 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1454 getFunctionNumber(), MI->getOperand(2).getImm(),
1457 // Form and emit the add.
1458 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1459 .addReg(MI->getOperand(0).getReg())
1461 .addReg(MI->getOperand(1).getReg())
1462 // Add predicate operands.
1463 .addImm(MI->getOperand(3).getImm())
1464 .addReg(MI->getOperand(4).getReg())
1465 // Add 's' bit operand (always reg0 for this)
1476 case ARM::PICLDRSH: {
1477 // This is a pseudo op for a label + instruction sequence, which looks like:
1480 // The LCP0 label is referenced by a constant pool entry in order to get
1481 // a PC-relative address at the ldr instruction.
1484 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1485 getFunctionNumber(), MI->getOperand(2).getImm(),
1488 // Form and emit the load
1490 switch (MI->getOpcode()) {
1492 llvm_unreachable("Unexpected opcode!");
1493 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1494 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1495 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1496 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1497 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1498 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1499 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1500 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1502 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
1503 .addReg(MI->getOperand(0).getReg())
1505 .addReg(MI->getOperand(1).getReg())
1507 // Add predicate operands.
1508 .addImm(MI->getOperand(3).getImm())
1509 .addReg(MI->getOperand(4).getReg()));
1513 case ARM::CONSTPOOL_ENTRY: {
1514 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1515 /// in the function. The first operand is the ID# for this instruction, the
1516 /// second is the index into the MachineConstantPool that this is, the third
1517 /// is the size in bytes of this constant pool entry.
1518 /// The required alignment is specified on the basic block holding this MI.
1519 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1520 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1522 // If this is the first entry of the pool, mark it.
1523 if (!InConstantPool) {
1524 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1525 InConstantPool = true;
1528 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1530 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1531 if (MCPE.isMachineConstantPoolEntry())
1532 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1534 EmitGlobalConstant(MCPE.Val.ConstVal);
1537 case ARM::t2BR_JT: {
1538 // Lower and emit the instruction itself, then the jump table following it.
1539 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1541 .addReg(MI->getOperand(0).getReg())
1542 // Add predicate operands.
1546 // Output the data for the jump table itself
1550 case ARM::t2TBB_JT: {
1551 // Lower and emit the instruction itself, then the jump table following it.
1552 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
1554 .addReg(MI->getOperand(0).getReg())
1555 // Add predicate operands.
1559 // Output the data for the jump table itself
1561 // Make sure the next instruction is 2-byte aligned.
1565 case ARM::t2TBH_JT: {
1566 // Lower and emit the instruction itself, then the jump table following it.
1567 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
1569 .addReg(MI->getOperand(0).getReg())
1570 // Add predicate operands.
1574 // Output the data for the jump table itself
1580 // Lower and emit the instruction itself, then the jump table following it.
1583 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1584 ARM::MOVr : ARM::tMOVr;
1585 TmpInst.setOpcode(Opc);
1586 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1587 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1588 // Add predicate operands.
1589 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1590 TmpInst.addOperand(MCOperand::CreateReg(0));
1591 // Add 's' bit operand (always reg0 for this)
1592 if (Opc == ARM::MOVr)
1593 TmpInst.addOperand(MCOperand::CreateReg(0));
1594 OutStreamer.EmitInstruction(TmpInst);
1596 // Make sure the Thumb jump table is 4-byte aligned.
1597 if (Opc == ARM::tMOVr)
1600 // Output the data for the jump table itself
1605 // Lower and emit the instruction itself, then the jump table following it.
1608 if (MI->getOperand(1).getReg() == 0) {
1610 TmpInst.setOpcode(ARM::LDRi12);
1611 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1612 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1613 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1615 TmpInst.setOpcode(ARM::LDRrs);
1616 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1617 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1618 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1619 TmpInst.addOperand(MCOperand::CreateImm(0));
1621 // Add predicate operands.
1622 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1623 TmpInst.addOperand(MCOperand::CreateReg(0));
1624 OutStreamer.EmitInstruction(TmpInst);
1626 // Output the data for the jump table itself
1630 case ARM::BR_JTadd: {
1631 // Lower and emit the instruction itself, then the jump table following it.
1632 // add pc, target, idx
1633 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
1635 .addReg(MI->getOperand(0).getReg())
1636 .addReg(MI->getOperand(1).getReg())
1637 // Add predicate operands.
1640 // Add 's' bit operand (always reg0 for this)
1643 // Output the data for the jump table itself
1648 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1649 // FIXME: Remove this special case when they do.
1650 if (!Subtarget->isTargetDarwin()) {
1651 //.long 0xe7ffdefe @ trap
1652 uint32_t Val = 0xe7ffdefeUL;
1653 OutStreamer.AddComment("trap");
1654 OutStreamer.EmitIntValue(Val, 4);
1659 case ARM::TRAPNaCl: {
1660 //.long 0xe7fedef0 @ trap
1661 uint32_t Val = 0xe7fedef0UL;
1662 OutStreamer.AddComment("trap");
1663 OutStreamer.EmitIntValue(Val, 4);
1667 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1668 // FIXME: Remove this special case when they do.
1669 if (!Subtarget->isTargetDarwin()) {
1670 //.short 57086 @ trap
1671 uint16_t Val = 0xdefe;
1672 OutStreamer.AddComment("trap");
1673 OutStreamer.EmitIntValue(Val, 2);
1678 case ARM::t2Int_eh_sjlj_setjmp:
1679 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1680 case ARM::tInt_eh_sjlj_setjmp: {
1681 // Two incoming args: GPR:$src, GPR:$val
1684 // str $val, [$src, #4]
1689 unsigned SrcReg = MI->getOperand(0).getReg();
1690 unsigned ValReg = MI->getOperand(1).getReg();
1691 MCSymbol *Label = GetARMSJLJEHLabel();
1692 OutStreamer.AddComment("eh_setjmp begin");
1693 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1700 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
1710 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
1713 // The offset immediate is #4. The operand value is scaled by 4 for the
1714 // tSTR instruction.
1720 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1728 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1729 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
1730 .addExpr(SymbolExpr)
1734 OutStreamer.AddComment("eh_setjmp end");
1735 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
1743 OutStreamer.EmitLabel(Label);
1747 case ARM::Int_eh_sjlj_setjmp_nofp:
1748 case ARM::Int_eh_sjlj_setjmp: {
1749 // Two incoming args: GPR:$src, GPR:$val
1751 // str $val, [$src, #+4]
1755 unsigned SrcReg = MI->getOperand(0).getReg();
1756 unsigned ValReg = MI->getOperand(1).getReg();
1758 OutStreamer.AddComment("eh_setjmp begin");
1759 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1766 // 's' bit operand (always reg0 for this).
1769 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
1777 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1783 // 's' bit operand (always reg0 for this).
1786 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
1793 // 's' bit operand (always reg0 for this).
1796 OutStreamer.AddComment("eh_setjmp end");
1797 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
1803 // 's' bit operand (always reg0 for this).
1807 case ARM::Int_eh_sjlj_longjmp: {
1808 // ldr sp, [$src, #8]
1809 // ldr $scratch, [$src, #4]
1812 unsigned SrcReg = MI->getOperand(0).getReg();
1813 unsigned ScratchReg = MI->getOperand(1).getReg();
1814 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1822 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1830 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
1838 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1845 case ARM::tInt_eh_sjlj_longjmp: {
1846 // ldr $scratch, [$src, #8]
1848 // ldr $scratch, [$src, #4]
1851 unsigned SrcReg = MI->getOperand(0).getReg();
1852 unsigned ScratchReg = MI->getOperand(1).getReg();
1853 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1856 // The offset immediate is #8. The operand value is scaled by 4 for the
1857 // tLDR instruction.
1863 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
1870 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1878 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
1886 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
1896 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1898 OutStreamer.EmitInstruction(TmpInst);
1901 //===----------------------------------------------------------------------===//
1902 // Target Registry Stuff
1903 //===----------------------------------------------------------------------===//
1905 // Force static initialization.
1906 extern "C" void LLVMInitializeARMAsmPrinter() {
1907 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1908 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);