1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
57 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
58 cl::desc("enable experimental asmprinter gunk in the arm backend"));
70 class ARMAsmPrinter : public AsmPrinter {
72 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
73 /// make the right decision when printing asm code for different targets.
74 const ARMSubtarget *Subtarget;
76 /// AFI - Keep a pointer to ARMFunctionInfo for the current
80 /// MCP - Keep a pointer to constantpool entries of the current
82 const MachineConstantPool *MCP;
85 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
86 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
87 Subtarget = &TM.getSubtarget<ARMSubtarget>();
90 virtual const char *getPassName() const {
91 return "ARM Assembly Printer";
94 void EmitJumpTable(const MachineInstr *MI);
95 void EmitJump2Table(const MachineInstr *MI);
96 void printInstructionThroughMCStreamer(const MachineInstr *MI);
99 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
100 const char *Modifier = 0);
101 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
102 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
104 void printSORegOperand(const MachineInstr *MI, int OpNum,
106 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
108 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
110 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
112 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
114 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
115 const char *Modifier = 0);
116 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
117 const char *Modifier = 0);
118 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
120 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
122 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
124 const char *Modifier = 0);
125 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
127 void printMemBOption(const MachineInstr *MI, int OpNum,
129 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
132 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
134 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
135 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
137 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
140 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
142 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
146 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
149 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
150 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
152 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
154 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
156 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
158 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
160 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
163 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
165 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
167 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
169 void printPredicateOperand(const MachineInstr *MI, int OpNum,
171 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
173 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
175 void printPCLabel(const MachineInstr *MI, int OpNum,
177 void printRegisterList(const MachineInstr *MI, int OpNum,
179 void printCPInstOperand(const MachineInstr *MI, int OpNum,
181 const char *Modifier);
182 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
184 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
186 void printTBAddrMode(const MachineInstr *MI, int OpNum,
188 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
190 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
192 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
194 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
197 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
198 unsigned AsmVariant, const char *ExtraCode,
200 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
202 const char *ExtraCode, raw_ostream &O);
204 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
205 static const char *getRegisterName(unsigned RegNo);
207 virtual void EmitInstruction(const MachineInstr *MI);
208 bool runOnMachineFunction(MachineFunction &F);
210 virtual void EmitConstantPool() {} // we emit constant pools customly!
211 virtual void EmitFunctionEntryLabel();
212 void EmitStartOfAsmFile(Module &M);
213 void EmitEndOfAsmFile(Module &M);
215 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
216 MachineLocation Location;
217 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
218 // Frame address. Currently handles register +- offset only.
219 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
220 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
222 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
227 virtual unsigned getISAEncoding() {
228 // ARM/Darwin adds ISA to the DWARF info for each function.
229 if (!Subtarget->isTargetDarwin())
231 return Subtarget->isThumb() ?
232 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
235 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
236 const MachineBasicBlock *MBB) const;
237 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
239 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
241 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
242 SmallString<128> Str;
243 raw_svector_ostream OS(Str);
244 EmitMachineConstantPoolValue(MCPV, OS);
245 OutStreamer.EmitRawText(OS.str());
248 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
250 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
251 case 1: O << MAI->getData8bitsDirective(0); break;
252 case 2: O << MAI->getData16bitsDirective(0); break;
253 case 4: O << MAI->getData32bitsDirective(0); break;
254 default: assert(0 && "Unknown CPV size");
257 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
259 if (ACPV->isLSDA()) {
260 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
261 } else if (ACPV->isBlockAddress()) {
262 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
263 } else if (ACPV->isGlobalValue()) {
264 const GlobalValue *GV = ACPV->getGV();
265 bool isIndirect = Subtarget->isTargetDarwin() &&
266 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
268 O << *Mang->getSymbol(GV);
270 // FIXME: Remove this when Darwin transition to @GOT like syntax.
271 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
274 MachineModuleInfoMachO &MMIMachO =
275 MMI->getObjFileInfo<MachineModuleInfoMachO>();
276 MachineModuleInfoImpl::StubValueTy &StubSym =
277 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
278 MMIMachO.getGVStubEntry(Sym);
279 if (StubSym.getPointer() == 0)
280 StubSym = MachineModuleInfoImpl::
281 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
284 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
285 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
288 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
289 if (ACPV->getPCAdjustment() != 0) {
290 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
291 << getFunctionNumber() << "_" << ACPV->getLabelId()
292 << "+" << (unsigned)ACPV->getPCAdjustment();
293 if (ACPV->mustAddCurrentAddress())
299 } // end of anonymous namespace
301 #include "ARMGenAsmWriter.inc"
303 void ARMAsmPrinter::EmitFunctionEntryLabel() {
304 if (AFI->isThumbFunction()) {
305 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
306 if (!Subtarget->isTargetDarwin())
307 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
309 // This needs to emit to a temporary string to get properly quoted
310 // MCSymbols when they have spaces in them.
311 SmallString<128> Tmp;
312 raw_svector_ostream OS(Tmp);
313 OS << "\t.thumb_func\t" << *CurrentFnSym;
314 OutStreamer.EmitRawText(OS.str());
318 OutStreamer.EmitLabel(CurrentFnSym);
321 /// runOnMachineFunction - This uses the printInstruction()
322 /// method to print assembly for each instruction.
324 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
325 AFI = MF.getInfo<ARMFunctionInfo>();
326 MCP = MF.getConstantPool();
328 return AsmPrinter::runOnMachineFunction(MF);
331 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
332 raw_ostream &O, const char *Modifier) {
333 const MachineOperand &MO = MI->getOperand(OpNum);
334 unsigned TF = MO.getTargetFlags();
336 switch (MO.getType()) {
338 assert(0 && "<unknown operand type>");
339 case MachineOperand::MO_Register: {
340 unsigned Reg = MO.getReg();
341 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
342 if (Modifier && strcmp(Modifier, "lane") == 0) {
343 unsigned RegNum = getARMRegisterNumbering(Reg);
345 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
346 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
347 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
349 assert(!MO.getSubReg() && "Subregs should be eliminated!");
350 O << getRegisterName(Reg);
354 case MachineOperand::MO_Immediate: {
355 int64_t Imm = MO.getImm();
357 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
358 (TF & ARMII::MO_LO16))
360 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
361 (TF & ARMII::MO_HI16))
366 case MachineOperand::MO_MachineBasicBlock:
367 O << *MO.getMBB()->getSymbol();
369 case MachineOperand::MO_GlobalAddress: {
370 bool isCallOp = Modifier && !strcmp(Modifier, "call");
371 const GlobalValue *GV = MO.getGlobal();
373 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
374 (TF & ARMII::MO_LO16))
376 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
377 (TF & ARMII::MO_HI16))
379 O << *Mang->getSymbol(GV);
381 printOffset(MO.getOffset(), O);
383 if (isCallOp && Subtarget->isTargetELF() &&
384 TM.getRelocationModel() == Reloc::PIC_)
388 case MachineOperand::MO_ExternalSymbol: {
389 bool isCallOp = Modifier && !strcmp(Modifier, "call");
390 O << *GetExternalSymbolSymbol(MO.getSymbolName());
392 if (isCallOp && Subtarget->isTargetELF() &&
393 TM.getRelocationModel() == Reloc::PIC_)
397 case MachineOperand::MO_ConstantPoolIndex:
398 O << *GetCPISymbol(MO.getIndex());
400 case MachineOperand::MO_JumpTableIndex:
401 O << *GetJTISymbol(MO.getIndex());
406 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
407 const MCAsmInfo *MAI) {
408 // Break it up into two parts that make up a shifter immediate.
409 V = ARM_AM::getSOImmVal(V);
410 assert(V != -1 && "Not a valid so_imm value!");
412 unsigned Imm = ARM_AM::getSOImmValImm(V);
413 unsigned Rot = ARM_AM::getSOImmValRot(V);
415 // Print low-level immediate formation info, per
416 // A5.1.3: "Data-processing operands - Immediate".
418 O << "#" << Imm << ", " << Rot;
419 // Pretty printed version.
421 O << "\t" << MAI->getCommentString() << ' ';
422 O << (int)ARM_AM::rotr32(Imm, Rot);
429 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
430 /// immediate in bits 0-7.
431 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
433 const MachineOperand &MO = MI->getOperand(OpNum);
434 assert(MO.isImm() && "Not a valid so_imm value!");
435 printSOImm(O, MO.getImm(), isVerbose(), MAI);
438 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
439 /// followed by an 'orr' to materialize.
440 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
442 const MachineOperand &MO = MI->getOperand(OpNum);
443 assert(MO.isImm() && "Not a valid so_imm value!");
444 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
445 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
446 printSOImm(O, V1, isVerbose(), MAI);
448 printPredicateOperand(MI, 2, O);
450 printOperand(MI, 0, O);
452 printOperand(MI, 0, O);
454 printSOImm(O, V2, isVerbose(), MAI);
457 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
458 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
460 // REG REG 0,SH_OPC - e.g. R5, ROR R3
461 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
462 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
464 const MachineOperand &MO1 = MI->getOperand(Op);
465 const MachineOperand &MO2 = MI->getOperand(Op+1);
466 const MachineOperand &MO3 = MI->getOperand(Op+2);
468 O << getRegisterName(MO1.getReg());
470 // Print the shift opc.
471 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
472 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
474 O << ' ' << getRegisterName(MO2.getReg());
475 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
476 } else if (ShOpc != ARM_AM::rrx) {
477 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
481 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
483 const MachineOperand &MO1 = MI->getOperand(Op);
484 const MachineOperand &MO2 = MI->getOperand(Op+1);
485 const MachineOperand &MO3 = MI->getOperand(Op+2);
487 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
488 printOperand(MI, Op, O);
492 O << "[" << getRegisterName(MO1.getReg());
495 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
497 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
498 << ARM_AM::getAM2Offset(MO3.getImm());
504 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
505 << getRegisterName(MO2.getReg());
507 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
509 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
514 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
516 const MachineOperand &MO1 = MI->getOperand(Op);
517 const MachineOperand &MO2 = MI->getOperand(Op+1);
520 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
522 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
527 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
528 << getRegisterName(MO1.getReg());
530 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
532 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
536 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
538 const MachineOperand &MO1 = MI->getOperand(Op);
539 const MachineOperand &MO2 = MI->getOperand(Op+1);
540 const MachineOperand &MO3 = MI->getOperand(Op+2);
542 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
543 O << "[" << getRegisterName(MO1.getReg());
547 << (char)ARM_AM::getAM3Op(MO3.getImm())
548 << getRegisterName(MO2.getReg())
553 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
555 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
560 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
562 const MachineOperand &MO1 = MI->getOperand(Op);
563 const MachineOperand &MO2 = MI->getOperand(Op+1);
566 O << (char)ARM_AM::getAM3Op(MO2.getImm())
567 << getRegisterName(MO1.getReg());
571 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
573 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
577 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
579 const char *Modifier) {
580 const MachineOperand &MO2 = MI->getOperand(Op+1);
581 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
582 if (Modifier && strcmp(Modifier, "submode") == 0) {
583 O << ARM_AM::getAMSubModeStr(Mode);
584 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
585 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
586 if (Mode == ARM_AM::ia)
589 printOperand(MI, Op, O);
593 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
595 const char *Modifier) {
596 const MachineOperand &MO1 = MI->getOperand(Op);
597 const MachineOperand &MO2 = MI->getOperand(Op+1);
599 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
600 printOperand(MI, Op, O);
604 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
606 O << "[" << getRegisterName(MO1.getReg());
608 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
610 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
616 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
618 const MachineOperand &MO1 = MI->getOperand(Op);
619 const MachineOperand &MO2 = MI->getOperand(Op+1);
621 O << "[" << getRegisterName(MO1.getReg());
623 // FIXME: Both darwin as and GNU as violate ARM docs here.
624 O << ", :" << (MO2.getImm() << 3);
629 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
631 const MachineOperand &MO = MI->getOperand(Op);
632 if (MO.getReg() == 0)
635 O << ", " << getRegisterName(MO.getReg());
638 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
640 const char *Modifier) {
641 if (Modifier && strcmp(Modifier, "label") == 0) {
642 printPCLabel(MI, Op+1, O);
646 const MachineOperand &MO1 = MI->getOperand(Op);
647 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
648 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
652 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
654 const MachineOperand &MO = MI->getOperand(Op);
655 uint32_t v = ~MO.getImm();
656 int32_t lsb = CountTrailingZeros_32(v);
657 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
658 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
659 O << "#" << lsb << ", #" << width;
663 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
665 unsigned val = MI->getOperand(OpNum).getImm();
666 O << ARM_MB::MemBOptToString(val);
669 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
671 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
672 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
674 case ARM_AM::no_shift:
683 assert(0 && "unexpected shift opcode for shift immediate operand");
685 O << ARM_AM::getSORegOffset(ShiftOp);
688 //===--------------------------------------------------------------------===//
690 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
692 O << "#" << MI->getOperand(Op).getImm() * 4;
696 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
698 // (3 - the number of trailing zeros) is the number of then / else.
699 unsigned Mask = MI->getOperand(Op).getImm();
700 unsigned CondBit0 = Mask >> 4 & 1;
701 unsigned NumTZ = CountTrailingZeros_32(Mask);
702 assert(NumTZ <= 3 && "Invalid IT mask!");
703 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
704 bool T = ((Mask >> Pos) & 1) == CondBit0;
713 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
715 const MachineOperand &MO1 = MI->getOperand(Op);
716 const MachineOperand &MO2 = MI->getOperand(Op+1);
717 O << "[" << getRegisterName(MO1.getReg());
718 O << ", " << getRegisterName(MO2.getReg()) << "]";
722 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
725 const MachineOperand &MO1 = MI->getOperand(Op);
726 const MachineOperand &MO2 = MI->getOperand(Op+1);
727 const MachineOperand &MO3 = MI->getOperand(Op+2);
729 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
730 printOperand(MI, Op, O);
734 O << "[" << getRegisterName(MO1.getReg());
736 O << ", " << getRegisterName(MO3.getReg());
737 else if (unsigned ImmOffs = MO2.getImm())
738 O << ", #" << ImmOffs * Scale;
743 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
745 printThumbAddrModeRI5Operand(MI, Op, O, 1);
748 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
750 printThumbAddrModeRI5Operand(MI, Op, O, 2);
753 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
755 printThumbAddrModeRI5Operand(MI, Op, O, 4);
758 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
760 const MachineOperand &MO1 = MI->getOperand(Op);
761 const MachineOperand &MO2 = MI->getOperand(Op+1);
762 O << "[" << getRegisterName(MO1.getReg());
763 if (unsigned ImmOffs = MO2.getImm())
764 O << ", #" << ImmOffs*4;
768 //===--------------------------------------------------------------------===//
770 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
771 // register with shift forms.
773 // REG IMM, SH_OPC - e.g. R5, LSL #3
774 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
776 const MachineOperand &MO1 = MI->getOperand(OpNum);
777 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
779 unsigned Reg = MO1.getReg();
780 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
781 O << getRegisterName(Reg);
783 // Print the shift opc.
784 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
785 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
786 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
787 if (ShOpc != ARM_AM::rrx)
788 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
791 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
794 const MachineOperand &MO1 = MI->getOperand(OpNum);
795 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
797 O << "[" << getRegisterName(MO1.getReg());
799 unsigned OffImm = MO2.getImm();
800 if (OffImm) // Don't print +0.
801 O << ", #" << OffImm;
805 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
808 const MachineOperand &MO1 = MI->getOperand(OpNum);
809 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
811 O << "[" << getRegisterName(MO1.getReg());
813 int32_t OffImm = (int32_t)MO2.getImm();
816 O << ", #-" << -OffImm;
818 O << ", #" << OffImm;
822 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
825 const MachineOperand &MO1 = MI->getOperand(OpNum);
826 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
828 O << "[" << getRegisterName(MO1.getReg());
830 int32_t OffImm = (int32_t)MO2.getImm() / 4;
833 O << ", #-" << -OffImm * 4;
835 O << ", #" << OffImm * 4;
839 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
842 const MachineOperand &MO1 = MI->getOperand(OpNum);
843 int32_t OffImm = (int32_t)MO1.getImm();
846 O << "#-" << -OffImm;
851 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
854 const MachineOperand &MO1 = MI->getOperand(OpNum);
855 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
856 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
858 O << "[" << getRegisterName(MO1.getReg());
860 assert(MO2.getReg() && "Invalid so_reg load / store address!");
861 O << ", " << getRegisterName(MO2.getReg());
863 unsigned ShAmt = MO3.getImm();
865 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
866 O << ", lsl #" << ShAmt;
872 //===--------------------------------------------------------------------===//
874 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
876 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
878 O << ARMCondCodeToString(CC);
881 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
884 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
885 O << ARMCondCodeToString(CC);
888 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
890 unsigned Reg = MI->getOperand(OpNum).getReg();
892 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
897 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
899 int Id = (int)MI->getOperand(OpNum).getImm();
900 O << MAI->getPrivateGlobalPrefix()
901 << "PC" << getFunctionNumber() << "_" << Id;
904 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
907 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
908 if (MI->getOperand(i).isImplicit())
910 if ((int)i != OpNum) O << ", ";
911 printOperand(MI, i, O);
916 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
917 raw_ostream &O, const char *Modifier) {
918 assert(Modifier && "This operand only works with a modifier!");
919 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
921 if (!strcmp(Modifier, "label")) {
922 unsigned ID = MI->getOperand(OpNum).getImm();
923 OutStreamer.EmitLabel(GetCPISymbol(ID));
925 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
926 unsigned CPI = MI->getOperand(OpNum).getIndex();
928 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
930 if (MCPE.isMachineConstantPoolEntry()) {
931 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
933 EmitGlobalConstant(MCPE.Val.ConstVal);
938 MCSymbol *ARMAsmPrinter::
939 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
940 const MachineBasicBlock *MBB) const {
941 SmallString<60> Name;
942 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
943 << getFunctionNumber() << '_' << uid << '_' << uid2
944 << "_set_" << MBB->getNumber();
945 return OutContext.GetOrCreateSymbol(Name.str());
948 MCSymbol *ARMAsmPrinter::
949 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
950 SmallString<60> Name;
951 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
952 << getFunctionNumber() << '_' << uid << '_' << uid2;
953 return OutContext.GetOrCreateSymbol(Name.str());
956 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
958 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
960 const MachineOperand &MO1 = MI->getOperand(OpNum);
961 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
963 unsigned JTI = MO1.getIndex();
964 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
965 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
967 O << "\n" << *JTISymbol << ":\n";
969 const char *JTEntryDirective = MAI->getData32bitsDirective();
971 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
972 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
973 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
974 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
975 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
976 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
977 MachineBasicBlock *MBB = JTBBs[i];
978 bool isNew = JTSets.insert(MBB);
980 if (UseSet && isNew) {
982 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
983 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
986 O << JTEntryDirective << ' ';
988 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
989 else if (TM.getRelocationModel() == Reloc::PIC_)
990 O << *MBB->getSymbol() << '-' << *JTISymbol;
992 O << *MBB->getSymbol();
999 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
1001 const MachineOperand &MO1 = MI->getOperand(OpNum);
1002 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1003 unsigned JTI = MO1.getIndex();
1005 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1007 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
1009 O << "\n" << *JTISymbol << ":\n";
1011 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1012 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1013 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1014 bool ByteOffset = false, HalfWordOffset = false;
1015 if (MI->getOpcode() == ARM::t2TBB)
1017 else if (MI->getOpcode() == ARM::t2TBH)
1018 HalfWordOffset = true;
1020 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1021 MachineBasicBlock *MBB = JTBBs[i];
1023 O << MAI->getData8bitsDirective();
1024 else if (HalfWordOffset)
1025 O << MAI->getData16bitsDirective();
1027 if (ByteOffset || HalfWordOffset)
1028 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1030 O << "\tb.w " << *MBB->getSymbol();
1037 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1039 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1040 if (MI->getOpcode() == ARM::t2TBH)
1045 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1047 O << MI->getOperand(OpNum).getImm();
1050 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1052 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1053 O << '#' << FP->getValueAPF().convertToFloat();
1055 O << "\t\t" << MAI->getCommentString() << ' ';
1056 WriteAsOperand(O, FP, /*PrintType=*/false);
1060 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1062 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1063 O << '#' << FP->getValueAPF().convertToDouble();
1065 O << "\t\t" << MAI->getCommentString() << ' ';
1066 WriteAsOperand(O, FP, /*PrintType=*/false);
1070 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1072 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1074 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1075 O << "#0x" << utohexstr(Val);
1078 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1079 unsigned AsmVariant, const char *ExtraCode,
1081 // Does this asm operand have a single letter operand modifier?
1082 if (ExtraCode && ExtraCode[0]) {
1083 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1085 switch (ExtraCode[0]) {
1086 default: return true; // Unknown modifier.
1087 case 'a': // Print as a memory address.
1088 if (MI->getOperand(OpNum).isReg()) {
1089 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1093 case 'c': // Don't print "#" before an immediate operand.
1094 if (!MI->getOperand(OpNum).isImm())
1096 printNoHashImmediate(MI, OpNum, O);
1098 case 'P': // Print a VFP double precision register.
1099 case 'q': // Print a NEON quad precision register.
1100 printOperand(MI, OpNum, O);
1105 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1110 printOperand(MI, OpNum, O);
1114 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1115 unsigned OpNum, unsigned AsmVariant,
1116 const char *ExtraCode,
1118 if (ExtraCode && ExtraCode[0])
1119 return true; // Unknown modifier.
1121 const MachineOperand &MO = MI->getOperand(OpNum);
1122 assert(MO.isReg() && "unexpected inline asm memory operand");
1123 O << "[" << getRegisterName(MO.getReg()) << "]";
1127 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1129 printInstructionThroughMCStreamer(MI);
1133 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1136 SmallString<128> Str;
1137 raw_svector_ostream OS(Str);
1138 if (MI->getOpcode() == ARM::DBG_VALUE) {
1139 unsigned NOps = MI->getNumOperands();
1141 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1142 // cast away const; DIetc do not take const operands for some reason.
1143 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1146 // Frame address. Currently handles register +- offset only.
1147 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1148 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1151 printOperand(MI, NOps-2, OS);
1152 } else if (MI->getOpcode() == ARM::MOVs) {
1153 // FIXME: Thumb variants?
1154 const MachineOperand &Dst = MI->getOperand(0);
1155 const MachineOperand &MO1 = MI->getOperand(1);
1156 const MachineOperand &MO2 = MI->getOperand(2);
1157 const MachineOperand &MO3 = MI->getOperand(3);
1159 OS << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
1160 printSBitModifierOperand(MI, 6, OS);
1161 printPredicateOperand(MI, 4, OS);
1163 OS << '\t' << getRegisterName(Dst.getReg())
1164 << ", " << getRegisterName(MO1.getReg());
1166 if (ARM_AM::getSORegShOp(MO3.getImm()) != ARM_AM::rrx) {
1170 OS << getRegisterName(MO2.getReg());
1171 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
1173 OS << "#" << ARM_AM::getSORegOffset(MO3.getImm());
1178 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
1179 MI->getOperand(0).getReg() == ARM::SP &&
1180 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
1181 OS << '\t' << "push";
1182 printPredicateOperand(MI, 3, OS);
1184 printRegisterList(MI, 5, OS);
1187 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
1188 MI->getOperand(0).getReg() == ARM::SP &&
1189 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
1190 OS << '\t' << "pop";
1191 printPredicateOperand(MI, 3, OS);
1193 printRegisterList(MI, 5, OS);
1196 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
1197 MI->getOperand(0).getReg() == ARM::SP &&
1198 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
1199 OS << '\t' << "vpush";
1200 printPredicateOperand(MI, 3, OS);
1202 printRegisterList(MI, 5, OS);
1205 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
1206 MI->getOperand(0).getReg() == ARM::SP &&
1207 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
1208 OS << '\t' << "vpop";
1209 printPredicateOperand(MI, 3, OS);
1211 printRegisterList(MI, 5, OS);
1213 // TRAP and tTRAP need special handling for non-Darwin. The GNU binutils
1214 // don't (yet) support the 'trap' mnemonic. (Use decimal, not hex, to
1215 // be consistent with the MC instruction printer.)
1216 // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
1217 // Need a way to ask "isTargetDarwin()" there, first, though.
1218 if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
1219 OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
1220 } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
1221 OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
1223 printInstruction(MI, OS);
1225 // Output the instruction to the stream
1226 OutStreamer.EmitRawText(OS.str());
1228 // Make sure the instruction that follows TBB is 2-byte aligned.
1229 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1230 if (MI->getOpcode() == ARM::t2TBB)
1234 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1235 if (Subtarget->isTargetDarwin()) {
1236 Reloc::Model RelocM = TM.getRelocationModel();
1237 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1238 // Declare all the text sections up front (before the DWARF sections
1239 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1240 // them together at the beginning of the object file. This helps
1241 // avoid out-of-range branches that are due a fundamental limitation of
1242 // the way symbol offsets are encoded with the current Darwin ARM
1244 const TargetLoweringObjectFileMachO &TLOFMacho =
1245 static_cast<const TargetLoweringObjectFileMachO &>(
1246 getObjFileLowering());
1247 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1248 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1249 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1250 if (RelocM == Reloc::DynamicNoPIC) {
1251 const MCSection *sect =
1252 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1253 MCSectionMachO::S_SYMBOL_STUBS,
1254 12, SectionKind::getText());
1255 OutStreamer.SwitchSection(sect);
1257 const MCSection *sect =
1258 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1259 MCSectionMachO::S_SYMBOL_STUBS,
1260 16, SectionKind::getText());
1261 OutStreamer.SwitchSection(sect);
1263 const MCSection *StaticInitSect =
1264 OutContext.getMachOSection("__TEXT", "__StaticInit",
1265 MCSectionMachO::S_REGULAR |
1266 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1267 SectionKind::getText());
1268 OutStreamer.SwitchSection(StaticInitSect);
1272 // Use unified assembler syntax.
1273 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1275 // Emit ARM Build Attributes
1276 if (Subtarget->isTargetELF()) {
1278 std::string CPUString = Subtarget->getCPUString();
1279 if (CPUString != "generic")
1280 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1282 // FIXME: Emit FPU type
1283 if (Subtarget->hasVFP2())
1284 OutStreamer.EmitRawText("\t.eabi_attribute " +
1285 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1287 // Signal various FP modes.
1288 if (!UnsafeFPMath) {
1289 OutStreamer.EmitRawText("\t.eabi_attribute " +
1290 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1291 OutStreamer.EmitRawText("\t.eabi_attribute " +
1292 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1295 if (NoInfsFPMath && NoNaNsFPMath)
1296 OutStreamer.EmitRawText("\t.eabi_attribute " +
1297 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1299 OutStreamer.EmitRawText("\t.eabi_attribute " +
1300 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1302 // 8-bytes alignment stuff.
1303 OutStreamer.EmitRawText("\t.eabi_attribute " +
1304 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1305 OutStreamer.EmitRawText("\t.eabi_attribute " +
1306 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1308 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1309 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1310 OutStreamer.EmitRawText("\t.eabi_attribute " +
1311 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1312 OutStreamer.EmitRawText("\t.eabi_attribute " +
1313 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1315 // FIXME: Should we signal R9 usage?
1320 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1321 if (Subtarget->isTargetDarwin()) {
1322 // All darwin targets use mach-o.
1323 const TargetLoweringObjectFileMachO &TLOFMacho =
1324 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1325 MachineModuleInfoMachO &MMIMacho =
1326 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1328 // Output non-lazy-pointers for external and common global variables.
1329 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1331 if (!Stubs.empty()) {
1332 // Switch with ".non_lazy_symbol_pointer" directive.
1333 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1335 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1337 OutStreamer.EmitLabel(Stubs[i].first);
1338 // .indirect_symbol _foo
1339 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1340 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1343 // External to current translation unit.
1344 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1346 // Internal to current translation unit.
1348 // When we place the LSDA into the TEXT section, the type info
1349 // pointers need to be indirect and pc-rel. We accomplish this by
1350 // using NLPs; however, sometimes the types are local to the file.
1351 // We need to fill in the value for the NLP in those cases.
1352 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1354 4/*size*/, 0/*addrspace*/);
1358 OutStreamer.AddBlankLine();
1361 Stubs = MMIMacho.GetHiddenGVStubList();
1362 if (!Stubs.empty()) {
1363 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1365 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1367 OutStreamer.EmitLabel(Stubs[i].first);
1369 OutStreamer.EmitValue(MCSymbolRefExpr::
1370 Create(Stubs[i].second.getPointer(),
1372 4/*size*/, 0/*addrspace*/);
1376 OutStreamer.AddBlankLine();
1379 // Funny Darwin hack: This flag tells the linker that no global symbols
1380 // contain code that falls through to other global symbols (e.g. the obvious
1381 // implementation of multiple entry points). If this doesn't occur, the
1382 // linker can safely perform dead code stripping. Since LLVM never
1383 // generates code that does this, it is always safe to set.
1384 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1388 //===----------------------------------------------------------------------===//
1390 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
1391 unsigned LabelId, MCContext &Ctx) {
1393 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
1394 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
1398 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
1399 unsigned Opcode = MI->getOpcode();
1401 if (Opcode == ARM::BR_JTadd)
1403 else if (Opcode == ARM::BR_JTm)
1406 const MachineOperand &MO1 = MI->getOperand(OpNum);
1407 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1408 unsigned JTI = MO1.getIndex();
1410 // Emit a label for the jump table.
1411 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1412 OutStreamer.EmitLabel(JTISymbol);
1414 // Emit each entry of the table.
1415 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1416 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1417 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1419 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1420 MachineBasicBlock *MBB = JTBBs[i];
1421 // Construct an MCExpr for the entry. We want a value of the form:
1422 // (BasicBlockAddr - TableBeginAddr)
1424 // For example, a table with entries jumping to basic blocks BB0 and BB1
1427 // .word (LBB0 - LJTI_0_0)
1428 // .word (LBB1 - LJTI_0_0)
1429 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1431 if (TM.getRelocationModel() == Reloc::PIC_)
1432 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1435 OutStreamer.EmitValue(Expr, 4);
1439 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1440 unsigned Opcode = MI->getOpcode();
1441 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1442 const MachineOperand &MO1 = MI->getOperand(OpNum);
1443 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1444 unsigned JTI = MO1.getIndex();
1446 // Emit a label for the jump table.
1447 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1448 OutStreamer.EmitLabel(JTISymbol);
1450 // Emit each entry of the table.
1451 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1452 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1453 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1454 unsigned OffsetWidth = 4;
1455 if (MI->getOpcode() == ARM::t2TBB)
1457 else if (MI->getOpcode() == ARM::t2TBH)
1460 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1461 MachineBasicBlock *MBB = JTBBs[i];
1462 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1464 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1465 if (OffsetWidth == 4) {
1467 BrInst.setOpcode(ARM::t2B);
1468 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1469 OutStreamer.EmitInstruction(BrInst);
1472 // Otherwise it's an offset from the dispatch instruction. Construct an
1473 // MCExpr for the entry. We want a value of the form:
1474 // (BasicBlockAddr - TableBeginAddr) / 2
1476 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1479 // .byte (LBB0 - LJTI_0_0) / 2
1480 // .byte (LBB1 - LJTI_0_0) / 2
1481 const MCExpr *Expr =
1482 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1483 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1485 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1487 OutStreamer.EmitValue(Expr, OffsetWidth);
1490 // Make sure the instruction that follows TBB is 2-byte aligned.
1491 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1492 if (MI->getOpcode() == ARM::t2TBB)
1496 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1497 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1498 switch (MI->getOpcode()) {
1499 case ARM::t2MOVi32imm:
1500 assert(0 && "Should be lowered by thumb2it pass");
1502 case ARM::tPICADD: {
1503 // This is a pseudo op for a label + instruction sequence, which looks like:
1506 // This adds the address of LPC0 to r0.
1509 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1510 getFunctionNumber(), MI->getOperand(2).getImm(),
1513 // Form and emit the add.
1515 AddInst.setOpcode(ARM::tADDhirr);
1516 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1517 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1518 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1519 // Add predicate operands.
1520 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1521 AddInst.addOperand(MCOperand::CreateReg(0));
1522 OutStreamer.EmitInstruction(AddInst);
1525 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1526 // This is a pseudo op for a label + instruction sequence, which looks like:
1529 // This adds the address of LPC0 to r0.
1532 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1533 getFunctionNumber(), MI->getOperand(2).getImm(),
1536 // Form and emit the add.
1538 AddInst.setOpcode(ARM::ADDrr);
1539 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1540 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1541 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1542 // Add predicate operands.
1543 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1544 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1545 // Add 's' bit operand (always reg0 for this)
1546 AddInst.addOperand(MCOperand::CreateReg(0));
1547 OutStreamer.EmitInstruction(AddInst);
1557 case ARM::PICLDRSH: {
1558 // This is a pseudo op for a label + instruction sequence, which looks like:
1561 // The LCP0 label is referenced by a constant pool entry in order to get
1562 // a PC-relative address at the ldr instruction.
1565 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1566 getFunctionNumber(), MI->getOperand(2).getImm(),
1569 // Form and emit the load
1571 switch (MI->getOpcode()) {
1573 llvm_unreachable("Unexpected opcode!");
1574 case ARM::PICSTR: Opcode = ARM::STR; break;
1575 case ARM::PICSTRB: Opcode = ARM::STRB; break;
1576 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1577 case ARM::PICLDR: Opcode = ARM::LDR; break;
1578 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
1579 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1580 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1581 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1584 LdStInst.setOpcode(Opcode);
1585 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1586 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1587 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1588 LdStInst.addOperand(MCOperand::CreateImm(0));
1589 // Add predicate operands.
1590 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1591 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1592 OutStreamer.EmitInstruction(LdStInst);
1596 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1597 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1598 /// in the function. The first operand is the ID# for this instruction, the
1599 /// second is the index into the MachineConstantPool that this is, the third
1600 /// is the size in bytes of this constant pool entry.
1601 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1602 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1605 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1607 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1608 if (MCPE.isMachineConstantPoolEntry())
1609 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1611 EmitGlobalConstant(MCPE.Val.ConstVal);
1615 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1616 // This is a hack that lowers as a two instruction sequence.
1617 unsigned DstReg = MI->getOperand(0).getReg();
1618 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1620 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1621 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1625 TmpInst.setOpcode(ARM::MOVi);
1626 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1627 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1630 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1631 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1633 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1634 OutStreamer.EmitInstruction(TmpInst);
1639 TmpInst.setOpcode(ARM::ORRri);
1640 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1641 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1642 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1644 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1645 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1647 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1648 OutStreamer.EmitInstruction(TmpInst);
1652 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1653 // This is a hack that lowers as a two instruction sequence.
1654 unsigned DstReg = MI->getOperand(0).getReg();
1655 const MachineOperand &MO = MI->getOperand(1);
1658 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1659 V1 = MCOperand::CreateImm(ImmVal & 65535);
1660 V2 = MCOperand::CreateImm(ImmVal >> 16);
1661 } else if (MO.isGlobal()) {
1662 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
1663 const MCSymbolRefExpr *SymRef1 =
1664 MCSymbolRefExpr::Create(Symbol,
1665 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1666 const MCSymbolRefExpr *SymRef2 =
1667 MCSymbolRefExpr::Create(Symbol,
1668 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1669 V1 = MCOperand::CreateExpr(SymRef1);
1670 V2 = MCOperand::CreateExpr(SymRef2);
1672 // FIXME: External symbol?
1674 llvm_unreachable("cannot handle this operand");
1679 TmpInst.setOpcode(ARM::MOVi16);
1680 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1681 TmpInst.addOperand(V1); // lower16(imm)
1684 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1685 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1687 OutStreamer.EmitInstruction(TmpInst);
1692 TmpInst.setOpcode(ARM::MOVTi16);
1693 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1694 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1695 TmpInst.addOperand(V2); // upper16(imm)
1698 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1699 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1701 OutStreamer.EmitInstruction(TmpInst);
1708 case ARM::t2BR_JT: {
1709 // Lower and emit the instruction itself, then the jump table following it.
1711 MCInstLowering.Lower(MI, TmpInst);
1712 OutStreamer.EmitInstruction(TmpInst);
1719 case ARM::BR_JTadd: {
1720 // Lower and emit the instruction itself, then the jump table following it.
1722 MCInstLowering.Lower(MI, TmpInst);
1723 OutStreamer.EmitInstruction(TmpInst);
1728 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1729 // FIXME: Remove this special case when they do.
1730 if (!Subtarget->isTargetDarwin()) {
1731 //.long 0xe7ffdefe ${:comment} trap
1732 uint32_t Val = 0xe7ffdefeeUL;
1733 OutStreamer.AddComment("trap");
1734 OutStreamer.EmitIntValue(Val, 4);
1740 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1741 // FIXME: Remove this special case when they do.
1742 if (!Subtarget->isTargetDarwin()) {
1743 //.short 57086 ${:comment} trap
1744 uint16_t Val = 0xdefe;
1745 OutStreamer.AddComment("trap");
1746 OutStreamer.EmitIntValue(Val, 2);
1754 MCInstLowering.Lower(MI, TmpInst);
1755 OutStreamer.EmitInstruction(TmpInst);
1758 //===----------------------------------------------------------------------===//
1759 // Target Registry Stuff
1760 //===----------------------------------------------------------------------===//
1762 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1763 unsigned SyntaxVariant,
1764 const MCAsmInfo &MAI) {
1765 if (SyntaxVariant == 0)
1766 return new ARMInstPrinter(MAI);
1770 // Force static initialization.
1771 extern "C" void LLVMInitializeARMAsmPrinter() {
1772 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1773 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1775 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1776 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);