1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
21 #include "InstPrinter/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DebugInfo.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCSectionMachO.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/ARMBuildAttributes.h"
46 #include "llvm/Support/TargetParser.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
61 std::unique_ptr<MCStreamer> Streamer)
62 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
63 InConstantPool(false) {}
65 void ARMAsmPrinter::EmitFunctionBodyEnd() {
66 // Make sure to terminate any constant pools that were at the end
70 InConstantPool = false;
71 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
74 void ARMAsmPrinter::EmitFunctionEntryLabel() {
75 if (AFI->isThumbFunction()) {
76 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
77 OutStreamer->EmitThumbFunc(CurrentFnSym);
80 OutStreamer->EmitLabel(CurrentFnSym);
83 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
84 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!");
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!");
90 const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
97 OutStreamer->EmitValue(E, Size);
100 /// runOnMachineFunction - This uses the EmitInstruction()
101 /// method to print assembly for each instruction.
103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
104 AFI = MF.getInfo<ARMFunctionInfo>();
105 MCP = MF.getConstantPool();
106 Subtarget = &MF.getSubtarget<ARMSubtarget>();
108 SetupMachineFunction(MF);
110 if (Subtarget->isTargetCOFF()) {
111 bool Internal = MF.getFunction()->hasInternalLinkage();
112 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
113 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
114 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
116 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
117 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
118 OutStreamer->EmitCOFFSymbolType(Type);
119 OutStreamer->EndCOFFSymbolDef();
122 // Emit the rest of the function body.
125 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
126 // These are created per function, rather than per TU, since it's
127 // relatively easy to exceed the thumb branch range within a TU.
128 if (! ThumbIndirectPads.empty()) {
129 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
131 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
132 OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
133 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
134 .addReg(ThumbIndirectPads[i].first)
135 // Add predicate operands.
139 ThumbIndirectPads.clear();
142 // We didn't modify anything.
146 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
148 const MachineOperand &MO = MI->getOperand(OpNum);
149 unsigned TF = MO.getTargetFlags();
151 switch (MO.getType()) {
152 default: llvm_unreachable("<unknown operand type>");
153 case MachineOperand::MO_Register: {
154 unsigned Reg = MO.getReg();
155 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
156 assert(!MO.getSubReg() && "Subregs should be eliminated!");
157 if(ARM::GPRPairRegClass.contains(Reg)) {
158 const MachineFunction &MF = *MI->getParent()->getParent();
159 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
160 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
162 O << ARMInstPrinter::getRegisterName(Reg);
165 case MachineOperand::MO_Immediate: {
166 int64_t Imm = MO.getImm();
168 if (TF == ARMII::MO_LO16)
170 else if (TF == ARMII::MO_HI16)
175 case MachineOperand::MO_MachineBasicBlock:
176 O << *MO.getMBB()->getSymbol();
178 case MachineOperand::MO_GlobalAddress: {
179 const GlobalValue *GV = MO.getGlobal();
180 if (TF & ARMII::MO_LO16)
182 else if (TF & ARMII::MO_HI16)
184 O << *GetARMGVSymbol(GV, TF);
186 printOffset(MO.getOffset(), O);
187 if (TF == ARMII::MO_PLT)
191 case MachineOperand::MO_ConstantPoolIndex:
192 O << *GetCPISymbol(MO.getIndex());
197 //===--------------------------------------------------------------------===//
199 MCSymbol *ARMAsmPrinter::
200 GetARMJTIPICJumpTableLabel(unsigned uid) const {
201 const DataLayout *DL = TM.getDataLayout();
202 SmallString<60> Name;
203 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
204 << getFunctionNumber() << '_' << uid;
205 return OutContext.getOrCreateSymbol(Name);
209 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
210 const DataLayout *DL = TM.getDataLayout();
211 SmallString<60> Name;
212 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
213 << getFunctionNumber();
214 return OutContext.getOrCreateSymbol(Name);
217 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
218 unsigned AsmVariant, const char *ExtraCode,
220 // Does this asm operand have a single letter operand modifier?
221 if (ExtraCode && ExtraCode[0]) {
222 if (ExtraCode[1] != 0) return true; // Unknown modifier.
224 switch (ExtraCode[0]) {
226 // See if this is a generic print operand
227 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
228 case 'a': // Print as a memory address.
229 if (MI->getOperand(OpNum).isReg()) {
231 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
236 case 'c': // Don't print "#" before an immediate operand.
237 if (!MI->getOperand(OpNum).isImm())
239 O << MI->getOperand(OpNum).getImm();
241 case 'P': // Print a VFP double precision register.
242 case 'q': // Print a NEON quad precision register.
243 printOperand(MI, OpNum, O);
245 case 'y': // Print a VFP single precision register as indexed double.
246 if (MI->getOperand(OpNum).isReg()) {
247 unsigned Reg = MI->getOperand(OpNum).getReg();
248 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
249 // Find the 'd' register that has this 's' register as a sub-register,
250 // and determine the lane number.
251 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
252 if (!ARM::DPRRegClass.contains(*SR))
254 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
255 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
260 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
261 if (!MI->getOperand(OpNum).isImm())
263 O << ~(MI->getOperand(OpNum).getImm());
265 case 'L': // The low 16 bits of an immediate constant.
266 if (!MI->getOperand(OpNum).isImm())
268 O << (MI->getOperand(OpNum).getImm() & 0xffff);
270 case 'M': { // A register range suitable for LDM/STM.
271 if (!MI->getOperand(OpNum).isReg())
273 const MachineOperand &MO = MI->getOperand(OpNum);
274 unsigned RegBegin = MO.getReg();
275 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
276 // already got the operands in registers that are operands to the
277 // inline asm statement.
279 if (ARM::GPRPairRegClass.contains(RegBegin)) {
280 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
281 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
282 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
283 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
285 O << ARMInstPrinter::getRegisterName(RegBegin);
287 // FIXME: The register allocator not only may not have given us the
288 // registers in sequence, but may not be in ascending registers. This
289 // will require changes in the register allocator that'll need to be
290 // propagated down here if the operands change.
291 unsigned RegOps = OpNum + 1;
292 while (MI->getOperand(RegOps).isReg()) {
294 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
302 case 'R': // The most significant register of a pair.
303 case 'Q': { // The least significant register of a pair.
306 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
307 if (!FlagsOP.isImm())
309 unsigned Flags = FlagsOP.getImm();
311 // This operand may not be the one that actually provides the register. If
312 // it's tied to a previous one then we should refer instead to that one
313 // for registers and their classes.
315 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
316 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
317 unsigned OpFlags = MI->getOperand(OpNum).getImm();
318 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
320 Flags = MI->getOperand(OpNum).getImm();
322 // Later code expects OpNum to be pointing at the register rather than
327 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
329 InlineAsm::hasRegClassConstraint(Flags, RC);
330 if (RC == ARM::GPRPairRegClassID) {
333 const MachineOperand &MO = MI->getOperand(OpNum);
336 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
337 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
338 ARM::gsub_0 : ARM::gsub_1);
339 O << ARMInstPrinter::getRegisterName(Reg);
344 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
345 if (RegOp >= MI->getNumOperands())
347 const MachineOperand &MO = MI->getOperand(RegOp);
350 unsigned Reg = MO.getReg();
351 O << ARMInstPrinter::getRegisterName(Reg);
355 case 'e': // The low doubleword register of a NEON quad register.
356 case 'f': { // The high doubleword register of a NEON quad register.
357 if (!MI->getOperand(OpNum).isReg())
359 unsigned Reg = MI->getOperand(OpNum).getReg();
360 if (!ARM::QPRRegClass.contains(Reg))
362 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
363 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
364 ARM::dsub_0 : ARM::dsub_1);
365 O << ARMInstPrinter::getRegisterName(SubReg);
369 // This modifier is not yet supported.
370 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
372 case 'H': { // The highest-numbered register of a pair.
373 const MachineOperand &MO = MI->getOperand(OpNum);
376 const MachineFunction &MF = *MI->getParent()->getParent();
377 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
378 unsigned Reg = MO.getReg();
379 if(!ARM::GPRPairRegClass.contains(Reg))
381 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
382 O << ARMInstPrinter::getRegisterName(Reg);
388 printOperand(MI, OpNum, O);
392 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
393 unsigned OpNum, unsigned AsmVariant,
394 const char *ExtraCode,
396 // Does this asm operand have a single letter operand modifier?
397 if (ExtraCode && ExtraCode[0]) {
398 if (ExtraCode[1] != 0) return true; // Unknown modifier.
400 switch (ExtraCode[0]) {
401 case 'A': // A memory operand for a VLD1/VST1 instruction.
402 default: return true; // Unknown modifier.
403 case 'm': // The base register of a memory operand.
404 if (!MI->getOperand(OpNum).isReg())
406 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
411 const MachineOperand &MO = MI->getOperand(OpNum);
412 assert(MO.isReg() && "unexpected inline asm memory operand");
413 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
417 static bool isThumb(const MCSubtargetInfo& STI) {
418 return STI.getFeatureBits()[ARM::ModeThumb];
421 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
422 const MCSubtargetInfo *EndInfo) const {
423 // If either end mode is unknown (EndInfo == NULL) or different than
424 // the start mode, then restore the start mode.
425 const bool WasThumb = isThumb(StartInfo);
426 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
427 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
431 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
432 Triple TT(TM.getTargetTriple());
433 // Use unified assembler syntax.
434 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
436 // Emit ARM Build Attributes
437 if (TT.isOSBinFormatELF())
440 // Use the triple's architecture and subarchitecture to determine
441 // if we're thumb for the purposes of the top level code16 assembler
443 bool isThumb = TT.getArch() == Triple::thumb ||
444 TT.getArch() == Triple::thumbeb ||
445 TT.getSubArch() == Triple::ARMSubArch_v7m ||
446 TT.getSubArch() == Triple::ARMSubArch_v6m;
447 if (!M.getModuleInlineAsm().empty() && isThumb)
448 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
452 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
453 MachineModuleInfoImpl::StubValueTy &MCSym) {
455 OutStreamer.EmitLabel(StubLabel);
456 // .indirect_symbol _foo
457 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
460 // External to current translation unit.
461 OutStreamer.EmitIntValue(0, 4/*size*/);
463 // Internal to current translation unit.
465 // When we place the LSDA into the TEXT section, the type info
466 // pointers need to be indirect and pc-rel. We accomplish this by
467 // using NLPs; however, sometimes the types are local to the file.
468 // We need to fill in the value for the NLP in those cases.
469 OutStreamer.EmitValue(
470 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
475 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
476 Triple TT(TM.getTargetTriple());
477 if (TT.isOSBinFormatMachO()) {
478 // All darwin targets use mach-o.
479 const TargetLoweringObjectFileMachO &TLOFMacho =
480 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
481 MachineModuleInfoMachO &MMIMacho =
482 MMI->getObjFileInfo<MachineModuleInfoMachO>();
484 // Output non-lazy-pointers for external and common global variables.
485 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
487 if (!Stubs.empty()) {
488 // Switch with ".non_lazy_symbol_pointer" directive.
489 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
492 for (auto &Stub : Stubs)
493 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
496 OutStreamer->AddBlankLine();
499 Stubs = MMIMacho.GetHiddenGVStubList();
500 if (!Stubs.empty()) {
501 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
504 for (auto &Stub : Stubs)
505 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
508 OutStreamer->AddBlankLine();
511 // Funny Darwin hack: This flag tells the linker that no global symbols
512 // contain code that falls through to other global symbols (e.g. the obvious
513 // implementation of multiple entry points). If this doesn't occur, the
514 // linker can safely perform dead code stripping. Since LLVM never
515 // generates code that does this, it is always safe to set.
516 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
520 //===----------------------------------------------------------------------===//
521 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
523 // The following seem like one-off assembler flags, but they actually need
524 // to appear in the .ARM.attributes section in ELF.
525 // Instead of subclassing the MCELFStreamer, we do the work here.
527 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
528 const ARMSubtarget *Subtarget) {
530 return ARMBuildAttrs::v5TEJ;
532 if (Subtarget->hasV8Ops())
533 return ARMBuildAttrs::v8;
534 else if (Subtarget->hasV7Ops()) {
535 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
536 return ARMBuildAttrs::v7E_M;
537 return ARMBuildAttrs::v7;
538 } else if (Subtarget->hasV6T2Ops())
539 return ARMBuildAttrs::v6T2;
540 else if (Subtarget->hasV6MOps())
541 return ARMBuildAttrs::v6S_M;
542 else if (Subtarget->hasV6Ops())
543 return ARMBuildAttrs::v6;
544 else if (Subtarget->hasV5TEOps())
545 return ARMBuildAttrs::v5TE;
546 else if (Subtarget->hasV5TOps())
547 return ARMBuildAttrs::v5T;
548 else if (Subtarget->hasV4TOps())
549 return ARMBuildAttrs::v4T;
551 return ARMBuildAttrs::v4;
554 void ARMAsmPrinter::emitAttributes() {
555 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
556 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
558 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
560 ATS.switchVendor("aeabi");
562 // Compute ARM ELF Attributes based on the default subtarget that
563 // we'd have constructed. The existing ARM behavior isn't LTO clean
565 // FIXME: For ifunc related functions we could iterate over and look
566 // for a feature string that doesn't match the default one.
567 StringRef TT = TM.getTargetTriple();
568 StringRef CPU = TM.getTargetCPU();
569 StringRef FS = TM.getTargetFeatureString();
570 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
573 ArchFS = (Twine(ArchFS) + "," + FS).str();
577 const ARMBaseTargetMachine &ATM =
578 static_cast<const ARMBaseTargetMachine &>(TM);
579 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
581 std::string CPUString = STI.getCPUString();
583 if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
584 // FIXME: remove krait check when GNU tools support krait cpu
586 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
587 // We consider krait as a "cortex-a9" + hwdiv CPU
588 // Enable hwdiv through ".arch_extension idiv"
589 if (STI.hasDivide() || STI.hasDivideInARMMode())
590 ATS.emitArchExtension(ARM::AEK_HWDIV);
592 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
595 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
597 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
598 // profile is not applicable (e.g. pre v7, or cross-profile code)".
599 if (STI.hasV7Ops()) {
600 if (STI.isAClass()) {
601 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
602 ARMBuildAttrs::ApplicationProfile);
603 } else if (STI.isRClass()) {
604 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
605 ARMBuildAttrs::RealTimeProfile);
606 } else if (STI.isMClass()) {
607 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
608 ARMBuildAttrs::MicroControllerProfile);
612 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
613 STI.hasARMOps() ? ARMBuildAttrs::Allowed
614 : ARMBuildAttrs::Not_Allowed);
615 if (STI.isThumb1Only()) {
616 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
617 } else if (STI.hasThumb2()) {
618 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
619 ARMBuildAttrs::AllowThumb32);
623 /* NEON is not exactly a VFP architecture, but GAS emit one of
624 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
625 if (STI.hasFPARMv8()) {
627 ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
629 ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
630 } else if (STI.hasVFP4())
631 ATS.emitFPU(ARM::FK_NEON_VFPV4);
633 ATS.emitFPU(ARM::FK_NEON);
634 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
636 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
637 STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
638 ARMBuildAttrs::AllowNeonARMv8);
640 if (STI.hasFPARMv8())
641 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
642 // FPU, but there are two different names for it depending on the CPU.
643 ATS.emitFPU(STI.hasD16()
644 ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
646 else if (STI.hasVFP4())
647 ATS.emitFPU(STI.hasD16()
648 ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
650 else if (STI.hasVFP3())
651 ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV3_D16 : ARM::FK_VFPV3);
652 else if (STI.hasVFP2())
653 ATS.emitFPU(ARM::FK_VFPV2);
656 if (TM.getRelocationModel() == Reloc::PIC_) {
657 // PIC specific attributes.
658 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
659 ARMBuildAttrs::AddressRWPCRel);
660 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
661 ARMBuildAttrs::AddressROPCRel);
662 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
663 ARMBuildAttrs::AddressGOT);
665 // Allow direct addressing of imported data for all other relocation models.
666 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
667 ARMBuildAttrs::AddressDirect);
670 // Signal various FP modes.
671 if (!TM.Options.UnsafeFPMath) {
672 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
673 ARMBuildAttrs::IEEEDenormals);
674 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
676 // If the user has permitted this code to choose the IEEE 754
677 // rounding at run-time, emit the rounding attribute.
678 if (TM.Options.HonorSignDependentRoundingFPMathOption)
679 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
681 if (!STI.hasVFP2()) {
682 // When the target doesn't have an FPU (by design or
683 // intention), the assumptions made on the software support
684 // mirror that of the equivalent hardware support *if it
685 // existed*. For v7 and better we indicate that denormals are
686 // flushed preserving sign, and for V6 we indicate that
687 // denormals are flushed to positive zero.
689 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
690 ARMBuildAttrs::PreserveFPSign);
691 } else if (STI.hasVFP3()) {
692 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
693 // the sign bit of the zero matches the sign bit of the input or
694 // result that is being flushed to zero.
695 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
696 ARMBuildAttrs::PreserveFPSign);
698 // For VFPv2 implementations it is implementation defined as
699 // to whether denormals are flushed to positive zero or to
700 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
701 // LLVM has chosen to flush this to positive zero (most likely for
702 // GCC compatibility), so that's the chosen value here (the
703 // absence of its emission implies zero).
706 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
707 // equivalent of GCC's -ffinite-math-only flag.
708 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
709 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
710 ARMBuildAttrs::Allowed);
712 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
713 ARMBuildAttrs::AllowIEE754);
715 if (STI.allowsUnalignedMem())
716 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
717 ARMBuildAttrs::Allowed);
719 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
720 ARMBuildAttrs::Not_Allowed);
722 // FIXME: add more flags to ARMBuildAttributes.h
723 // 8-bytes alignment stuff.
724 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
725 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
727 // ABI_HardFP_use attribute to indicate single precision FP.
728 if (STI.isFPOnlySP())
729 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
730 ARMBuildAttrs::HardFPSinglePrecision);
732 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
733 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
734 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
736 // FIXME: Should we signal R9 usage?
739 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
741 // FIXME: To support emitting this build attribute as GCC does, the
742 // -mfp16-format option and associated plumbing must be
743 // supported. For now the __fp16 type is exposed by default, so this
744 // attribute should be emitted with value 1.
745 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
746 ARMBuildAttrs::FP16FormatIEEE);
748 if (STI.hasMPExtension())
749 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
751 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
752 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
753 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
754 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
755 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
756 // otherwise, the default value (AllowDIVIfExists) applies.
757 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
758 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
761 if (const Module *SourceModule = MMI->getModule()) {
762 // ABI_PCS_wchar_t to indicate wchar_t width
763 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
764 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
765 SourceModule->getModuleFlag("wchar_size"))) {
766 int WCharWidth = WCharWidthValue->getZExtValue();
767 assert((WCharWidth == 2 || WCharWidth == 4) &&
768 "wchar_t width must be 2 or 4 bytes");
769 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
772 // ABI_enum_size to indicate enum width
773 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
774 // (all enums contain a value needing 32 bits to encode).
775 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
776 SourceModule->getModuleFlag("min_enum_size"))) {
777 int EnumWidth = EnumWidthValue->getZExtValue();
778 assert((EnumWidth == 1 || EnumWidth == 4) &&
779 "Minimum enum width must be 1 or 4 bytes");
780 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
781 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
786 // TODO: We currently only support either reserving the register, or treating
787 // it as another callee-saved register, but not as SB or a TLS pointer; It
788 // would instead be nicer to push this from the frontend as metadata, as we do
789 // for the wchar and enum size tags
790 if (STI.isR9Reserved())
791 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
793 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
795 if (STI.hasTrustZone() && STI.hasVirtualization())
796 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
797 ARMBuildAttrs::AllowTZVirtualization);
798 else if (STI.hasTrustZone())
799 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
800 ARMBuildAttrs::AllowTZ);
801 else if (STI.hasVirtualization())
802 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
803 ARMBuildAttrs::AllowVirtualization);
805 ATS.finishAttributeSection();
808 //===----------------------------------------------------------------------===//
810 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
811 unsigned LabelId, MCContext &Ctx) {
813 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
814 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
818 static MCSymbolRefExpr::VariantKind
819 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
821 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
822 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
823 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
824 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
825 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
826 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
828 llvm_unreachable("Invalid ARMCPModifier!");
831 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
832 unsigned char TargetFlags) {
833 if (Subtarget->isTargetMachO()) {
834 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
835 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
838 return getSymbol(GV);
840 // FIXME: Remove this when Darwin transition to @GOT like syntax.
841 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
842 MachineModuleInfoMachO &MMIMachO =
843 MMI->getObjFileInfo<MachineModuleInfoMachO>();
844 MachineModuleInfoImpl::StubValueTy &StubSym =
845 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
846 : MMIMachO.getGVStubEntry(MCSym);
847 if (!StubSym.getPointer())
848 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
849 !GV->hasInternalLinkage());
851 } else if (Subtarget->isTargetCOFF()) {
852 assert(Subtarget->isTargetWindows() &&
853 "Windows is the only supported COFF target");
855 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
857 return getSymbol(GV);
859 SmallString<128> Name;
861 getNameWithPrefix(Name, GV);
863 return OutContext.getOrCreateSymbol(Name);
864 } else if (Subtarget->isTargetELF()) {
865 return getSymbol(GV);
867 llvm_unreachable("unexpected target");
871 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
872 const DataLayout *DL = TM.getDataLayout();
873 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
875 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
878 if (ACPV->isLSDA()) {
879 MCSym = getCurExceptionSym();
880 } else if (ACPV->isBlockAddress()) {
881 const BlockAddress *BA =
882 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
883 MCSym = GetBlockAddressSymbol(BA);
884 } else if (ACPV->isGlobalValue()) {
885 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
887 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
888 // flag the global as MO_NONLAZY.
889 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
890 MCSym = GetARMGVSymbol(GV, TF);
891 } else if (ACPV->isMachineBasicBlock()) {
892 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
893 MCSym = MBB->getSymbol();
895 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
896 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
897 MCSym = GetExternalSymbolSymbol(Sym);
900 // Create an MCSymbol for the reference.
902 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
905 if (ACPV->getPCAdjustment()) {
906 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
910 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
912 MCBinaryExpr::createAdd(PCRelExpr,
913 MCConstantExpr::create(ACPV->getPCAdjustment(),
916 if (ACPV->mustAddCurrentAddress()) {
917 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
918 // label, so just emit a local label end reference that instead.
919 MCSymbol *DotSym = OutContext.createTempSymbol();
920 OutStreamer->EmitLabel(DotSym);
921 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
922 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
924 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
926 OutStreamer->EmitValue(Expr, Size);
929 void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
930 const MachineOperand &MO1 = MI->getOperand(1);
931 unsigned JTI = MO1.getIndex();
933 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
937 // Emit a label for the jump table.
938 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
939 OutStreamer->EmitLabel(JTISymbol);
941 // Mark the jump table as data-in-code.
942 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
944 // Emit each entry of the table.
945 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
949 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
950 MachineBasicBlock *MBB = JTBBs[i];
951 // Construct an MCExpr for the entry. We want a value of the form:
952 // (BasicBlockAddr - TableBeginAddr)
954 // For example, a table with entries jumping to basic blocks BB0 and BB1
957 // .word (LBB0 - LJTI_0_0)
958 // .word (LBB1 - LJTI_0_0)
959 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
961 if (TM.getRelocationModel() == Reloc::PIC_)
962 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
965 // If we're generating a table of Thumb addresses in static relocation
966 // model, we need to add one to keep interworking correctly.
967 else if (AFI->isThumbFunction())
968 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
970 OutStreamer->EmitValue(Expr, 4);
972 // Mark the end of jump table data-in-code region.
973 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
976 void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
977 const MachineOperand &MO1 = MI->getOperand(1);
978 unsigned JTI = MO1.getIndex();
980 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
981 OutStreamer->EmitLabel(JTISymbol);
983 // Emit each entry of the table.
984 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
985 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
986 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
988 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
989 MachineBasicBlock *MBB = JTBBs[i];
990 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
992 // If this isn't a TBB or TBH, the entries are direct branch instructions.
993 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
994 .addExpr(MBBSymbolExpr)
1000 void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
1001 unsigned OffsetWidth) {
1002 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1003 const MachineOperand &MO1 = MI->getOperand(1);
1004 unsigned JTI = MO1.getIndex();
1006 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1007 OutStreamer->EmitLabel(JTISymbol);
1009 // Emit each entry of the table.
1010 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1011 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1012 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1014 // Mark the jump table as data-in-code.
1015 OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1016 : MCDR_DataRegionJT16);
1018 for (auto MBB : JTBBs) {
1019 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1021 // Otherwise it's an offset from the dispatch instruction. Construct an
1022 // MCExpr for the entry. We want a value of the form:
1023 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1025 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1028 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1029 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1030 // where LCPI0_0 is a label defined just before the TBB instruction using
1032 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1033 const MCExpr *Expr = MCBinaryExpr::createAdd(
1034 MCSymbolRefExpr::create(TBInstPC, OutContext),
1035 MCConstantExpr::create(4, OutContext), OutContext);
1036 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1037 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1039 OutStreamer->EmitValue(Expr, OffsetWidth);
1041 // Mark the end of jump table data-in-code region. 32-bit offsets use
1042 // actual branch instructions here, so we don't mark those as a data-region
1044 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1046 // Make sure the next instruction is 2-byte aligned.
1050 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1051 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1052 "Only instruction which are involved into frame setup code are allowed");
1054 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1055 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1056 const MachineFunction &MF = *MI->getParent()->getParent();
1057 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1058 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1060 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1061 unsigned Opc = MI->getOpcode();
1062 unsigned SrcReg, DstReg;
1064 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1065 // Two special cases:
1066 // 1) tPUSH does not have src/dst regs.
1067 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1068 // load. Yes, this is pretty fragile, but for now I don't see better
1070 SrcReg = DstReg = ARM::SP;
1072 SrcReg = MI->getOperand(1).getReg();
1073 DstReg = MI->getOperand(0).getReg();
1076 // Try to figure out the unwinding opcode out of src / dst regs.
1077 if (MI->mayStore()) {
1079 assert(DstReg == ARM::SP &&
1080 "Only stack pointer as a destination reg is supported");
1082 SmallVector<unsigned, 4> RegList;
1083 // Skip src & dst reg, and pred ops.
1084 unsigned StartOp = 2 + 2;
1085 // Use all the operands.
1086 unsigned NumOffset = 0;
1091 llvm_unreachable("Unsupported opcode for unwinding information");
1093 // Special case here: no src & dst reg, but two extra imp ops.
1094 StartOp = 2; NumOffset = 2;
1095 case ARM::STMDB_UPD:
1096 case ARM::t2STMDB_UPD:
1097 case ARM::VSTMDDB_UPD:
1098 assert(SrcReg == ARM::SP &&
1099 "Only stack pointer as a source reg is supported");
1100 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1102 const MachineOperand &MO = MI->getOperand(i);
1103 // Actually, there should never be any impdef stuff here. Skip it
1104 // temporary to workaround PR11902.
1105 if (MO.isImplicit())
1107 RegList.push_back(MO.getReg());
1110 case ARM::STR_PRE_IMM:
1111 case ARM::STR_PRE_REG:
1112 case ARM::t2STR_PRE:
1113 assert(MI->getOperand(2).getReg() == ARM::SP &&
1114 "Only stack pointer as a source reg is supported");
1115 RegList.push_back(SrcReg);
1118 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1119 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1121 // Changes of stack / frame pointer.
1122 if (SrcReg == ARM::SP) {
1127 llvm_unreachable("Unsupported opcode for unwinding information");
1133 Offset = -MI->getOperand(2).getImm();
1137 Offset = MI->getOperand(2).getImm();
1140 Offset = MI->getOperand(2).getImm()*4;
1144 Offset = -MI->getOperand(2).getImm()*4;
1146 case ARM::tLDRpci: {
1147 // Grab the constpool index and check, whether it corresponds to
1148 // original or cloned constpool entry.
1149 unsigned CPI = MI->getOperand(1).getIndex();
1150 const MachineConstantPool *MCP = MF.getConstantPool();
1151 if (CPI >= MCP->getConstants().size())
1152 CPI = AFI.getOriginalCPIdx(CPI);
1153 assert(CPI != -1U && "Invalid constpool index");
1155 // Derive the actual offset.
1156 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1157 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1158 // FIXME: Check for user, it should be "add" instruction!
1159 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1164 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1165 if (DstReg == FramePtr && FramePtr != ARM::SP)
1166 // Set-up of the frame pointer. Positive values correspond to "add"
1168 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1169 else if (DstReg == ARM::SP) {
1170 // Change of SP by an offset. Positive values correspond to "sub"
1172 ATS.emitPad(Offset);
1174 // Move of SP to a register. Positive values correspond to an "add"
1176 ATS.emitMovSP(DstReg, -Offset);
1179 } else if (DstReg == ARM::SP) {
1181 llvm_unreachable("Unsupported opcode for unwinding information");
1185 llvm_unreachable("Unsupported opcode for unwinding information");
1190 // Simple pseudo-instructions have their lowering (with expansion to real
1191 // instructions) auto-generated.
1192 #include "ARMGenMCPseudoLowering.inc"
1194 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1195 const DataLayout *DL = TM.getDataLayout();
1197 // If we just ended a constant pool, mark it as such.
1198 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1199 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1200 InConstantPool = false;
1203 // Emit unwinding stuff for frame-related instructions
1204 if (Subtarget->isTargetEHABICompatible() &&
1205 MI->getFlag(MachineInstr::FrameSetup))
1206 EmitUnwindingInstruction(MI);
1208 // Do any auto-generated pseudo lowerings.
1209 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1212 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1213 "Pseudo flag setting opcode should be expanded early");
1215 // Check for manual lowerings.
1216 unsigned Opc = MI->getOpcode();
1218 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1219 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1221 case ARM::tLEApcrel:
1222 case ARM::t2LEApcrel: {
1223 // FIXME: Need to also handle globals and externals
1224 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1225 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1226 ARM::t2LEApcrel ? ARM::t2ADR
1227 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1229 .addReg(MI->getOperand(0).getReg())
1230 .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1231 // Add predicate operands.
1232 .addImm(MI->getOperand(2).getImm())
1233 .addReg(MI->getOperand(3).getReg()));
1236 case ARM::LEApcrelJT:
1237 case ARM::tLEApcrelJT:
1238 case ARM::t2LEApcrelJT: {
1239 MCSymbol *JTIPICSymbol =
1240 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1241 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1242 ARM::t2LEApcrelJT ? ARM::t2ADR
1243 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1245 .addReg(MI->getOperand(0).getReg())
1246 .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1247 // Add predicate operands.
1248 .addImm(MI->getOperand(2).getImm())
1249 .addReg(MI->getOperand(3).getReg()));
1252 // Darwin call instructions are just normal call instructions with different
1253 // clobber semantics (they clobber R9).
1254 case ARM::BX_CALL: {
1255 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1258 // Add predicate operands.
1261 // Add 's' bit operand (always reg0 for this)
1264 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1265 .addReg(MI->getOperand(0).getReg()));
1268 case ARM::tBX_CALL: {
1269 if (Subtarget->hasV5TOps())
1270 llvm_unreachable("Expected BLX to be selected for v5t+");
1272 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1273 // that the saved lr has its LSB set correctly (the arch doesn't
1275 // So here we generate a bl to a small jump pad that does bx rN.
1276 // The jump pads are emitted after the function body.
1278 unsigned TReg = MI->getOperand(0).getReg();
1279 MCSymbol *TRegSym = nullptr;
1280 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1281 if (ThumbIndirectPads[i].first == TReg) {
1282 TRegSym = ThumbIndirectPads[i].second;
1288 TRegSym = OutContext.createTempSymbol();
1289 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1292 // Create a link-saving branch to the Reg Indirect Jump Pad.
1293 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1294 // Predicate comes first here.
1295 .addImm(ARMCC::AL).addReg(0)
1296 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1299 case ARM::BMOVPCRX_CALL: {
1300 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1303 // Add predicate operands.
1306 // Add 's' bit operand (always reg0 for this)
1309 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1311 .addReg(MI->getOperand(0).getReg())
1312 // Add predicate operands.
1315 // Add 's' bit operand (always reg0 for this)
1319 case ARM::BMOVPCB_CALL: {
1320 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1323 // Add predicate operands.
1326 // Add 's' bit operand (always reg0 for this)
1329 const MachineOperand &Op = MI->getOperand(0);
1330 const GlobalValue *GV = Op.getGlobal();
1331 const unsigned TF = Op.getTargetFlags();
1332 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1333 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1334 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1336 // Add predicate operands.
1341 case ARM::MOVi16_ga_pcrel:
1342 case ARM::t2MOVi16_ga_pcrel: {
1344 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1345 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1347 unsigned TF = MI->getOperand(1).getTargetFlags();
1348 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1349 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1350 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1352 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1353 getFunctionNumber(),
1354 MI->getOperand(2).getImm(), OutContext);
1355 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1356 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1357 const MCExpr *PCRelExpr =
1358 ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1359 MCBinaryExpr::createAdd(LabelSymExpr,
1360 MCConstantExpr::create(PCAdj, OutContext),
1361 OutContext), OutContext), OutContext);
1362 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1364 // Add predicate operands.
1365 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1366 TmpInst.addOperand(MCOperand::createReg(0));
1367 // Add 's' bit operand (always reg0 for this)
1368 TmpInst.addOperand(MCOperand::createReg(0));
1369 EmitToStreamer(*OutStreamer, TmpInst);
1372 case ARM::MOVTi16_ga_pcrel:
1373 case ARM::t2MOVTi16_ga_pcrel: {
1375 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1376 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1377 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1378 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1380 unsigned TF = MI->getOperand(2).getTargetFlags();
1381 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1382 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1383 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1385 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1386 getFunctionNumber(),
1387 MI->getOperand(3).getImm(), OutContext);
1388 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1389 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1390 const MCExpr *PCRelExpr =
1391 ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1392 MCBinaryExpr::createAdd(LabelSymExpr,
1393 MCConstantExpr::create(PCAdj, OutContext),
1394 OutContext), OutContext), OutContext);
1395 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1396 // Add predicate operands.
1397 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1398 TmpInst.addOperand(MCOperand::createReg(0));
1399 // Add 's' bit operand (always reg0 for this)
1400 TmpInst.addOperand(MCOperand::createReg(0));
1401 EmitToStreamer(*OutStreamer, TmpInst);
1404 case ARM::tPICADD: {
1405 // This is a pseudo op for a label + instruction sequence, which looks like:
1408 // This adds the address of LPC0 to r0.
1411 OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1412 getFunctionNumber(),
1413 MI->getOperand(2).getImm(),
1416 // Form and emit the add.
1417 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1418 .addReg(MI->getOperand(0).getReg())
1419 .addReg(MI->getOperand(0).getReg())
1421 // Add predicate operands.
1427 // This is a pseudo op for a label + instruction sequence, which looks like:
1430 // This adds the address of LPC0 to r0.
1433 OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1434 getFunctionNumber(),
1435 MI->getOperand(2).getImm(),
1438 // Form and emit the add.
1439 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1440 .addReg(MI->getOperand(0).getReg())
1442 .addReg(MI->getOperand(1).getReg())
1443 // Add predicate operands.
1444 .addImm(MI->getOperand(3).getImm())
1445 .addReg(MI->getOperand(4).getReg())
1446 // Add 's' bit operand (always reg0 for this)
1457 case ARM::PICLDRSH: {
1458 // This is a pseudo op for a label + instruction sequence, which looks like:
1461 // The LCP0 label is referenced by a constant pool entry in order to get
1462 // a PC-relative address at the ldr instruction.
1465 OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1466 getFunctionNumber(),
1467 MI->getOperand(2).getImm(),
1470 // Form and emit the load
1472 switch (MI->getOpcode()) {
1474 llvm_unreachable("Unexpected opcode!");
1475 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1476 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1477 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1478 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1479 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1480 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1481 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1482 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1484 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1485 .addReg(MI->getOperand(0).getReg())
1487 .addReg(MI->getOperand(1).getReg())
1489 // Add predicate operands.
1490 .addImm(MI->getOperand(3).getImm())
1491 .addReg(MI->getOperand(4).getReg()));
1495 case ARM::CONSTPOOL_ENTRY: {
1496 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1497 /// in the function. The first operand is the ID# for this instruction, the
1498 /// second is the index into the MachineConstantPool that this is, the third
1499 /// is the size in bytes of this constant pool entry.
1500 /// The required alignment is specified on the basic block holding this MI.
1501 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1502 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1504 // If this is the first entry of the pool, mark it.
1505 if (!InConstantPool) {
1506 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1507 InConstantPool = true;
1510 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1512 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1513 if (MCPE.isMachineConstantPoolEntry())
1514 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1516 EmitGlobalConstant(MCPE.Val.ConstVal);
1519 case ARM::JUMPTABLE_ADDRS:
1520 EmitJumpTableAddrs(MI);
1522 case ARM::JUMPTABLE_INSTS:
1523 EmitJumpTableInsts(MI);
1525 case ARM::JUMPTABLE_TBB:
1526 case ARM::JUMPTABLE_TBH:
1527 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1529 case ARM::t2BR_JT: {
1530 // Lower and emit the instruction itself, then the jump table following it.
1531 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1533 .addReg(MI->getOperand(0).getReg())
1534 // Add predicate operands.
1540 case ARM::t2TBH_JT: {
1541 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1542 // Lower and emit the PC label, then the instruction itself.
1543 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1544 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1545 .addReg(MI->getOperand(0).getReg())
1546 .addReg(MI->getOperand(1).getReg())
1547 // Add predicate operands.
1554 // Lower and emit the instruction itself, then the jump table following it.
1557 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1558 ARM::MOVr : ARM::tMOVr;
1559 TmpInst.setOpcode(Opc);
1560 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1561 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1562 // Add predicate operands.
1563 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1564 TmpInst.addOperand(MCOperand::createReg(0));
1565 // Add 's' bit operand (always reg0 for this)
1566 if (Opc == ARM::MOVr)
1567 TmpInst.addOperand(MCOperand::createReg(0));
1568 EmitToStreamer(*OutStreamer, TmpInst);
1572 // Lower and emit the instruction itself, then the jump table following it.
1575 if (MI->getOperand(1).getReg() == 0) {
1577 TmpInst.setOpcode(ARM::LDRi12);
1578 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1579 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1580 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1582 TmpInst.setOpcode(ARM::LDRrs);
1583 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1584 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1585 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1586 TmpInst.addOperand(MCOperand::createImm(0));
1588 // Add predicate operands.
1589 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1590 TmpInst.addOperand(MCOperand::createReg(0));
1591 EmitToStreamer(*OutStreamer, TmpInst);
1594 case ARM::BR_JTadd: {
1595 // Lower and emit the instruction itself, then the jump table following it.
1596 // add pc, target, idx
1597 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1599 .addReg(MI->getOperand(0).getReg())
1600 .addReg(MI->getOperand(1).getReg())
1601 // Add predicate operands.
1604 // Add 's' bit operand (always reg0 for this)
1609 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1612 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1613 // FIXME: Remove this special case when they do.
1614 if (!Subtarget->isTargetMachO()) {
1615 //.long 0xe7ffdefe @ trap
1616 uint32_t Val = 0xe7ffdefeUL;
1617 OutStreamer->AddComment("trap");
1618 OutStreamer->EmitIntValue(Val, 4);
1623 case ARM::TRAPNaCl: {
1624 //.long 0xe7fedef0 @ trap
1625 uint32_t Val = 0xe7fedef0UL;
1626 OutStreamer->AddComment("trap");
1627 OutStreamer->EmitIntValue(Val, 4);
1631 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1632 // FIXME: Remove this special case when they do.
1633 if (!Subtarget->isTargetMachO()) {
1634 //.short 57086 @ trap
1635 uint16_t Val = 0xdefe;
1636 OutStreamer->AddComment("trap");
1637 OutStreamer->EmitIntValue(Val, 2);
1642 case ARM::t2Int_eh_sjlj_setjmp:
1643 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1644 case ARM::tInt_eh_sjlj_setjmp: {
1645 // Two incoming args: GPR:$src, GPR:$val
1648 // str $val, [$src, #4]
1653 unsigned SrcReg = MI->getOperand(0).getReg();
1654 unsigned ValReg = MI->getOperand(1).getReg();
1655 MCSymbol *Label = GetARMSJLJEHLabel();
1656 OutStreamer->AddComment("eh_setjmp begin");
1657 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1664 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1674 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1677 // The offset immediate is #4. The operand value is scaled by 4 for the
1678 // tSTR instruction.
1684 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1692 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1693 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1694 .addExpr(SymbolExpr)
1698 OutStreamer->AddComment("eh_setjmp end");
1699 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1707 OutStreamer->EmitLabel(Label);
1711 case ARM::Int_eh_sjlj_setjmp_nofp:
1712 case ARM::Int_eh_sjlj_setjmp: {
1713 // Two incoming args: GPR:$src, GPR:$val
1715 // str $val, [$src, #+4]
1719 unsigned SrcReg = MI->getOperand(0).getReg();
1720 unsigned ValReg = MI->getOperand(1).getReg();
1722 OutStreamer->AddComment("eh_setjmp begin");
1723 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1730 // 's' bit operand (always reg0 for this).
1733 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1741 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1747 // 's' bit operand (always reg0 for this).
1750 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1757 // 's' bit operand (always reg0 for this).
1760 OutStreamer->AddComment("eh_setjmp end");
1761 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1767 // 's' bit operand (always reg0 for this).
1771 case ARM::Int_eh_sjlj_longjmp: {
1772 // ldr sp, [$src, #8]
1773 // ldr $scratch, [$src, #4]
1776 unsigned SrcReg = MI->getOperand(0).getReg();
1777 unsigned ScratchReg = MI->getOperand(1).getReg();
1778 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1786 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1794 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1802 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1809 case ARM::tInt_eh_sjlj_longjmp: {
1810 // ldr $scratch, [$src, #8]
1812 // ldr $scratch, [$src, #4]
1815 unsigned SrcReg = MI->getOperand(0).getReg();
1816 unsigned ScratchReg = MI->getOperand(1).getReg();
1817 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1820 // The offset immediate is #8. The operand value is scaled by 4 for the
1821 // tLDR instruction.
1827 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1834 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1842 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1850 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
1860 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1862 EmitToStreamer(*OutStreamer, TmpInst);
1865 //===----------------------------------------------------------------------===//
1866 // Target Registry Stuff
1867 //===----------------------------------------------------------------------===//
1869 // Force static initialization.
1870 extern "C" void LLVMInitializeARMAsmPrinter() {
1871 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1872 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1873 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1874 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);