1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMArchExtName.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/ADT/SetVector.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/DebugInfo.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/COFF.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ELF.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
55 #include "llvm/Target/TargetMachine.h"
59 #define DEBUG_TYPE "asm-printer"
61 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
62 std::unique_ptr<MCStreamer> Streamer)
63 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
64 InConstantPool(false) {}
66 void ARMAsmPrinter::EmitFunctionBodyEnd() {
67 // Make sure to terminate any constant pools that were at the end
71 InConstantPool = false;
72 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
75 void ARMAsmPrinter::EmitFunctionEntryLabel() {
76 if (AFI->isThumbFunction()) {
77 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
78 OutStreamer.EmitThumbFunc(CurrentFnSym);
81 OutStreamer.EmitLabel(CurrentFnSym);
84 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
85 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
86 assert(Size && "C++ constructor pointer had zero size!");
88 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
89 assert(GV && "C++ constructor pointer was not a GlobalValue!");
91 const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
93 (Subtarget->isTargetELF()
94 ? MCSymbolRefExpr::VK_ARM_TARGET1
95 : MCSymbolRefExpr::VK_None),
98 OutStreamer.EmitValue(E, Size);
101 /// runOnMachineFunction - This uses the EmitInstruction()
102 /// method to print assembly for each instruction.
104 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
105 AFI = MF.getInfo<ARMFunctionInfo>();
106 MCP = MF.getConstantPool();
107 Subtarget = &MF.getSubtarget<ARMSubtarget>();
109 SetupMachineFunction(MF);
111 if (Subtarget->isTargetCOFF()) {
112 bool Internal = MF.getFunction()->hasInternalLinkage();
113 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
114 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
115 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
117 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
118 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
119 OutStreamer.EmitCOFFSymbolType(Type);
120 OutStreamer.EndCOFFSymbolDef();
123 // Emit the rest of the function body.
126 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
127 // These are created per function, rather than per TU, since it's
128 // relatively easy to exceed the thumb branch range within a TU.
129 if (! ThumbIndirectPads.empty()) {
130 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
132 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
133 OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
134 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
135 .addReg(ThumbIndirectPads[i].first)
136 // Add predicate operands.
140 ThumbIndirectPads.clear();
143 // We didn't modify anything.
147 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
148 raw_ostream &O, const char *Modifier) {
149 const MachineOperand &MO = MI->getOperand(OpNum);
150 unsigned TF = MO.getTargetFlags();
152 switch (MO.getType()) {
153 default: llvm_unreachable("<unknown operand type>");
154 case MachineOperand::MO_Register: {
155 unsigned Reg = MO.getReg();
156 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
157 assert(!MO.getSubReg() && "Subregs should be eliminated!");
158 if(ARM::GPRPairRegClass.contains(Reg)) {
159 const MachineFunction &MF = *MI->getParent()->getParent();
160 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
161 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
163 O << ARMInstPrinter::getRegisterName(Reg);
166 case MachineOperand::MO_Immediate: {
167 int64_t Imm = MO.getImm();
169 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
170 (TF == ARMII::MO_LO16))
172 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
173 (TF == ARMII::MO_HI16))
178 case MachineOperand::MO_MachineBasicBlock:
179 O << *MO.getMBB()->getSymbol();
181 case MachineOperand::MO_GlobalAddress: {
182 const GlobalValue *GV = MO.getGlobal();
183 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
184 (TF & ARMII::MO_LO16))
186 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
187 (TF & ARMII::MO_HI16))
189 O << *GetARMGVSymbol(GV, TF);
191 printOffset(MO.getOffset(), O);
192 if (TF == ARMII::MO_PLT)
196 case MachineOperand::MO_ConstantPoolIndex:
197 O << *GetCPISymbol(MO.getIndex());
202 //===--------------------------------------------------------------------===//
204 MCSymbol *ARMAsmPrinter::
205 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
206 const DataLayout *DL = TM.getDataLayout();
207 SmallString<60> Name;
208 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
209 << getFunctionNumber() << '_' << uid << '_' << uid2;
210 return OutContext.GetOrCreateSymbol(Name.str());
214 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
215 const DataLayout *DL = TM.getDataLayout();
216 SmallString<60> Name;
217 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
218 << getFunctionNumber();
219 return OutContext.GetOrCreateSymbol(Name.str());
222 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
223 unsigned AsmVariant, const char *ExtraCode,
225 // Does this asm operand have a single letter operand modifier?
226 if (ExtraCode && ExtraCode[0]) {
227 if (ExtraCode[1] != 0) return true; // Unknown modifier.
229 switch (ExtraCode[0]) {
231 // See if this is a generic print operand
232 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
233 case 'a': // Print as a memory address.
234 if (MI->getOperand(OpNum).isReg()) {
236 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
241 case 'c': // Don't print "#" before an immediate operand.
242 if (!MI->getOperand(OpNum).isImm())
244 O << MI->getOperand(OpNum).getImm();
246 case 'P': // Print a VFP double precision register.
247 case 'q': // Print a NEON quad precision register.
248 printOperand(MI, OpNum, O);
250 case 'y': // Print a VFP single precision register as indexed double.
251 if (MI->getOperand(OpNum).isReg()) {
252 unsigned Reg = MI->getOperand(OpNum).getReg();
253 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
254 // Find the 'd' register that has this 's' register as a sub-register,
255 // and determine the lane number.
256 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
257 if (!ARM::DPRRegClass.contains(*SR))
259 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
260 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
265 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
266 if (!MI->getOperand(OpNum).isImm())
268 O << ~(MI->getOperand(OpNum).getImm());
270 case 'L': // The low 16 bits of an immediate constant.
271 if (!MI->getOperand(OpNum).isImm())
273 O << (MI->getOperand(OpNum).getImm() & 0xffff);
275 case 'M': { // A register range suitable for LDM/STM.
276 if (!MI->getOperand(OpNum).isReg())
278 const MachineOperand &MO = MI->getOperand(OpNum);
279 unsigned RegBegin = MO.getReg();
280 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
281 // already got the operands in registers that are operands to the
282 // inline asm statement.
284 if (ARM::GPRPairRegClass.contains(RegBegin)) {
285 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
286 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
287 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
288 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
290 O << ARMInstPrinter::getRegisterName(RegBegin);
292 // FIXME: The register allocator not only may not have given us the
293 // registers in sequence, but may not be in ascending registers. This
294 // will require changes in the register allocator that'll need to be
295 // propagated down here if the operands change.
296 unsigned RegOps = OpNum + 1;
297 while (MI->getOperand(RegOps).isReg()) {
299 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
307 case 'R': // The most significant register of a pair.
308 case 'Q': { // The least significant register of a pair.
311 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
312 if (!FlagsOP.isImm())
314 unsigned Flags = FlagsOP.getImm();
316 // This operand may not be the one that actually provides the register. If
317 // it's tied to a previous one then we should refer instead to that one
318 // for registers and their classes.
320 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
321 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
322 unsigned OpFlags = MI->getOperand(OpNum).getImm();
323 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
325 Flags = MI->getOperand(OpNum).getImm();
327 // Later code expects OpNum to be pointing at the register rather than
332 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
334 InlineAsm::hasRegClassConstraint(Flags, RC);
335 if (RC == ARM::GPRPairRegClassID) {
338 const MachineOperand &MO = MI->getOperand(OpNum);
341 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
342 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
343 ARM::gsub_0 : ARM::gsub_1);
344 O << ARMInstPrinter::getRegisterName(Reg);
349 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
350 if (RegOp >= MI->getNumOperands())
352 const MachineOperand &MO = MI->getOperand(RegOp);
355 unsigned Reg = MO.getReg();
356 O << ARMInstPrinter::getRegisterName(Reg);
360 case 'e': // The low doubleword register of a NEON quad register.
361 case 'f': { // The high doubleword register of a NEON quad register.
362 if (!MI->getOperand(OpNum).isReg())
364 unsigned Reg = MI->getOperand(OpNum).getReg();
365 if (!ARM::QPRRegClass.contains(Reg))
367 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
368 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
369 ARM::dsub_0 : ARM::dsub_1);
370 O << ARMInstPrinter::getRegisterName(SubReg);
374 // This modifier is not yet supported.
375 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
377 case 'H': { // The highest-numbered register of a pair.
378 const MachineOperand &MO = MI->getOperand(OpNum);
381 const MachineFunction &MF = *MI->getParent()->getParent();
382 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
383 unsigned Reg = MO.getReg();
384 if(!ARM::GPRPairRegClass.contains(Reg))
386 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
387 O << ARMInstPrinter::getRegisterName(Reg);
393 printOperand(MI, OpNum, O);
397 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
398 unsigned OpNum, unsigned AsmVariant,
399 const char *ExtraCode,
401 // Does this asm operand have a single letter operand modifier?
402 if (ExtraCode && ExtraCode[0]) {
403 if (ExtraCode[1] != 0) return true; // Unknown modifier.
405 switch (ExtraCode[0]) {
406 case 'A': // A memory operand for a VLD1/VST1 instruction.
407 default: return true; // Unknown modifier.
408 case 'm': // The base register of a memory operand.
409 if (!MI->getOperand(OpNum).isReg())
411 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
416 const MachineOperand &MO = MI->getOperand(OpNum);
417 assert(MO.isReg() && "unexpected inline asm memory operand");
418 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
422 static bool isThumb(const MCSubtargetInfo& STI) {
423 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
426 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
427 const MCSubtargetInfo *EndInfo) const {
428 // If either end mode is unknown (EndInfo == NULL) or different than
429 // the start mode, then restore the start mode.
430 const bool WasThumb = isThumb(StartInfo);
431 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
432 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
436 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
437 Triple TT(TM.getTargetTriple());
438 // Use unified assembler syntax.
439 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
441 // Emit ARM Build Attributes
442 if (TT.isOSBinFormatELF())
445 // Use the triple's architecture and subarchitecture to determine
446 // if we're thumb for the purposes of the top level code16 assembler
448 bool isThumb = TT.getArch() == Triple::thumb ||
449 TT.getArch() == Triple::thumbeb ||
450 TT.getSubArch() == Triple::ARMSubArch_v7m ||
451 TT.getSubArch() == Triple::ARMSubArch_v6m;
452 if (!M.getModuleInlineAsm().empty() && isThumb)
453 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
457 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
458 MachineModuleInfoImpl::StubValueTy &MCSym) {
460 OutStreamer.EmitLabel(StubLabel);
461 // .indirect_symbol _foo
462 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
465 // External to current translation unit.
466 OutStreamer.EmitIntValue(0, 4/*size*/);
468 // Internal to current translation unit.
470 // When we place the LSDA into the TEXT section, the type info
471 // pointers need to be indirect and pc-rel. We accomplish this by
472 // using NLPs; however, sometimes the types are local to the file.
473 // We need to fill in the value for the NLP in those cases.
474 OutStreamer.EmitValue(
475 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
480 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
481 Triple TT(TM.getTargetTriple());
482 if (TT.isOSBinFormatMachO()) {
483 // All darwin targets use mach-o.
484 const TargetLoweringObjectFileMachO &TLOFMacho =
485 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
486 MachineModuleInfoMachO &MMIMacho =
487 MMI->getObjFileInfo<MachineModuleInfoMachO>();
489 // Output non-lazy-pointers for external and common global variables.
490 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
492 if (!Stubs.empty()) {
493 // Switch with ".non_lazy_symbol_pointer" directive.
494 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
497 for (auto &Stub : Stubs)
498 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
501 OutStreamer.AddBlankLine();
504 Stubs = MMIMacho.GetHiddenGVStubList();
505 if (!Stubs.empty()) {
506 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
509 for (auto &Stub : Stubs)
510 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
513 OutStreamer.AddBlankLine();
516 // Funny Darwin hack: This flag tells the linker that no global symbols
517 // contain code that falls through to other global symbols (e.g. the obvious
518 // implementation of multiple entry points). If this doesn't occur, the
519 // linker can safely perform dead code stripping. Since LLVM never
520 // generates code that does this, it is always safe to set.
521 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
524 // Emit a .data.rel section containing any stubs that were created.
525 if (TT.isOSBinFormatELF()) {
526 const TargetLoweringObjectFileELF &TLOFELF =
527 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
529 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
531 // Output stubs for external and common global variables.
532 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
533 if (!Stubs.empty()) {
534 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
535 const DataLayout *TD = TM.getDataLayout();
537 for (auto &stub: Stubs) {
538 OutStreamer.EmitLabel(stub.first);
539 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
540 TD->getPointerSize(0));
547 //===----------------------------------------------------------------------===//
548 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
550 // The following seem like one-off assembler flags, but they actually need
551 // to appear in the .ARM.attributes section in ELF.
552 // Instead of subclassing the MCELFStreamer, we do the work here.
554 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
555 const ARMSubtarget *Subtarget) {
557 return ARMBuildAttrs::v5TEJ;
559 if (Subtarget->hasV8Ops())
560 return ARMBuildAttrs::v8;
561 else if (Subtarget->hasV7Ops()) {
562 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
563 return ARMBuildAttrs::v7E_M;
564 return ARMBuildAttrs::v7;
565 } else if (Subtarget->hasV6T2Ops())
566 return ARMBuildAttrs::v6T2;
567 else if (Subtarget->hasV6MOps())
568 return ARMBuildAttrs::v6S_M;
569 else if (Subtarget->hasV6Ops())
570 return ARMBuildAttrs::v6;
571 else if (Subtarget->hasV5TEOps())
572 return ARMBuildAttrs::v5TE;
573 else if (Subtarget->hasV5TOps())
574 return ARMBuildAttrs::v5T;
575 else if (Subtarget->hasV4TOps())
576 return ARMBuildAttrs::v4T;
578 return ARMBuildAttrs::v4;
581 void ARMAsmPrinter::emitAttributes() {
582 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
583 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
585 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
587 ATS.switchVendor("aeabi");
589 // Compute ARM ELF Attributes based on the default subtarget that
590 // we'd have constructed. The existing ARM behavior isn't LTO clean
592 // FIXME: For ifunc related functions we could iterate over and look
593 // for a feature string that doesn't match the default one.
594 StringRef TT = TM.getTargetTriple();
595 StringRef CPU = TM.getTargetCPU();
596 StringRef FS = TM.getTargetFeatureString();
597 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
600 ArchFS = ArchFS + "," + FS.str();
604 const ARMBaseTargetMachine &ATM =
605 static_cast<const ARMBaseTargetMachine &>(TM);
606 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
608 std::string CPUString = STI.getCPUString();
610 if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
611 // FIXME: remove krait check when GNU tools support krait cpu
613 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
614 // We consider krait as a "cortex-a9" + hwdiv CPU
615 // Enable hwdiv through ".arch_extension idiv"
616 if (STI.hasDivide() || STI.hasDivideInARMMode())
617 ATS.emitArchExtension(ARM::HWDIV);
619 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
622 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
624 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
625 // profile is not applicable (e.g. pre v7, or cross-profile code)".
626 if (STI.hasV7Ops()) {
627 if (STI.isAClass()) {
628 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
629 ARMBuildAttrs::ApplicationProfile);
630 } else if (STI.isRClass()) {
631 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632 ARMBuildAttrs::RealTimeProfile);
633 } else if (STI.isMClass()) {
634 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
635 ARMBuildAttrs::MicroControllerProfile);
639 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
640 STI.hasARMOps() ? ARMBuildAttrs::Allowed
641 : ARMBuildAttrs::Not_Allowed);
642 if (STI.isThumb1Only()) {
643 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
644 } else if (STI.hasThumb2()) {
645 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
646 ARMBuildAttrs::AllowThumb32);
650 /* NEON is not exactly a VFP architecture, but GAS emit one of
651 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
652 if (STI.hasFPARMv8()) {
654 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
656 ATS.emitFPU(ARM::NEON_FP_ARMV8);
657 } else if (STI.hasVFP4())
658 ATS.emitFPU(ARM::NEON_VFPV4);
660 ATS.emitFPU(ARM::NEON);
661 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
663 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
664 STI.hasV8_1a() ? ARMBuildAttrs::AllowNeonARMv8_1a:
665 ARMBuildAttrs::AllowNeonARMv8);
667 if (STI.hasFPARMv8())
668 // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
669 // FPU, but there are two different names for it depending on the CPU.
670 ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
671 else if (STI.hasVFP4())
672 ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
673 else if (STI.hasVFP3())
674 ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
675 else if (STI.hasVFP2())
676 ATS.emitFPU(ARM::VFPV2);
679 if (TM.getRelocationModel() == Reloc::PIC_) {
680 // PIC specific attributes.
681 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
682 ARMBuildAttrs::AddressRWPCRel);
683 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
684 ARMBuildAttrs::AddressROPCRel);
685 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
686 ARMBuildAttrs::AddressGOT);
688 // Allow direct addressing of imported data for all other relocation models.
689 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
690 ARMBuildAttrs::AddressDirect);
693 // Signal various FP modes.
694 if (!TM.Options.UnsafeFPMath) {
695 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
696 ARMBuildAttrs::IEEEDenormals);
697 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
699 // If the user has permitted this code to choose the IEEE 754
700 // rounding at run-time, emit the rounding attribute.
701 if (TM.Options.HonorSignDependentRoundingFPMathOption)
702 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
704 if (!STI.hasVFP2()) {
705 // When the target doesn't have an FPU (by design or
706 // intention), the assumptions made on the software support
707 // mirror that of the equivalent hardware support *if it
708 // existed*. For v7 and better we indicate that denormals are
709 // flushed preserving sign, and for V6 we indicate that
710 // denormals are flushed to positive zero.
712 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
713 ARMBuildAttrs::PreserveFPSign);
714 } else if (STI.hasVFP3()) {
715 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
716 // the sign bit of the zero matches the sign bit of the input or
717 // result that is being flushed to zero.
718 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
719 ARMBuildAttrs::PreserveFPSign);
721 // For VFPv2 implementations it is implementation defined as
722 // to whether denormals are flushed to positive zero or to
723 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
724 // LLVM has chosen to flush this to positive zero (most likely for
725 // GCC compatibility), so that's the chosen value here (the
726 // absence of its emission implies zero).
729 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
730 // equivalent of GCC's -ffinite-math-only flag.
731 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
732 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
733 ARMBuildAttrs::Allowed);
735 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
736 ARMBuildAttrs::AllowIEE754);
738 if (STI.allowsUnalignedMem())
739 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
740 ARMBuildAttrs::Allowed);
742 ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
743 ARMBuildAttrs::Not_Allowed);
745 // FIXME: add more flags to ARMBuildAttributes.h
746 // 8-bytes alignment stuff.
747 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
748 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
750 // ABI_HardFP_use attribute to indicate single precision FP.
751 if (STI.isFPOnlySP())
752 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
753 ARMBuildAttrs::HardFPSinglePrecision);
755 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
756 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
757 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
759 // FIXME: Should we signal R9 usage?
762 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
764 // FIXME: To support emitting this build attribute as GCC does, the
765 // -mfp16-format option and associated plumbing must be
766 // supported. For now the __fp16 type is exposed by default, so this
767 // attribute should be emitted with value 1.
768 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
769 ARMBuildAttrs::FP16FormatIEEE);
771 if (STI.hasMPExtension())
772 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
774 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
775 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
776 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
777 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
778 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
779 // otherwise, the default value (AllowDIVIfExists) applies.
780 if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
781 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
784 if (const Module *SourceModule = MMI->getModule()) {
785 // ABI_PCS_wchar_t to indicate wchar_t width
786 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
787 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
788 SourceModule->getModuleFlag("wchar_size"))) {
789 int WCharWidth = WCharWidthValue->getZExtValue();
790 assert((WCharWidth == 2 || WCharWidth == 4) &&
791 "wchar_t width must be 2 or 4 bytes");
792 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
795 // ABI_enum_size to indicate enum width
796 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
797 // (all enums contain a value needing 32 bits to encode).
798 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
799 SourceModule->getModuleFlag("min_enum_size"))) {
800 int EnumWidth = EnumWidthValue->getZExtValue();
801 assert((EnumWidth == 1 || EnumWidth == 4) &&
802 "Minimum enum width must be 1 or 4 bytes");
803 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
804 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
809 // TODO: We currently only support either reserving the register, or treating
810 // it as another callee-saved register, but not as SB or a TLS pointer; It
811 // would instead be nicer to push this from the frontend as metadata, as we do
812 // for the wchar and enum size tags
813 if (STI.isR9Reserved())
814 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
816 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
818 if (STI.hasTrustZone() && STI.hasVirtualization())
819 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
820 ARMBuildAttrs::AllowTZVirtualization);
821 else if (STI.hasTrustZone())
822 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
823 ARMBuildAttrs::AllowTZ);
824 else if (STI.hasVirtualization())
825 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
826 ARMBuildAttrs::AllowVirtualization);
828 ATS.finishAttributeSection();
831 //===----------------------------------------------------------------------===//
833 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
834 unsigned LabelId, MCContext &Ctx) {
836 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
837 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
841 static MCSymbolRefExpr::VariantKind
842 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
844 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
845 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
846 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
847 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
848 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
849 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
851 llvm_unreachable("Invalid ARMCPModifier!");
854 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
855 unsigned char TargetFlags) {
856 if (Subtarget->isTargetMachO()) {
857 bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
858 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
861 return getSymbol(GV);
863 // FIXME: Remove this when Darwin transition to @GOT like syntax.
864 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
865 MachineModuleInfoMachO &MMIMachO =
866 MMI->getObjFileInfo<MachineModuleInfoMachO>();
867 MachineModuleInfoImpl::StubValueTy &StubSym =
868 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
869 : MMIMachO.getGVStubEntry(MCSym);
870 if (!StubSym.getPointer())
871 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
872 !GV->hasInternalLinkage());
874 } else if (Subtarget->isTargetCOFF()) {
875 assert(Subtarget->isTargetWindows() &&
876 "Windows is the only supported COFF target");
878 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
880 return getSymbol(GV);
882 SmallString<128> Name;
884 getNameWithPrefix(Name, GV);
886 return OutContext.GetOrCreateSymbol(Name);
887 } else if (Subtarget->isTargetELF()) {
888 return getSymbol(GV);
890 llvm_unreachable("unexpected target");
894 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
895 const DataLayout *DL = TM.getDataLayout();
896 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
898 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
901 if (ACPV->isLSDA()) {
902 MCSym = getCurExceptionSym();
903 } else if (ACPV->isBlockAddress()) {
904 const BlockAddress *BA =
905 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
906 MCSym = GetBlockAddressSymbol(BA);
907 } else if (ACPV->isGlobalValue()) {
908 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
910 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
911 // flag the global as MO_NONLAZY.
912 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
913 MCSym = GetARMGVSymbol(GV, TF);
914 } else if (ACPV->isMachineBasicBlock()) {
915 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
916 MCSym = MBB->getSymbol();
918 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
919 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
920 MCSym = GetExternalSymbolSymbol(Sym);
923 // Create an MCSymbol for the reference.
925 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
928 if (ACPV->getPCAdjustment()) {
929 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
933 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
935 MCBinaryExpr::CreateAdd(PCRelExpr,
936 MCConstantExpr::Create(ACPV->getPCAdjustment(),
939 if (ACPV->mustAddCurrentAddress()) {
940 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
941 // label, so just emit a local label end reference that instead.
942 MCSymbol *DotSym = OutContext.CreateTempSymbol();
943 OutStreamer.EmitLabel(DotSym);
944 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
945 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
947 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
949 OutStreamer.EmitValue(Expr, Size);
952 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
953 unsigned Opcode = MI->getOpcode();
955 if (Opcode == ARM::BR_JTadd)
957 else if (Opcode == ARM::BR_JTm)
960 const MachineOperand &MO1 = MI->getOperand(OpNum);
961 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
962 unsigned JTI = MO1.getIndex();
964 // Emit a label for the jump table.
965 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
966 OutStreamer.EmitLabel(JTISymbol);
968 // Mark the jump table as data-in-code.
969 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
971 // Emit each entry of the table.
972 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
973 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
974 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
976 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
977 MachineBasicBlock *MBB = JTBBs[i];
978 // Construct an MCExpr for the entry. We want a value of the form:
979 // (BasicBlockAddr - TableBeginAddr)
981 // For example, a table with entries jumping to basic blocks BB0 and BB1
984 // .word (LBB0 - LJTI_0_0)
985 // .word (LBB1 - LJTI_0_0)
986 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
988 if (TM.getRelocationModel() == Reloc::PIC_)
989 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
992 // If we're generating a table of Thumb addresses in static relocation
993 // model, we need to add one to keep interworking correctly.
994 else if (AFI->isThumbFunction())
995 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
997 OutStreamer.EmitValue(Expr, 4);
999 // Mark the end of jump table data-in-code region.
1000 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1003 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1004 unsigned Opcode = MI->getOpcode();
1005 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1006 const MachineOperand &MO1 = MI->getOperand(OpNum);
1007 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1008 unsigned JTI = MO1.getIndex();
1010 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1011 OutStreamer.EmitLabel(JTISymbol);
1013 // Emit each entry of the table.
1014 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1015 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1016 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1017 unsigned OffsetWidth = 4;
1018 if (MI->getOpcode() == ARM::t2TBB_JT) {
1020 // Mark the jump table as data-in-code.
1021 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1022 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
1024 // Mark the jump table as data-in-code.
1025 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1028 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1029 MachineBasicBlock *MBB = JTBBs[i];
1030 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1032 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1033 if (OffsetWidth == 4) {
1034 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
1035 .addExpr(MBBSymbolExpr)
1040 // Otherwise it's an offset from the dispatch instruction. Construct an
1041 // MCExpr for the entry. We want a value of the form:
1042 // (BasicBlockAddr - TableBeginAddr) / 2
1044 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1047 // .byte (LBB0 - LJTI_0_0) / 2
1048 // .byte (LBB1 - LJTI_0_0) / 2
1049 const MCExpr *Expr =
1050 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1051 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1053 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1055 OutStreamer.EmitValue(Expr, OffsetWidth);
1057 // Mark the end of jump table data-in-code region. 32-bit offsets use
1058 // actual branch instructions here, so we don't mark those as a data-region
1060 if (OffsetWidth != 4)
1061 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1064 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1065 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1066 "Only instruction which are involved into frame setup code are allowed");
1068 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
1069 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1070 const MachineFunction &MF = *MI->getParent()->getParent();
1071 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1072 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1074 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1075 unsigned Opc = MI->getOpcode();
1076 unsigned SrcReg, DstReg;
1078 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1079 // Two special cases:
1080 // 1) tPUSH does not have src/dst regs.
1081 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1082 // load. Yes, this is pretty fragile, but for now I don't see better
1084 SrcReg = DstReg = ARM::SP;
1086 SrcReg = MI->getOperand(1).getReg();
1087 DstReg = MI->getOperand(0).getReg();
1090 // Try to figure out the unwinding opcode out of src / dst regs.
1091 if (MI->mayStore()) {
1093 assert(DstReg == ARM::SP &&
1094 "Only stack pointer as a destination reg is supported");
1096 SmallVector<unsigned, 4> RegList;
1097 // Skip src & dst reg, and pred ops.
1098 unsigned StartOp = 2 + 2;
1099 // Use all the operands.
1100 unsigned NumOffset = 0;
1105 llvm_unreachable("Unsupported opcode for unwinding information");
1107 // Special case here: no src & dst reg, but two extra imp ops.
1108 StartOp = 2; NumOffset = 2;
1109 case ARM::STMDB_UPD:
1110 case ARM::t2STMDB_UPD:
1111 case ARM::VSTMDDB_UPD:
1112 assert(SrcReg == ARM::SP &&
1113 "Only stack pointer as a source reg is supported");
1114 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1116 const MachineOperand &MO = MI->getOperand(i);
1117 // Actually, there should never be any impdef stuff here. Skip it
1118 // temporary to workaround PR11902.
1119 if (MO.isImplicit())
1121 RegList.push_back(MO.getReg());
1124 case ARM::STR_PRE_IMM:
1125 case ARM::STR_PRE_REG:
1126 case ARM::t2STR_PRE:
1127 assert(MI->getOperand(2).getReg() == ARM::SP &&
1128 "Only stack pointer as a source reg is supported");
1129 RegList.push_back(SrcReg);
1132 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1133 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1135 // Changes of stack / frame pointer.
1136 if (SrcReg == ARM::SP) {
1141 llvm_unreachable("Unsupported opcode for unwinding information");
1147 Offset = -MI->getOperand(2).getImm();
1151 Offset = MI->getOperand(2).getImm();
1154 Offset = MI->getOperand(2).getImm()*4;
1158 Offset = -MI->getOperand(2).getImm()*4;
1160 case ARM::tLDRpci: {
1161 // Grab the constpool index and check, whether it corresponds to
1162 // original or cloned constpool entry.
1163 unsigned CPI = MI->getOperand(1).getIndex();
1164 const MachineConstantPool *MCP = MF.getConstantPool();
1165 if (CPI >= MCP->getConstants().size())
1166 CPI = AFI.getOriginalCPIdx(CPI);
1167 assert(CPI != -1U && "Invalid constpool index");
1169 // Derive the actual offset.
1170 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1171 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1172 // FIXME: Check for user, it should be "add" instruction!
1173 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1178 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1179 if (DstReg == FramePtr && FramePtr != ARM::SP)
1180 // Set-up of the frame pointer. Positive values correspond to "add"
1182 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1183 else if (DstReg == ARM::SP) {
1184 // Change of SP by an offset. Positive values correspond to "sub"
1186 ATS.emitPad(Offset);
1188 // Move of SP to a register. Positive values correspond to an "add"
1190 ATS.emitMovSP(DstReg, -Offset);
1193 } else if (DstReg == ARM::SP) {
1195 llvm_unreachable("Unsupported opcode for unwinding information");
1199 llvm_unreachable("Unsupported opcode for unwinding information");
1204 // Simple pseudo-instructions have their lowering (with expansion to real
1205 // instructions) auto-generated.
1206 #include "ARMGenMCPseudoLowering.inc"
1208 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1209 const DataLayout *DL = TM.getDataLayout();
1211 // If we just ended a constant pool, mark it as such.
1212 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1213 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1214 InConstantPool = false;
1217 // Emit unwinding stuff for frame-related instructions
1218 if (Subtarget->isTargetEHABICompatible() &&
1219 MI->getFlag(MachineInstr::FrameSetup))
1220 EmitUnwindingInstruction(MI);
1222 // Do any auto-generated pseudo lowerings.
1223 if (emitPseudoExpansionLowering(OutStreamer, MI))
1226 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1227 "Pseudo flag setting opcode should be expanded early");
1229 // Check for manual lowerings.
1230 unsigned Opc = MI->getOpcode();
1232 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1233 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1235 case ARM::tLEApcrel:
1236 case ARM::t2LEApcrel: {
1237 // FIXME: Need to also handle globals and externals
1238 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1239 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1240 ARM::t2LEApcrel ? ARM::t2ADR
1241 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1243 .addReg(MI->getOperand(0).getReg())
1244 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1245 // Add predicate operands.
1246 .addImm(MI->getOperand(2).getImm())
1247 .addReg(MI->getOperand(3).getReg()));
1250 case ARM::LEApcrelJT:
1251 case ARM::tLEApcrelJT:
1252 case ARM::t2LEApcrelJT: {
1253 MCSymbol *JTIPICSymbol =
1254 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1255 MI->getOperand(2).getImm());
1256 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1257 ARM::t2LEApcrelJT ? ARM::t2ADR
1258 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1260 .addReg(MI->getOperand(0).getReg())
1261 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1262 // Add predicate operands.
1263 .addImm(MI->getOperand(3).getImm())
1264 .addReg(MI->getOperand(4).getReg()));
1267 // Darwin call instructions are just normal call instructions with different
1268 // clobber semantics (they clobber R9).
1269 case ARM::BX_CALL: {
1270 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1273 // Add predicate operands.
1276 // Add 's' bit operand (always reg0 for this)
1279 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1280 .addReg(MI->getOperand(0).getReg()));
1283 case ARM::tBX_CALL: {
1284 if (Subtarget->hasV5TOps())
1285 llvm_unreachable("Expected BLX to be selected for v5t+");
1287 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1288 // that the saved lr has its LSB set correctly (the arch doesn't
1290 // So here we generate a bl to a small jump pad that does bx rN.
1291 // The jump pads are emitted after the function body.
1293 unsigned TReg = MI->getOperand(0).getReg();
1294 MCSymbol *TRegSym = nullptr;
1295 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1296 if (ThumbIndirectPads[i].first == TReg) {
1297 TRegSym = ThumbIndirectPads[i].second;
1303 TRegSym = OutContext.CreateTempSymbol();
1304 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1307 // Create a link-saving branch to the Reg Indirect Jump Pad.
1308 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
1309 // Predicate comes first here.
1310 .addImm(ARMCC::AL).addReg(0)
1311 .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
1314 case ARM::BMOVPCRX_CALL: {
1315 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1318 // Add predicate operands.
1321 // Add 's' bit operand (always reg0 for this)
1324 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1326 .addReg(MI->getOperand(0).getReg())
1327 // Add predicate operands.
1330 // Add 's' bit operand (always reg0 for this)
1334 case ARM::BMOVPCB_CALL: {
1335 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1338 // Add predicate operands.
1341 // Add 's' bit operand (always reg0 for this)
1344 const MachineOperand &Op = MI->getOperand(0);
1345 const GlobalValue *GV = Op.getGlobal();
1346 const unsigned TF = Op.getTargetFlags();
1347 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1348 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1349 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1351 // Add predicate operands.
1356 case ARM::MOVi16_ga_pcrel:
1357 case ARM::t2MOVi16_ga_pcrel: {
1359 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1360 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1362 unsigned TF = MI->getOperand(1).getTargetFlags();
1363 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1364 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1365 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1367 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1368 getFunctionNumber(),
1369 MI->getOperand(2).getImm(), OutContext);
1370 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1371 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1372 const MCExpr *PCRelExpr =
1373 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1374 MCBinaryExpr::CreateAdd(LabelSymExpr,
1375 MCConstantExpr::Create(PCAdj, OutContext),
1376 OutContext), OutContext), OutContext);
1377 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1379 // Add predicate operands.
1380 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1381 TmpInst.addOperand(MCOperand::CreateReg(0));
1382 // Add 's' bit operand (always reg0 for this)
1383 TmpInst.addOperand(MCOperand::CreateReg(0));
1384 EmitToStreamer(OutStreamer, TmpInst);
1387 case ARM::MOVTi16_ga_pcrel:
1388 case ARM::t2MOVTi16_ga_pcrel: {
1390 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1391 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1392 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1393 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1395 unsigned TF = MI->getOperand(2).getTargetFlags();
1396 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1397 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1398 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1400 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1401 getFunctionNumber(),
1402 MI->getOperand(3).getImm(), OutContext);
1403 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1404 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1405 const MCExpr *PCRelExpr =
1406 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1407 MCBinaryExpr::CreateAdd(LabelSymExpr,
1408 MCConstantExpr::Create(PCAdj, OutContext),
1409 OutContext), OutContext), OutContext);
1410 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1411 // Add predicate operands.
1412 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1413 TmpInst.addOperand(MCOperand::CreateReg(0));
1414 // Add 's' bit operand (always reg0 for this)
1415 TmpInst.addOperand(MCOperand::CreateReg(0));
1416 EmitToStreamer(OutStreamer, TmpInst);
1419 case ARM::tPICADD: {
1420 // This is a pseudo op for a label + instruction sequence, which looks like:
1423 // This adds the address of LPC0 to r0.
1426 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1427 getFunctionNumber(), MI->getOperand(2).getImm(),
1430 // Form and emit the add.
1431 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1432 .addReg(MI->getOperand(0).getReg())
1433 .addReg(MI->getOperand(0).getReg())
1435 // Add predicate operands.
1441 // This is a pseudo op for a label + instruction sequence, which looks like:
1444 // This adds the address of LPC0 to r0.
1447 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1448 getFunctionNumber(), MI->getOperand(2).getImm(),
1451 // Form and emit the add.
1452 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1453 .addReg(MI->getOperand(0).getReg())
1455 .addReg(MI->getOperand(1).getReg())
1456 // Add predicate operands.
1457 .addImm(MI->getOperand(3).getImm())
1458 .addReg(MI->getOperand(4).getReg())
1459 // Add 's' bit operand (always reg0 for this)
1470 case ARM::PICLDRSH: {
1471 // This is a pseudo op for a label + instruction sequence, which looks like:
1474 // The LCP0 label is referenced by a constant pool entry in order to get
1475 // a PC-relative address at the ldr instruction.
1478 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1479 getFunctionNumber(), MI->getOperand(2).getImm(),
1482 // Form and emit the load
1484 switch (MI->getOpcode()) {
1486 llvm_unreachable("Unexpected opcode!");
1487 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1488 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1489 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1490 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1491 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1492 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1493 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1494 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1496 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1497 .addReg(MI->getOperand(0).getReg())
1499 .addReg(MI->getOperand(1).getReg())
1501 // Add predicate operands.
1502 .addImm(MI->getOperand(3).getImm())
1503 .addReg(MI->getOperand(4).getReg()));
1507 case ARM::CONSTPOOL_ENTRY: {
1508 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1509 /// in the function. The first operand is the ID# for this instruction, the
1510 /// second is the index into the MachineConstantPool that this is, the third
1511 /// is the size in bytes of this constant pool entry.
1512 /// The required alignment is specified on the basic block holding this MI.
1513 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1514 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1516 // If this is the first entry of the pool, mark it.
1517 if (!InConstantPool) {
1518 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1519 InConstantPool = true;
1522 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1524 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1525 if (MCPE.isMachineConstantPoolEntry())
1526 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1528 EmitGlobalConstant(MCPE.Val.ConstVal);
1531 case ARM::t2BR_JT: {
1532 // Lower and emit the instruction itself, then the jump table following it.
1533 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1535 .addReg(MI->getOperand(0).getReg())
1536 // Add predicate operands.
1540 // Output the data for the jump table itself
1544 case ARM::t2TBB_JT: {
1545 // Lower and emit the instruction itself, then the jump table following it.
1546 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1548 .addReg(MI->getOperand(0).getReg())
1549 // Add predicate operands.
1553 // Output the data for the jump table itself
1555 // Make sure the next instruction is 2-byte aligned.
1559 case ARM::t2TBH_JT: {
1560 // Lower and emit the instruction itself, then the jump table following it.
1561 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1563 .addReg(MI->getOperand(0).getReg())
1564 // Add predicate operands.
1568 // Output the data for the jump table itself
1574 // Lower and emit the instruction itself, then the jump table following it.
1577 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1578 ARM::MOVr : ARM::tMOVr;
1579 TmpInst.setOpcode(Opc);
1580 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1581 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1582 // Add predicate operands.
1583 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1584 TmpInst.addOperand(MCOperand::CreateReg(0));
1585 // Add 's' bit operand (always reg0 for this)
1586 if (Opc == ARM::MOVr)
1587 TmpInst.addOperand(MCOperand::CreateReg(0));
1588 EmitToStreamer(OutStreamer, TmpInst);
1590 // Make sure the Thumb jump table is 4-byte aligned.
1591 if (Opc == ARM::tMOVr)
1594 // Output the data for the jump table itself
1599 // Lower and emit the instruction itself, then the jump table following it.
1602 if (MI->getOperand(1).getReg() == 0) {
1604 TmpInst.setOpcode(ARM::LDRi12);
1605 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1606 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1607 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1609 TmpInst.setOpcode(ARM::LDRrs);
1610 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1611 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1612 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1613 TmpInst.addOperand(MCOperand::CreateImm(0));
1615 // Add predicate operands.
1616 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1617 TmpInst.addOperand(MCOperand::CreateReg(0));
1618 EmitToStreamer(OutStreamer, TmpInst);
1620 // Output the data for the jump table itself
1624 case ARM::BR_JTadd: {
1625 // Lower and emit the instruction itself, then the jump table following it.
1626 // add pc, target, idx
1627 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1629 .addReg(MI->getOperand(0).getReg())
1630 .addReg(MI->getOperand(1).getReg())
1631 // Add predicate operands.
1634 // Add 's' bit operand (always reg0 for this)
1637 // Output the data for the jump table itself
1642 OutStreamer.EmitZeros(MI->getOperand(1).getImm());
1645 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1646 // FIXME: Remove this special case when they do.
1647 if (!Subtarget->isTargetMachO()) {
1648 //.long 0xe7ffdefe @ trap
1649 uint32_t Val = 0xe7ffdefeUL;
1650 OutStreamer.AddComment("trap");
1651 OutStreamer.EmitIntValue(Val, 4);
1656 case ARM::TRAPNaCl: {
1657 //.long 0xe7fedef0 @ trap
1658 uint32_t Val = 0xe7fedef0UL;
1659 OutStreamer.AddComment("trap");
1660 OutStreamer.EmitIntValue(Val, 4);
1664 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1665 // FIXME: Remove this special case when they do.
1666 if (!Subtarget->isTargetMachO()) {
1667 //.short 57086 @ trap
1668 uint16_t Val = 0xdefe;
1669 OutStreamer.AddComment("trap");
1670 OutStreamer.EmitIntValue(Val, 2);
1675 case ARM::t2Int_eh_sjlj_setjmp:
1676 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1677 case ARM::tInt_eh_sjlj_setjmp: {
1678 // Two incoming args: GPR:$src, GPR:$val
1681 // str $val, [$src, #4]
1686 unsigned SrcReg = MI->getOperand(0).getReg();
1687 unsigned ValReg = MI->getOperand(1).getReg();
1688 MCSymbol *Label = GetARMSJLJEHLabel();
1689 OutStreamer.AddComment("eh_setjmp begin");
1690 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1697 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1707 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1710 // The offset immediate is #4. The operand value is scaled by 4 for the
1711 // tSTR instruction.
1717 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1725 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1726 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1727 .addExpr(SymbolExpr)
1731 OutStreamer.AddComment("eh_setjmp end");
1732 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1740 OutStreamer.EmitLabel(Label);
1744 case ARM::Int_eh_sjlj_setjmp_nofp:
1745 case ARM::Int_eh_sjlj_setjmp: {
1746 // Two incoming args: GPR:$src, GPR:$val
1748 // str $val, [$src, #+4]
1752 unsigned SrcReg = MI->getOperand(0).getReg();
1753 unsigned ValReg = MI->getOperand(1).getReg();
1755 OutStreamer.AddComment("eh_setjmp begin");
1756 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1763 // 's' bit operand (always reg0 for this).
1766 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1774 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1780 // 's' bit operand (always reg0 for this).
1783 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1790 // 's' bit operand (always reg0 for this).
1793 OutStreamer.AddComment("eh_setjmp end");
1794 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1800 // 's' bit operand (always reg0 for this).
1804 case ARM::Int_eh_sjlj_longjmp: {
1805 // ldr sp, [$src, #8]
1806 // ldr $scratch, [$src, #4]
1809 unsigned SrcReg = MI->getOperand(0).getReg();
1810 unsigned ScratchReg = MI->getOperand(1).getReg();
1811 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1819 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1827 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1835 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1842 case ARM::tInt_eh_sjlj_longjmp: {
1843 // ldr $scratch, [$src, #8]
1845 // ldr $scratch, [$src, #4]
1848 unsigned SrcReg = MI->getOperand(0).getReg();
1849 unsigned ScratchReg = MI->getOperand(1).getReg();
1850 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1853 // The offset immediate is #8. The operand value is scaled by 4 for the
1854 // tLDR instruction.
1860 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1867 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1875 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1883 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1893 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1895 EmitToStreamer(OutStreamer, TmpInst);
1898 //===----------------------------------------------------------------------===//
1899 // Target Registry Stuff
1900 //===----------------------------------------------------------------------===//
1902 // Force static initialization.
1903 extern "C" void LLVMInitializeARMAsmPrinter() {
1904 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1905 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1906 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1907 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);