1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFPUName.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMTargetMachine.h"
21 #include "ARMTargetObjectFile.h"
22 #include "InstPrinter/ARMInstPrinter.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "MCTargetDesc/ARMMCExpr.h"
25 #include "llvm/ADT/SetVector.h"
26 #include "llvm/ADT/SmallString.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/IR/Type.h"
36 #include "llvm/MC/MCAsmInfo.h"
37 #include "llvm/MC/MCAssembler.h"
38 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCELFStreamer.h"
40 #include "llvm/MC/MCInst.h"
41 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCObjectStreamer.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/MC/MCStreamer.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/ARMBuildAttributes.h"
47 #include "llvm/Support/COFF.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ELF.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/TargetRegistry.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetMachine.h"
58 #define DEBUG_TYPE "asm-printer"
60 void ARMAsmPrinter::EmitFunctionBodyEnd() {
61 // Make sure to terminate any constant pools that were at the end
65 InConstantPool = false;
66 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
69 void ARMAsmPrinter::EmitFunctionEntryLabel() {
70 if (AFI->isThumbFunction()) {
71 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
72 OutStreamer.EmitThumbFunc(CurrentFnSym);
75 OutStreamer.EmitLabel(CurrentFnSym);
78 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
79 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
80 assert(Size && "C++ constructor pointer had zero size!");
82 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
83 assert(GV && "C++ constructor pointer was not a GlobalValue!");
85 const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
86 (Subtarget->isTargetELF()
87 ? MCSymbolRefExpr::VK_ARM_TARGET1
88 : MCSymbolRefExpr::VK_None),
91 OutStreamer.EmitValue(E, Size);
94 /// runOnMachineFunction - This uses the EmitInstruction()
95 /// method to print assembly for each instruction.
97 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
98 AFI = MF.getInfo<ARMFunctionInfo>();
99 MCP = MF.getConstantPool();
101 SetupMachineFunction(MF);
103 if (Subtarget->isTargetCOFF()) {
104 bool Internal = MF.getFunction()->hasInternalLinkage();
105 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
106 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
107 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
109 OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
110 OutStreamer.EmitCOFFSymbolStorageClass(Scl);
111 OutStreamer.EmitCOFFSymbolType(Type);
112 OutStreamer.EndCOFFSymbolDef();
115 // Have common code print out the function header with linkage info etc.
116 EmitFunctionHeader();
118 // Emit the rest of the function body.
121 // We didn't modify anything.
125 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
126 raw_ostream &O, const char *Modifier) {
127 const MachineOperand &MO = MI->getOperand(OpNum);
128 unsigned TF = MO.getTargetFlags();
130 switch (MO.getType()) {
131 default: llvm_unreachable("<unknown operand type>");
132 case MachineOperand::MO_Register: {
133 unsigned Reg = MO.getReg();
134 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
135 assert(!MO.getSubReg() && "Subregs should be eliminated!");
136 if(ARM::GPRPairRegClass.contains(Reg)) {
137 const MachineFunction &MF = *MI->getParent()->getParent();
138 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
139 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
141 O << ARMInstPrinter::getRegisterName(Reg);
144 case MachineOperand::MO_Immediate: {
145 int64_t Imm = MO.getImm();
147 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
148 (TF == ARMII::MO_LO16))
150 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
151 (TF == ARMII::MO_HI16))
156 case MachineOperand::MO_MachineBasicBlock:
157 O << *MO.getMBB()->getSymbol();
159 case MachineOperand::MO_GlobalAddress: {
160 const GlobalValue *GV = MO.getGlobal();
161 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
162 (TF & ARMII::MO_LO16))
164 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
165 (TF & ARMII::MO_HI16))
169 printOffset(MO.getOffset(), O);
170 if (TF == ARMII::MO_PLT)
174 case MachineOperand::MO_ConstantPoolIndex:
175 O << *GetCPISymbol(MO.getIndex());
180 //===--------------------------------------------------------------------===//
182 MCSymbol *ARMAsmPrinter::
183 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
184 const DataLayout *DL = TM.getDataLayout();
185 SmallString<60> Name;
186 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
187 << getFunctionNumber() << '_' << uid << '_' << uid2;
188 return OutContext.GetOrCreateSymbol(Name.str());
192 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
193 const DataLayout *DL = TM.getDataLayout();
194 SmallString<60> Name;
195 raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
196 << getFunctionNumber();
197 return OutContext.GetOrCreateSymbol(Name.str());
200 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
201 unsigned AsmVariant, const char *ExtraCode,
203 // Does this asm operand have a single letter operand modifier?
204 if (ExtraCode && ExtraCode[0]) {
205 if (ExtraCode[1] != 0) return true; // Unknown modifier.
207 switch (ExtraCode[0]) {
209 // See if this is a generic print operand
210 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
211 case 'a': // Print as a memory address.
212 if (MI->getOperand(OpNum).isReg()) {
214 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
219 case 'c': // Don't print "#" before an immediate operand.
220 if (!MI->getOperand(OpNum).isImm())
222 O << MI->getOperand(OpNum).getImm();
224 case 'P': // Print a VFP double precision register.
225 case 'q': // Print a NEON quad precision register.
226 printOperand(MI, OpNum, O);
228 case 'y': // Print a VFP single precision register as indexed double.
229 if (MI->getOperand(OpNum).isReg()) {
230 unsigned Reg = MI->getOperand(OpNum).getReg();
231 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
232 // Find the 'd' register that has this 's' register as a sub-register,
233 // and determine the lane number.
234 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
235 if (!ARM::DPRRegClass.contains(*SR))
237 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
238 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
243 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
244 if (!MI->getOperand(OpNum).isImm())
246 O << ~(MI->getOperand(OpNum).getImm());
248 case 'L': // The low 16 bits of an immediate constant.
249 if (!MI->getOperand(OpNum).isImm())
251 O << (MI->getOperand(OpNum).getImm() & 0xffff);
253 case 'M': { // A register range suitable for LDM/STM.
254 if (!MI->getOperand(OpNum).isReg())
256 const MachineOperand &MO = MI->getOperand(OpNum);
257 unsigned RegBegin = MO.getReg();
258 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
259 // already got the operands in registers that are operands to the
260 // inline asm statement.
262 if (ARM::GPRPairRegClass.contains(RegBegin)) {
263 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
264 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
265 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
266 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
268 O << ARMInstPrinter::getRegisterName(RegBegin);
270 // FIXME: The register allocator not only may not have given us the
271 // registers in sequence, but may not be in ascending registers. This
272 // will require changes in the register allocator that'll need to be
273 // propagated down here if the operands change.
274 unsigned RegOps = OpNum + 1;
275 while (MI->getOperand(RegOps).isReg()) {
277 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
285 case 'R': // The most significant register of a pair.
286 case 'Q': { // The least significant register of a pair.
289 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
290 if (!FlagsOP.isImm())
292 unsigned Flags = FlagsOP.getImm();
294 // This operand may not be the one that actually provides the register. If
295 // it's tied to a previous one then we should refer instead to that one
296 // for registers and their classes.
298 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
299 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
300 unsigned OpFlags = MI->getOperand(OpNum).getImm();
301 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
303 Flags = MI->getOperand(OpNum).getImm();
305 // Later code expects OpNum to be pointing at the register rather than
310 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
312 InlineAsm::hasRegClassConstraint(Flags, RC);
313 if (RC == ARM::GPRPairRegClassID) {
316 const MachineOperand &MO = MI->getOperand(OpNum);
319 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
320 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
321 ARM::gsub_0 : ARM::gsub_1);
322 O << ARMInstPrinter::getRegisterName(Reg);
327 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
328 if (RegOp >= MI->getNumOperands())
330 const MachineOperand &MO = MI->getOperand(RegOp);
333 unsigned Reg = MO.getReg();
334 O << ARMInstPrinter::getRegisterName(Reg);
338 case 'e': // The low doubleword register of a NEON quad register.
339 case 'f': { // The high doubleword register of a NEON quad register.
340 if (!MI->getOperand(OpNum).isReg())
342 unsigned Reg = MI->getOperand(OpNum).getReg();
343 if (!ARM::QPRRegClass.contains(Reg))
345 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
346 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
347 ARM::dsub_0 : ARM::dsub_1);
348 O << ARMInstPrinter::getRegisterName(SubReg);
352 // This modifier is not yet supported.
353 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
355 case 'H': { // The highest-numbered register of a pair.
356 const MachineOperand &MO = MI->getOperand(OpNum);
359 const MachineFunction &MF = *MI->getParent()->getParent();
360 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
361 unsigned Reg = MO.getReg();
362 if(!ARM::GPRPairRegClass.contains(Reg))
364 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
365 O << ARMInstPrinter::getRegisterName(Reg);
371 printOperand(MI, OpNum, O);
375 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
376 unsigned OpNum, unsigned AsmVariant,
377 const char *ExtraCode,
379 // Does this asm operand have a single letter operand modifier?
380 if (ExtraCode && ExtraCode[0]) {
381 if (ExtraCode[1] != 0) return true; // Unknown modifier.
383 switch (ExtraCode[0]) {
384 case 'A': // A memory operand for a VLD1/VST1 instruction.
385 default: return true; // Unknown modifier.
386 case 'm': // The base register of a memory operand.
387 if (!MI->getOperand(OpNum).isReg())
389 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
394 const MachineOperand &MO = MI->getOperand(OpNum);
395 assert(MO.isReg() && "unexpected inline asm memory operand");
396 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
400 static bool isThumb(const MCSubtargetInfo& STI) {
401 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
404 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
405 const MCSubtargetInfo *EndInfo) const {
406 // If either end mode is unknown (EndInfo == NULL) or different than
407 // the start mode, then restore the start mode.
408 const bool WasThumb = isThumb(StartInfo);
409 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
410 OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
414 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
415 if (Subtarget->isTargetMachO()) {
416 Reloc::Model RelocM = TM.getRelocationModel();
417 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
418 // Declare all the text sections up front (before the DWARF sections
419 // emitted by AsmPrinter::doInitialization) so the assembler will keep
420 // them together at the beginning of the object file. This helps
421 // avoid out-of-range branches that are due a fundamental limitation of
422 // the way symbol offsets are encoded with the current Darwin ARM
424 const TargetLoweringObjectFileMachO &TLOFMacho =
425 static_cast<const TargetLoweringObjectFileMachO &>(
426 getObjFileLowering());
428 // Collect the set of sections our functions will go into.
429 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
430 SmallPtrSet<const MCSection *, 8> > TextSections;
431 // Default text section comes first.
432 TextSections.insert(TLOFMacho.getTextSection());
433 // Now any user defined text sections from function attributes.
434 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
435 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
436 TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
437 // Now the coalescable sections.
438 TextSections.insert(TLOFMacho.getTextCoalSection());
439 TextSections.insert(TLOFMacho.getConstTextCoalSection());
441 // Emit the sections in the .s file header to fix the order.
442 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
443 OutStreamer.SwitchSection(TextSections[i]);
445 if (RelocM == Reloc::DynamicNoPIC) {
446 const MCSection *sect =
447 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
448 MachO::S_SYMBOL_STUBS,
449 12, SectionKind::getText());
450 OutStreamer.SwitchSection(sect);
452 const MCSection *sect =
453 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
454 MachO::S_SYMBOL_STUBS,
455 16, SectionKind::getText());
456 OutStreamer.SwitchSection(sect);
458 const MCSection *StaticInitSect =
459 OutContext.getMachOSection("__TEXT", "__StaticInit",
461 MachO::S_ATTR_PURE_INSTRUCTIONS,
462 SectionKind::getText());
463 OutStreamer.SwitchSection(StaticInitSect);
466 // Compiling with debug info should not affect the code
467 // generation. Ensure the cstring section comes before the
468 // optional __DWARF secion. Otherwise, PC-relative loads would
469 // have to use different instruction sequences at "-g" in order to
470 // reach global data in the same object file.
471 OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
474 // Use unified assembler syntax.
475 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
477 // Emit ARM Build Attributes
478 if (Subtarget->isTargetELF())
483 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
484 MachineModuleInfoImpl::StubValueTy &MCSym) {
486 OutStreamer.EmitLabel(StubLabel);
487 // .indirect_symbol _foo
488 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
491 // External to current translation unit.
492 OutStreamer.EmitIntValue(0, 4/*size*/);
494 // Internal to current translation unit.
496 // When we place the LSDA into the TEXT section, the type info
497 // pointers need to be indirect and pc-rel. We accomplish this by
498 // using NLPs; however, sometimes the types are local to the file.
499 // We need to fill in the value for the NLP in those cases.
500 OutStreamer.EmitValue(
501 MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
506 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
507 if (Subtarget->isTargetMachO()) {
508 // All darwin targets use mach-o.
509 const TargetLoweringObjectFileMachO &TLOFMacho =
510 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
511 MachineModuleInfoMachO &MMIMacho =
512 MMI->getObjFileInfo<MachineModuleInfoMachO>();
514 // Output non-lazy-pointers for external and common global variables.
515 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
517 if (!Stubs.empty()) {
518 // Switch with ".non_lazy_symbol_pointer" directive.
519 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
522 for (auto &Stub : Stubs)
523 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
526 OutStreamer.AddBlankLine();
529 Stubs = MMIMacho.GetHiddenGVStubList();
530 if (!Stubs.empty()) {
531 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
534 for (auto &Stub : Stubs)
535 emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
538 OutStreamer.AddBlankLine();
541 // Funny Darwin hack: This flag tells the linker that no global symbols
542 // contain code that falls through to other global symbols (e.g. the obvious
543 // implementation of multiple entry points). If this doesn't occur, the
544 // linker can safely perform dead code stripping. Since LLVM never
545 // generates code that does this, it is always safe to set.
546 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
549 // Emit a .data.rel section containing any stubs that were created.
550 if (Subtarget->isTargetELF()) {
551 const TargetLoweringObjectFileELF &TLOFELF =
552 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
554 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
556 // Output stubs for external and common global variables.
557 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
558 if (!Stubs.empty()) {
559 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
560 const DataLayout *TD = TM.getDataLayout();
562 for (auto &stub: Stubs) {
563 OutStreamer.EmitLabel(stub.first);
564 OutStreamer.EmitSymbolValue(stub.second.getPointer(),
565 TD->getPointerSize(0));
572 //===----------------------------------------------------------------------===//
573 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
575 // The following seem like one-off assembler flags, but they actually need
576 // to appear in the .ARM.attributes section in ELF.
577 // Instead of subclassing the MCELFStreamer, we do the work here.
579 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
580 const ARMSubtarget *Subtarget) {
582 return ARMBuildAttrs::v5TEJ;
584 if (Subtarget->hasV8Ops())
585 return ARMBuildAttrs::v8;
586 else if (Subtarget->hasV7Ops()) {
587 if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
588 return ARMBuildAttrs::v7E_M;
589 return ARMBuildAttrs::v7;
590 } else if (Subtarget->hasV6T2Ops())
591 return ARMBuildAttrs::v6T2;
592 else if (Subtarget->hasV6MOps())
593 return ARMBuildAttrs::v6S_M;
594 else if (Subtarget->hasV6Ops())
595 return ARMBuildAttrs::v6;
596 else if (Subtarget->hasV5TEOps())
597 return ARMBuildAttrs::v5TE;
598 else if (Subtarget->hasV5TOps())
599 return ARMBuildAttrs::v5T;
600 else if (Subtarget->hasV4TOps())
601 return ARMBuildAttrs::v4T;
603 return ARMBuildAttrs::v4;
606 void ARMAsmPrinter::emitAttributes() {
607 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
608 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
610 ATS.switchVendor("aeabi");
612 std::string CPUString = Subtarget->getCPUString();
614 // FIXME: remove krait check when GNU tools support krait cpu
615 if (CPUString != "generic" && CPUString != "krait")
616 ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
618 ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
619 getArchForCPU(CPUString, Subtarget));
621 // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
622 // profile is not applicable (e.g. pre v7, or cross-profile code)".
623 if (Subtarget->hasV7Ops()) {
624 if (Subtarget->isAClass()) {
625 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
626 ARMBuildAttrs::ApplicationProfile);
627 } else if (Subtarget->isRClass()) {
628 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
629 ARMBuildAttrs::RealTimeProfile);
630 } else if (Subtarget->isMClass()) {
631 ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
632 ARMBuildAttrs::MicroControllerProfile);
636 ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
637 ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
638 if (Subtarget->isThumb1Only()) {
639 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
640 ARMBuildAttrs::Allowed);
641 } else if (Subtarget->hasThumb2()) {
642 ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
643 ARMBuildAttrs::AllowThumb32);
646 if (Subtarget->hasNEON()) {
647 /* NEON is not exactly a VFP architecture, but GAS emit one of
648 * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
649 if (Subtarget->hasFPARMv8()) {
650 if (Subtarget->hasCrypto())
651 ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
653 ATS.emitFPU(ARM::NEON_FP_ARMV8);
655 else if (Subtarget->hasVFP4())
656 ATS.emitFPU(ARM::NEON_VFPV4);
658 ATS.emitFPU(ARM::NEON);
659 // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
660 if (Subtarget->hasV8Ops())
661 ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
662 ARMBuildAttrs::AllowNeonARMv8);
664 if (Subtarget->hasFPARMv8())
665 ATS.emitFPU(ARM::FP_ARMV8);
666 else if (Subtarget->hasVFP4())
667 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
668 else if (Subtarget->hasVFP3())
669 ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
670 else if (Subtarget->hasVFP2())
671 ATS.emitFPU(ARM::VFPV2);
674 // Signal various FP modes.
675 if (!TM.Options.UnsafeFPMath) {
676 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
677 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
678 ARMBuildAttrs::Allowed);
681 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
682 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
683 ARMBuildAttrs::Allowed);
685 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
686 ARMBuildAttrs::AllowIEE754);
688 // FIXME: add more flags to ARMBuildAttributes.h
689 // 8-bytes alignment stuff.
690 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
691 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
693 // ABI_HardFP_use attribute to indicate single precision FP.
694 if (Subtarget->isFPOnlySP())
695 ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
696 ARMBuildAttrs::HardFPSinglePrecision);
698 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
699 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
700 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
702 // FIXME: Should we signal R9 usage?
704 if (Subtarget->hasFP16())
705 ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
707 if (Subtarget->hasMPExtension())
708 ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
710 // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
711 // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
712 // It is not possible to produce DisallowDIV: if hwdiv is present in the base
713 // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
714 // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
715 // otherwise, the default value (AllowDIVIfExists) applies.
716 if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
717 ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
719 if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
720 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
721 ARMBuildAttrs::AllowTZVirtualization);
722 else if (Subtarget->hasTrustZone())
723 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
724 ARMBuildAttrs::AllowTZ);
725 else if (Subtarget->hasVirtualization())
726 ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
727 ARMBuildAttrs::AllowVirtualization);
729 ATS.finishAttributeSection();
732 //===----------------------------------------------------------------------===//
734 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
735 unsigned LabelId, MCContext &Ctx) {
737 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
738 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
742 static MCSymbolRefExpr::VariantKind
743 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
745 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
746 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
747 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_TPOFF;
748 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_GOTTPOFF;
749 case ARMCP::GOT: return MCSymbolRefExpr::VK_GOT;
750 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_GOTOFF;
752 llvm_unreachable("Invalid ARMCPModifier!");
755 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
756 unsigned char TargetFlags) {
757 bool isIndirect = Subtarget->isTargetMachO() &&
758 (TargetFlags & ARMII::MO_NONLAZY) &&
759 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
761 return getSymbol(GV);
763 // FIXME: Remove this when Darwin transition to @GOT like syntax.
764 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
765 MachineModuleInfoMachO &MMIMachO =
766 MMI->getObjFileInfo<MachineModuleInfoMachO>();
767 MachineModuleInfoImpl::StubValueTy &StubSym =
768 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
769 MMIMachO.getGVStubEntry(MCSym);
770 if (!StubSym.getPointer())
771 StubSym = MachineModuleInfoImpl::
772 StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
777 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
778 const DataLayout *DL = TM.getDataLayout();
779 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
781 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
784 if (ACPV->isLSDA()) {
785 SmallString<128> Str;
786 raw_svector_ostream OS(Str);
787 OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
788 MCSym = OutContext.GetOrCreateSymbol(OS.str());
789 } else if (ACPV->isBlockAddress()) {
790 const BlockAddress *BA =
791 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
792 MCSym = GetBlockAddressSymbol(BA);
793 } else if (ACPV->isGlobalValue()) {
794 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
796 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
797 // flag the global as MO_NONLAZY.
798 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
799 MCSym = GetARMGVSymbol(GV, TF);
800 } else if (ACPV->isMachineBasicBlock()) {
801 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
802 MCSym = MBB->getSymbol();
804 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
805 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
806 MCSym = GetExternalSymbolSymbol(Sym);
809 // Create an MCSymbol for the reference.
811 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
814 if (ACPV->getPCAdjustment()) {
815 MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
819 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
821 MCBinaryExpr::CreateAdd(PCRelExpr,
822 MCConstantExpr::Create(ACPV->getPCAdjustment(),
825 if (ACPV->mustAddCurrentAddress()) {
826 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
827 // label, so just emit a local label end reference that instead.
828 MCSymbol *DotSym = OutContext.CreateTempSymbol();
829 OutStreamer.EmitLabel(DotSym);
830 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
831 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
833 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
835 OutStreamer.EmitValue(Expr, Size);
838 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
839 unsigned Opcode = MI->getOpcode();
841 if (Opcode == ARM::BR_JTadd)
843 else if (Opcode == ARM::BR_JTm)
846 const MachineOperand &MO1 = MI->getOperand(OpNum);
847 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
848 unsigned JTI = MO1.getIndex();
850 // Emit a label for the jump table.
851 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
852 OutStreamer.EmitLabel(JTISymbol);
854 // Mark the jump table as data-in-code.
855 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
857 // Emit each entry of the table.
858 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
859 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
860 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
862 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
863 MachineBasicBlock *MBB = JTBBs[i];
864 // Construct an MCExpr for the entry. We want a value of the form:
865 // (BasicBlockAddr - TableBeginAddr)
867 // For example, a table with entries jumping to basic blocks BB0 and BB1
870 // .word (LBB0 - LJTI_0_0)
871 // .word (LBB1 - LJTI_0_0)
872 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
874 if (TM.getRelocationModel() == Reloc::PIC_)
875 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
878 // If we're generating a table of Thumb addresses in static relocation
879 // model, we need to add one to keep interworking correctly.
880 else if (AFI->isThumbFunction())
881 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
883 OutStreamer.EmitValue(Expr, 4);
885 // Mark the end of jump table data-in-code region.
886 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
889 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
890 unsigned Opcode = MI->getOpcode();
891 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
892 const MachineOperand &MO1 = MI->getOperand(OpNum);
893 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
894 unsigned JTI = MO1.getIndex();
896 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
897 OutStreamer.EmitLabel(JTISymbol);
899 // Emit each entry of the table.
900 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
901 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
902 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
903 unsigned OffsetWidth = 4;
904 if (MI->getOpcode() == ARM::t2TBB_JT) {
906 // Mark the jump table as data-in-code.
907 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
908 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
910 // Mark the jump table as data-in-code.
911 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
914 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
915 MachineBasicBlock *MBB = JTBBs[i];
916 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
918 // If this isn't a TBB or TBH, the entries are direct branch instructions.
919 if (OffsetWidth == 4) {
920 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
921 .addExpr(MBBSymbolExpr)
926 // Otherwise it's an offset from the dispatch instruction. Construct an
927 // MCExpr for the entry. We want a value of the form:
928 // (BasicBlockAddr - TableBeginAddr) / 2
930 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
933 // .byte (LBB0 - LJTI_0_0) / 2
934 // .byte (LBB1 - LJTI_0_0) / 2
936 MCBinaryExpr::CreateSub(MBBSymbolExpr,
937 MCSymbolRefExpr::Create(JTISymbol, OutContext),
939 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
941 OutStreamer.EmitValue(Expr, OffsetWidth);
943 // Mark the end of jump table data-in-code region. 32-bit offsets use
944 // actual branch instructions here, so we don't mark those as a data-region
946 if (OffsetWidth != 4)
947 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
950 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
951 assert(MI->getFlag(MachineInstr::FrameSetup) &&
952 "Only instruction which are involved into frame setup code are allowed");
954 MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
955 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
956 const MachineFunction &MF = *MI->getParent()->getParent();
957 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
958 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
960 unsigned FramePtr = RegInfo->getFrameRegister(MF);
961 unsigned Opc = MI->getOpcode();
962 unsigned SrcReg, DstReg;
964 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
965 // Two special cases:
966 // 1) tPUSH does not have src/dst regs.
967 // 2) for Thumb1 code we sometimes materialize the constant via constpool
968 // load. Yes, this is pretty fragile, but for now I don't see better
970 SrcReg = DstReg = ARM::SP;
972 SrcReg = MI->getOperand(1).getReg();
973 DstReg = MI->getOperand(0).getReg();
976 // Try to figure out the unwinding opcode out of src / dst regs.
977 if (MI->mayStore()) {
979 assert(DstReg == ARM::SP &&
980 "Only stack pointer as a destination reg is supported");
982 SmallVector<unsigned, 4> RegList;
983 // Skip src & dst reg, and pred ops.
984 unsigned StartOp = 2 + 2;
985 // Use all the operands.
986 unsigned NumOffset = 0;
991 llvm_unreachable("Unsupported opcode for unwinding information");
993 // Special case here: no src & dst reg, but two extra imp ops.
994 StartOp = 2; NumOffset = 2;
996 case ARM::t2STMDB_UPD:
997 case ARM::VSTMDDB_UPD:
998 assert(SrcReg == ARM::SP &&
999 "Only stack pointer as a source reg is supported");
1000 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1002 const MachineOperand &MO = MI->getOperand(i);
1003 // Actually, there should never be any impdef stuff here. Skip it
1004 // temporary to workaround PR11902.
1005 if (MO.isImplicit())
1007 RegList.push_back(MO.getReg());
1010 case ARM::STR_PRE_IMM:
1011 case ARM::STR_PRE_REG:
1012 case ARM::t2STR_PRE:
1013 assert(MI->getOperand(2).getReg() == ARM::SP &&
1014 "Only stack pointer as a source reg is supported");
1015 RegList.push_back(SrcReg);
1018 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1019 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1021 // Changes of stack / frame pointer.
1022 if (SrcReg == ARM::SP) {
1027 llvm_unreachable("Unsupported opcode for unwinding information");
1033 Offset = -MI->getOperand(2).getImm();
1037 Offset = MI->getOperand(2).getImm();
1040 Offset = MI->getOperand(2).getImm()*4;
1044 Offset = -MI->getOperand(2).getImm()*4;
1046 case ARM::tLDRpci: {
1047 // Grab the constpool index and check, whether it corresponds to
1048 // original or cloned constpool entry.
1049 unsigned CPI = MI->getOperand(1).getIndex();
1050 const MachineConstantPool *MCP = MF.getConstantPool();
1051 if (CPI >= MCP->getConstants().size())
1052 CPI = AFI.getOriginalCPIdx(CPI);
1053 assert(CPI != -1U && "Invalid constpool index");
1055 // Derive the actual offset.
1056 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1057 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1058 // FIXME: Check for user, it should be "add" instruction!
1059 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1064 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1065 if (DstReg == FramePtr && FramePtr != ARM::SP)
1066 // Set-up of the frame pointer. Positive values correspond to "add"
1068 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1069 else if (DstReg == ARM::SP) {
1070 // Change of SP by an offset. Positive values correspond to "sub"
1072 ATS.emitPad(Offset);
1074 // Move of SP to a register. Positive values correspond to an "add"
1076 ATS.emitMovSP(DstReg, -Offset);
1079 } else if (DstReg == ARM::SP) {
1081 llvm_unreachable("Unsupported opcode for unwinding information");
1085 llvm_unreachable("Unsupported opcode for unwinding information");
1090 // Simple pseudo-instructions have their lowering (with expansion to real
1091 // instructions) auto-generated.
1092 #include "ARMGenMCPseudoLowering.inc"
1094 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1095 const DataLayout *DL = TM.getDataLayout();
1097 // If we just ended a constant pool, mark it as such.
1098 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1099 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1100 InConstantPool = false;
1103 // Emit unwinding stuff for frame-related instructions
1104 if (Subtarget->isTargetEHABICompatible() &&
1105 MI->getFlag(MachineInstr::FrameSetup))
1106 EmitUnwindingInstruction(MI);
1108 // Do any auto-generated pseudo lowerings.
1109 if (emitPseudoExpansionLowering(OutStreamer, MI))
1112 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1113 "Pseudo flag setting opcode should be expanded early");
1115 // Check for manual lowerings.
1116 unsigned Opc = MI->getOpcode();
1118 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1119 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1121 case ARM::tLEApcrel:
1122 case ARM::t2LEApcrel: {
1123 // FIXME: Need to also handle globals and externals
1124 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1125 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1126 ARM::t2LEApcrel ? ARM::t2ADR
1127 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1129 .addReg(MI->getOperand(0).getReg())
1130 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1131 // Add predicate operands.
1132 .addImm(MI->getOperand(2).getImm())
1133 .addReg(MI->getOperand(3).getReg()));
1136 case ARM::LEApcrelJT:
1137 case ARM::tLEApcrelJT:
1138 case ARM::t2LEApcrelJT: {
1139 MCSymbol *JTIPICSymbol =
1140 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1141 MI->getOperand(2).getImm());
1142 EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
1143 ARM::t2LEApcrelJT ? ARM::t2ADR
1144 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1146 .addReg(MI->getOperand(0).getReg())
1147 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1148 // Add predicate operands.
1149 .addImm(MI->getOperand(3).getImm())
1150 .addReg(MI->getOperand(4).getReg()));
1153 // Darwin call instructions are just normal call instructions with different
1154 // clobber semantics (they clobber R9).
1155 case ARM::BX_CALL: {
1156 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1159 // Add predicate operands.
1162 // Add 's' bit operand (always reg0 for this)
1165 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1166 .addReg(MI->getOperand(0).getReg()));
1169 case ARM::tBX_CALL: {
1170 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1173 // Add predicate operands.
1177 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1178 .addReg(MI->getOperand(0).getReg())
1179 // Add predicate operands.
1184 case ARM::BMOVPCRX_CALL: {
1185 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1188 // Add predicate operands.
1191 // Add 's' bit operand (always reg0 for this)
1194 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1196 .addReg(MI->getOperand(0).getReg())
1197 // Add predicate operands.
1200 // Add 's' bit operand (always reg0 for this)
1204 case ARM::BMOVPCB_CALL: {
1205 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
1208 // Add predicate operands.
1211 // Add 's' bit operand (always reg0 for this)
1214 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1215 MCSymbol *GVSym = getSymbol(GV);
1216 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1217 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
1219 // Add predicate operands.
1224 case ARM::MOVi16_ga_pcrel:
1225 case ARM::t2MOVi16_ga_pcrel: {
1227 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1228 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1230 unsigned TF = MI->getOperand(1).getTargetFlags();
1231 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1232 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1233 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1235 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1236 getFunctionNumber(),
1237 MI->getOperand(2).getImm(), OutContext);
1238 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1239 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1240 const MCExpr *PCRelExpr =
1241 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1242 MCBinaryExpr::CreateAdd(LabelSymExpr,
1243 MCConstantExpr::Create(PCAdj, OutContext),
1244 OutContext), OutContext), OutContext);
1245 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1247 // Add predicate operands.
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 // Add 's' bit operand (always reg0 for this)
1251 TmpInst.addOperand(MCOperand::CreateReg(0));
1252 EmitToStreamer(OutStreamer, TmpInst);
1255 case ARM::MOVTi16_ga_pcrel:
1256 case ARM::t2MOVTi16_ga_pcrel: {
1258 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1259 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1260 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1261 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1263 unsigned TF = MI->getOperand(2).getTargetFlags();
1264 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1265 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1266 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1268 MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
1269 getFunctionNumber(),
1270 MI->getOperand(3).getImm(), OutContext);
1271 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1272 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1273 const MCExpr *PCRelExpr =
1274 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1275 MCBinaryExpr::CreateAdd(LabelSymExpr,
1276 MCConstantExpr::Create(PCAdj, OutContext),
1277 OutContext), OutContext), OutContext);
1278 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1279 // Add predicate operands.
1280 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1281 TmpInst.addOperand(MCOperand::CreateReg(0));
1282 // Add 's' bit operand (always reg0 for this)
1283 TmpInst.addOperand(MCOperand::CreateReg(0));
1284 EmitToStreamer(OutStreamer, TmpInst);
1287 case ARM::tPICADD: {
1288 // This is a pseudo op for a label + instruction sequence, which looks like:
1291 // This adds the address of LPC0 to r0.
1294 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1295 getFunctionNumber(), MI->getOperand(2).getImm(),
1298 // Form and emit the add.
1299 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
1300 .addReg(MI->getOperand(0).getReg())
1301 .addReg(MI->getOperand(0).getReg())
1303 // Add predicate operands.
1309 // This is a pseudo op for a label + instruction sequence, which looks like:
1312 // This adds the address of LPC0 to r0.
1315 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1316 getFunctionNumber(), MI->getOperand(2).getImm(),
1319 // Form and emit the add.
1320 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1321 .addReg(MI->getOperand(0).getReg())
1323 .addReg(MI->getOperand(1).getReg())
1324 // Add predicate operands.
1325 .addImm(MI->getOperand(3).getImm())
1326 .addReg(MI->getOperand(4).getReg())
1327 // Add 's' bit operand (always reg0 for this)
1338 case ARM::PICLDRSH: {
1339 // This is a pseudo op for a label + instruction sequence, which looks like:
1342 // The LCP0 label is referenced by a constant pool entry in order to get
1343 // a PC-relative address at the ldr instruction.
1346 OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
1347 getFunctionNumber(), MI->getOperand(2).getImm(),
1350 // Form and emit the load
1352 switch (MI->getOpcode()) {
1354 llvm_unreachable("Unexpected opcode!");
1355 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1356 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1357 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1358 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1359 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1360 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1361 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1362 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1364 EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
1365 .addReg(MI->getOperand(0).getReg())
1367 .addReg(MI->getOperand(1).getReg())
1369 // Add predicate operands.
1370 .addImm(MI->getOperand(3).getImm())
1371 .addReg(MI->getOperand(4).getReg()));
1375 case ARM::CONSTPOOL_ENTRY: {
1376 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1377 /// in the function. The first operand is the ID# for this instruction, the
1378 /// second is the index into the MachineConstantPool that this is, the third
1379 /// is the size in bytes of this constant pool entry.
1380 /// The required alignment is specified on the basic block holding this MI.
1381 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1382 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1384 // If this is the first entry of the pool, mark it.
1385 if (!InConstantPool) {
1386 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1387 InConstantPool = true;
1390 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1392 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1393 if (MCPE.isMachineConstantPoolEntry())
1394 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1396 EmitGlobalConstant(MCPE.Val.ConstVal);
1399 case ARM::t2BR_JT: {
1400 // Lower and emit the instruction itself, then the jump table following it.
1401 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1403 .addReg(MI->getOperand(0).getReg())
1404 // Add predicate operands.
1408 // Output the data for the jump table itself
1412 case ARM::t2TBB_JT: {
1413 // Lower and emit the instruction itself, then the jump table following it.
1414 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
1416 .addReg(MI->getOperand(0).getReg())
1417 // Add predicate operands.
1421 // Output the data for the jump table itself
1423 // Make sure the next instruction is 2-byte aligned.
1427 case ARM::t2TBH_JT: {
1428 // Lower and emit the instruction itself, then the jump table following it.
1429 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
1431 .addReg(MI->getOperand(0).getReg())
1432 // Add predicate operands.
1436 // Output the data for the jump table itself
1442 // Lower and emit the instruction itself, then the jump table following it.
1445 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1446 ARM::MOVr : ARM::tMOVr;
1447 TmpInst.setOpcode(Opc);
1448 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1449 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1450 // Add predicate operands.
1451 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1452 TmpInst.addOperand(MCOperand::CreateReg(0));
1453 // Add 's' bit operand (always reg0 for this)
1454 if (Opc == ARM::MOVr)
1455 TmpInst.addOperand(MCOperand::CreateReg(0));
1456 EmitToStreamer(OutStreamer, TmpInst);
1458 // Make sure the Thumb jump table is 4-byte aligned.
1459 if (Opc == ARM::tMOVr)
1462 // Output the data for the jump table itself
1467 // Lower and emit the instruction itself, then the jump table following it.
1470 if (MI->getOperand(1).getReg() == 0) {
1472 TmpInst.setOpcode(ARM::LDRi12);
1473 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1474 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1475 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1477 TmpInst.setOpcode(ARM::LDRrs);
1478 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1479 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1480 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1481 TmpInst.addOperand(MCOperand::CreateImm(0));
1483 // Add predicate operands.
1484 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1485 TmpInst.addOperand(MCOperand::CreateReg(0));
1486 EmitToStreamer(OutStreamer, TmpInst);
1488 // Output the data for the jump table itself
1492 case ARM::BR_JTadd: {
1493 // Lower and emit the instruction itself, then the jump table following it.
1494 // add pc, target, idx
1495 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
1497 .addReg(MI->getOperand(0).getReg())
1498 .addReg(MI->getOperand(1).getReg())
1499 // Add predicate operands.
1502 // Add 's' bit operand (always reg0 for this)
1505 // Output the data for the jump table itself
1510 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1511 // FIXME: Remove this special case when they do.
1512 if (!Subtarget->isTargetMachO()) {
1513 //.long 0xe7ffdefe @ trap
1514 uint32_t Val = 0xe7ffdefeUL;
1515 OutStreamer.AddComment("trap");
1516 OutStreamer.EmitIntValue(Val, 4);
1521 case ARM::TRAPNaCl: {
1522 //.long 0xe7fedef0 @ trap
1523 uint32_t Val = 0xe7fedef0UL;
1524 OutStreamer.AddComment("trap");
1525 OutStreamer.EmitIntValue(Val, 4);
1529 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1530 // FIXME: Remove this special case when they do.
1531 if (!Subtarget->isTargetMachO()) {
1532 //.short 57086 @ trap
1533 uint16_t Val = 0xdefe;
1534 OutStreamer.AddComment("trap");
1535 OutStreamer.EmitIntValue(Val, 2);
1540 case ARM::t2Int_eh_sjlj_setjmp:
1541 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1542 case ARM::tInt_eh_sjlj_setjmp: {
1543 // Two incoming args: GPR:$src, GPR:$val
1546 // str $val, [$src, #4]
1551 unsigned SrcReg = MI->getOperand(0).getReg();
1552 unsigned ValReg = MI->getOperand(1).getReg();
1553 MCSymbol *Label = GetARMSJLJEHLabel();
1554 OutStreamer.AddComment("eh_setjmp begin");
1555 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1562 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
1572 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
1575 // The offset immediate is #4. The operand value is scaled by 4 for the
1576 // tSTR instruction.
1582 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1590 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1591 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
1592 .addExpr(SymbolExpr)
1596 OutStreamer.AddComment("eh_setjmp end");
1597 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
1605 OutStreamer.EmitLabel(Label);
1609 case ARM::Int_eh_sjlj_setjmp_nofp:
1610 case ARM::Int_eh_sjlj_setjmp: {
1611 // Two incoming args: GPR:$src, GPR:$val
1613 // str $val, [$src, #+4]
1617 unsigned SrcReg = MI->getOperand(0).getReg();
1618 unsigned ValReg = MI->getOperand(1).getReg();
1620 OutStreamer.AddComment("eh_setjmp begin");
1621 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1628 // 's' bit operand (always reg0 for this).
1631 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
1639 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1645 // 's' bit operand (always reg0 for this).
1648 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
1655 // 's' bit operand (always reg0 for this).
1658 OutStreamer.AddComment("eh_setjmp end");
1659 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
1665 // 's' bit operand (always reg0 for this).
1669 case ARM::Int_eh_sjlj_longjmp: {
1670 // ldr sp, [$src, #8]
1671 // ldr $scratch, [$src, #4]
1674 unsigned SrcReg = MI->getOperand(0).getReg();
1675 unsigned ScratchReg = MI->getOperand(1).getReg();
1676 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1684 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1692 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
1700 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
1707 case ARM::tInt_eh_sjlj_longjmp: {
1708 // ldr $scratch, [$src, #8]
1710 // ldr $scratch, [$src, #4]
1713 unsigned SrcReg = MI->getOperand(0).getReg();
1714 unsigned ScratchReg = MI->getOperand(1).getReg();
1715 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1718 // The offset immediate is #8. The operand value is scaled by 4 for the
1719 // tLDR instruction.
1725 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
1732 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1740 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
1748 EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
1758 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1760 EmitToStreamer(OutStreamer, TmpInst);
1763 //===----------------------------------------------------------------------===//
1764 // Target Registry Stuff
1765 //===----------------------------------------------------------------------===//
1767 // Force static initialization.
1768 extern "C" void LLVMInitializeARMAsmPrinter() {
1769 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
1770 RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
1771 RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
1772 RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);