1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
57 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden, cl::init(true),
58 cl::desc("enable experimental asmprinter gunk in the arm backend"));
70 class ARMAsmPrinter : public AsmPrinter {
72 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
73 /// make the right decision when printing asm code for different targets.
74 const ARMSubtarget *Subtarget;
76 /// AFI - Keep a pointer to ARMFunctionInfo for the current
80 /// MCP - Keep a pointer to constantpool entries of the current
82 const MachineConstantPool *MCP;
85 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
86 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
87 Subtarget = &TM.getSubtarget<ARMSubtarget>();
90 virtual const char *getPassName() const {
91 return "ARM Assembly Printer";
94 void EmitJumpTable(const MachineInstr *MI);
95 void EmitJump2Table(const MachineInstr *MI);
96 void printInstructionThroughMCStreamer(const MachineInstr *MI);
99 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
100 const char *Modifier = 0);
101 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
102 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
104 void printSORegOperand(const MachineInstr *MI, int OpNum,
106 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
108 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
110 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
112 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
114 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
115 const char *Modifier = 0);
116 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
117 const char *Modifier = 0);
118 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
120 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
122 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
124 const char *Modifier = 0);
125 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
127 void printMemBOption(const MachineInstr *MI, int OpNum,
129 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
132 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
134 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
135 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
137 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
140 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
142 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
146 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
149 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
150 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
152 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
154 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
156 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
158 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
160 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
163 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
165 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
167 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
169 void printPredicateOperand(const MachineInstr *MI, int OpNum,
171 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
173 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
175 void printPCLabel(const MachineInstr *MI, int OpNum,
177 void printRegisterList(const MachineInstr *MI, int OpNum,
179 void printCPInstOperand(const MachineInstr *MI, int OpNum,
181 const char *Modifier);
182 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
184 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
186 void printTBAddrMode(const MachineInstr *MI, int OpNum,
188 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
190 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
192 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
194 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
197 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
198 unsigned AsmVariant, const char *ExtraCode,
200 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
202 const char *ExtraCode, raw_ostream &O);
204 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
205 static const char *getRegisterName(unsigned RegNo);
207 virtual void EmitInstruction(const MachineInstr *MI);
208 bool runOnMachineFunction(MachineFunction &F);
210 virtual void EmitConstantPool() {} // we emit constant pools customly!
211 virtual void EmitFunctionEntryLabel();
212 void EmitStartOfAsmFile(Module &M);
213 void EmitEndOfAsmFile(Module &M);
215 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
217 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
218 MachineLocation Location;
219 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
220 // Frame address. Currently handles register +- offset only.
221 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
222 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
224 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
229 virtual unsigned getISAEncoding() {
230 // ARM/Darwin adds ISA to the DWARF info for each function.
231 if (!Subtarget->isTargetDarwin())
233 return Subtarget->isThumb() ?
234 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
237 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
238 const MachineBasicBlock *MBB) const;
239 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
241 MCSymbol *GetARMSJLJEHLabel(void) const;
243 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
245 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
246 SmallString<128> Str;
247 raw_svector_ostream OS(Str);
248 EmitMachineConstantPoolValue(MCPV, OS);
249 OutStreamer.EmitRawText(OS.str());
252 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
254 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
255 case 1: O << MAI->getData8bitsDirective(0); break;
256 case 2: O << MAI->getData16bitsDirective(0); break;
257 case 4: O << MAI->getData32bitsDirective(0); break;
258 default: assert(0 && "Unknown CPV size");
261 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
263 if (ACPV->isLSDA()) {
264 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
265 } else if (ACPV->isBlockAddress()) {
266 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
267 } else if (ACPV->isGlobalValue()) {
268 const GlobalValue *GV = ACPV->getGV();
269 bool isIndirect = Subtarget->isTargetDarwin() &&
270 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
272 O << *Mang->getSymbol(GV);
274 // FIXME: Remove this when Darwin transition to @GOT like syntax.
275 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
278 MachineModuleInfoMachO &MMIMachO =
279 MMI->getObjFileInfo<MachineModuleInfoMachO>();
280 MachineModuleInfoImpl::StubValueTy &StubSym =
281 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
282 MMIMachO.getGVStubEntry(Sym);
283 if (StubSym.getPointer() == 0)
284 StubSym = MachineModuleInfoImpl::
285 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
288 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
289 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
292 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
293 if (ACPV->getPCAdjustment() != 0) {
294 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
295 << getFunctionNumber() << "_" << ACPV->getLabelId()
296 << "+" << (unsigned)ACPV->getPCAdjustment();
297 if (ACPV->mustAddCurrentAddress())
303 } // end of anonymous namespace
305 #include "ARMGenAsmWriter.inc"
307 void ARMAsmPrinter::EmitFunctionEntryLabel() {
308 if (AFI->isThumbFunction()) {
309 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
310 if (!Subtarget->isTargetDarwin())
311 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
313 // This needs to emit to a temporary string to get properly quoted
314 // MCSymbols when they have spaces in them.
315 SmallString<128> Tmp;
316 raw_svector_ostream OS(Tmp);
317 OS << "\t.thumb_func\t" << *CurrentFnSym;
318 OutStreamer.EmitRawText(OS.str());
322 OutStreamer.EmitLabel(CurrentFnSym);
325 /// runOnMachineFunction - This uses the printInstruction()
326 /// method to print assembly for each instruction.
328 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
329 AFI = MF.getInfo<ARMFunctionInfo>();
330 MCP = MF.getConstantPool();
332 return AsmPrinter::runOnMachineFunction(MF);
335 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
336 raw_ostream &O, const char *Modifier) {
337 const MachineOperand &MO = MI->getOperand(OpNum);
338 unsigned TF = MO.getTargetFlags();
340 switch (MO.getType()) {
342 assert(0 && "<unknown operand type>");
343 case MachineOperand::MO_Register: {
344 unsigned Reg = MO.getReg();
345 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
346 if (Modifier && strcmp(Modifier, "lane") == 0) {
347 unsigned RegNum = getARMRegisterNumbering(Reg);
349 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
350 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
351 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
353 assert(!MO.getSubReg() && "Subregs should be eliminated!");
354 O << getRegisterName(Reg);
358 case MachineOperand::MO_Immediate: {
359 int64_t Imm = MO.getImm();
361 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
362 (TF & ARMII::MO_LO16))
364 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
365 (TF & ARMII::MO_HI16))
370 case MachineOperand::MO_MachineBasicBlock:
371 O << *MO.getMBB()->getSymbol();
373 case MachineOperand::MO_GlobalAddress: {
374 bool isCallOp = Modifier && !strcmp(Modifier, "call");
375 const GlobalValue *GV = MO.getGlobal();
377 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
378 (TF & ARMII::MO_LO16))
380 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
381 (TF & ARMII::MO_HI16))
383 O << *Mang->getSymbol(GV);
385 printOffset(MO.getOffset(), O);
387 if (isCallOp && Subtarget->isTargetELF() &&
388 TM.getRelocationModel() == Reloc::PIC_)
392 case MachineOperand::MO_ExternalSymbol: {
393 bool isCallOp = Modifier && !strcmp(Modifier, "call");
394 O << *GetExternalSymbolSymbol(MO.getSymbolName());
396 if (isCallOp && Subtarget->isTargetELF() &&
397 TM.getRelocationModel() == Reloc::PIC_)
401 case MachineOperand::MO_ConstantPoolIndex:
402 O << *GetCPISymbol(MO.getIndex());
404 case MachineOperand::MO_JumpTableIndex:
405 O << *GetJTISymbol(MO.getIndex());
410 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
411 const MCAsmInfo *MAI) {
412 // Break it up into two parts that make up a shifter immediate.
413 V = ARM_AM::getSOImmVal(V);
414 assert(V != -1 && "Not a valid so_imm value!");
416 unsigned Imm = ARM_AM::getSOImmValImm(V);
417 unsigned Rot = ARM_AM::getSOImmValRot(V);
419 // Print low-level immediate formation info, per
420 // A5.1.3: "Data-processing operands - Immediate".
422 O << "#" << Imm << ", " << Rot;
423 // Pretty printed version.
425 O << "\t" << MAI->getCommentString() << ' ';
426 O << (int)ARM_AM::rotr32(Imm, Rot);
433 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
434 /// immediate in bits 0-7.
435 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
437 const MachineOperand &MO = MI->getOperand(OpNum);
438 assert(MO.isImm() && "Not a valid so_imm value!");
439 printSOImm(O, MO.getImm(), isVerbose(), MAI);
442 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
443 /// followed by an 'orr' to materialize.
444 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
446 const MachineOperand &MO = MI->getOperand(OpNum);
447 assert(MO.isImm() && "Not a valid so_imm value!");
448 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
449 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
450 printSOImm(O, V1, isVerbose(), MAI);
452 printPredicateOperand(MI, 2, O);
454 printOperand(MI, 0, O);
456 printOperand(MI, 0, O);
458 printSOImm(O, V2, isVerbose(), MAI);
461 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
462 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
464 // REG REG 0,SH_OPC - e.g. R5, ROR R3
465 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
466 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
468 const MachineOperand &MO1 = MI->getOperand(Op);
469 const MachineOperand &MO2 = MI->getOperand(Op+1);
470 const MachineOperand &MO3 = MI->getOperand(Op+2);
472 O << getRegisterName(MO1.getReg());
474 // Print the shift opc.
475 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
476 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
478 O << ' ' << getRegisterName(MO2.getReg());
479 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
480 } else if (ShOpc != ARM_AM::rrx) {
481 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
485 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
487 const MachineOperand &MO1 = MI->getOperand(Op);
488 const MachineOperand &MO2 = MI->getOperand(Op+1);
489 const MachineOperand &MO3 = MI->getOperand(Op+2);
491 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
492 printOperand(MI, Op, O);
496 O << "[" << getRegisterName(MO1.getReg());
499 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
501 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
502 << ARM_AM::getAM2Offset(MO3.getImm());
508 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
509 << getRegisterName(MO2.getReg());
511 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
513 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
518 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
520 const MachineOperand &MO1 = MI->getOperand(Op);
521 const MachineOperand &MO2 = MI->getOperand(Op+1);
524 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
526 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
531 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
532 << getRegisterName(MO1.getReg());
534 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
536 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
540 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
542 const MachineOperand &MO1 = MI->getOperand(Op);
543 const MachineOperand &MO2 = MI->getOperand(Op+1);
544 const MachineOperand &MO3 = MI->getOperand(Op+2);
546 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
547 O << "[" << getRegisterName(MO1.getReg());
551 << (char)ARM_AM::getAM3Op(MO3.getImm())
552 << getRegisterName(MO2.getReg())
557 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
559 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
564 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
566 const MachineOperand &MO1 = MI->getOperand(Op);
567 const MachineOperand &MO2 = MI->getOperand(Op+1);
570 O << (char)ARM_AM::getAM3Op(MO2.getImm())
571 << getRegisterName(MO1.getReg());
575 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
577 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
581 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
583 const char *Modifier) {
584 const MachineOperand &MO2 = MI->getOperand(Op+1);
585 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
586 if (Modifier && strcmp(Modifier, "submode") == 0) {
587 O << ARM_AM::getAMSubModeStr(Mode);
588 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
589 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
590 if (Mode == ARM_AM::ia)
593 printOperand(MI, Op, O);
597 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
599 const char *Modifier) {
600 const MachineOperand &MO1 = MI->getOperand(Op);
601 const MachineOperand &MO2 = MI->getOperand(Op+1);
603 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
604 printOperand(MI, Op, O);
608 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
610 O << "[" << getRegisterName(MO1.getReg());
612 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
614 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
620 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
622 const MachineOperand &MO1 = MI->getOperand(Op);
623 const MachineOperand &MO2 = MI->getOperand(Op+1);
625 O << "[" << getRegisterName(MO1.getReg());
627 // FIXME: Both darwin as and GNU as violate ARM docs here.
628 O << ", :" << (MO2.getImm() << 3);
633 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
635 const MachineOperand &MO = MI->getOperand(Op);
636 if (MO.getReg() == 0)
639 O << ", " << getRegisterName(MO.getReg());
642 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
644 const char *Modifier) {
645 if (Modifier && strcmp(Modifier, "label") == 0) {
646 printPCLabel(MI, Op+1, O);
650 const MachineOperand &MO1 = MI->getOperand(Op);
651 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
652 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
656 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
658 const MachineOperand &MO = MI->getOperand(Op);
659 uint32_t v = ~MO.getImm();
660 int32_t lsb = CountTrailingZeros_32(v);
661 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
662 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
663 O << "#" << lsb << ", #" << width;
667 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
669 unsigned val = MI->getOperand(OpNum).getImm();
670 O << ARM_MB::MemBOptToString(val);
673 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
675 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
676 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
678 case ARM_AM::no_shift:
687 assert(0 && "unexpected shift opcode for shift immediate operand");
689 O << ARM_AM::getSORegOffset(ShiftOp);
692 //===--------------------------------------------------------------------===//
694 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
696 O << "#" << MI->getOperand(Op).getImm() * 4;
700 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
702 // (3 - the number of trailing zeros) is the number of then / else.
703 unsigned Mask = MI->getOperand(Op).getImm();
704 unsigned CondBit0 = Mask >> 4 & 1;
705 unsigned NumTZ = CountTrailingZeros_32(Mask);
706 assert(NumTZ <= 3 && "Invalid IT mask!");
707 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
708 bool T = ((Mask >> Pos) & 1) == CondBit0;
717 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
719 const MachineOperand &MO1 = MI->getOperand(Op);
720 const MachineOperand &MO2 = MI->getOperand(Op+1);
721 O << "[" << getRegisterName(MO1.getReg());
722 O << ", " << getRegisterName(MO2.getReg()) << "]";
726 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
729 const MachineOperand &MO1 = MI->getOperand(Op);
730 const MachineOperand &MO2 = MI->getOperand(Op+1);
731 const MachineOperand &MO3 = MI->getOperand(Op+2);
733 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
734 printOperand(MI, Op, O);
738 O << "[" << getRegisterName(MO1.getReg());
740 O << ", " << getRegisterName(MO3.getReg());
741 else if (unsigned ImmOffs = MO2.getImm())
742 O << ", #" << ImmOffs * Scale;
747 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
749 printThumbAddrModeRI5Operand(MI, Op, O, 1);
752 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
754 printThumbAddrModeRI5Operand(MI, Op, O, 2);
757 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
759 printThumbAddrModeRI5Operand(MI, Op, O, 4);
762 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
764 const MachineOperand &MO1 = MI->getOperand(Op);
765 const MachineOperand &MO2 = MI->getOperand(Op+1);
766 O << "[" << getRegisterName(MO1.getReg());
767 if (unsigned ImmOffs = MO2.getImm())
768 O << ", #" << ImmOffs*4;
772 //===--------------------------------------------------------------------===//
774 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
775 // register with shift forms.
777 // REG IMM, SH_OPC - e.g. R5, LSL #3
778 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
780 const MachineOperand &MO1 = MI->getOperand(OpNum);
781 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
783 unsigned Reg = MO1.getReg();
784 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
785 O << getRegisterName(Reg);
787 // Print the shift opc.
788 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
789 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
790 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
791 if (ShOpc != ARM_AM::rrx)
792 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
795 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
798 const MachineOperand &MO1 = MI->getOperand(OpNum);
799 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
801 O << "[" << getRegisterName(MO1.getReg());
803 unsigned OffImm = MO2.getImm();
804 if (OffImm) // Don't print +0.
805 O << ", #" << OffImm;
809 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
812 const MachineOperand &MO1 = MI->getOperand(OpNum);
813 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
815 O << "[" << getRegisterName(MO1.getReg());
817 int32_t OffImm = (int32_t)MO2.getImm();
820 O << ", #-" << -OffImm;
822 O << ", #" << OffImm;
826 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
829 const MachineOperand &MO1 = MI->getOperand(OpNum);
830 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
832 O << "[" << getRegisterName(MO1.getReg());
834 int32_t OffImm = (int32_t)MO2.getImm() / 4;
837 O << ", #-" << -OffImm * 4;
839 O << ", #" << OffImm * 4;
843 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
846 const MachineOperand &MO1 = MI->getOperand(OpNum);
847 int32_t OffImm = (int32_t)MO1.getImm();
850 O << "#-" << -OffImm;
855 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
858 const MachineOperand &MO1 = MI->getOperand(OpNum);
859 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
860 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
862 O << "[" << getRegisterName(MO1.getReg());
864 assert(MO2.getReg() && "Invalid so_reg load / store address!");
865 O << ", " << getRegisterName(MO2.getReg());
867 unsigned ShAmt = MO3.getImm();
869 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
870 O << ", lsl #" << ShAmt;
876 //===--------------------------------------------------------------------===//
878 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
880 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
882 O << ARMCondCodeToString(CC);
885 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
888 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
889 O << ARMCondCodeToString(CC);
892 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
894 unsigned Reg = MI->getOperand(OpNum).getReg();
896 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
901 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
903 int Id = (int)MI->getOperand(OpNum).getImm();
904 O << MAI->getPrivateGlobalPrefix()
905 << "PC" << getFunctionNumber() << "_" << Id;
908 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
911 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
912 if (MI->getOperand(i).isImplicit())
914 if ((int)i != OpNum) O << ", ";
915 printOperand(MI, i, O);
920 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
921 raw_ostream &O, const char *Modifier) {
922 assert(Modifier && "This operand only works with a modifier!");
923 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
925 if (!strcmp(Modifier, "label")) {
926 unsigned ID = MI->getOperand(OpNum).getImm();
927 OutStreamer.EmitLabel(GetCPISymbol(ID));
929 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
930 unsigned CPI = MI->getOperand(OpNum).getIndex();
932 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
934 if (MCPE.isMachineConstantPoolEntry()) {
935 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
937 EmitGlobalConstant(MCPE.Val.ConstVal);
942 MCSymbol *ARMAsmPrinter::
943 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
944 const MachineBasicBlock *MBB) const {
945 SmallString<60> Name;
946 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
947 << getFunctionNumber() << '_' << uid << '_' << uid2
948 << "_set_" << MBB->getNumber();
949 return OutContext.GetOrCreateSymbol(Name.str());
952 MCSymbol *ARMAsmPrinter::
953 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
954 SmallString<60> Name;
955 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
956 << getFunctionNumber() << '_' << uid << '_' << uid2;
957 return OutContext.GetOrCreateSymbol(Name.str());
961 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
962 SmallString<60> Name;
963 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
964 << getFunctionNumber();
965 return OutContext.GetOrCreateSymbol(Name.str());
968 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
970 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
972 const MachineOperand &MO1 = MI->getOperand(OpNum);
973 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
975 unsigned JTI = MO1.getIndex();
976 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
977 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
979 O << "\n" << *JTISymbol << ":\n";
981 const char *JTEntryDirective = MAI->getData32bitsDirective();
983 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
984 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
985 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
986 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
987 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
988 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
989 MachineBasicBlock *MBB = JTBBs[i];
990 bool isNew = JTSets.insert(MBB);
992 if (UseSet && isNew) {
994 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
995 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
998 O << JTEntryDirective << ' ';
1000 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
1001 else if (TM.getRelocationModel() == Reloc::PIC_)
1002 O << *MBB->getSymbol() << '-' << *JTISymbol;
1004 O << *MBB->getSymbol();
1011 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
1013 const MachineOperand &MO1 = MI->getOperand(OpNum);
1014 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1015 unsigned JTI = MO1.getIndex();
1017 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1019 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
1021 O << "\n" << *JTISymbol << ":\n";
1023 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1024 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1025 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1026 bool ByteOffset = false, HalfWordOffset = false;
1027 if (MI->getOpcode() == ARM::t2TBB)
1029 else if (MI->getOpcode() == ARM::t2TBH)
1030 HalfWordOffset = true;
1032 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1033 MachineBasicBlock *MBB = JTBBs[i];
1035 O << MAI->getData8bitsDirective();
1036 else if (HalfWordOffset)
1037 O << MAI->getData16bitsDirective();
1039 if (ByteOffset || HalfWordOffset)
1040 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1042 O << "\tb.w " << *MBB->getSymbol();
1049 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1051 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1052 if (MI->getOpcode() == ARM::t2TBH)
1057 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1059 O << MI->getOperand(OpNum).getImm();
1062 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1064 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1065 O << '#' << FP->getValueAPF().convertToFloat();
1067 O << "\t\t" << MAI->getCommentString() << ' ';
1068 WriteAsOperand(O, FP, /*PrintType=*/false);
1072 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1074 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1075 O << '#' << FP->getValueAPF().convertToDouble();
1077 O << "\t\t" << MAI->getCommentString() << ' ';
1078 WriteAsOperand(O, FP, /*PrintType=*/false);
1082 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1084 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1086 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1087 O << "#0x" << utohexstr(Val);
1090 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1091 unsigned AsmVariant, const char *ExtraCode,
1093 // Does this asm operand have a single letter operand modifier?
1094 if (ExtraCode && ExtraCode[0]) {
1095 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1097 switch (ExtraCode[0]) {
1098 default: return true; // Unknown modifier.
1099 case 'a': // Print as a memory address.
1100 if (MI->getOperand(OpNum).isReg()) {
1101 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1105 case 'c': // Don't print "#" before an immediate operand.
1106 if (!MI->getOperand(OpNum).isImm())
1108 printNoHashImmediate(MI, OpNum, O);
1110 case 'P': // Print a VFP double precision register.
1111 case 'q': // Print a NEON quad precision register.
1112 printOperand(MI, OpNum, O);
1117 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1122 printOperand(MI, OpNum, O);
1126 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1127 unsigned OpNum, unsigned AsmVariant,
1128 const char *ExtraCode,
1130 if (ExtraCode && ExtraCode[0])
1131 return true; // Unknown modifier.
1133 const MachineOperand &MO = MI->getOperand(OpNum);
1134 assert(MO.isReg() && "unexpected inline asm memory operand");
1135 O << "[" << getRegisterName(MO.getReg()) << "]";
1139 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1141 printInstructionThroughMCStreamer(MI);
1145 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1148 SmallString<128> Str;
1149 raw_svector_ostream OS(Str);
1150 if (MI->getOpcode() == ARM::DBG_VALUE) {
1151 PrintDebugValueComment(MI, OS);
1152 } else if (MI->getOpcode() == ARM::MOVs) {
1153 // FIXME: Thumb variants?
1154 const MachineOperand &Dst = MI->getOperand(0);
1155 const MachineOperand &MO1 = MI->getOperand(1);
1156 const MachineOperand &MO2 = MI->getOperand(2);
1157 const MachineOperand &MO3 = MI->getOperand(3);
1159 OS << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
1160 printSBitModifierOperand(MI, 6, OS);
1161 printPredicateOperand(MI, 4, OS);
1163 OS << '\t' << getRegisterName(Dst.getReg())
1164 << ", " << getRegisterName(MO1.getReg());
1166 if (ARM_AM::getSORegShOp(MO3.getImm()) != ARM_AM::rrx) {
1170 OS << getRegisterName(MO2.getReg());
1171 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
1173 OS << "#" << ARM_AM::getSORegOffset(MO3.getImm());
1178 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
1179 MI->getOperand(0).getReg() == ARM::SP &&
1180 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
1181 OS << '\t' << "push";
1182 printPredicateOperand(MI, 3, OS);
1184 printRegisterList(MI, 5, OS);
1187 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
1188 MI->getOperand(0).getReg() == ARM::SP &&
1189 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
1190 OS << '\t' << "pop";
1191 printPredicateOperand(MI, 3, OS);
1193 printRegisterList(MI, 5, OS);
1196 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
1197 MI->getOperand(0).getReg() == ARM::SP &&
1198 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
1199 OS << '\t' << "vpush";
1200 printPredicateOperand(MI, 3, OS);
1202 printRegisterList(MI, 5, OS);
1205 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
1206 MI->getOperand(0).getReg() == ARM::SP &&
1207 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
1208 OS << '\t' << "vpop";
1209 printPredicateOperand(MI, 3, OS);
1211 printRegisterList(MI, 5, OS);
1213 // TRAP and tTRAP need special handling for non-Darwin. The GNU binutils
1214 // don't (yet) support the 'trap' mnemonic. (Use decimal, not hex, to
1215 // be consistent with the MC instruction printer.)
1216 // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
1217 // Need a way to ask "isTargetDarwin()" there, first, though.
1218 if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
1219 OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
1220 } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
1221 OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
1223 printInstruction(MI, OS);
1225 // Output the instruction to the stream
1226 OutStreamer.EmitRawText(OS.str());
1228 // Make sure the instruction that follows TBB is 2-byte aligned.
1229 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1230 if (MI->getOpcode() == ARM::t2TBB)
1234 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1235 if (Subtarget->isTargetDarwin()) {
1236 Reloc::Model RelocM = TM.getRelocationModel();
1237 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1238 // Declare all the text sections up front (before the DWARF sections
1239 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1240 // them together at the beginning of the object file. This helps
1241 // avoid out-of-range branches that are due a fundamental limitation of
1242 // the way symbol offsets are encoded with the current Darwin ARM
1244 const TargetLoweringObjectFileMachO &TLOFMacho =
1245 static_cast<const TargetLoweringObjectFileMachO &>(
1246 getObjFileLowering());
1247 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1248 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1249 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1250 if (RelocM == Reloc::DynamicNoPIC) {
1251 const MCSection *sect =
1252 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1253 MCSectionMachO::S_SYMBOL_STUBS,
1254 12, SectionKind::getText());
1255 OutStreamer.SwitchSection(sect);
1257 const MCSection *sect =
1258 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1259 MCSectionMachO::S_SYMBOL_STUBS,
1260 16, SectionKind::getText());
1261 OutStreamer.SwitchSection(sect);
1263 const MCSection *StaticInitSect =
1264 OutContext.getMachOSection("__TEXT", "__StaticInit",
1265 MCSectionMachO::S_REGULAR |
1266 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1267 SectionKind::getText());
1268 OutStreamer.SwitchSection(StaticInitSect);
1272 // Use unified assembler syntax.
1273 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1275 // Emit ARM Build Attributes
1276 if (Subtarget->isTargetELF()) {
1278 std::string CPUString = Subtarget->getCPUString();
1279 if (CPUString != "generic")
1280 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1282 // FIXME: Emit FPU type
1283 if (Subtarget->hasVFP2())
1284 OutStreamer.EmitRawText("\t.eabi_attribute " +
1285 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1287 // Signal various FP modes.
1288 if (!UnsafeFPMath) {
1289 OutStreamer.EmitRawText("\t.eabi_attribute " +
1290 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1291 OutStreamer.EmitRawText("\t.eabi_attribute " +
1292 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1295 if (NoInfsFPMath && NoNaNsFPMath)
1296 OutStreamer.EmitRawText("\t.eabi_attribute " +
1297 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1299 OutStreamer.EmitRawText("\t.eabi_attribute " +
1300 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1302 // 8-bytes alignment stuff.
1303 OutStreamer.EmitRawText("\t.eabi_attribute " +
1304 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1305 OutStreamer.EmitRawText("\t.eabi_attribute " +
1306 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1308 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1309 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1310 OutStreamer.EmitRawText("\t.eabi_attribute " +
1311 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1312 OutStreamer.EmitRawText("\t.eabi_attribute " +
1313 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1315 // FIXME: Should we signal R9 usage?
1320 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1321 if (Subtarget->isTargetDarwin()) {
1322 // All darwin targets use mach-o.
1323 const TargetLoweringObjectFileMachO &TLOFMacho =
1324 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1325 MachineModuleInfoMachO &MMIMacho =
1326 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1328 // Output non-lazy-pointers for external and common global variables.
1329 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1331 if (!Stubs.empty()) {
1332 // Switch with ".non_lazy_symbol_pointer" directive.
1333 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1335 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1337 OutStreamer.EmitLabel(Stubs[i].first);
1338 // .indirect_symbol _foo
1339 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1340 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1343 // External to current translation unit.
1344 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1346 // Internal to current translation unit.
1348 // When we place the LSDA into the TEXT section, the type info
1349 // pointers need to be indirect and pc-rel. We accomplish this by
1350 // using NLPs; however, sometimes the types are local to the file.
1351 // We need to fill in the value for the NLP in those cases.
1352 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1354 4/*size*/, 0/*addrspace*/);
1358 OutStreamer.AddBlankLine();
1361 Stubs = MMIMacho.GetHiddenGVStubList();
1362 if (!Stubs.empty()) {
1363 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1365 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1367 OutStreamer.EmitLabel(Stubs[i].first);
1369 OutStreamer.EmitValue(MCSymbolRefExpr::
1370 Create(Stubs[i].second.getPointer(),
1372 4/*size*/, 0/*addrspace*/);
1376 OutStreamer.AddBlankLine();
1379 // Funny Darwin hack: This flag tells the linker that no global symbols
1380 // contain code that falls through to other global symbols (e.g. the obvious
1381 // implementation of multiple entry points). If this doesn't occur, the
1382 // linker can safely perform dead code stripping. Since LLVM never
1383 // generates code that does this, it is always safe to set.
1384 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1388 //===----------------------------------------------------------------------===//
1390 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
1391 unsigned LabelId, MCContext &Ctx) {
1393 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
1394 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
1398 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
1399 unsigned Opcode = MI->getOpcode();
1401 if (Opcode == ARM::BR_JTadd)
1403 else if (Opcode == ARM::BR_JTm)
1406 const MachineOperand &MO1 = MI->getOperand(OpNum);
1407 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1408 unsigned JTI = MO1.getIndex();
1410 // Emit a label for the jump table.
1411 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1412 OutStreamer.EmitLabel(JTISymbol);
1414 // Emit each entry of the table.
1415 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1416 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1417 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1419 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1420 MachineBasicBlock *MBB = JTBBs[i];
1421 // Construct an MCExpr for the entry. We want a value of the form:
1422 // (BasicBlockAddr - TableBeginAddr)
1424 // For example, a table with entries jumping to basic blocks BB0 and BB1
1427 // .word (LBB0 - LJTI_0_0)
1428 // .word (LBB1 - LJTI_0_0)
1429 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1431 if (TM.getRelocationModel() == Reloc::PIC_)
1432 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1435 OutStreamer.EmitValue(Expr, 4);
1439 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1440 unsigned Opcode = MI->getOpcode();
1441 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1442 const MachineOperand &MO1 = MI->getOperand(OpNum);
1443 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1444 unsigned JTI = MO1.getIndex();
1446 // Emit a label for the jump table.
1447 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1448 OutStreamer.EmitLabel(JTISymbol);
1450 // Emit each entry of the table.
1451 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1452 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1453 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1454 unsigned OffsetWidth = 4;
1455 if (MI->getOpcode() == ARM::t2TBB)
1457 else if (MI->getOpcode() == ARM::t2TBH)
1460 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1461 MachineBasicBlock *MBB = JTBBs[i];
1462 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1464 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1465 if (OffsetWidth == 4) {
1467 BrInst.setOpcode(ARM::t2B);
1468 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1469 OutStreamer.EmitInstruction(BrInst);
1472 // Otherwise it's an offset from the dispatch instruction. Construct an
1473 // MCExpr for the entry. We want a value of the form:
1474 // (BasicBlockAddr - TableBeginAddr) / 2
1476 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1479 // .byte (LBB0 - LJTI_0_0) / 2
1480 // .byte (LBB1 - LJTI_0_0) / 2
1481 const MCExpr *Expr =
1482 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1483 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1485 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1487 OutStreamer.EmitValue(Expr, OffsetWidth);
1490 // Make sure the instruction that follows TBB is 2-byte aligned.
1491 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1492 if (MI->getOpcode() == ARM::t2TBB)
1496 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1498 unsigned NOps = MI->getNumOperands();
1500 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1501 // cast away const; DIetc do not take const operands for some reason.
1502 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1505 // Frame address. Currently handles register +- offset only.
1506 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1507 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1510 printOperand(MI, NOps-2, OS);
1513 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1514 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1515 switch (MI->getOpcode()) {
1516 case ARM::t2MOVi32imm:
1517 assert(0 && "Should be lowered by thumb2it pass");
1519 case ARM::DBG_VALUE: {
1520 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1521 SmallString<128> TmpStr;
1522 raw_svector_ostream OS(TmpStr);
1523 PrintDebugValueComment(MI, OS);
1524 OutStreamer.EmitRawText(StringRef(OS.str()));
1528 case ARM::tPICADD: {
1529 // This is a pseudo op for a label + instruction sequence, which looks like:
1532 // This adds the address of LPC0 to r0.
1535 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1536 getFunctionNumber(), MI->getOperand(2).getImm(),
1539 // Form and emit the add.
1541 AddInst.setOpcode(ARM::tADDhirr);
1542 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1543 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1544 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1545 // Add predicate operands.
1546 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1547 AddInst.addOperand(MCOperand::CreateReg(0));
1548 OutStreamer.EmitInstruction(AddInst);
1551 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1552 // This is a pseudo op for a label + instruction sequence, which looks like:
1555 // This adds the address of LPC0 to r0.
1558 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1559 getFunctionNumber(), MI->getOperand(2).getImm(),
1562 // Form and emit the add.
1564 AddInst.setOpcode(ARM::ADDrr);
1565 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1566 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1567 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1568 // Add predicate operands.
1569 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1570 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1571 // Add 's' bit operand (always reg0 for this)
1572 AddInst.addOperand(MCOperand::CreateReg(0));
1573 OutStreamer.EmitInstruction(AddInst);
1583 case ARM::PICLDRSH: {
1584 // This is a pseudo op for a label + instruction sequence, which looks like:
1587 // The LCP0 label is referenced by a constant pool entry in order to get
1588 // a PC-relative address at the ldr instruction.
1591 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1592 getFunctionNumber(), MI->getOperand(2).getImm(),
1595 // Form and emit the load
1597 switch (MI->getOpcode()) {
1599 llvm_unreachable("Unexpected opcode!");
1600 case ARM::PICSTR: Opcode = ARM::STR; break;
1601 case ARM::PICSTRB: Opcode = ARM::STRB; break;
1602 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1603 case ARM::PICLDR: Opcode = ARM::LDR; break;
1604 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
1605 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1606 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1607 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1610 LdStInst.setOpcode(Opcode);
1611 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1612 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1613 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1614 LdStInst.addOperand(MCOperand::CreateImm(0));
1615 // Add predicate operands.
1616 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1617 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1618 OutStreamer.EmitInstruction(LdStInst);
1622 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1623 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1624 /// in the function. The first operand is the ID# for this instruction, the
1625 /// second is the index into the MachineConstantPool that this is, the third
1626 /// is the size in bytes of this constant pool entry.
1627 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1628 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1631 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1633 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1634 if (MCPE.isMachineConstantPoolEntry())
1635 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1637 EmitGlobalConstant(MCPE.Val.ConstVal);
1641 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1642 // This is a hack that lowers as a two instruction sequence.
1643 unsigned DstReg = MI->getOperand(0).getReg();
1644 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1646 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1647 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1651 TmpInst.setOpcode(ARM::MOVi);
1652 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1653 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1656 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1657 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1659 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1660 OutStreamer.EmitInstruction(TmpInst);
1665 TmpInst.setOpcode(ARM::ORRri);
1666 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1667 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1668 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1670 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1671 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1673 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1674 OutStreamer.EmitInstruction(TmpInst);
1678 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1679 // This is a hack that lowers as a two instruction sequence.
1680 unsigned DstReg = MI->getOperand(0).getReg();
1681 const MachineOperand &MO = MI->getOperand(1);
1684 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1685 V1 = MCOperand::CreateImm(ImmVal & 65535);
1686 V2 = MCOperand::CreateImm(ImmVal >> 16);
1687 } else if (MO.isGlobal()) {
1688 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
1689 const MCSymbolRefExpr *SymRef1 =
1690 MCSymbolRefExpr::Create(Symbol,
1691 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1692 const MCSymbolRefExpr *SymRef2 =
1693 MCSymbolRefExpr::Create(Symbol,
1694 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1695 V1 = MCOperand::CreateExpr(SymRef1);
1696 V2 = MCOperand::CreateExpr(SymRef2);
1698 // FIXME: External symbol?
1700 llvm_unreachable("cannot handle this operand");
1705 TmpInst.setOpcode(ARM::MOVi16);
1706 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1707 TmpInst.addOperand(V1); // lower16(imm)
1710 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1711 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1713 OutStreamer.EmitInstruction(TmpInst);
1718 TmpInst.setOpcode(ARM::MOVTi16);
1719 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1720 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1721 TmpInst.addOperand(V2); // upper16(imm)
1724 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1725 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1727 OutStreamer.EmitInstruction(TmpInst);
1734 case ARM::t2BR_JT: {
1735 // Lower and emit the instruction itself, then the jump table following it.
1737 MCInstLowering.Lower(MI, TmpInst);
1738 OutStreamer.EmitInstruction(TmpInst);
1745 case ARM::BR_JTadd: {
1746 // Lower and emit the instruction itself, then the jump table following it.
1748 MCInstLowering.Lower(MI, TmpInst);
1749 OutStreamer.EmitInstruction(TmpInst);
1754 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1755 // FIXME: Remove this special case when they do.
1756 if (!Subtarget->isTargetDarwin()) {
1757 //.long 0xe7ffdefe ${:comment} trap
1758 uint32_t Val = 0xe7ffdefeUL;
1759 OutStreamer.AddComment("trap");
1760 OutStreamer.EmitIntValue(Val, 4);
1766 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1767 // FIXME: Remove this special case when they do.
1768 if (!Subtarget->isTargetDarwin()) {
1769 //.short 57086 ${:comment} trap
1770 uint16_t Val = 0xdefe;
1771 OutStreamer.AddComment("trap");
1772 OutStreamer.EmitIntValue(Val, 2);
1777 case ARM::t2Int_eh_sjlj_setjmp:
1778 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1779 case ARM::tInt_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
1780 // Two incoming args: GPR:$src, GPR:$val
1783 // str $val, [$src, #4]
1788 unsigned SrcReg = MI->getOperand(0).getReg();
1789 unsigned ValReg = MI->getOperand(1).getReg();
1790 MCSymbol *Label = GetARMSJLJEHLabel();
1793 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1794 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1795 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1797 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1798 OutStreamer.AddComment("eh_setjmp begin");
1799 OutStreamer.EmitInstruction(TmpInst);
1803 TmpInst.setOpcode(ARM::tADDi3);
1804 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1806 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1807 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1808 TmpInst.addOperand(MCOperand::CreateImm(7));
1810 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1811 TmpInst.addOperand(MCOperand::CreateReg(0));
1812 OutStreamer.EmitInstruction(TmpInst);
1816 TmpInst.setOpcode(ARM::tSTR);
1817 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1818 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1819 // The offset immediate is #4. The operand value is scaled by 4 for the
1820 // tSTR instruction.
1821 TmpInst.addOperand(MCOperand::CreateImm(1));
1822 TmpInst.addOperand(MCOperand::CreateReg(0));
1824 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1825 TmpInst.addOperand(MCOperand::CreateReg(0));
1826 OutStreamer.EmitInstruction(TmpInst);
1830 TmpInst.setOpcode(ARM::tMOVi8);
1831 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1832 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1833 TmpInst.addOperand(MCOperand::CreateImm(0));
1835 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1836 TmpInst.addOperand(MCOperand::CreateReg(0));
1837 OutStreamer.EmitInstruction(TmpInst);
1840 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1842 TmpInst.setOpcode(ARM::tB);
1843 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1844 OutStreamer.EmitInstruction(TmpInst);
1848 TmpInst.setOpcode(ARM::tMOVi8);
1849 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1850 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1851 TmpInst.addOperand(MCOperand::CreateImm(1));
1853 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1854 TmpInst.addOperand(MCOperand::CreateReg(0));
1855 OutStreamer.AddComment("eh_setjmp end");
1856 OutStreamer.EmitInstruction(TmpInst);
1858 OutStreamer.EmitLabel(Label);
1862 case ARM::Int_eh_sjlj_setjmp_nofp:
1863 case ARM::Int_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
1864 // Two incoming args: GPR:$src, GPR:$val
1866 // str $val, [$src, #+4]
1870 unsigned SrcReg = MI->getOperand(0).getReg();
1871 unsigned ValReg = MI->getOperand(1).getReg();
1875 TmpInst.setOpcode(ARM::ADDri);
1876 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1877 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1878 TmpInst.addOperand(MCOperand::CreateImm(8));
1880 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1881 TmpInst.addOperand(MCOperand::CreateReg(0));
1882 // 's' bit operand (always reg0 for this).
1883 TmpInst.addOperand(MCOperand::CreateReg(0));
1884 OutStreamer.AddComment("eh_setjmp begin");
1885 OutStreamer.EmitInstruction(TmpInst);
1889 TmpInst.setOpcode(ARM::STR);
1890 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1891 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1892 TmpInst.addOperand(MCOperand::CreateReg(0));
1893 TmpInst.addOperand(MCOperand::CreateImm(4));
1895 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1896 TmpInst.addOperand(MCOperand::CreateReg(0));
1897 OutStreamer.EmitInstruction(TmpInst);
1901 TmpInst.setOpcode(ARM::MOVi);
1902 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1903 TmpInst.addOperand(MCOperand::CreateImm(0));
1905 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1906 TmpInst.addOperand(MCOperand::CreateReg(0));
1907 // 's' bit operand (always reg0 for this).
1908 TmpInst.addOperand(MCOperand::CreateReg(0));
1909 OutStreamer.EmitInstruction(TmpInst);
1913 TmpInst.setOpcode(ARM::ADDri);
1914 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1915 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1916 TmpInst.addOperand(MCOperand::CreateImm(0));
1918 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1919 TmpInst.addOperand(MCOperand::CreateReg(0));
1920 // 's' bit operand (always reg0 for this).
1921 TmpInst.addOperand(MCOperand::CreateReg(0));
1922 OutStreamer.EmitInstruction(TmpInst);
1926 TmpInst.setOpcode(ARM::MOVi);
1927 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1928 TmpInst.addOperand(MCOperand::CreateImm(1));
1930 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1931 TmpInst.addOperand(MCOperand::CreateReg(0));
1932 // 's' bit operand (always reg0 for this).
1933 TmpInst.addOperand(MCOperand::CreateReg(0));
1934 OutStreamer.AddComment("eh_setjmp end");
1935 OutStreamer.EmitInstruction(TmpInst);
1939 case ARM::Int_eh_sjlj_longjmp: {
1940 // ldr sp, [$src, #8]
1941 // ldr $scratch, [$src, #4]
1944 unsigned SrcReg = MI->getOperand(0).getReg();
1945 unsigned ScratchReg = MI->getOperand(1).getReg();
1948 TmpInst.setOpcode(ARM::LDR);
1949 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1950 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1951 TmpInst.addOperand(MCOperand::CreateReg(0));
1952 TmpInst.addOperand(MCOperand::CreateImm(8));
1954 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1955 TmpInst.addOperand(MCOperand::CreateReg(0));
1956 OutStreamer.EmitInstruction(TmpInst);
1960 TmpInst.setOpcode(ARM::LDR);
1961 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1962 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1963 TmpInst.addOperand(MCOperand::CreateReg(0));
1964 TmpInst.addOperand(MCOperand::CreateImm(4));
1966 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1967 TmpInst.addOperand(MCOperand::CreateReg(0));
1968 OutStreamer.EmitInstruction(TmpInst);
1972 TmpInst.setOpcode(ARM::LDR);
1973 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1974 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1975 TmpInst.addOperand(MCOperand::CreateReg(0));
1976 TmpInst.addOperand(MCOperand::CreateImm(0));
1978 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1979 TmpInst.addOperand(MCOperand::CreateReg(0));
1980 OutStreamer.EmitInstruction(TmpInst);
1984 TmpInst.setOpcode(ARM::BRIND);
1985 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1987 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1988 TmpInst.addOperand(MCOperand::CreateReg(0));
1989 OutStreamer.EmitInstruction(TmpInst);
1993 case ARM::tInt_eh_sjlj_longjmp: {
1994 // ldr $scratch, [$src, #8]
1996 // ldr $scratch, [$src, #4]
1999 unsigned SrcReg = MI->getOperand(0).getReg();
2000 unsigned ScratchReg = MI->getOperand(1).getReg();
2003 TmpInst.setOpcode(ARM::tLDR);
2004 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2005 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2006 // The offset immediate is #8. The operand value is scaled by 4 for the
2007 // tSTR instruction.
2008 TmpInst.addOperand(MCOperand::CreateImm(2));
2009 TmpInst.addOperand(MCOperand::CreateReg(0));
2011 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2012 TmpInst.addOperand(MCOperand::CreateReg(0));
2013 OutStreamer.EmitInstruction(TmpInst);
2017 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
2018 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
2019 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2021 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2022 TmpInst.addOperand(MCOperand::CreateReg(0));
2023 OutStreamer.EmitInstruction(TmpInst);
2027 TmpInst.setOpcode(ARM::tLDR);
2028 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2029 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2030 TmpInst.addOperand(MCOperand::CreateImm(1));
2031 TmpInst.addOperand(MCOperand::CreateReg(0));
2033 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2034 TmpInst.addOperand(MCOperand::CreateReg(0));
2035 OutStreamer.EmitInstruction(TmpInst);
2039 TmpInst.setOpcode(ARM::tLDR);
2040 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
2041 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
2042 TmpInst.addOperand(MCOperand::CreateImm(0));
2043 TmpInst.addOperand(MCOperand::CreateReg(0));
2045 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2046 TmpInst.addOperand(MCOperand::CreateReg(0));
2047 OutStreamer.EmitInstruction(TmpInst);
2051 TmpInst.setOpcode(ARM::tBX_RET_vararg);
2052 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
2054 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
2055 TmpInst.addOperand(MCOperand::CreateReg(0));
2056 OutStreamer.EmitInstruction(TmpInst);
2063 MCInstLowering.Lower(MI, TmpInst);
2064 OutStreamer.EmitInstruction(TmpInst);
2067 //===----------------------------------------------------------------------===//
2068 // Target Registry Stuff
2069 //===----------------------------------------------------------------------===//
2071 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
2072 unsigned SyntaxVariant,
2073 const MCAsmInfo &MAI) {
2074 if (SyntaxVariant == 0)
2075 return new ARMInstPrinter(MAI);
2079 // Force static initialization.
2080 extern "C" void LLVMInitializeARMAsmPrinter() {
2081 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2082 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
2084 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
2085 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);