1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/TargetRegistry.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 // This structure holds all attributes, accounting for
104 // their string/numeric value, so we can later emmit them
105 // in declaration order, keeping all in the same vector
106 struct AttributeItemType {
114 StringRef StringValue;
117 MCObjectStreamer &Streamer;
118 StringRef CurrentVendor;
119 SmallVector<AttributeItemType, 64> Contents;
121 // Account for the ULEB/String size of each item,
122 // not just the number of items
124 // FIXME: this should be in a more generic place, but
125 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
126 size_t getULEBSize(int Value) {
130 Size += sizeof(int8_t); // Is this really necessary?
136 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
137 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
139 void MaybeSwitchVendor(StringRef Vendor) {
140 assert(!Vendor.empty() && "Vendor cannot be empty.");
142 if (CurrentVendor.empty())
143 CurrentVendor = Vendor;
144 else if (CurrentVendor == Vendor)
149 CurrentVendor = Vendor;
151 assert(Contents.size() == 0);
154 void EmitAttribute(unsigned Attribute, unsigned Value) {
155 AttributeItemType attr = {
156 AttributeItemType::NumericAttribute,
161 ContentsSize += getULEBSize(Attribute);
162 ContentsSize += getULEBSize(Value);
163 Contents.push_back(attr);
166 void EmitTextAttribute(unsigned Attribute, StringRef String) {
167 AttributeItemType attr = {
168 AttributeItemType::TextAttribute,
173 ContentsSize += getULEBSize(Attribute);
175 ContentsSize += String.size()+1;
177 Contents.push_back(attr);
181 // Vendor size + Vendor name + '\0'
182 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
185 const size_t TagHeaderSize = 1 + 4;
187 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
188 Streamer.EmitBytes(CurrentVendor, 0);
189 Streamer.EmitIntValue(0, 1); // '\0'
191 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
192 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
194 // Size should have been accounted for already, now
195 // emit each field as its type (ULEB or String)
196 for (unsigned int i=0; i<Contents.size(); ++i) {
197 AttributeItemType item = Contents[i];
198 Streamer.EmitULEB128IntValue(item.Tag, 0);
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue, 0);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(UppercaseString(item.StringValue), 0);
205 Streamer.EmitIntValue(0, 1); // '\0'
208 assert(0 && "Invalid attribute type");
216 } // end of anonymous namespace
218 MachineLocation ARMAsmPrinter::
219 getDebugValueLocation(const MachineInstr *MI) const {
220 MachineLocation Location;
221 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
222 // Frame address. Currently handles register +- offset only.
223 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
224 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
226 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
231 /// EmitDwarfRegOp - Emit dwarf register operation.
232 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
233 const TargetRegisterInfo *RI = TM.getRegisterInfo();
234 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
235 AsmPrinter::EmitDwarfRegOp(MLoc);
237 unsigned Reg = MLoc.getReg();
238 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
239 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
240 // S registers are described as bit-pieces of a register
241 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
242 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
248 OutStreamer.AddComment("DW_OP_regx for S register");
249 EmitInt8(dwarf::DW_OP_regx);
251 OutStreamer.AddComment(Twine(SReg));
255 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
261 EmitInt8(dwarf::DW_OP_bit_piece);
265 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
266 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
267 // Q registers Q0-Q15 are described by composing two D registers together.
268 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
271 unsigned QReg = Reg - ARM::Q0;
272 unsigned D1 = 256 + 2 * QReg;
273 unsigned D2 = D1 + 1;
275 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
276 EmitInt8(dwarf::DW_OP_regx);
278 OutStreamer.AddComment("DW_OP_piece 8");
279 EmitInt8(dwarf::DW_OP_piece);
282 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
283 EmitInt8(dwarf::DW_OP_regx);
285 OutStreamer.AddComment("DW_OP_piece 8");
286 EmitInt8(dwarf::DW_OP_piece);
292 void ARMAsmPrinter::EmitFunctionEntryLabel() {
293 OutStreamer.ForceCodeRegion();
295 if (AFI->isThumbFunction()) {
296 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
297 OutStreamer.EmitThumbFunc(CurrentFnSym);
300 OutStreamer.EmitLabel(CurrentFnSym);
303 /// runOnMachineFunction - This uses the EmitInstruction()
304 /// method to print assembly for each instruction.
306 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
307 AFI = MF.getInfo<ARMFunctionInfo>();
308 MCP = MF.getConstantPool();
310 return AsmPrinter::runOnMachineFunction(MF);
313 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
314 raw_ostream &O, const char *Modifier) {
315 const MachineOperand &MO = MI->getOperand(OpNum);
316 unsigned TF = MO.getTargetFlags();
318 switch (MO.getType()) {
320 assert(0 && "<unknown operand type>");
321 case MachineOperand::MO_Register: {
322 unsigned Reg = MO.getReg();
323 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
324 assert(!MO.getSubReg() && "Subregs should be eliminated!");
325 O << ARMInstPrinter::getRegisterName(Reg);
328 case MachineOperand::MO_Immediate: {
329 int64_t Imm = MO.getImm();
331 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
332 (TF == ARMII::MO_LO16))
334 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
335 (TF == ARMII::MO_HI16))
340 case MachineOperand::MO_MachineBasicBlock:
341 O << *MO.getMBB()->getSymbol();
343 case MachineOperand::MO_GlobalAddress: {
344 const GlobalValue *GV = MO.getGlobal();
345 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
346 (TF & ARMII::MO_LO16))
348 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
349 (TF & ARMII::MO_HI16))
351 O << *Mang->getSymbol(GV);
353 printOffset(MO.getOffset(), O);
354 if (TF == ARMII::MO_PLT)
358 case MachineOperand::MO_ExternalSymbol: {
359 O << *GetExternalSymbolSymbol(MO.getSymbolName());
360 if (TF == ARMII::MO_PLT)
364 case MachineOperand::MO_ConstantPoolIndex:
365 O << *GetCPISymbol(MO.getIndex());
367 case MachineOperand::MO_JumpTableIndex:
368 O << *GetJTISymbol(MO.getIndex());
373 //===--------------------------------------------------------------------===//
375 MCSymbol *ARMAsmPrinter::
376 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
377 const MachineBasicBlock *MBB) const {
378 SmallString<60> Name;
379 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
380 << getFunctionNumber() << '_' << uid << '_' << uid2
381 << "_set_" << MBB->getNumber();
382 return OutContext.GetOrCreateSymbol(Name.str());
385 MCSymbol *ARMAsmPrinter::
386 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
387 SmallString<60> Name;
388 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
389 << getFunctionNumber() << '_' << uid << '_' << uid2;
390 return OutContext.GetOrCreateSymbol(Name.str());
394 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
395 SmallString<60> Name;
396 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
397 << getFunctionNumber();
398 return OutContext.GetOrCreateSymbol(Name.str());
401 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
402 unsigned AsmVariant, const char *ExtraCode,
404 // Does this asm operand have a single letter operand modifier?
405 if (ExtraCode && ExtraCode[0]) {
406 if (ExtraCode[1] != 0) return true; // Unknown modifier.
408 switch (ExtraCode[0]) {
409 default: return true; // Unknown modifier.
410 case 'a': // Print as a memory address.
411 if (MI->getOperand(OpNum).isReg()) {
413 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
418 case 'c': // Don't print "#" before an immediate operand.
419 if (!MI->getOperand(OpNum).isImm())
421 O << MI->getOperand(OpNum).getImm();
423 case 'P': // Print a VFP double precision register.
424 case 'q': // Print a NEON quad precision register.
425 printOperand(MI, OpNum, O);
427 case 'y': // Print a VFP single precision register as indexed double.
428 // This uses the ordering of the alias table to get the first 'd' register
429 // that overlaps the 's' register. Also, s0 is an odd register, hence the
430 // odd modulus check below.
431 if (MI->getOperand(OpNum).isReg()) {
432 unsigned Reg = MI->getOperand(OpNum).getReg();
433 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
434 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
435 (((Reg % 2) == 1) ? "[0]" : "[1]");
439 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
440 if (!MI->getOperand(OpNum).isImm())
442 O << ~(MI->getOperand(OpNum).getImm());
444 case 'L': // The low 16 bits of an immediate constant.
445 if (!MI->getOperand(OpNum).isImm())
447 O << (MI->getOperand(OpNum).getImm() & 0xffff);
449 case 'M': { // A register range suitable for LDM/STM.
450 if (!MI->getOperand(OpNum).isReg())
452 const MachineOperand &MO = MI->getOperand(OpNum);
453 unsigned RegBegin = MO.getReg();
454 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
455 // already got the operands in registers that are operands to the
456 // inline asm statement.
458 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
460 // FIXME: The register allocator not only may not have given us the
461 // registers in sequence, but may not be in ascending registers. This
462 // will require changes in the register allocator that'll need to be
463 // propagated down here if the operands change.
464 unsigned RegOps = OpNum + 1;
465 while (MI->getOperand(RegOps).isReg()) {
467 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
475 case 'R': // The most significant register of a pair.
476 case 'Q': { // The least significant register of a pair.
479 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
480 if (!FlagsOP.isImm())
482 unsigned Flags = FlagsOP.getImm();
483 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
486 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
487 if (RegOp >= MI->getNumOperands())
489 const MachineOperand &MO = MI->getOperand(RegOp);
492 unsigned Reg = MO.getReg();
493 O << ARMInstPrinter::getRegisterName(Reg);
497 // These modifiers are not yet supported.
498 case 'p': // The high single-precision register of a VFP double-precision
500 case 'e': // The low doubleword register of a NEON quad register.
501 case 'f': // The high doubleword register of a NEON quad register.
502 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
503 case 'H': // The highest-numbered register of a pair.
508 printOperand(MI, OpNum, O);
512 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
513 unsigned OpNum, unsigned AsmVariant,
514 const char *ExtraCode,
516 // Does this asm operand have a single letter operand modifier?
517 if (ExtraCode && ExtraCode[0]) {
518 if (ExtraCode[1] != 0) return true; // Unknown modifier.
520 switch (ExtraCode[0]) {
521 case 'A': // A memory operand for a VLD1/VST1 instruction.
522 default: return true; // Unknown modifier.
523 case 'm': // The base register of a memory operand.
524 if (!MI->getOperand(OpNum).isReg())
526 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
531 const MachineOperand &MO = MI->getOperand(OpNum);
532 assert(MO.isReg() && "unexpected inline asm memory operand");
533 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
537 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
538 if (Subtarget->isTargetDarwin()) {
539 Reloc::Model RelocM = TM.getRelocationModel();
540 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
541 // Declare all the text sections up front (before the DWARF sections
542 // emitted by AsmPrinter::doInitialization) so the assembler will keep
543 // them together at the beginning of the object file. This helps
544 // avoid out-of-range branches that are due a fundamental limitation of
545 // the way symbol offsets are encoded with the current Darwin ARM
547 const TargetLoweringObjectFileMachO &TLOFMacho =
548 static_cast<const TargetLoweringObjectFileMachO &>(
549 getObjFileLowering());
550 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
551 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
552 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
553 if (RelocM == Reloc::DynamicNoPIC) {
554 const MCSection *sect =
555 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
556 MCSectionMachO::S_SYMBOL_STUBS,
557 12, SectionKind::getText());
558 OutStreamer.SwitchSection(sect);
560 const MCSection *sect =
561 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
562 MCSectionMachO::S_SYMBOL_STUBS,
563 16, SectionKind::getText());
564 OutStreamer.SwitchSection(sect);
566 const MCSection *StaticInitSect =
567 OutContext.getMachOSection("__TEXT", "__StaticInit",
568 MCSectionMachO::S_REGULAR |
569 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
570 SectionKind::getText());
571 OutStreamer.SwitchSection(StaticInitSect);
575 // Use unified assembler syntax.
576 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
578 // Emit ARM Build Attributes
579 if (Subtarget->isTargetELF()) {
586 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
587 if (Subtarget->isTargetDarwin()) {
588 // All darwin targets use mach-o.
589 const TargetLoweringObjectFileMachO &TLOFMacho =
590 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
591 MachineModuleInfoMachO &MMIMacho =
592 MMI->getObjFileInfo<MachineModuleInfoMachO>();
594 // Output non-lazy-pointers for external and common global variables.
595 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
597 if (!Stubs.empty()) {
598 // Switch with ".non_lazy_symbol_pointer" directive.
599 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
601 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
603 OutStreamer.EmitLabel(Stubs[i].first);
604 // .indirect_symbol _foo
605 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
606 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
609 // External to current translation unit.
610 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
612 // Internal to current translation unit.
614 // When we place the LSDA into the TEXT section, the type info
615 // pointers need to be indirect and pc-rel. We accomplish this by
616 // using NLPs; however, sometimes the types are local to the file.
617 // We need to fill in the value for the NLP in those cases.
618 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
620 4/*size*/, 0/*addrspace*/);
624 OutStreamer.AddBlankLine();
627 Stubs = MMIMacho.GetHiddenGVStubList();
628 if (!Stubs.empty()) {
629 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
631 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
633 OutStreamer.EmitLabel(Stubs[i].first);
635 OutStreamer.EmitValue(MCSymbolRefExpr::
636 Create(Stubs[i].second.getPointer(),
638 4/*size*/, 0/*addrspace*/);
642 OutStreamer.AddBlankLine();
645 // Funny Darwin hack: This flag tells the linker that no global symbols
646 // contain code that falls through to other global symbols (e.g. the obvious
647 // implementation of multiple entry points). If this doesn't occur, the
648 // linker can safely perform dead code stripping. Since LLVM never
649 // generates code that does this, it is always safe to set.
650 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
654 //===----------------------------------------------------------------------===//
655 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
657 // The following seem like one-off assembler flags, but they actually need
658 // to appear in the .ARM.attributes section in ELF.
659 // Instead of subclassing the MCELFStreamer, we do the work here.
661 void ARMAsmPrinter::emitAttributes() {
663 emitARMAttributeSection();
665 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
666 bool emitFPU = false;
667 AttributeEmitter *AttrEmitter;
668 if (OutStreamer.hasRawTextSupport()) {
669 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
672 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
673 AttrEmitter = new ObjectAttributeEmitter(O);
676 AttrEmitter->MaybeSwitchVendor("aeabi");
678 std::string CPUString = Subtarget->getCPUString();
680 if (CPUString == "cortex-a8" ||
681 Subtarget->isCortexA8()) {
682 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
683 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
684 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
685 ARMBuildAttrs::ApplicationProfile);
686 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
687 ARMBuildAttrs::Allowed);
688 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
689 ARMBuildAttrs::AllowThumb32);
690 // Fixme: figure out when this is emitted.
691 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
692 // ARMBuildAttrs::AllowWMMXv1);
695 /// ADD additional Else-cases here!
696 } else if (CPUString == "xscale") {
697 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
698 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
699 ARMBuildAttrs::Allowed);
700 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
701 ARMBuildAttrs::Allowed);
702 } else if (CPUString == "generic") {
703 // FIXME: Why these defaults?
704 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
706 ARMBuildAttrs::Allowed);
707 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
708 ARMBuildAttrs::Allowed);
711 if (Subtarget->hasNEON() && emitFPU) {
712 /* NEON is not exactly a VFP architecture, but GAS emit one of
713 * neon/vfpv3/vfpv2 for .fpu parameters */
714 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
715 /* If emitted for NEON, omit from VFP below, since you can have both
716 * NEON and VFP in build attributes but only one .fpu */
721 if (Subtarget->hasVFP3()) {
722 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
723 ARMBuildAttrs::AllowFPv3A);
725 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
728 } else if (Subtarget->hasVFP2()) {
729 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
730 ARMBuildAttrs::AllowFPv2);
732 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
735 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
736 * since NEON can have 1 (allowed) or 2 (MAC operations) */
737 if (Subtarget->hasNEON()) {
738 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
739 ARMBuildAttrs::Allowed);
742 // Signal various FP modes.
744 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
745 ARMBuildAttrs::Allowed);
746 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
747 ARMBuildAttrs::Allowed);
750 if (NoInfsFPMath && NoNaNsFPMath)
751 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
752 ARMBuildAttrs::Allowed);
754 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
755 ARMBuildAttrs::AllowIEE754);
757 // FIXME: add more flags to ARMBuildAttrs.h
758 // 8-bytes alignment stuff.
759 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
760 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
762 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
763 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
764 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
765 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
767 // FIXME: Should we signal R9 usage?
769 if (Subtarget->hasDivide())
770 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
772 AttrEmitter->Finish();
776 void ARMAsmPrinter::emitARMAttributeSection() {
778 // [ <section-length> "vendor-name"
779 // [ <file-tag> <size> <attribute>*
780 // | <section-tag> <size> <section-number>* 0 <attribute>*
781 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
785 if (OutStreamer.hasRawTextSupport())
788 const ARMElfTargetObjectFile &TLOFELF =
789 static_cast<const ARMElfTargetObjectFile &>
790 (getObjFileLowering());
792 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
795 OutStreamer.EmitIntValue(0x41, 1);
798 //===----------------------------------------------------------------------===//
800 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
801 unsigned LabelId, MCContext &Ctx) {
803 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
804 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
808 static MCSymbolRefExpr::VariantKind
809 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
811 default: llvm_unreachable("Unknown modifier!");
812 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
813 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
814 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
815 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
816 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
817 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
819 return MCSymbolRefExpr::VK_None;
822 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
823 bool isIndirect = Subtarget->isTargetDarwin() &&
824 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
826 return Mang->getSymbol(GV);
828 // FIXME: Remove this when Darwin transition to @GOT like syntax.
829 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
830 MachineModuleInfoMachO &MMIMachO =
831 MMI->getObjFileInfo<MachineModuleInfoMachO>();
832 MachineModuleInfoImpl::StubValueTy &StubSym =
833 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
834 MMIMachO.getGVStubEntry(MCSym);
835 if (StubSym.getPointer() == 0)
836 StubSym = MachineModuleInfoImpl::
837 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
842 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
843 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
845 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
848 if (ACPV->isLSDA()) {
849 SmallString<128> Str;
850 raw_svector_ostream OS(Str);
851 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
852 MCSym = OutContext.GetOrCreateSymbol(OS.str());
853 } else if (ACPV->isBlockAddress()) {
854 const BlockAddress *BA =
855 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
856 MCSym = GetBlockAddressSymbol(BA);
857 } else if (ACPV->isGlobalValue()) {
858 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
859 MCSym = GetARMGVSymbol(GV);
860 } else if (ACPV->isMachineBasicBlock()) {
861 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
862 MCSym = MBB->getSymbol();
864 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
865 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
866 MCSym = GetExternalSymbolSymbol(Sym);
869 // Create an MCSymbol for the reference.
871 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
874 if (ACPV->getPCAdjustment()) {
875 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
879 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
881 MCBinaryExpr::CreateAdd(PCRelExpr,
882 MCConstantExpr::Create(ACPV->getPCAdjustment(),
885 if (ACPV->mustAddCurrentAddress()) {
886 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
887 // label, so just emit a local label end reference that instead.
888 MCSymbol *DotSym = OutContext.CreateTempSymbol();
889 OutStreamer.EmitLabel(DotSym);
890 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
891 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
893 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
895 OutStreamer.EmitValue(Expr, Size);
898 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
899 unsigned Opcode = MI->getOpcode();
901 if (Opcode == ARM::BR_JTadd)
903 else if (Opcode == ARM::BR_JTm)
906 const MachineOperand &MO1 = MI->getOperand(OpNum);
907 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
908 unsigned JTI = MO1.getIndex();
910 // Tag the jump table appropriately for precise disassembly.
911 OutStreamer.EmitJumpTable32Region();
913 // Emit a label for the jump table.
914 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
915 OutStreamer.EmitLabel(JTISymbol);
917 // Emit each entry of the table.
918 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
919 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
920 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
922 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
923 MachineBasicBlock *MBB = JTBBs[i];
924 // Construct an MCExpr for the entry. We want a value of the form:
925 // (BasicBlockAddr - TableBeginAddr)
927 // For example, a table with entries jumping to basic blocks BB0 and BB1
930 // .word (LBB0 - LJTI_0_0)
931 // .word (LBB1 - LJTI_0_0)
932 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
934 if (TM.getRelocationModel() == Reloc::PIC_)
935 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
938 // If we're generating a table of Thumb addresses in static relocation
939 // model, we need to add one to keep interworking correctly.
940 else if (AFI->isThumbFunction())
941 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
943 OutStreamer.EmitValue(Expr, 4);
947 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
948 unsigned Opcode = MI->getOpcode();
949 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
950 const MachineOperand &MO1 = MI->getOperand(OpNum);
951 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
952 unsigned JTI = MO1.getIndex();
954 // Emit a label for the jump table.
955 if (MI->getOpcode() == ARM::t2TBB_JT) {
956 OutStreamer.EmitJumpTable8Region();
957 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
958 OutStreamer.EmitJumpTable16Region();
960 OutStreamer.EmitJumpTable32Region();
963 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
964 OutStreamer.EmitLabel(JTISymbol);
966 // Emit each entry of the table.
967 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
968 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
969 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
970 unsigned OffsetWidth = 4;
971 if (MI->getOpcode() == ARM::t2TBB_JT)
973 else if (MI->getOpcode() == ARM::t2TBH_JT)
976 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
977 MachineBasicBlock *MBB = JTBBs[i];
978 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
980 // If this isn't a TBB or TBH, the entries are direct branch instructions.
981 if (OffsetWidth == 4) {
983 BrInst.setOpcode(ARM::t2B);
984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
986 BrInst.addOperand(MCOperand::CreateReg(0));
987 OutStreamer.EmitInstruction(BrInst);
990 // Otherwise it's an offset from the dispatch instruction. Construct an
991 // MCExpr for the entry. We want a value of the form:
992 // (BasicBlockAddr - TableBeginAddr) / 2
994 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
997 // .byte (LBB0 - LJTI_0_0) / 2
998 // .byte (LBB1 - LJTI_0_0) / 2
1000 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1001 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1003 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1005 OutStreamer.EmitValue(Expr, OffsetWidth);
1009 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1011 unsigned NOps = MI->getNumOperands();
1013 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1014 // cast away const; DIetc do not take const operands for some reason.
1015 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1018 // Frame address. Currently handles register +- offset only.
1019 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1020 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1023 printOperand(MI, NOps-2, OS);
1026 static void populateADROperands(MCInst &Inst, unsigned Dest,
1027 const MCSymbol *Label,
1028 unsigned pred, unsigned ccreg,
1030 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1031 Inst.addOperand(MCOperand::CreateReg(Dest));
1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1033 // Add predicate operands.
1034 Inst.addOperand(MCOperand::CreateImm(pred));
1035 Inst.addOperand(MCOperand::CreateReg(ccreg));
1038 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1042 // Emit the instruction as usual, just patch the opcode.
1043 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1044 TmpInst.setOpcode(Opcode);
1045 OutStreamer.EmitInstruction(TmpInst);
1048 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1049 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1050 "Only instruction which are involved into frame setup code are allowed");
1052 const MachineFunction &MF = *MI->getParent()->getParent();
1053 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1054 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1056 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1057 unsigned Opc = MI->getOpcode();
1058 unsigned SrcReg, DstReg;
1060 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1061 // Two special cases:
1062 // 1) tPUSH does not have src/dst regs.
1063 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1064 // load. Yes, this is pretty fragile, but for now I don't see better
1066 SrcReg = DstReg = ARM::SP;
1068 SrcReg = MI->getOperand(1).getReg();
1069 DstReg = MI->getOperand(0).getReg();
1072 // Try to figure out the unwinding opcode out of src / dst regs.
1073 if (MI->getDesc().mayStore()) {
1075 assert(DstReg == ARM::SP &&
1076 "Only stack pointer as a destination reg is supported");
1078 SmallVector<unsigned, 4> RegList;
1079 // Skip src & dst reg, and pred ops.
1080 unsigned StartOp = 2 + 2;
1081 // Use all the operands.
1082 unsigned NumOffset = 0;
1087 assert(0 && "Unsupported opcode for unwinding information");
1089 // Special case here: no src & dst reg, but two extra imp ops.
1090 StartOp = 2; NumOffset = 2;
1091 case ARM::STMDB_UPD:
1092 case ARM::t2STMDB_UPD:
1093 case ARM::VSTMDDB_UPD:
1094 assert(SrcReg == ARM::SP &&
1095 "Only stack pointer as a source reg is supported");
1096 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1098 RegList.push_back(MI->getOperand(i).getReg());
1100 case ARM::STR_PRE_IMM:
1101 case ARM::STR_PRE_REG:
1102 assert(MI->getOperand(2).getReg() == ARM::SP &&
1103 "Only stack pointer as a source reg is supported");
1104 RegList.push_back(SrcReg);
1107 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1109 // Changes of stack / frame pointer.
1110 if (SrcReg == ARM::SP) {
1115 assert(0 && "Unsupported opcode for unwinding information");
1120 Offset = -MI->getOperand(2).getImm();
1123 Offset = MI->getOperand(2).getImm();
1126 Offset = MI->getOperand(2).getImm()*4;
1130 Offset = -MI->getOperand(2).getImm()*4;
1132 case ARM::tLDRpci: {
1133 // Grab the constpool index and check, whether it corresponds to
1134 // original or cloned constpool entry.
1135 unsigned CPI = MI->getOperand(1).getIndex();
1136 const MachineConstantPool *MCP = MF.getConstantPool();
1137 if (CPI >= MCP->getConstants().size())
1138 CPI = AFI.getOriginalCPIdx(CPI);
1139 assert(CPI != -1U && "Invalid constpool index");
1141 // Derive the actual offset.
1142 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1143 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1144 // FIXME: Check for user, it should be "add" instruction!
1145 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1150 if (DstReg == FramePtr && FramePtr != ARM::SP)
1151 // Set-up of the frame pointer. Positive values correspond to "add"
1153 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1154 else if (DstReg == ARM::SP) {
1155 // Change of SP by an offset. Positive values correspond to "sub"
1157 OutStreamer.EmitPad(Offset);
1160 assert(0 && "Unsupported opcode for unwinding information");
1162 } else if (DstReg == ARM::SP) {
1163 // FIXME: .movsp goes here
1165 assert(0 && "Unsupported opcode for unwinding information");
1169 assert(0 && "Unsupported opcode for unwinding information");
1174 extern cl::opt<bool> EnableARMEHABI;
1176 // Simple pseudo-instructions have their lowering (with expansion to real
1177 // instructions) auto-generated.
1178 #include "ARMGenMCPseudoLowering.inc"
1180 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1181 if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1182 OutStreamer.EmitCodeRegion();
1184 // Emit unwinding stuff for frame-related instructions
1185 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1186 EmitUnwindingInstruction(MI);
1188 // Do any auto-generated pseudo lowerings.
1189 if (emitPseudoExpansionLowering(OutStreamer, MI))
1192 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1193 "Pseudo flag setting opcode should be expanded early");
1195 // Check for manual lowerings.
1196 unsigned Opc = MI->getOpcode();
1198 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1199 case ARM::DBG_VALUE: {
1200 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1201 SmallString<128> TmpStr;
1202 raw_svector_ostream OS(TmpStr);
1203 PrintDebugValueComment(MI, OS);
1204 OutStreamer.EmitRawText(StringRef(OS.str()));
1209 case ARM::tLEApcrel:
1210 case ARM::t2LEApcrel: {
1211 // FIXME: Need to also handle globals and externals
1213 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1214 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1216 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1217 GetCPISymbol(MI->getOperand(1).getIndex()),
1218 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1220 OutStreamer.EmitInstruction(TmpInst);
1223 case ARM::LEApcrelJT:
1224 case ARM::tLEApcrelJT:
1225 case ARM::t2LEApcrelJT: {
1227 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1228 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1230 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1231 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1232 MI->getOperand(2).getImm()),
1233 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1235 OutStreamer.EmitInstruction(TmpInst);
1238 // Darwin call instructions are just normal call instructions with different
1239 // clobber semantics (they clobber R9).
1240 case ARM::BXr9_CALL:
1241 case ARM::BX_CALL: {
1244 TmpInst.setOpcode(ARM::MOVr);
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1247 // Add predicate operands.
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 // Add 's' bit operand (always reg0 for this)
1251 TmpInst.addOperand(MCOperand::CreateReg(0));
1252 OutStreamer.EmitInstruction(TmpInst);
1256 TmpInst.setOpcode(ARM::BX);
1257 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1258 OutStreamer.EmitInstruction(TmpInst);
1262 case ARM::tBXr9_CALL:
1263 case ARM::tBX_CALL: {
1266 TmpInst.setOpcode(ARM::tMOVr);
1267 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1268 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1269 // Add predicate operands.
1270 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1271 TmpInst.addOperand(MCOperand::CreateReg(0));
1272 OutStreamer.EmitInstruction(TmpInst);
1276 TmpInst.setOpcode(ARM::tBX);
1277 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1278 // Add predicate operands.
1279 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1280 TmpInst.addOperand(MCOperand::CreateReg(0));
1281 OutStreamer.EmitInstruction(TmpInst);
1285 case ARM::BMOVPCRXr9_CALL:
1286 case ARM::BMOVPCRX_CALL: {
1289 TmpInst.setOpcode(ARM::MOVr);
1290 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1291 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1292 // Add predicate operands.
1293 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1294 TmpInst.addOperand(MCOperand::CreateReg(0));
1295 // Add 's' bit operand (always reg0 for this)
1296 TmpInst.addOperand(MCOperand::CreateReg(0));
1297 OutStreamer.EmitInstruction(TmpInst);
1301 TmpInst.setOpcode(ARM::MOVr);
1302 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1303 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1304 // Add predicate operands.
1305 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1306 TmpInst.addOperand(MCOperand::CreateReg(0));
1307 // Add 's' bit operand (always reg0 for this)
1308 TmpInst.addOperand(MCOperand::CreateReg(0));
1309 OutStreamer.EmitInstruction(TmpInst);
1313 case ARM::MOVi16_ga_pcrel:
1314 case ARM::t2MOVi16_ga_pcrel: {
1316 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1317 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1319 unsigned TF = MI->getOperand(1).getTargetFlags();
1320 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1321 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1322 MCSymbol *GVSym = GetARMGVSymbol(GV);
1323 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1325 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1326 getFunctionNumber(),
1327 MI->getOperand(2).getImm(), OutContext);
1328 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1329 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1330 const MCExpr *PCRelExpr =
1331 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1332 MCBinaryExpr::CreateAdd(LabelSymExpr,
1333 MCConstantExpr::Create(PCAdj, OutContext),
1334 OutContext), OutContext), OutContext);
1335 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1337 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1338 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1341 // Add predicate operands.
1342 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1343 TmpInst.addOperand(MCOperand::CreateReg(0));
1344 // Add 's' bit operand (always reg0 for this)
1345 TmpInst.addOperand(MCOperand::CreateReg(0));
1346 OutStreamer.EmitInstruction(TmpInst);
1349 case ARM::MOVTi16_ga_pcrel:
1350 case ARM::t2MOVTi16_ga_pcrel: {
1352 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1353 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1354 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1355 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1357 unsigned TF = MI->getOperand(2).getTargetFlags();
1358 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1359 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1360 MCSymbol *GVSym = GetARMGVSymbol(GV);
1361 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1363 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1364 getFunctionNumber(),
1365 MI->getOperand(3).getImm(), OutContext);
1366 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1367 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1368 const MCExpr *PCRelExpr =
1369 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1370 MCBinaryExpr::CreateAdd(LabelSymExpr,
1371 MCConstantExpr::Create(PCAdj, OutContext),
1372 OutContext), OutContext), OutContext);
1373 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1375 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1376 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1378 // Add predicate operands.
1379 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1380 TmpInst.addOperand(MCOperand::CreateReg(0));
1381 // Add 's' bit operand (always reg0 for this)
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 OutStreamer.EmitInstruction(TmpInst);
1386 case ARM::tPICADD: {
1387 // This is a pseudo op for a label + instruction sequence, which looks like:
1390 // This adds the address of LPC0 to r0.
1393 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1394 getFunctionNumber(), MI->getOperand(2).getImm(),
1397 // Form and emit the add.
1399 AddInst.setOpcode(ARM::tADDhirr);
1400 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1401 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1402 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1403 // Add predicate operands.
1404 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1405 AddInst.addOperand(MCOperand::CreateReg(0));
1406 OutStreamer.EmitInstruction(AddInst);
1410 // This is a pseudo op for a label + instruction sequence, which looks like:
1413 // This adds the address of LPC0 to r0.
1416 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1417 getFunctionNumber(), MI->getOperand(2).getImm(),
1420 // Form and emit the add.
1422 AddInst.setOpcode(ARM::ADDrr);
1423 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1424 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1425 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1426 // Add predicate operands.
1427 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1428 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1429 // Add 's' bit operand (always reg0 for this)
1430 AddInst.addOperand(MCOperand::CreateReg(0));
1431 OutStreamer.EmitInstruction(AddInst);
1441 case ARM::PICLDRSH: {
1442 // This is a pseudo op for a label + instruction sequence, which looks like:
1445 // The LCP0 label is referenced by a constant pool entry in order to get
1446 // a PC-relative address at the ldr instruction.
1449 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1450 getFunctionNumber(), MI->getOperand(2).getImm(),
1453 // Form and emit the load
1455 switch (MI->getOpcode()) {
1457 llvm_unreachable("Unexpected opcode!");
1458 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1459 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1460 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1461 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1462 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1463 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1464 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1465 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1468 LdStInst.setOpcode(Opcode);
1469 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1470 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1471 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1472 LdStInst.addOperand(MCOperand::CreateImm(0));
1473 // Add predicate operands.
1474 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1475 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1476 OutStreamer.EmitInstruction(LdStInst);
1480 case ARM::CONSTPOOL_ENTRY: {
1481 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1482 /// in the function. The first operand is the ID# for this instruction, the
1483 /// second is the index into the MachineConstantPool that this is, the third
1484 /// is the size in bytes of this constant pool entry.
1485 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1486 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1490 // Mark the constant pool entry as data if we're not already in a data
1492 OutStreamer.EmitDataRegion();
1493 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1495 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1496 if (MCPE.isMachineConstantPoolEntry())
1497 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1499 EmitGlobalConstant(MCPE.Val.ConstVal);
1502 case ARM::t2BR_JT: {
1503 // Lower and emit the instruction itself, then the jump table following it.
1505 TmpInst.setOpcode(ARM::tMOVr);
1506 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1507 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1508 // Add predicate operands.
1509 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1510 TmpInst.addOperand(MCOperand::CreateReg(0));
1511 OutStreamer.EmitInstruction(TmpInst);
1512 // Output the data for the jump table itself
1516 case ARM::t2TBB_JT: {
1517 // Lower and emit the instruction itself, then the jump table following it.
1520 TmpInst.setOpcode(ARM::t2TBB);
1521 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1522 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1523 // Add predicate operands.
1524 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1525 TmpInst.addOperand(MCOperand::CreateReg(0));
1526 OutStreamer.EmitInstruction(TmpInst);
1527 // Output the data for the jump table itself
1529 // Make sure the next instruction is 2-byte aligned.
1533 case ARM::t2TBH_JT: {
1534 // Lower and emit the instruction itself, then the jump table following it.
1537 TmpInst.setOpcode(ARM::t2TBH);
1538 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1539 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1540 // Add predicate operands.
1541 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1542 TmpInst.addOperand(MCOperand::CreateReg(0));
1543 OutStreamer.EmitInstruction(TmpInst);
1544 // Output the data for the jump table itself
1550 // Lower and emit the instruction itself, then the jump table following it.
1553 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1554 ARM::MOVr : ARM::tMOVr;
1555 TmpInst.setOpcode(Opc);
1556 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1557 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1558 // Add predicate operands.
1559 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1560 TmpInst.addOperand(MCOperand::CreateReg(0));
1561 // Add 's' bit operand (always reg0 for this)
1562 if (Opc == ARM::MOVr)
1563 TmpInst.addOperand(MCOperand::CreateReg(0));
1564 OutStreamer.EmitInstruction(TmpInst);
1566 // Make sure the Thumb jump table is 4-byte aligned.
1567 if (Opc == ARM::tMOVr)
1570 // Output the data for the jump table itself
1575 // Lower and emit the instruction itself, then the jump table following it.
1578 if (MI->getOperand(1).getReg() == 0) {
1580 TmpInst.setOpcode(ARM::LDRi12);
1581 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1582 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1583 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1585 TmpInst.setOpcode(ARM::LDRrs);
1586 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1587 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1588 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1589 TmpInst.addOperand(MCOperand::CreateImm(0));
1591 // Add predicate operands.
1592 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1593 TmpInst.addOperand(MCOperand::CreateReg(0));
1594 OutStreamer.EmitInstruction(TmpInst);
1596 // Output the data for the jump table itself
1600 case ARM::BR_JTadd: {
1601 // Lower and emit the instruction itself, then the jump table following it.
1602 // add pc, target, idx
1604 TmpInst.setOpcode(ARM::ADDrr);
1605 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1606 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1607 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1608 // Add predicate operands.
1609 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1610 TmpInst.addOperand(MCOperand::CreateReg(0));
1611 // Add 's' bit operand (always reg0 for this)
1612 TmpInst.addOperand(MCOperand::CreateReg(0));
1613 OutStreamer.EmitInstruction(TmpInst);
1615 // Output the data for the jump table itself
1620 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1621 // FIXME: Remove this special case when they do.
1622 if (!Subtarget->isTargetDarwin()) {
1623 //.long 0xe7ffdefe @ trap
1624 uint32_t Val = 0xe7ffdefeUL;
1625 OutStreamer.AddComment("trap");
1626 OutStreamer.EmitIntValue(Val, 4);
1632 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1633 // FIXME: Remove this special case when they do.
1634 if (!Subtarget->isTargetDarwin()) {
1635 //.short 57086 @ trap
1636 uint16_t Val = 0xdefe;
1637 OutStreamer.AddComment("trap");
1638 OutStreamer.EmitIntValue(Val, 2);
1643 case ARM::t2Int_eh_sjlj_setjmp:
1644 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1645 case ARM::tInt_eh_sjlj_setjmp: {
1646 // Two incoming args: GPR:$src, GPR:$val
1649 // str $val, [$src, #4]
1654 unsigned SrcReg = MI->getOperand(0).getReg();
1655 unsigned ValReg = MI->getOperand(1).getReg();
1656 MCSymbol *Label = GetARMSJLJEHLabel();
1659 TmpInst.setOpcode(ARM::tMOVr);
1660 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1661 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1663 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1664 TmpInst.addOperand(MCOperand::CreateReg(0));
1665 OutStreamer.AddComment("eh_setjmp begin");
1666 OutStreamer.EmitInstruction(TmpInst);
1670 TmpInst.setOpcode(ARM::tADDi3);
1671 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1673 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1674 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1675 TmpInst.addOperand(MCOperand::CreateImm(7));
1677 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1678 TmpInst.addOperand(MCOperand::CreateReg(0));
1679 OutStreamer.EmitInstruction(TmpInst);
1683 TmpInst.setOpcode(ARM::tSTRi);
1684 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1685 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1686 // The offset immediate is #4. The operand value is scaled by 4 for the
1687 // tSTR instruction.
1688 TmpInst.addOperand(MCOperand::CreateImm(1));
1690 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1691 TmpInst.addOperand(MCOperand::CreateReg(0));
1692 OutStreamer.EmitInstruction(TmpInst);
1696 TmpInst.setOpcode(ARM::tMOVi8);
1697 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1698 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1699 TmpInst.addOperand(MCOperand::CreateImm(0));
1701 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1702 TmpInst.addOperand(MCOperand::CreateReg(0));
1703 OutStreamer.EmitInstruction(TmpInst);
1706 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1708 TmpInst.setOpcode(ARM::tB);
1709 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1710 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1711 TmpInst.addOperand(MCOperand::CreateReg(0));
1712 OutStreamer.EmitInstruction(TmpInst);
1716 TmpInst.setOpcode(ARM::tMOVi8);
1717 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1718 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1719 TmpInst.addOperand(MCOperand::CreateImm(1));
1721 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1722 TmpInst.addOperand(MCOperand::CreateReg(0));
1723 OutStreamer.AddComment("eh_setjmp end");
1724 OutStreamer.EmitInstruction(TmpInst);
1726 OutStreamer.EmitLabel(Label);
1730 case ARM::Int_eh_sjlj_setjmp_nofp:
1731 case ARM::Int_eh_sjlj_setjmp: {
1732 // Two incoming args: GPR:$src, GPR:$val
1734 // str $val, [$src, #+4]
1738 unsigned SrcReg = MI->getOperand(0).getReg();
1739 unsigned ValReg = MI->getOperand(1).getReg();
1743 TmpInst.setOpcode(ARM::ADDri);
1744 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1745 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1746 TmpInst.addOperand(MCOperand::CreateImm(8));
1748 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1749 TmpInst.addOperand(MCOperand::CreateReg(0));
1750 // 's' bit operand (always reg0 for this).
1751 TmpInst.addOperand(MCOperand::CreateReg(0));
1752 OutStreamer.AddComment("eh_setjmp begin");
1753 OutStreamer.EmitInstruction(TmpInst);
1757 TmpInst.setOpcode(ARM::STRi12);
1758 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1759 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1760 TmpInst.addOperand(MCOperand::CreateImm(4));
1762 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1763 TmpInst.addOperand(MCOperand::CreateReg(0));
1764 OutStreamer.EmitInstruction(TmpInst);
1768 TmpInst.setOpcode(ARM::MOVi);
1769 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1770 TmpInst.addOperand(MCOperand::CreateImm(0));
1772 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1773 TmpInst.addOperand(MCOperand::CreateReg(0));
1774 // 's' bit operand (always reg0 for this).
1775 TmpInst.addOperand(MCOperand::CreateReg(0));
1776 OutStreamer.EmitInstruction(TmpInst);
1780 TmpInst.setOpcode(ARM::ADDri);
1781 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1782 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1783 TmpInst.addOperand(MCOperand::CreateImm(0));
1785 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1786 TmpInst.addOperand(MCOperand::CreateReg(0));
1787 // 's' bit operand (always reg0 for this).
1788 TmpInst.addOperand(MCOperand::CreateReg(0));
1789 OutStreamer.EmitInstruction(TmpInst);
1793 TmpInst.setOpcode(ARM::MOVi);
1794 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1795 TmpInst.addOperand(MCOperand::CreateImm(1));
1797 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1798 TmpInst.addOperand(MCOperand::CreateReg(0));
1799 // 's' bit operand (always reg0 for this).
1800 TmpInst.addOperand(MCOperand::CreateReg(0));
1801 OutStreamer.AddComment("eh_setjmp end");
1802 OutStreamer.EmitInstruction(TmpInst);
1806 case ARM::Int_eh_sjlj_longjmp: {
1807 // ldr sp, [$src, #8]
1808 // ldr $scratch, [$src, #4]
1811 unsigned SrcReg = MI->getOperand(0).getReg();
1812 unsigned ScratchReg = MI->getOperand(1).getReg();
1815 TmpInst.setOpcode(ARM::LDRi12);
1816 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1817 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1818 TmpInst.addOperand(MCOperand::CreateImm(8));
1820 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1821 TmpInst.addOperand(MCOperand::CreateReg(0));
1822 OutStreamer.EmitInstruction(TmpInst);
1826 TmpInst.setOpcode(ARM::LDRi12);
1827 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1828 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1829 TmpInst.addOperand(MCOperand::CreateImm(4));
1831 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1832 TmpInst.addOperand(MCOperand::CreateReg(0));
1833 OutStreamer.EmitInstruction(TmpInst);
1837 TmpInst.setOpcode(ARM::LDRi12);
1838 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1839 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1840 TmpInst.addOperand(MCOperand::CreateImm(0));
1842 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1843 TmpInst.addOperand(MCOperand::CreateReg(0));
1844 OutStreamer.EmitInstruction(TmpInst);
1848 TmpInst.setOpcode(ARM::BX);
1849 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1851 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1852 TmpInst.addOperand(MCOperand::CreateReg(0));
1853 OutStreamer.EmitInstruction(TmpInst);
1857 case ARM::tInt_eh_sjlj_longjmp: {
1858 // ldr $scratch, [$src, #8]
1860 // ldr $scratch, [$src, #4]
1863 unsigned SrcReg = MI->getOperand(0).getReg();
1864 unsigned ScratchReg = MI->getOperand(1).getReg();
1867 TmpInst.setOpcode(ARM::tLDRi);
1868 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1869 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1870 // The offset immediate is #8. The operand value is scaled by 4 for the
1871 // tLDR instruction.
1872 TmpInst.addOperand(MCOperand::CreateImm(2));
1874 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1875 TmpInst.addOperand(MCOperand::CreateReg(0));
1876 OutStreamer.EmitInstruction(TmpInst);
1880 TmpInst.setOpcode(ARM::tMOVr);
1881 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1882 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1884 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1885 TmpInst.addOperand(MCOperand::CreateReg(0));
1886 OutStreamer.EmitInstruction(TmpInst);
1890 TmpInst.setOpcode(ARM::tLDRi);
1891 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1892 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1893 TmpInst.addOperand(MCOperand::CreateImm(1));
1895 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1896 TmpInst.addOperand(MCOperand::CreateReg(0));
1897 OutStreamer.EmitInstruction(TmpInst);
1901 TmpInst.setOpcode(ARM::tLDRr);
1902 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1903 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1904 TmpInst.addOperand(MCOperand::CreateReg(0));
1906 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1907 TmpInst.addOperand(MCOperand::CreateReg(0));
1908 OutStreamer.EmitInstruction(TmpInst);
1912 TmpInst.setOpcode(ARM::tBX);
1913 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1915 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1916 TmpInst.addOperand(MCOperand::CreateReg(0));
1917 OutStreamer.EmitInstruction(TmpInst);
1924 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1926 OutStreamer.EmitInstruction(TmpInst);
1929 //===----------------------------------------------------------------------===//
1930 // Target Registry Stuff
1931 //===----------------------------------------------------------------------===//
1933 // Force static initialization.
1934 extern "C" void LLVMInitializeARMAsmPrinter() {
1935 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1936 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);