1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/TargetRegistry.h"
54 #include "llvm/Support/raw_ostream.h"
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
68 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
69 virtual void Finish() = 0;
70 virtual ~AttributeEmitter() {}
73 class AsmAttributeEmitter : public AttributeEmitter {
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
85 void EmitTextAttribute(unsigned Attribute, StringRef String) {
87 case ARMBuildAttrs::CPU_name:
88 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
90 /* GAS requires .fpu to be emitted regardless of EABI attribute */
91 case ARMBuildAttrs::Advanced_SIMD_arch:
92 case ARMBuildAttrs::VFP_arch:
93 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
95 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
101 class ObjectAttributeEmitter : public AttributeEmitter {
102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
113 StringRef StringValue;
116 MCObjectStreamer &Streamer;
117 StringRef CurrentVendor;
118 SmallVector<AttributeItemType, 64> Contents;
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
129 Size += sizeof(int8_t); // Is this really necessary?
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
148 CurrentVendor = Vendor;
150 assert(Contents.size() == 0);
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
172 ContentsSize += getULEBSize(Attribute);
174 ContentsSize += String.size()+1;
176 Contents.push_back(attr);
180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
184 const size_t TagHeaderSize = 1 + 4;
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
187 Streamer.EmitBytes(CurrentVendor, 0);
188 Streamer.EmitIntValue(0, 1); // '\0'
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
197 Streamer.EmitULEB128IntValue(item.Tag, 0);
199 case AttributeItemType::NumericAttribute:
200 Streamer.EmitULEB128IntValue(item.IntValue, 0);
202 case AttributeItemType::TextAttribute:
203 Streamer.EmitBytes(item.StringValue.upper(), 0);
204 Streamer.EmitIntValue(0, 1); // '\0'
207 assert(0 && "Invalid attribute type");
215 } // end of anonymous namespace
217 MachineLocation ARMAsmPrinter::
218 getDebugValueLocation(const MachineInstr *MI) const {
219 MachineLocation Location;
220 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
221 // Frame address. Currently handles register +- offset only.
222 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
223 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
225 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
230 /// EmitDwarfRegOp - Emit dwarf register operation.
231 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
232 const TargetRegisterInfo *RI = TM.getRegisterInfo();
233 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
234 AsmPrinter::EmitDwarfRegOp(MLoc);
236 unsigned Reg = MLoc.getReg();
237 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
238 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
239 // S registers are described as bit-pieces of a register
240 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
241 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
243 unsigned SReg = Reg - ARM::S0;
244 bool odd = SReg & 0x1;
245 unsigned Rx = 256 + (SReg >> 1);
247 OutStreamer.AddComment("DW_OP_regx for S register");
248 EmitInt8(dwarf::DW_OP_regx);
250 OutStreamer.AddComment(Twine(SReg));
254 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
260 EmitInt8(dwarf::DW_OP_bit_piece);
264 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
265 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
266 // Q registers Q0-Q15 are described by composing two D registers together.
267 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
270 unsigned QReg = Reg - ARM::Q0;
271 unsigned D1 = 256 + 2 * QReg;
272 unsigned D2 = D1 + 1;
274 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
275 EmitInt8(dwarf::DW_OP_regx);
277 OutStreamer.AddComment("DW_OP_piece 8");
278 EmitInt8(dwarf::DW_OP_piece);
281 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
282 EmitInt8(dwarf::DW_OP_regx);
284 OutStreamer.AddComment("DW_OP_piece 8");
285 EmitInt8(dwarf::DW_OP_piece);
291 void ARMAsmPrinter::EmitFunctionEntryLabel() {
292 OutStreamer.ForceCodeRegion();
294 if (AFI->isThumbFunction()) {
295 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
296 OutStreamer.EmitThumbFunc(CurrentFnSym);
299 OutStreamer.EmitLabel(CurrentFnSym);
302 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
303 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
304 assert(Size && "C++ constructor pointer had zero size!");
306 const GlobalValue *GV = dyn_cast<GlobalValue>(CV);
307 assert(GV && "C++ constructor pointer was not a GlobalValue!");
309 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
310 (Subtarget->isTargetDarwin()
311 ? MCSymbolRefExpr::VK_None
312 : MCSymbolRefExpr::VK_ARM_TARGET1),
315 OutStreamer.EmitValue(E, Size);
318 /// runOnMachineFunction - This uses the EmitInstruction()
319 /// method to print assembly for each instruction.
321 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
322 AFI = MF.getInfo<ARMFunctionInfo>();
323 MCP = MF.getConstantPool();
325 return AsmPrinter::runOnMachineFunction(MF);
328 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
329 raw_ostream &O, const char *Modifier) {
330 const MachineOperand &MO = MI->getOperand(OpNum);
331 unsigned TF = MO.getTargetFlags();
333 switch (MO.getType()) {
335 assert(0 && "<unknown operand type>");
336 case MachineOperand::MO_Register: {
337 unsigned Reg = MO.getReg();
338 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
339 assert(!MO.getSubReg() && "Subregs should be eliminated!");
340 O << ARMInstPrinter::getRegisterName(Reg);
343 case MachineOperand::MO_Immediate: {
344 int64_t Imm = MO.getImm();
346 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
347 (TF == ARMII::MO_LO16))
349 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
350 (TF == ARMII::MO_HI16))
355 case MachineOperand::MO_MachineBasicBlock:
356 O << *MO.getMBB()->getSymbol();
358 case MachineOperand::MO_GlobalAddress: {
359 const GlobalValue *GV = MO.getGlobal();
360 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
361 (TF & ARMII::MO_LO16))
363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
364 (TF & ARMII::MO_HI16))
366 O << *Mang->getSymbol(GV);
368 printOffset(MO.getOffset(), O);
369 if (TF == ARMII::MO_PLT)
373 case MachineOperand::MO_ExternalSymbol: {
374 O << *GetExternalSymbolSymbol(MO.getSymbolName());
375 if (TF == ARMII::MO_PLT)
379 case MachineOperand::MO_ConstantPoolIndex:
380 O << *GetCPISymbol(MO.getIndex());
382 case MachineOperand::MO_JumpTableIndex:
383 O << *GetJTISymbol(MO.getIndex());
388 //===--------------------------------------------------------------------===//
390 MCSymbol *ARMAsmPrinter::
391 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
392 const MachineBasicBlock *MBB) const {
393 SmallString<60> Name;
394 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
395 << getFunctionNumber() << '_' << uid << '_' << uid2
396 << "_set_" << MBB->getNumber();
397 return OutContext.GetOrCreateSymbol(Name.str());
400 MCSymbol *ARMAsmPrinter::
401 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
402 SmallString<60> Name;
403 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
404 << getFunctionNumber() << '_' << uid << '_' << uid2;
405 return OutContext.GetOrCreateSymbol(Name.str());
409 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
410 SmallString<60> Name;
411 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
412 << getFunctionNumber();
413 return OutContext.GetOrCreateSymbol(Name.str());
416 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
417 unsigned AsmVariant, const char *ExtraCode,
419 // Does this asm operand have a single letter operand modifier?
420 if (ExtraCode && ExtraCode[0]) {
421 if (ExtraCode[1] != 0) return true; // Unknown modifier.
423 switch (ExtraCode[0]) {
424 default: return true; // Unknown modifier.
425 case 'a': // Print as a memory address.
426 if (MI->getOperand(OpNum).isReg()) {
428 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
433 case 'c': // Don't print "#" before an immediate operand.
434 if (!MI->getOperand(OpNum).isImm())
436 O << MI->getOperand(OpNum).getImm();
438 case 'P': // Print a VFP double precision register.
439 case 'q': // Print a NEON quad precision register.
440 printOperand(MI, OpNum, O);
442 case 'y': // Print a VFP single precision register as indexed double.
443 // This uses the ordering of the alias table to get the first 'd' register
444 // that overlaps the 's' register. Also, s0 is an odd register, hence the
445 // odd modulus check below.
446 if (MI->getOperand(OpNum).isReg()) {
447 unsigned Reg = MI->getOperand(OpNum).getReg();
448 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
449 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
450 (((Reg % 2) == 1) ? "[0]" : "[1]");
454 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
455 if (!MI->getOperand(OpNum).isImm())
457 O << ~(MI->getOperand(OpNum).getImm());
459 case 'L': // The low 16 bits of an immediate constant.
460 if (!MI->getOperand(OpNum).isImm())
462 O << (MI->getOperand(OpNum).getImm() & 0xffff);
464 case 'M': { // A register range suitable for LDM/STM.
465 if (!MI->getOperand(OpNum).isReg())
467 const MachineOperand &MO = MI->getOperand(OpNum);
468 unsigned RegBegin = MO.getReg();
469 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
470 // already got the operands in registers that are operands to the
471 // inline asm statement.
473 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
475 // FIXME: The register allocator not only may not have given us the
476 // registers in sequence, but may not be in ascending registers. This
477 // will require changes in the register allocator that'll need to be
478 // propagated down here if the operands change.
479 unsigned RegOps = OpNum + 1;
480 while (MI->getOperand(RegOps).isReg()) {
482 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
490 case 'R': // The most significant register of a pair.
491 case 'Q': { // The least significant register of a pair.
494 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
495 if (!FlagsOP.isImm())
497 unsigned Flags = FlagsOP.getImm();
498 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
501 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
502 if (RegOp >= MI->getNumOperands())
504 const MachineOperand &MO = MI->getOperand(RegOp);
507 unsigned Reg = MO.getReg();
508 O << ARMInstPrinter::getRegisterName(Reg);
512 case 'e': // The low doubleword register of a NEON quad register.
513 case 'f': { // The high doubleword register of a NEON quad register.
514 if (!MI->getOperand(OpNum).isReg())
516 unsigned Reg = MI->getOperand(OpNum).getReg();
517 if (!ARM::QPRRegClass.contains(Reg))
519 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
520 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
521 ARM::dsub_0 : ARM::dsub_1);
522 O << ARMInstPrinter::getRegisterName(SubReg);
526 // These modifiers are not yet supported.
527 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
528 case 'H': // The highest-numbered register of a pair.
533 printOperand(MI, OpNum, O);
537 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
538 unsigned OpNum, unsigned AsmVariant,
539 const char *ExtraCode,
541 // Does this asm operand have a single letter operand modifier?
542 if (ExtraCode && ExtraCode[0]) {
543 if (ExtraCode[1] != 0) return true; // Unknown modifier.
545 switch (ExtraCode[0]) {
546 case 'A': // A memory operand for a VLD1/VST1 instruction.
547 default: return true; // Unknown modifier.
548 case 'm': // The base register of a memory operand.
549 if (!MI->getOperand(OpNum).isReg())
551 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
556 const MachineOperand &MO = MI->getOperand(OpNum);
557 assert(MO.isReg() && "unexpected inline asm memory operand");
558 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
562 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
563 if (Subtarget->isTargetDarwin()) {
564 Reloc::Model RelocM = TM.getRelocationModel();
565 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
566 // Declare all the text sections up front (before the DWARF sections
567 // emitted by AsmPrinter::doInitialization) so the assembler will keep
568 // them together at the beginning of the object file. This helps
569 // avoid out-of-range branches that are due a fundamental limitation of
570 // the way symbol offsets are encoded with the current Darwin ARM
572 const TargetLoweringObjectFileMachO &TLOFMacho =
573 static_cast<const TargetLoweringObjectFileMachO &>(
574 getObjFileLowering());
575 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
576 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
577 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
578 if (RelocM == Reloc::DynamicNoPIC) {
579 const MCSection *sect =
580 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
581 MCSectionMachO::S_SYMBOL_STUBS,
582 12, SectionKind::getText());
583 OutStreamer.SwitchSection(sect);
585 const MCSection *sect =
586 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
587 MCSectionMachO::S_SYMBOL_STUBS,
588 16, SectionKind::getText());
589 OutStreamer.SwitchSection(sect);
591 const MCSection *StaticInitSect =
592 OutContext.getMachOSection("__TEXT", "__StaticInit",
593 MCSectionMachO::S_REGULAR |
594 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
595 SectionKind::getText());
596 OutStreamer.SwitchSection(StaticInitSect);
600 // Use unified assembler syntax.
601 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
603 // Emit ARM Build Attributes
604 if (Subtarget->isTargetELF()) {
611 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
612 if (Subtarget->isTargetDarwin()) {
613 // All darwin targets use mach-o.
614 const TargetLoweringObjectFileMachO &TLOFMacho =
615 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
616 MachineModuleInfoMachO &MMIMacho =
617 MMI->getObjFileInfo<MachineModuleInfoMachO>();
619 // Output non-lazy-pointers for external and common global variables.
620 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
622 if (!Stubs.empty()) {
623 // Switch with ".non_lazy_symbol_pointer" directive.
624 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
626 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
628 OutStreamer.EmitLabel(Stubs[i].first);
629 // .indirect_symbol _foo
630 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
631 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
634 // External to current translation unit.
635 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
637 // Internal to current translation unit.
639 // When we place the LSDA into the TEXT section, the type info
640 // pointers need to be indirect and pc-rel. We accomplish this by
641 // using NLPs; however, sometimes the types are local to the file.
642 // We need to fill in the value for the NLP in those cases.
643 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
645 4/*size*/, 0/*addrspace*/);
649 OutStreamer.AddBlankLine();
652 Stubs = MMIMacho.GetHiddenGVStubList();
653 if (!Stubs.empty()) {
654 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
656 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
658 OutStreamer.EmitLabel(Stubs[i].first);
660 OutStreamer.EmitValue(MCSymbolRefExpr::
661 Create(Stubs[i].second.getPointer(),
663 4/*size*/, 0/*addrspace*/);
667 OutStreamer.AddBlankLine();
670 // Funny Darwin hack: This flag tells the linker that no global symbols
671 // contain code that falls through to other global symbols (e.g. the obvious
672 // implementation of multiple entry points). If this doesn't occur, the
673 // linker can safely perform dead code stripping. Since LLVM never
674 // generates code that does this, it is always safe to set.
675 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
679 //===----------------------------------------------------------------------===//
680 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
682 // The following seem like one-off assembler flags, but they actually need
683 // to appear in the .ARM.attributes section in ELF.
684 // Instead of subclassing the MCELFStreamer, we do the work here.
686 void ARMAsmPrinter::emitAttributes() {
688 emitARMAttributeSection();
690 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
691 bool emitFPU = false;
692 AttributeEmitter *AttrEmitter;
693 if (OutStreamer.hasRawTextSupport()) {
694 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
697 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
698 AttrEmitter = new ObjectAttributeEmitter(O);
701 AttrEmitter->MaybeSwitchVendor("aeabi");
703 std::string CPUString = Subtarget->getCPUString();
705 if (CPUString == "cortex-a8" ||
706 Subtarget->isCortexA8()) {
707 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
708 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
709 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
710 ARMBuildAttrs::ApplicationProfile);
711 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
712 ARMBuildAttrs::Allowed);
713 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
714 ARMBuildAttrs::AllowThumb32);
715 // Fixme: figure out when this is emitted.
716 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
717 // ARMBuildAttrs::AllowWMMXv1);
720 /// ADD additional Else-cases here!
721 } else if (CPUString == "xscale") {
722 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
723 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
724 ARMBuildAttrs::Allowed);
725 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
726 ARMBuildAttrs::Allowed);
727 } else if (CPUString == "generic") {
728 // FIXME: Why these defaults?
729 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
730 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
731 ARMBuildAttrs::Allowed);
732 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
733 ARMBuildAttrs::Allowed);
736 if (Subtarget->hasNEON() && emitFPU) {
737 /* NEON is not exactly a VFP architecture, but GAS emit one of
738 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
739 if (Subtarget->hasNEONVFP4())
740 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon-vfpv4");
742 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
743 /* If emitted for NEON, omit from VFP below, since you can have both
744 * NEON and VFP in build attributes but only one .fpu */
749 if (Subtarget->hasVFP4()) {
750 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
751 ARMBuildAttrs::AllowFPv4A);
753 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
756 } else if (Subtarget->hasVFP3()) {
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
758 ARMBuildAttrs::AllowFPv3A);
760 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
763 } else if (Subtarget->hasVFP2()) {
764 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
765 ARMBuildAttrs::AllowFPv2);
767 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
770 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
771 * since NEON can have 1 (allowed) or 2 (MAC operations) */
772 if (Subtarget->hasNEON()) {
773 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
774 ARMBuildAttrs::Allowed);
777 // Signal various FP modes.
778 if (!TM.Options.UnsafeFPMath) {
779 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
780 ARMBuildAttrs::Allowed);
781 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
782 ARMBuildAttrs::Allowed);
785 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
786 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
787 ARMBuildAttrs::Allowed);
789 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
790 ARMBuildAttrs::AllowIEE754);
792 // FIXME: add more flags to ARMBuildAttrs.h
793 // 8-bytes alignment stuff.
794 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
795 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
797 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
798 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
799 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
800 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
802 // FIXME: Should we signal R9 usage?
804 if (Subtarget->hasDivide())
805 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
807 AttrEmitter->Finish();
811 void ARMAsmPrinter::emitARMAttributeSection() {
813 // [ <section-length> "vendor-name"
814 // [ <file-tag> <size> <attribute>*
815 // | <section-tag> <size> <section-number>* 0 <attribute>*
816 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
820 if (OutStreamer.hasRawTextSupport())
823 const ARMElfTargetObjectFile &TLOFELF =
824 static_cast<const ARMElfTargetObjectFile &>
825 (getObjFileLowering());
827 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
830 OutStreamer.EmitIntValue(0x41, 1);
833 //===----------------------------------------------------------------------===//
835 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
836 unsigned LabelId, MCContext &Ctx) {
838 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
839 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
843 static MCSymbolRefExpr::VariantKind
844 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
846 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
847 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
848 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
849 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
850 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
851 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
853 llvm_unreachable("Invalid ARMCPModifier!");
856 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
857 bool isIndirect = Subtarget->isTargetDarwin() &&
858 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
860 return Mang->getSymbol(GV);
862 // FIXME: Remove this when Darwin transition to @GOT like syntax.
863 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
864 MachineModuleInfoMachO &MMIMachO =
865 MMI->getObjFileInfo<MachineModuleInfoMachO>();
866 MachineModuleInfoImpl::StubValueTy &StubSym =
867 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
868 MMIMachO.getGVStubEntry(MCSym);
869 if (StubSym.getPointer() == 0)
870 StubSym = MachineModuleInfoImpl::
871 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
876 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
877 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
879 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
882 if (ACPV->isLSDA()) {
883 SmallString<128> Str;
884 raw_svector_ostream OS(Str);
885 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
886 MCSym = OutContext.GetOrCreateSymbol(OS.str());
887 } else if (ACPV->isBlockAddress()) {
888 const BlockAddress *BA =
889 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
890 MCSym = GetBlockAddressSymbol(BA);
891 } else if (ACPV->isGlobalValue()) {
892 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
893 MCSym = GetARMGVSymbol(GV);
894 } else if (ACPV->isMachineBasicBlock()) {
895 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
896 MCSym = MBB->getSymbol();
898 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
899 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
900 MCSym = GetExternalSymbolSymbol(Sym);
903 // Create an MCSymbol for the reference.
905 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
908 if (ACPV->getPCAdjustment()) {
909 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
913 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
915 MCBinaryExpr::CreateAdd(PCRelExpr,
916 MCConstantExpr::Create(ACPV->getPCAdjustment(),
919 if (ACPV->mustAddCurrentAddress()) {
920 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
921 // label, so just emit a local label end reference that instead.
922 MCSymbol *DotSym = OutContext.CreateTempSymbol();
923 OutStreamer.EmitLabel(DotSym);
924 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
925 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
927 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
929 OutStreamer.EmitValue(Expr, Size);
932 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
933 unsigned Opcode = MI->getOpcode();
935 if (Opcode == ARM::BR_JTadd)
937 else if (Opcode == ARM::BR_JTm)
940 const MachineOperand &MO1 = MI->getOperand(OpNum);
941 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
942 unsigned JTI = MO1.getIndex();
944 // Tag the jump table appropriately for precise disassembly.
945 OutStreamer.EmitJumpTable32Region();
947 // Emit a label for the jump table.
948 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
949 OutStreamer.EmitLabel(JTISymbol);
951 // Emit each entry of the table.
952 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
953 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
954 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
956 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
957 MachineBasicBlock *MBB = JTBBs[i];
958 // Construct an MCExpr for the entry. We want a value of the form:
959 // (BasicBlockAddr - TableBeginAddr)
961 // For example, a table with entries jumping to basic blocks BB0 and BB1
964 // .word (LBB0 - LJTI_0_0)
965 // .word (LBB1 - LJTI_0_0)
966 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
968 if (TM.getRelocationModel() == Reloc::PIC_)
969 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
972 // If we're generating a table of Thumb addresses in static relocation
973 // model, we need to add one to keep interworking correctly.
974 else if (AFI->isThumbFunction())
975 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
977 OutStreamer.EmitValue(Expr, 4);
981 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
982 unsigned Opcode = MI->getOpcode();
983 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
984 const MachineOperand &MO1 = MI->getOperand(OpNum);
985 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
986 unsigned JTI = MO1.getIndex();
988 // Emit a label for the jump table.
989 if (MI->getOpcode() == ARM::t2TBB_JT) {
990 OutStreamer.EmitJumpTable8Region();
991 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
992 OutStreamer.EmitJumpTable16Region();
994 OutStreamer.EmitJumpTable32Region();
997 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
998 OutStreamer.EmitLabel(JTISymbol);
1000 // Emit each entry of the table.
1001 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1002 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1003 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1004 unsigned OffsetWidth = 4;
1005 if (MI->getOpcode() == ARM::t2TBB_JT)
1007 else if (MI->getOpcode() == ARM::t2TBH_JT)
1010 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1011 MachineBasicBlock *MBB = JTBBs[i];
1012 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1014 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1015 if (OffsetWidth == 4) {
1017 BrInst.setOpcode(ARM::t2B);
1018 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1019 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1020 BrInst.addOperand(MCOperand::CreateReg(0));
1021 OutStreamer.EmitInstruction(BrInst);
1024 // Otherwise it's an offset from the dispatch instruction. Construct an
1025 // MCExpr for the entry. We want a value of the form:
1026 // (BasicBlockAddr - TableBeginAddr) / 2
1028 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1031 // .byte (LBB0 - LJTI_0_0) / 2
1032 // .byte (LBB1 - LJTI_0_0) / 2
1033 const MCExpr *Expr =
1034 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1035 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1037 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1039 OutStreamer.EmitValue(Expr, OffsetWidth);
1043 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1045 unsigned NOps = MI->getNumOperands();
1047 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1048 // cast away const; DIetc do not take const operands for some reason.
1049 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1052 // Frame address. Currently handles register +- offset only.
1053 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1054 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1057 printOperand(MI, NOps-2, OS);
1060 static void populateADROperands(MCInst &Inst, unsigned Dest,
1061 const MCSymbol *Label,
1062 unsigned pred, unsigned ccreg,
1064 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1065 Inst.addOperand(MCOperand::CreateReg(Dest));
1066 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1067 // Add predicate operands.
1068 Inst.addOperand(MCOperand::CreateImm(pred));
1069 Inst.addOperand(MCOperand::CreateReg(ccreg));
1072 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1076 // Emit the instruction as usual, just patch the opcode.
1077 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1078 TmpInst.setOpcode(Opcode);
1079 OutStreamer.EmitInstruction(TmpInst);
1082 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1083 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1084 "Only instruction which are involved into frame setup code are allowed");
1086 const MachineFunction &MF = *MI->getParent()->getParent();
1087 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1088 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1090 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1091 unsigned Opc = MI->getOpcode();
1092 unsigned SrcReg, DstReg;
1094 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1095 // Two special cases:
1096 // 1) tPUSH does not have src/dst regs.
1097 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1098 // load. Yes, this is pretty fragile, but for now I don't see better
1100 SrcReg = DstReg = ARM::SP;
1102 SrcReg = MI->getOperand(1).getReg();
1103 DstReg = MI->getOperand(0).getReg();
1106 // Try to figure out the unwinding opcode out of src / dst regs.
1107 if (MI->mayStore()) {
1109 assert(DstReg == ARM::SP &&
1110 "Only stack pointer as a destination reg is supported");
1112 SmallVector<unsigned, 4> RegList;
1113 // Skip src & dst reg, and pred ops.
1114 unsigned StartOp = 2 + 2;
1115 // Use all the operands.
1116 unsigned NumOffset = 0;
1121 assert(0 && "Unsupported opcode for unwinding information");
1123 // Special case here: no src & dst reg, but two extra imp ops.
1124 StartOp = 2; NumOffset = 2;
1125 case ARM::STMDB_UPD:
1126 case ARM::t2STMDB_UPD:
1127 case ARM::VSTMDDB_UPD:
1128 assert(SrcReg == ARM::SP &&
1129 "Only stack pointer as a source reg is supported");
1130 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1132 RegList.push_back(MI->getOperand(i).getReg());
1134 case ARM::STR_PRE_IMM:
1135 case ARM::STR_PRE_REG:
1136 case ARM::t2STR_PRE:
1137 assert(MI->getOperand(2).getReg() == ARM::SP &&
1138 "Only stack pointer as a source reg is supported");
1139 RegList.push_back(SrcReg);
1142 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1144 // Changes of stack / frame pointer.
1145 if (SrcReg == ARM::SP) {
1150 assert(0 && "Unsupported opcode for unwinding information");
1156 Offset = -MI->getOperand(2).getImm();
1160 Offset = MI->getOperand(2).getImm();
1163 Offset = MI->getOperand(2).getImm()*4;
1167 Offset = -MI->getOperand(2).getImm()*4;
1169 case ARM::tLDRpci: {
1170 // Grab the constpool index and check, whether it corresponds to
1171 // original or cloned constpool entry.
1172 unsigned CPI = MI->getOperand(1).getIndex();
1173 const MachineConstantPool *MCP = MF.getConstantPool();
1174 if (CPI >= MCP->getConstants().size())
1175 CPI = AFI.getOriginalCPIdx(CPI);
1176 assert(CPI != -1U && "Invalid constpool index");
1178 // Derive the actual offset.
1179 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1180 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1181 // FIXME: Check for user, it should be "add" instruction!
1182 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1187 if (DstReg == FramePtr && FramePtr != ARM::SP)
1188 // Set-up of the frame pointer. Positive values correspond to "add"
1190 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1191 else if (DstReg == ARM::SP) {
1192 // Change of SP by an offset. Positive values correspond to "sub"
1194 OutStreamer.EmitPad(Offset);
1197 assert(0 && "Unsupported opcode for unwinding information");
1199 } else if (DstReg == ARM::SP) {
1200 // FIXME: .movsp goes here
1202 assert(0 && "Unsupported opcode for unwinding information");
1206 assert(0 && "Unsupported opcode for unwinding information");
1211 extern cl::opt<bool> EnableARMEHABI;
1213 // Simple pseudo-instructions have their lowering (with expansion to real
1214 // instructions) auto-generated.
1215 #include "ARMGenMCPseudoLowering.inc"
1217 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1218 if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1219 OutStreamer.EmitCodeRegion();
1221 // Emit unwinding stuff for frame-related instructions
1222 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1223 EmitUnwindingInstruction(MI);
1225 // Do any auto-generated pseudo lowerings.
1226 if (emitPseudoExpansionLowering(OutStreamer, MI))
1229 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1230 "Pseudo flag setting opcode should be expanded early");
1232 // Check for manual lowerings.
1233 unsigned Opc = MI->getOpcode();
1235 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1236 case ARM::DBG_VALUE: {
1237 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1238 SmallString<128> TmpStr;
1239 raw_svector_ostream OS(TmpStr);
1240 PrintDebugValueComment(MI, OS);
1241 OutStreamer.EmitRawText(StringRef(OS.str()));
1246 case ARM::tLEApcrel:
1247 case ARM::t2LEApcrel: {
1248 // FIXME: Need to also handle globals and externals
1250 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1251 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1253 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1254 GetCPISymbol(MI->getOperand(1).getIndex()),
1255 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1257 OutStreamer.EmitInstruction(TmpInst);
1260 case ARM::LEApcrelJT:
1261 case ARM::tLEApcrelJT:
1262 case ARM::t2LEApcrelJT: {
1264 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1265 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1267 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1268 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1269 MI->getOperand(2).getImm()),
1270 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1272 OutStreamer.EmitInstruction(TmpInst);
1275 // Darwin call instructions are just normal call instructions with different
1276 // clobber semantics (they clobber R9).
1277 case ARM::BXr9_CALL:
1278 case ARM::BX_CALL: {
1281 TmpInst.setOpcode(ARM::MOVr);
1282 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1283 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1284 // Add predicate operands.
1285 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1286 TmpInst.addOperand(MCOperand::CreateReg(0));
1287 // Add 's' bit operand (always reg0 for this)
1288 TmpInst.addOperand(MCOperand::CreateReg(0));
1289 OutStreamer.EmitInstruction(TmpInst);
1293 TmpInst.setOpcode(ARM::BX);
1294 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1295 OutStreamer.EmitInstruction(TmpInst);
1299 case ARM::tBXr9_CALL:
1300 case ARM::tBX_CALL: {
1303 TmpInst.setOpcode(ARM::tMOVr);
1304 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1305 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1306 // Add predicate operands.
1307 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1308 TmpInst.addOperand(MCOperand::CreateReg(0));
1309 OutStreamer.EmitInstruction(TmpInst);
1313 TmpInst.setOpcode(ARM::tBX);
1314 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1315 // Add predicate operands.
1316 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
1318 OutStreamer.EmitInstruction(TmpInst);
1322 case ARM::BMOVPCRXr9_CALL:
1323 case ARM::BMOVPCRX_CALL: {
1326 TmpInst.setOpcode(ARM::MOVr);
1327 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1328 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1329 // Add predicate operands.
1330 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1331 TmpInst.addOperand(MCOperand::CreateReg(0));
1332 // Add 's' bit operand (always reg0 for this)
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 OutStreamer.EmitInstruction(TmpInst);
1338 TmpInst.setOpcode(ARM::MOVr);
1339 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1340 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1341 // Add predicate operands.
1342 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1343 TmpInst.addOperand(MCOperand::CreateReg(0));
1344 // Add 's' bit operand (always reg0 for this)
1345 TmpInst.addOperand(MCOperand::CreateReg(0));
1346 OutStreamer.EmitInstruction(TmpInst);
1350 case ARM::MOVi16_ga_pcrel:
1351 case ARM::t2MOVi16_ga_pcrel: {
1353 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1354 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1356 unsigned TF = MI->getOperand(1).getTargetFlags();
1357 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1358 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1359 MCSymbol *GVSym = GetARMGVSymbol(GV);
1360 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1362 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1363 getFunctionNumber(),
1364 MI->getOperand(2).getImm(), OutContext);
1365 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1366 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1367 const MCExpr *PCRelExpr =
1368 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1369 MCBinaryExpr::CreateAdd(LabelSymExpr,
1370 MCConstantExpr::Create(PCAdj, OutContext),
1371 OutContext), OutContext), OutContext);
1372 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1374 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1375 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1378 // Add predicate operands.
1379 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1380 TmpInst.addOperand(MCOperand::CreateReg(0));
1381 // Add 's' bit operand (always reg0 for this)
1382 TmpInst.addOperand(MCOperand::CreateReg(0));
1383 OutStreamer.EmitInstruction(TmpInst);
1386 case ARM::MOVTi16_ga_pcrel:
1387 case ARM::t2MOVTi16_ga_pcrel: {
1389 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1390 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1391 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1392 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1394 unsigned TF = MI->getOperand(2).getTargetFlags();
1395 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1396 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1397 MCSymbol *GVSym = GetARMGVSymbol(GV);
1398 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1400 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1401 getFunctionNumber(),
1402 MI->getOperand(3).getImm(), OutContext);
1403 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1404 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1405 const MCExpr *PCRelExpr =
1406 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1407 MCBinaryExpr::CreateAdd(LabelSymExpr,
1408 MCConstantExpr::Create(PCAdj, OutContext),
1409 OutContext), OutContext), OutContext);
1410 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1412 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1413 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1415 // Add predicate operands.
1416 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1417 TmpInst.addOperand(MCOperand::CreateReg(0));
1418 // Add 's' bit operand (always reg0 for this)
1419 TmpInst.addOperand(MCOperand::CreateReg(0));
1420 OutStreamer.EmitInstruction(TmpInst);
1423 case ARM::tPICADD: {
1424 // This is a pseudo op for a label + instruction sequence, which looks like:
1427 // This adds the address of LPC0 to r0.
1430 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1431 getFunctionNumber(), MI->getOperand(2).getImm(),
1434 // Form and emit the add.
1436 AddInst.setOpcode(ARM::tADDhirr);
1437 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1438 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1439 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1440 // Add predicate operands.
1441 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1442 AddInst.addOperand(MCOperand::CreateReg(0));
1443 OutStreamer.EmitInstruction(AddInst);
1447 // This is a pseudo op for a label + instruction sequence, which looks like:
1450 // This adds the address of LPC0 to r0.
1453 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1454 getFunctionNumber(), MI->getOperand(2).getImm(),
1457 // Form and emit the add.
1459 AddInst.setOpcode(ARM::ADDrr);
1460 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1461 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1462 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1463 // Add predicate operands.
1464 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1465 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1466 // Add 's' bit operand (always reg0 for this)
1467 AddInst.addOperand(MCOperand::CreateReg(0));
1468 OutStreamer.EmitInstruction(AddInst);
1478 case ARM::PICLDRSH: {
1479 // This is a pseudo op for a label + instruction sequence, which looks like:
1482 // The LCP0 label is referenced by a constant pool entry in order to get
1483 // a PC-relative address at the ldr instruction.
1486 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1487 getFunctionNumber(), MI->getOperand(2).getImm(),
1490 // Form and emit the load
1492 switch (MI->getOpcode()) {
1494 llvm_unreachable("Unexpected opcode!");
1495 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1496 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1497 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1498 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1499 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1500 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1501 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1502 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1505 LdStInst.setOpcode(Opcode);
1506 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1507 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1508 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1509 LdStInst.addOperand(MCOperand::CreateImm(0));
1510 // Add predicate operands.
1511 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1512 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1513 OutStreamer.EmitInstruction(LdStInst);
1517 case ARM::CONSTPOOL_ENTRY: {
1518 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1519 /// in the function. The first operand is the ID# for this instruction, the
1520 /// second is the index into the MachineConstantPool that this is, the third
1521 /// is the size in bytes of this constant pool entry.
1522 /// The required alignment is specified on the basic block holding this MI.
1523 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1524 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1526 // Mark the constant pool entry as data if we're not already in a data
1528 OutStreamer.EmitDataRegion();
1529 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1531 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1532 if (MCPE.isMachineConstantPoolEntry())
1533 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1535 EmitGlobalConstant(MCPE.Val.ConstVal);
1538 case ARM::t2BR_JT: {
1539 // Lower and emit the instruction itself, then the jump table following it.
1541 TmpInst.setOpcode(ARM::tMOVr);
1542 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1543 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1544 // Add predicate operands.
1545 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1546 TmpInst.addOperand(MCOperand::CreateReg(0));
1547 OutStreamer.EmitInstruction(TmpInst);
1548 // Output the data for the jump table itself
1552 case ARM::t2TBB_JT: {
1553 // Lower and emit the instruction itself, then the jump table following it.
1556 TmpInst.setOpcode(ARM::t2TBB);
1557 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1558 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1559 // Add predicate operands.
1560 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1561 TmpInst.addOperand(MCOperand::CreateReg(0));
1562 OutStreamer.EmitInstruction(TmpInst);
1563 // Output the data for the jump table itself
1565 // Make sure the next instruction is 2-byte aligned.
1569 case ARM::t2TBH_JT: {
1570 // Lower and emit the instruction itself, then the jump table following it.
1573 TmpInst.setOpcode(ARM::t2TBH);
1574 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1575 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1576 // Add predicate operands.
1577 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1578 TmpInst.addOperand(MCOperand::CreateReg(0));
1579 OutStreamer.EmitInstruction(TmpInst);
1580 // Output the data for the jump table itself
1586 // Lower and emit the instruction itself, then the jump table following it.
1589 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1590 ARM::MOVr : ARM::tMOVr;
1591 TmpInst.setOpcode(Opc);
1592 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1593 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1594 // Add predicate operands.
1595 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1596 TmpInst.addOperand(MCOperand::CreateReg(0));
1597 // Add 's' bit operand (always reg0 for this)
1598 if (Opc == ARM::MOVr)
1599 TmpInst.addOperand(MCOperand::CreateReg(0));
1600 OutStreamer.EmitInstruction(TmpInst);
1602 // Make sure the Thumb jump table is 4-byte aligned.
1603 if (Opc == ARM::tMOVr)
1606 // Output the data for the jump table itself
1611 // Lower and emit the instruction itself, then the jump table following it.
1614 if (MI->getOperand(1).getReg() == 0) {
1616 TmpInst.setOpcode(ARM::LDRi12);
1617 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1618 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1619 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1621 TmpInst.setOpcode(ARM::LDRrs);
1622 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1623 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1624 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1625 TmpInst.addOperand(MCOperand::CreateImm(0));
1627 // Add predicate operands.
1628 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1629 TmpInst.addOperand(MCOperand::CreateReg(0));
1630 OutStreamer.EmitInstruction(TmpInst);
1632 // Output the data for the jump table itself
1636 case ARM::BR_JTadd: {
1637 // Lower and emit the instruction itself, then the jump table following it.
1638 // add pc, target, idx
1640 TmpInst.setOpcode(ARM::ADDrr);
1641 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1642 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1643 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1644 // Add predicate operands.
1645 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1646 TmpInst.addOperand(MCOperand::CreateReg(0));
1647 // Add 's' bit operand (always reg0 for this)
1648 TmpInst.addOperand(MCOperand::CreateReg(0));
1649 OutStreamer.EmitInstruction(TmpInst);
1651 // Output the data for the jump table itself
1656 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1657 // FIXME: Remove this special case when they do.
1658 if (!Subtarget->isTargetDarwin()) {
1659 //.long 0xe7ffdefe @ trap
1660 uint32_t Val = 0xe7ffdefeUL;
1661 OutStreamer.AddComment("trap");
1662 OutStreamer.EmitIntValue(Val, 4);
1668 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1669 // FIXME: Remove this special case when they do.
1670 if (!Subtarget->isTargetDarwin()) {
1671 //.short 57086 @ trap
1672 uint16_t Val = 0xdefe;
1673 OutStreamer.AddComment("trap");
1674 OutStreamer.EmitIntValue(Val, 2);
1679 case ARM::t2Int_eh_sjlj_setjmp:
1680 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1681 case ARM::tInt_eh_sjlj_setjmp: {
1682 // Two incoming args: GPR:$src, GPR:$val
1685 // str $val, [$src, #4]
1690 unsigned SrcReg = MI->getOperand(0).getReg();
1691 unsigned ValReg = MI->getOperand(1).getReg();
1692 MCSymbol *Label = GetARMSJLJEHLabel();
1695 TmpInst.setOpcode(ARM::tMOVr);
1696 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1697 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1699 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1700 TmpInst.addOperand(MCOperand::CreateReg(0));
1701 OutStreamer.AddComment("eh_setjmp begin");
1702 OutStreamer.EmitInstruction(TmpInst);
1706 TmpInst.setOpcode(ARM::tADDi3);
1707 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1709 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1710 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1711 TmpInst.addOperand(MCOperand::CreateImm(7));
1713 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1714 TmpInst.addOperand(MCOperand::CreateReg(0));
1715 OutStreamer.EmitInstruction(TmpInst);
1719 TmpInst.setOpcode(ARM::tSTRi);
1720 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1721 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1722 // The offset immediate is #4. The operand value is scaled by 4 for the
1723 // tSTR instruction.
1724 TmpInst.addOperand(MCOperand::CreateImm(1));
1726 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1727 TmpInst.addOperand(MCOperand::CreateReg(0));
1728 OutStreamer.EmitInstruction(TmpInst);
1732 TmpInst.setOpcode(ARM::tMOVi8);
1733 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1734 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1735 TmpInst.addOperand(MCOperand::CreateImm(0));
1737 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1738 TmpInst.addOperand(MCOperand::CreateReg(0));
1739 OutStreamer.EmitInstruction(TmpInst);
1742 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1744 TmpInst.setOpcode(ARM::tB);
1745 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1746 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1747 TmpInst.addOperand(MCOperand::CreateReg(0));
1748 OutStreamer.EmitInstruction(TmpInst);
1752 TmpInst.setOpcode(ARM::tMOVi8);
1753 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1754 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1755 TmpInst.addOperand(MCOperand::CreateImm(1));
1757 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1758 TmpInst.addOperand(MCOperand::CreateReg(0));
1759 OutStreamer.AddComment("eh_setjmp end");
1760 OutStreamer.EmitInstruction(TmpInst);
1762 OutStreamer.EmitLabel(Label);
1766 case ARM::Int_eh_sjlj_setjmp_nofp:
1767 case ARM::Int_eh_sjlj_setjmp: {
1768 // Two incoming args: GPR:$src, GPR:$val
1770 // str $val, [$src, #+4]
1774 unsigned SrcReg = MI->getOperand(0).getReg();
1775 unsigned ValReg = MI->getOperand(1).getReg();
1779 TmpInst.setOpcode(ARM::ADDri);
1780 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1781 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1782 TmpInst.addOperand(MCOperand::CreateImm(8));
1784 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1785 TmpInst.addOperand(MCOperand::CreateReg(0));
1786 // 's' bit operand (always reg0 for this).
1787 TmpInst.addOperand(MCOperand::CreateReg(0));
1788 OutStreamer.AddComment("eh_setjmp begin");
1789 OutStreamer.EmitInstruction(TmpInst);
1793 TmpInst.setOpcode(ARM::STRi12);
1794 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1795 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1796 TmpInst.addOperand(MCOperand::CreateImm(4));
1798 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1799 TmpInst.addOperand(MCOperand::CreateReg(0));
1800 OutStreamer.EmitInstruction(TmpInst);
1804 TmpInst.setOpcode(ARM::MOVi);
1805 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1806 TmpInst.addOperand(MCOperand::CreateImm(0));
1808 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1809 TmpInst.addOperand(MCOperand::CreateReg(0));
1810 // 's' bit operand (always reg0 for this).
1811 TmpInst.addOperand(MCOperand::CreateReg(0));
1812 OutStreamer.EmitInstruction(TmpInst);
1816 TmpInst.setOpcode(ARM::ADDri);
1817 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1818 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1819 TmpInst.addOperand(MCOperand::CreateImm(0));
1821 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1822 TmpInst.addOperand(MCOperand::CreateReg(0));
1823 // 's' bit operand (always reg0 for this).
1824 TmpInst.addOperand(MCOperand::CreateReg(0));
1825 OutStreamer.EmitInstruction(TmpInst);
1829 TmpInst.setOpcode(ARM::MOVi);
1830 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1831 TmpInst.addOperand(MCOperand::CreateImm(1));
1833 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1834 TmpInst.addOperand(MCOperand::CreateReg(0));
1835 // 's' bit operand (always reg0 for this).
1836 TmpInst.addOperand(MCOperand::CreateReg(0));
1837 OutStreamer.AddComment("eh_setjmp end");
1838 OutStreamer.EmitInstruction(TmpInst);
1842 case ARM::Int_eh_sjlj_longjmp: {
1843 // ldr sp, [$src, #8]
1844 // ldr $scratch, [$src, #4]
1847 unsigned SrcReg = MI->getOperand(0).getReg();
1848 unsigned ScratchReg = MI->getOperand(1).getReg();
1851 TmpInst.setOpcode(ARM::LDRi12);
1852 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1853 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1854 TmpInst.addOperand(MCOperand::CreateImm(8));
1856 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1857 TmpInst.addOperand(MCOperand::CreateReg(0));
1858 OutStreamer.EmitInstruction(TmpInst);
1862 TmpInst.setOpcode(ARM::LDRi12);
1863 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1864 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1865 TmpInst.addOperand(MCOperand::CreateImm(4));
1867 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1868 TmpInst.addOperand(MCOperand::CreateReg(0));
1869 OutStreamer.EmitInstruction(TmpInst);
1873 TmpInst.setOpcode(ARM::LDRi12);
1874 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1875 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1876 TmpInst.addOperand(MCOperand::CreateImm(0));
1878 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1879 TmpInst.addOperand(MCOperand::CreateReg(0));
1880 OutStreamer.EmitInstruction(TmpInst);
1884 TmpInst.setOpcode(ARM::BX);
1885 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1887 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1888 TmpInst.addOperand(MCOperand::CreateReg(0));
1889 OutStreamer.EmitInstruction(TmpInst);
1893 case ARM::tInt_eh_sjlj_longjmp: {
1894 // ldr $scratch, [$src, #8]
1896 // ldr $scratch, [$src, #4]
1899 unsigned SrcReg = MI->getOperand(0).getReg();
1900 unsigned ScratchReg = MI->getOperand(1).getReg();
1903 TmpInst.setOpcode(ARM::tLDRi);
1904 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1905 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1906 // The offset immediate is #8. The operand value is scaled by 4 for the
1907 // tLDR instruction.
1908 TmpInst.addOperand(MCOperand::CreateImm(2));
1910 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1911 TmpInst.addOperand(MCOperand::CreateReg(0));
1912 OutStreamer.EmitInstruction(TmpInst);
1916 TmpInst.setOpcode(ARM::tMOVr);
1917 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1918 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1920 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1921 TmpInst.addOperand(MCOperand::CreateReg(0));
1922 OutStreamer.EmitInstruction(TmpInst);
1926 TmpInst.setOpcode(ARM::tLDRi);
1927 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1928 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1929 TmpInst.addOperand(MCOperand::CreateImm(1));
1931 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1932 TmpInst.addOperand(MCOperand::CreateReg(0));
1933 OutStreamer.EmitInstruction(TmpInst);
1937 TmpInst.setOpcode(ARM::tLDRr);
1938 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1939 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1940 TmpInst.addOperand(MCOperand::CreateReg(0));
1942 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1943 TmpInst.addOperand(MCOperand::CreateReg(0));
1944 OutStreamer.EmitInstruction(TmpInst);
1948 TmpInst.setOpcode(ARM::tBX);
1949 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1951 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1952 TmpInst.addOperand(MCOperand::CreateReg(0));
1953 OutStreamer.EmitInstruction(TmpInst);
1960 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1962 OutStreamer.EmitInstruction(TmpInst);
1965 //===----------------------------------------------------------------------===//
1966 // Target Registry Stuff
1967 //===----------------------------------------------------------------------===//
1969 // Force static initialization.
1970 extern "C" void LLVMInitializeARMAsmPrinter() {
1971 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1972 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);