1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/TargetRegistry.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 // This structure holds all attributes, accounting for
104 // their string/numeric value, so we can later emmit them
105 // in declaration order, keeping all in the same vector
106 struct AttributeItemType {
114 StringRef StringValue;
117 MCObjectStreamer &Streamer;
118 StringRef CurrentVendor;
119 SmallVector<AttributeItemType, 64> Contents;
121 // Account for the ULEB/String size of each item,
122 // not just the number of items
124 // FIXME: this should be in a more generic place, but
125 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
126 size_t getULEBSize(int Value) {
130 Size += sizeof(int8_t); // Is this really necessary?
136 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
137 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
139 void MaybeSwitchVendor(StringRef Vendor) {
140 assert(!Vendor.empty() && "Vendor cannot be empty.");
142 if (CurrentVendor.empty())
143 CurrentVendor = Vendor;
144 else if (CurrentVendor == Vendor)
149 CurrentVendor = Vendor;
151 assert(Contents.size() == 0);
154 void EmitAttribute(unsigned Attribute, unsigned Value) {
155 AttributeItemType attr = {
156 AttributeItemType::NumericAttribute,
161 ContentsSize += getULEBSize(Attribute);
162 ContentsSize += getULEBSize(Value);
163 Contents.push_back(attr);
166 void EmitTextAttribute(unsigned Attribute, StringRef String) {
167 AttributeItemType attr = {
168 AttributeItemType::TextAttribute,
173 ContentsSize += getULEBSize(Attribute);
175 ContentsSize += String.size()+1;
177 Contents.push_back(attr);
181 // Vendor size + Vendor name + '\0'
182 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
185 const size_t TagHeaderSize = 1 + 4;
187 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
188 Streamer.EmitBytes(CurrentVendor, 0);
189 Streamer.EmitIntValue(0, 1); // '\0'
191 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
192 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
194 // Size should have been accounted for already, now
195 // emit each field as its type (ULEB or String)
196 for (unsigned int i=0; i<Contents.size(); ++i) {
197 AttributeItemType item = Contents[i];
198 Streamer.EmitULEB128IntValue(item.Tag, 0);
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue, 0);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(UppercaseString(item.StringValue), 0);
205 Streamer.EmitIntValue(0, 1); // '\0'
208 assert(0 && "Invalid attribute type");
216 } // end of anonymous namespace
218 MachineLocation ARMAsmPrinter::
219 getDebugValueLocation(const MachineInstr *MI) const {
220 MachineLocation Location;
221 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
222 // Frame address. Currently handles register +- offset only.
223 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
224 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
226 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
231 /// EmitDwarfRegOp - Emit dwarf register operation.
232 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
233 const TargetRegisterInfo *RI = TM.getRegisterInfo();
234 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
235 AsmPrinter::EmitDwarfRegOp(MLoc);
237 unsigned Reg = MLoc.getReg();
238 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
239 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
240 // S registers are described as bit-pieces of a register
241 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
242 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
248 OutStreamer.AddComment("DW_OP_regx for S register");
249 EmitInt8(dwarf::DW_OP_regx);
251 OutStreamer.AddComment(Twine(SReg));
255 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
261 EmitInt8(dwarf::DW_OP_bit_piece);
265 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
266 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
267 // Q registers Q0-Q15 are described by composing two D registers together.
268 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
271 unsigned QReg = Reg - ARM::Q0;
272 unsigned D1 = 256 + 2 * QReg;
273 unsigned D2 = D1 + 1;
275 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
276 EmitInt8(dwarf::DW_OP_regx);
278 OutStreamer.AddComment("DW_OP_piece 8");
279 EmitInt8(dwarf::DW_OP_piece);
282 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
283 EmitInt8(dwarf::DW_OP_regx);
285 OutStreamer.AddComment("DW_OP_piece 8");
286 EmitInt8(dwarf::DW_OP_piece);
292 void ARMAsmPrinter::EmitFunctionEntryLabel() {
293 if (AFI->isThumbFunction()) {
294 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
295 OutStreamer.EmitThumbFunc(CurrentFnSym);
298 OutStreamer.EmitLabel(CurrentFnSym);
301 /// runOnMachineFunction - This uses the EmitInstruction()
302 /// method to print assembly for each instruction.
304 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
305 AFI = MF.getInfo<ARMFunctionInfo>();
306 MCP = MF.getConstantPool();
308 return AsmPrinter::runOnMachineFunction(MF);
311 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
312 raw_ostream &O, const char *Modifier) {
313 const MachineOperand &MO = MI->getOperand(OpNum);
314 unsigned TF = MO.getTargetFlags();
316 switch (MO.getType()) {
318 assert(0 && "<unknown operand type>");
319 case MachineOperand::MO_Register: {
320 unsigned Reg = MO.getReg();
321 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
322 assert(!MO.getSubReg() && "Subregs should be eliminated!");
323 O << ARMInstPrinter::getRegisterName(Reg);
326 case MachineOperand::MO_Immediate: {
327 int64_t Imm = MO.getImm();
329 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
330 (TF == ARMII::MO_LO16))
332 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
333 (TF == ARMII::MO_HI16))
338 case MachineOperand::MO_MachineBasicBlock:
339 O << *MO.getMBB()->getSymbol();
341 case MachineOperand::MO_GlobalAddress: {
342 const GlobalValue *GV = MO.getGlobal();
343 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
344 (TF & ARMII::MO_LO16))
346 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
347 (TF & ARMII::MO_HI16))
349 O << *Mang->getSymbol(GV);
351 printOffset(MO.getOffset(), O);
352 if (TF == ARMII::MO_PLT)
356 case MachineOperand::MO_ExternalSymbol: {
357 O << *GetExternalSymbolSymbol(MO.getSymbolName());
358 if (TF == ARMII::MO_PLT)
362 case MachineOperand::MO_ConstantPoolIndex:
363 O << *GetCPISymbol(MO.getIndex());
365 case MachineOperand::MO_JumpTableIndex:
366 O << *GetJTISymbol(MO.getIndex());
371 //===--------------------------------------------------------------------===//
373 MCSymbol *ARMAsmPrinter::
374 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
375 const MachineBasicBlock *MBB) const {
376 SmallString<60> Name;
377 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
378 << getFunctionNumber() << '_' << uid << '_' << uid2
379 << "_set_" << MBB->getNumber();
380 return OutContext.GetOrCreateSymbol(Name.str());
383 MCSymbol *ARMAsmPrinter::
384 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
385 SmallString<60> Name;
386 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
387 << getFunctionNumber() << '_' << uid << '_' << uid2;
388 return OutContext.GetOrCreateSymbol(Name.str());
392 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
393 SmallString<60> Name;
394 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
395 << getFunctionNumber();
396 return OutContext.GetOrCreateSymbol(Name.str());
399 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
400 unsigned AsmVariant, const char *ExtraCode,
402 // Does this asm operand have a single letter operand modifier?
403 if (ExtraCode && ExtraCode[0]) {
404 if (ExtraCode[1] != 0) return true; // Unknown modifier.
406 switch (ExtraCode[0]) {
407 default: return true; // Unknown modifier.
408 case 'a': // Print as a memory address.
409 if (MI->getOperand(OpNum).isReg()) {
411 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
416 case 'c': // Don't print "#" before an immediate operand.
417 if (!MI->getOperand(OpNum).isImm())
419 O << MI->getOperand(OpNum).getImm();
421 case 'P': // Print a VFP double precision register.
422 case 'q': // Print a NEON quad precision register.
423 printOperand(MI, OpNum, O);
425 case 'y': // Print a VFP single precision register as indexed double.
426 // This uses the ordering of the alias table to get the first 'd' register
427 // that overlaps the 's' register. Also, s0 is an odd register, hence the
428 // odd modulus check below.
429 if (MI->getOperand(OpNum).isReg()) {
430 unsigned Reg = MI->getOperand(OpNum).getReg();
431 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
432 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
433 (((Reg % 2) == 1) ? "[0]" : "[1]");
437 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
438 if (!MI->getOperand(OpNum).isImm())
440 O << ~(MI->getOperand(OpNum).getImm());
442 case 'L': // The low 16 bits of an immediate constant.
443 if (!MI->getOperand(OpNum).isImm())
445 O << (MI->getOperand(OpNum).getImm() & 0xffff);
447 case 'M': { // A register range suitable for LDM/STM.
448 if (!MI->getOperand(OpNum).isReg())
450 const MachineOperand &MO = MI->getOperand(OpNum);
451 unsigned RegBegin = MO.getReg();
452 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
453 // already got the operands in registers that are operands to the
454 // inline asm statement.
456 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
458 // FIXME: The register allocator not only may not have given us the
459 // registers in sequence, but may not be in ascending registers. This
460 // will require changes in the register allocator that'll need to be
461 // propagated down here if the operands change.
462 unsigned RegOps = OpNum + 1;
463 while (MI->getOperand(RegOps).isReg()) {
465 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
473 case 'R': // The most significant register of a pair.
474 case 'Q': { // The least significant register of a pair.
477 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
478 if (!FlagsOP.isImm())
480 unsigned Flags = FlagsOP.getImm();
481 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
484 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
485 if (RegOp >= MI->getNumOperands())
487 const MachineOperand &MO = MI->getOperand(RegOp);
490 unsigned Reg = MO.getReg();
491 O << ARMInstPrinter::getRegisterName(Reg);
495 // These modifiers are not yet supported.
496 case 'p': // The high single-precision register of a VFP double-precision
498 case 'e': // The low doubleword register of a NEON quad register.
499 case 'f': // The high doubleword register of a NEON quad register.
500 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
501 case 'H': // The highest-numbered register of a pair.
506 printOperand(MI, OpNum, O);
510 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
511 unsigned OpNum, unsigned AsmVariant,
512 const char *ExtraCode,
514 // Does this asm operand have a single letter operand modifier?
515 if (ExtraCode && ExtraCode[0]) {
516 if (ExtraCode[1] != 0) return true; // Unknown modifier.
518 switch (ExtraCode[0]) {
519 case 'A': // A memory operand for a VLD1/VST1 instruction.
520 default: return true; // Unknown modifier.
521 case 'm': // The base register of a memory operand.
522 if (!MI->getOperand(OpNum).isReg())
524 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
529 const MachineOperand &MO = MI->getOperand(OpNum);
530 assert(MO.isReg() && "unexpected inline asm memory operand");
531 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
535 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
536 if (Subtarget->isTargetDarwin()) {
537 Reloc::Model RelocM = TM.getRelocationModel();
538 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
539 // Declare all the text sections up front (before the DWARF sections
540 // emitted by AsmPrinter::doInitialization) so the assembler will keep
541 // them together at the beginning of the object file. This helps
542 // avoid out-of-range branches that are due a fundamental limitation of
543 // the way symbol offsets are encoded with the current Darwin ARM
545 const TargetLoweringObjectFileMachO &TLOFMacho =
546 static_cast<const TargetLoweringObjectFileMachO &>(
547 getObjFileLowering());
548 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
549 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
550 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
551 if (RelocM == Reloc::DynamicNoPIC) {
552 const MCSection *sect =
553 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
554 MCSectionMachO::S_SYMBOL_STUBS,
555 12, SectionKind::getText());
556 OutStreamer.SwitchSection(sect);
558 const MCSection *sect =
559 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
560 MCSectionMachO::S_SYMBOL_STUBS,
561 16, SectionKind::getText());
562 OutStreamer.SwitchSection(sect);
564 const MCSection *StaticInitSect =
565 OutContext.getMachOSection("__TEXT", "__StaticInit",
566 MCSectionMachO::S_REGULAR |
567 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
568 SectionKind::getText());
569 OutStreamer.SwitchSection(StaticInitSect);
573 // Use unified assembler syntax.
574 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
576 // Emit ARM Build Attributes
577 if (Subtarget->isTargetELF()) {
584 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
585 if (Subtarget->isTargetDarwin()) {
586 // All darwin targets use mach-o.
587 const TargetLoweringObjectFileMachO &TLOFMacho =
588 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
589 MachineModuleInfoMachO &MMIMacho =
590 MMI->getObjFileInfo<MachineModuleInfoMachO>();
592 // Output non-lazy-pointers for external and common global variables.
593 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
595 if (!Stubs.empty()) {
596 // Switch with ".non_lazy_symbol_pointer" directive.
597 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
599 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
601 OutStreamer.EmitLabel(Stubs[i].first);
602 // .indirect_symbol _foo
603 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
604 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
607 // External to current translation unit.
608 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
610 // Internal to current translation unit.
612 // When we place the LSDA into the TEXT section, the type info
613 // pointers need to be indirect and pc-rel. We accomplish this by
614 // using NLPs; however, sometimes the types are local to the file.
615 // We need to fill in the value for the NLP in those cases.
616 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
618 4/*size*/, 0/*addrspace*/);
622 OutStreamer.AddBlankLine();
625 Stubs = MMIMacho.GetHiddenGVStubList();
626 if (!Stubs.empty()) {
627 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
629 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
631 OutStreamer.EmitLabel(Stubs[i].first);
633 OutStreamer.EmitValue(MCSymbolRefExpr::
634 Create(Stubs[i].second.getPointer(),
636 4/*size*/, 0/*addrspace*/);
640 OutStreamer.AddBlankLine();
643 // Funny Darwin hack: This flag tells the linker that no global symbols
644 // contain code that falls through to other global symbols (e.g. the obvious
645 // implementation of multiple entry points). If this doesn't occur, the
646 // linker can safely perform dead code stripping. Since LLVM never
647 // generates code that does this, it is always safe to set.
648 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
652 //===----------------------------------------------------------------------===//
653 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
655 // The following seem like one-off assembler flags, but they actually need
656 // to appear in the .ARM.attributes section in ELF.
657 // Instead of subclassing the MCELFStreamer, we do the work here.
659 void ARMAsmPrinter::emitAttributes() {
661 emitARMAttributeSection();
663 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
664 bool emitFPU = false;
665 AttributeEmitter *AttrEmitter;
666 if (OutStreamer.hasRawTextSupport()) {
667 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
670 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
671 AttrEmitter = new ObjectAttributeEmitter(O);
674 AttrEmitter->MaybeSwitchVendor("aeabi");
676 std::string CPUString = Subtarget->getCPUString();
678 if (CPUString == "cortex-a8" ||
679 Subtarget->isCortexA8()) {
680 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
681 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
682 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
683 ARMBuildAttrs::ApplicationProfile);
684 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
685 ARMBuildAttrs::Allowed);
686 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
687 ARMBuildAttrs::AllowThumb32);
688 // Fixme: figure out when this is emitted.
689 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
690 // ARMBuildAttrs::AllowWMMXv1);
693 /// ADD additional Else-cases here!
694 } else if (CPUString == "xscale") {
695 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
696 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
697 ARMBuildAttrs::Allowed);
698 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
699 ARMBuildAttrs::Allowed);
700 } else if (CPUString == "generic") {
701 // FIXME: Why these defaults?
702 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
703 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
704 ARMBuildAttrs::Allowed);
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
706 ARMBuildAttrs::Allowed);
709 if (Subtarget->hasNEON() && emitFPU) {
710 /* NEON is not exactly a VFP architecture, but GAS emit one of
711 * neon/vfpv3/vfpv2 for .fpu parameters */
712 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
713 /* If emitted for NEON, omit from VFP below, since you can have both
714 * NEON and VFP in build attributes but only one .fpu */
719 if (Subtarget->hasVFP3()) {
720 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
721 ARMBuildAttrs::AllowFPv3A);
723 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
726 } else if (Subtarget->hasVFP2()) {
727 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
728 ARMBuildAttrs::AllowFPv2);
730 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
733 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
734 * since NEON can have 1 (allowed) or 2 (MAC operations) */
735 if (Subtarget->hasNEON()) {
736 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
737 ARMBuildAttrs::Allowed);
740 // Signal various FP modes.
742 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
743 ARMBuildAttrs::Allowed);
744 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
745 ARMBuildAttrs::Allowed);
748 if (NoInfsFPMath && NoNaNsFPMath)
749 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
750 ARMBuildAttrs::Allowed);
752 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
753 ARMBuildAttrs::AllowIEE754);
755 // FIXME: add more flags to ARMBuildAttrs.h
756 // 8-bytes alignment stuff.
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
758 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
760 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
761 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
762 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
763 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
765 // FIXME: Should we signal R9 usage?
767 if (Subtarget->hasDivide())
768 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
770 AttrEmitter->Finish();
774 void ARMAsmPrinter::emitARMAttributeSection() {
776 // [ <section-length> "vendor-name"
777 // [ <file-tag> <size> <attribute>*
778 // | <section-tag> <size> <section-number>* 0 <attribute>*
779 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
783 if (OutStreamer.hasRawTextSupport())
786 const ARMElfTargetObjectFile &TLOFELF =
787 static_cast<const ARMElfTargetObjectFile &>
788 (getObjFileLowering());
790 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
793 OutStreamer.EmitIntValue(0x41, 1);
796 //===----------------------------------------------------------------------===//
798 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
799 unsigned LabelId, MCContext &Ctx) {
801 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
802 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
806 static MCSymbolRefExpr::VariantKind
807 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
809 default: llvm_unreachable("Unknown modifier!");
810 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
811 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
812 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
813 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
814 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
815 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
817 return MCSymbolRefExpr::VK_None;
820 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
821 bool isIndirect = Subtarget->isTargetDarwin() &&
822 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
824 return Mang->getSymbol(GV);
826 // FIXME: Remove this when Darwin transition to @GOT like syntax.
827 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
828 MachineModuleInfoMachO &MMIMachO =
829 MMI->getObjFileInfo<MachineModuleInfoMachO>();
830 MachineModuleInfoImpl::StubValueTy &StubSym =
831 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
832 MMIMachO.getGVStubEntry(MCSym);
833 if (StubSym.getPointer() == 0)
834 StubSym = MachineModuleInfoImpl::
835 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
840 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
841 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
843 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
846 if (ACPV->isLSDA()) {
847 SmallString<128> Str;
848 raw_svector_ostream OS(Str);
849 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
850 MCSym = OutContext.GetOrCreateSymbol(OS.str());
851 } else if (ACPV->isBlockAddress()) {
852 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
853 } else if (ACPV->isGlobalValue()) {
854 const GlobalValue *GV = ACPV->getGV();
855 MCSym = GetARMGVSymbol(GV);
857 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
858 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
861 // Create an MCSymbol for the reference.
863 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
866 if (ACPV->getPCAdjustment()) {
867 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
871 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
873 MCBinaryExpr::CreateAdd(PCRelExpr,
874 MCConstantExpr::Create(ACPV->getPCAdjustment(),
877 if (ACPV->mustAddCurrentAddress()) {
878 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
879 // label, so just emit a local label end reference that instead.
880 MCSymbol *DotSym = OutContext.CreateTempSymbol();
881 OutStreamer.EmitLabel(DotSym);
882 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
883 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
885 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
887 OutStreamer.EmitValue(Expr, Size);
890 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
891 unsigned Opcode = MI->getOpcode();
893 if (Opcode == ARM::BR_JTadd)
895 else if (Opcode == ARM::BR_JTm)
898 const MachineOperand &MO1 = MI->getOperand(OpNum);
899 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
900 unsigned JTI = MO1.getIndex();
902 // Emit a label for the jump table.
903 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
904 OutStreamer.EmitLabel(JTISymbol);
906 // Emit each entry of the table.
907 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
908 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
909 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
911 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
912 MachineBasicBlock *MBB = JTBBs[i];
913 // Construct an MCExpr for the entry. We want a value of the form:
914 // (BasicBlockAddr - TableBeginAddr)
916 // For example, a table with entries jumping to basic blocks BB0 and BB1
919 // .word (LBB0 - LJTI_0_0)
920 // .word (LBB1 - LJTI_0_0)
921 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
923 if (TM.getRelocationModel() == Reloc::PIC_)
924 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
927 // If we're generating a table of Thumb addresses in static relocation
928 // model, we need to add one to keep interworking correctly.
929 else if (AFI->isThumbFunction())
930 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
932 OutStreamer.EmitValue(Expr, 4);
936 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
937 unsigned Opcode = MI->getOpcode();
938 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
939 const MachineOperand &MO1 = MI->getOperand(OpNum);
940 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
941 unsigned JTI = MO1.getIndex();
943 // Emit a label for the jump table.
944 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
945 OutStreamer.EmitLabel(JTISymbol);
947 // Emit each entry of the table.
948 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
949 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
950 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
951 unsigned OffsetWidth = 4;
952 if (MI->getOpcode() == ARM::t2TBB_JT)
954 else if (MI->getOpcode() == ARM::t2TBH_JT)
957 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
958 MachineBasicBlock *MBB = JTBBs[i];
959 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
961 // If this isn't a TBB or TBH, the entries are direct branch instructions.
962 if (OffsetWidth == 4) {
964 BrInst.setOpcode(ARM::t2B);
965 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
966 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
967 BrInst.addOperand(MCOperand::CreateReg(0));
968 OutStreamer.EmitInstruction(BrInst);
971 // Otherwise it's an offset from the dispatch instruction. Construct an
972 // MCExpr for the entry. We want a value of the form:
973 // (BasicBlockAddr - TableBeginAddr) / 2
975 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
978 // .byte (LBB0 - LJTI_0_0) / 2
979 // .byte (LBB1 - LJTI_0_0) / 2
981 MCBinaryExpr::CreateSub(MBBSymbolExpr,
982 MCSymbolRefExpr::Create(JTISymbol, OutContext),
984 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
986 OutStreamer.EmitValue(Expr, OffsetWidth);
990 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
992 unsigned NOps = MI->getNumOperands();
994 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
995 // cast away const; DIetc do not take const operands for some reason.
996 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
999 // Frame address. Currently handles register +- offset only.
1000 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1001 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1004 printOperand(MI, NOps-2, OS);
1007 static void populateADROperands(MCInst &Inst, unsigned Dest,
1008 const MCSymbol *Label,
1009 unsigned pred, unsigned ccreg,
1011 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1012 Inst.addOperand(MCOperand::CreateReg(Dest));
1013 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1014 // Add predicate operands.
1015 Inst.addOperand(MCOperand::CreateImm(pred));
1016 Inst.addOperand(MCOperand::CreateReg(ccreg));
1019 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1023 // Emit the instruction as usual, just patch the opcode.
1024 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1025 TmpInst.setOpcode(Opcode);
1026 OutStreamer.EmitInstruction(TmpInst);
1029 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1030 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1031 "Only instruction which are involved into frame setup code are allowed");
1033 const MachineFunction &MF = *MI->getParent()->getParent();
1034 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1035 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1037 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1038 unsigned Opc = MI->getOpcode();
1039 unsigned SrcReg, DstReg;
1041 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1042 // Two special cases:
1043 // 1) tPUSH does not have src/dst regs.
1044 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1045 // load. Yes, this is pretty fragile, but for now I don't see better
1047 SrcReg = DstReg = ARM::SP;
1049 SrcReg = MI->getOperand(1).getReg();
1050 DstReg = MI->getOperand(0).getReg();
1053 // Try to figure out the unwinding opcode out of src / dst regs.
1054 if (MI->getDesc().mayStore()) {
1056 assert(DstReg == ARM::SP &&
1057 "Only stack pointer as a destination reg is supported");
1059 SmallVector<unsigned, 4> RegList;
1060 // Skip src & dst reg, and pred ops.
1061 unsigned StartOp = 2 + 2;
1062 // Use all the operands.
1063 unsigned NumOffset = 0;
1068 assert(0 && "Unsupported opcode for unwinding information");
1070 // Special case here: no src & dst reg, but two extra imp ops.
1071 StartOp = 2; NumOffset = 2;
1072 case ARM::STMDB_UPD:
1073 case ARM::t2STMDB_UPD:
1074 case ARM::VSTMDDB_UPD:
1075 assert(SrcReg == ARM::SP &&
1076 "Only stack pointer as a source reg is supported");
1077 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1079 RegList.push_back(MI->getOperand(i).getReg());
1081 case ARM::STR_PRE_IMM:
1082 case ARM::STR_PRE_REG:
1083 assert(MI->getOperand(2).getReg() == ARM::SP &&
1084 "Only stack pointer as a source reg is supported");
1085 RegList.push_back(SrcReg);
1088 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1090 // Changes of stack / frame pointer.
1091 if (SrcReg == ARM::SP) {
1096 assert(0 && "Unsupported opcode for unwinding information");
1101 Offset = -MI->getOperand(2).getImm();
1104 Offset = MI->getOperand(2).getImm();
1107 Offset = MI->getOperand(2).getImm()*4;
1111 Offset = -MI->getOperand(2).getImm()*4;
1113 case ARM::tLDRpci: {
1114 // Grab the constpool index and check, whether it corresponds to
1115 // original or cloned constpool entry.
1116 unsigned CPI = MI->getOperand(1).getIndex();
1117 const MachineConstantPool *MCP = MF.getConstantPool();
1118 if (CPI >= MCP->getConstants().size())
1119 CPI = AFI.getOriginalCPIdx(CPI);
1120 assert(CPI != -1U && "Invalid constpool index");
1122 // Derive the actual offset.
1123 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1124 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1125 // FIXME: Check for user, it should be "add" instruction!
1126 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1131 if (DstReg == FramePtr && FramePtr != ARM::SP)
1132 // Set-up of the frame pointer. Positive values correspond to "add"
1134 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1135 else if (DstReg == ARM::SP) {
1136 // Change of SP by an offset. Positive values correspond to "sub"
1138 OutStreamer.EmitPad(Offset);
1141 assert(0 && "Unsupported opcode for unwinding information");
1143 } else if (DstReg == ARM::SP) {
1144 // FIXME: .movsp goes here
1146 assert(0 && "Unsupported opcode for unwinding information");
1150 assert(0 && "Unsupported opcode for unwinding information");
1155 extern cl::opt<bool> EnableARMEHABI;
1157 // Simple pseudo-instructions have their lowering (with expansion to real
1158 // instructions) auto-generated.
1159 #include "ARMGenMCPseudoLowering.inc"
1161 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1162 // Emit unwinding stuff for frame-related instructions
1163 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1164 EmitUnwindingInstruction(MI);
1166 // Do any auto-generated pseudo lowerings.
1167 if (emitPseudoExpansionLowering(OutStreamer, MI))
1170 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1171 "Pseudo flag setting opcode should be expanded early");
1173 // Check for manual lowerings.
1174 unsigned Opc = MI->getOpcode();
1176 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1177 case ARM::DBG_VALUE: {
1178 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1179 SmallString<128> TmpStr;
1180 raw_svector_ostream OS(TmpStr);
1181 PrintDebugValueComment(MI, OS);
1182 OutStreamer.EmitRawText(StringRef(OS.str()));
1187 case ARM::tLEApcrel:
1188 case ARM::t2LEApcrel: {
1189 // FIXME: Need to also handle globals and externals
1191 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1192 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1194 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1195 GetCPISymbol(MI->getOperand(1).getIndex()),
1196 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1198 OutStreamer.EmitInstruction(TmpInst);
1201 case ARM::LEApcrelJT:
1202 case ARM::tLEApcrelJT:
1203 case ARM::t2LEApcrelJT: {
1205 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1206 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1208 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1209 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1210 MI->getOperand(2).getImm()),
1211 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1213 OutStreamer.EmitInstruction(TmpInst);
1216 // Darwin call instructions are just normal call instructions with different
1217 // clobber semantics (they clobber R9).
1218 case ARM::BXr9_CALL:
1219 case ARM::BX_CALL: {
1222 TmpInst.setOpcode(ARM::MOVr);
1223 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1224 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1225 // Add predicate operands.
1226 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1227 TmpInst.addOperand(MCOperand::CreateReg(0));
1228 // Add 's' bit operand (always reg0 for this)
1229 TmpInst.addOperand(MCOperand::CreateReg(0));
1230 OutStreamer.EmitInstruction(TmpInst);
1234 TmpInst.setOpcode(ARM::BX);
1235 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1236 OutStreamer.EmitInstruction(TmpInst);
1240 case ARM::tBXr9_CALL:
1241 case ARM::tBX_CALL: {
1244 TmpInst.setOpcode(ARM::tMOVr);
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1247 // Add predicate operands.
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1249 TmpInst.addOperand(MCOperand::CreateReg(0));
1250 OutStreamer.EmitInstruction(TmpInst);
1254 TmpInst.setOpcode(ARM::tBX);
1255 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1256 // Add predicate operands.
1257 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1258 TmpInst.addOperand(MCOperand::CreateReg(0));
1259 OutStreamer.EmitInstruction(TmpInst);
1263 case ARM::BMOVPCRXr9_CALL:
1264 case ARM::BMOVPCRX_CALL: {
1267 TmpInst.setOpcode(ARM::MOVr);
1268 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1269 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1270 // Add predicate operands.
1271 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1272 TmpInst.addOperand(MCOperand::CreateReg(0));
1273 // Add 's' bit operand (always reg0 for this)
1274 TmpInst.addOperand(MCOperand::CreateReg(0));
1275 OutStreamer.EmitInstruction(TmpInst);
1279 TmpInst.setOpcode(ARM::MOVr);
1280 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1281 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1282 // Add predicate operands.
1283 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1284 TmpInst.addOperand(MCOperand::CreateReg(0));
1285 // Add 's' bit operand (always reg0 for this)
1286 TmpInst.addOperand(MCOperand::CreateReg(0));
1287 OutStreamer.EmitInstruction(TmpInst);
1291 case ARM::MOVi16_ga_pcrel:
1292 case ARM::t2MOVi16_ga_pcrel: {
1294 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1295 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1297 unsigned TF = MI->getOperand(1).getTargetFlags();
1298 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1299 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1300 MCSymbol *GVSym = GetARMGVSymbol(GV);
1301 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1303 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1304 getFunctionNumber(),
1305 MI->getOperand(2).getImm(), OutContext);
1306 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1307 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1308 const MCExpr *PCRelExpr =
1309 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1310 MCBinaryExpr::CreateAdd(LabelSymExpr,
1311 MCConstantExpr::Create(PCAdj, OutContext),
1312 OutContext), OutContext), OutContext);
1313 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1315 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1316 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1319 // Add predicate operands.
1320 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1321 TmpInst.addOperand(MCOperand::CreateReg(0));
1322 // Add 's' bit operand (always reg0 for this)
1323 TmpInst.addOperand(MCOperand::CreateReg(0));
1324 OutStreamer.EmitInstruction(TmpInst);
1327 case ARM::MOVTi16_ga_pcrel:
1328 case ARM::t2MOVTi16_ga_pcrel: {
1330 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1331 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1332 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1333 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1335 unsigned TF = MI->getOperand(2).getTargetFlags();
1336 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1337 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1338 MCSymbol *GVSym = GetARMGVSymbol(GV);
1339 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1341 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1342 getFunctionNumber(),
1343 MI->getOperand(3).getImm(), OutContext);
1344 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1345 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1346 const MCExpr *PCRelExpr =
1347 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1348 MCBinaryExpr::CreateAdd(LabelSymExpr,
1349 MCConstantExpr::Create(PCAdj, OutContext),
1350 OutContext), OutContext), OutContext);
1351 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1353 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1354 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1356 // Add predicate operands.
1357 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1358 TmpInst.addOperand(MCOperand::CreateReg(0));
1359 // Add 's' bit operand (always reg0 for this)
1360 TmpInst.addOperand(MCOperand::CreateReg(0));
1361 OutStreamer.EmitInstruction(TmpInst);
1364 case ARM::tPICADD: {
1365 // This is a pseudo op for a label + instruction sequence, which looks like:
1368 // This adds the address of LPC0 to r0.
1371 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1372 getFunctionNumber(), MI->getOperand(2).getImm(),
1375 // Form and emit the add.
1377 AddInst.setOpcode(ARM::tADDhirr);
1378 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1379 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1380 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1381 // Add predicate operands.
1382 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1383 AddInst.addOperand(MCOperand::CreateReg(0));
1384 OutStreamer.EmitInstruction(AddInst);
1388 // This is a pseudo op for a label + instruction sequence, which looks like:
1391 // This adds the address of LPC0 to r0.
1394 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1395 getFunctionNumber(), MI->getOperand(2).getImm(),
1398 // Form and emit the add.
1400 AddInst.setOpcode(ARM::ADDrr);
1401 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1402 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1403 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1404 // Add predicate operands.
1405 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1406 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1407 // Add 's' bit operand (always reg0 for this)
1408 AddInst.addOperand(MCOperand::CreateReg(0));
1409 OutStreamer.EmitInstruction(AddInst);
1419 case ARM::PICLDRSH: {
1420 // This is a pseudo op for a label + instruction sequence, which looks like:
1423 // The LCP0 label is referenced by a constant pool entry in order to get
1424 // a PC-relative address at the ldr instruction.
1427 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1428 getFunctionNumber(), MI->getOperand(2).getImm(),
1431 // Form and emit the load
1433 switch (MI->getOpcode()) {
1435 llvm_unreachable("Unexpected opcode!");
1436 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1437 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1438 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1439 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1440 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1441 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1442 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1443 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1446 LdStInst.setOpcode(Opcode);
1447 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1448 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1449 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1450 LdStInst.addOperand(MCOperand::CreateImm(0));
1451 // Add predicate operands.
1452 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1453 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1454 OutStreamer.EmitInstruction(LdStInst);
1458 case ARM::CONSTPOOL_ENTRY: {
1459 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1460 /// in the function. The first operand is the ID# for this instruction, the
1461 /// second is the index into the MachineConstantPool that this is, the third
1462 /// is the size in bytes of this constant pool entry.
1463 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1464 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1467 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1469 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1470 if (MCPE.isMachineConstantPoolEntry())
1471 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1473 EmitGlobalConstant(MCPE.Val.ConstVal);
1477 case ARM::t2BR_JT: {
1478 // Lower and emit the instruction itself, then the jump table following it.
1480 TmpInst.setOpcode(ARM::tMOVr);
1481 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1482 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1483 // Add predicate operands.
1484 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1485 TmpInst.addOperand(MCOperand::CreateReg(0));
1486 OutStreamer.EmitInstruction(TmpInst);
1487 // Output the data for the jump table itself
1491 case ARM::t2TBB_JT: {
1492 // Lower and emit the instruction itself, then the jump table following it.
1495 TmpInst.setOpcode(ARM::t2TBB);
1496 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1497 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1498 // Add predicate operands.
1499 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1500 TmpInst.addOperand(MCOperand::CreateReg(0));
1501 OutStreamer.EmitInstruction(TmpInst);
1502 // Output the data for the jump table itself
1504 // Make sure the next instruction is 2-byte aligned.
1508 case ARM::t2TBH_JT: {
1509 // Lower and emit the instruction itself, then the jump table following it.
1512 TmpInst.setOpcode(ARM::t2TBH);
1513 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1514 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1515 // Add predicate operands.
1516 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1517 TmpInst.addOperand(MCOperand::CreateReg(0));
1518 OutStreamer.EmitInstruction(TmpInst);
1519 // Output the data for the jump table itself
1525 // Lower and emit the instruction itself, then the jump table following it.
1528 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1529 ARM::MOVr : ARM::tMOVr;
1530 TmpInst.setOpcode(Opc);
1531 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1532 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1533 // Add predicate operands.
1534 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1535 TmpInst.addOperand(MCOperand::CreateReg(0));
1536 // Add 's' bit operand (always reg0 for this)
1537 if (Opc == ARM::MOVr)
1538 TmpInst.addOperand(MCOperand::CreateReg(0));
1539 OutStreamer.EmitInstruction(TmpInst);
1541 // Make sure the Thumb jump table is 4-byte aligned.
1542 if (Opc == ARM::tMOVr)
1545 // Output the data for the jump table itself
1550 // Lower and emit the instruction itself, then the jump table following it.
1553 if (MI->getOperand(1).getReg() == 0) {
1555 TmpInst.setOpcode(ARM::LDRi12);
1556 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1557 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1558 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1560 TmpInst.setOpcode(ARM::LDRrs);
1561 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1562 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1563 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1564 TmpInst.addOperand(MCOperand::CreateImm(0));
1566 // Add predicate operands.
1567 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1568 TmpInst.addOperand(MCOperand::CreateReg(0));
1569 OutStreamer.EmitInstruction(TmpInst);
1571 // Output the data for the jump table itself
1575 case ARM::BR_JTadd: {
1576 // Lower and emit the instruction itself, then the jump table following it.
1577 // add pc, target, idx
1579 TmpInst.setOpcode(ARM::ADDrr);
1580 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1581 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1582 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1583 // Add predicate operands.
1584 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1585 TmpInst.addOperand(MCOperand::CreateReg(0));
1586 // Add 's' bit operand (always reg0 for this)
1587 TmpInst.addOperand(MCOperand::CreateReg(0));
1588 OutStreamer.EmitInstruction(TmpInst);
1590 // Output the data for the jump table itself
1595 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1596 // FIXME: Remove this special case when they do.
1597 if (!Subtarget->isTargetDarwin()) {
1598 //.long 0xe7ffdefe @ trap
1599 uint32_t Val = 0xe7ffdefeUL;
1600 OutStreamer.AddComment("trap");
1601 OutStreamer.EmitIntValue(Val, 4);
1607 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1608 // FIXME: Remove this special case when they do.
1609 if (!Subtarget->isTargetDarwin()) {
1610 //.short 57086 @ trap
1611 uint16_t Val = 0xdefe;
1612 OutStreamer.AddComment("trap");
1613 OutStreamer.EmitIntValue(Val, 2);
1618 case ARM::t2Int_eh_sjlj_setjmp:
1619 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1620 case ARM::tInt_eh_sjlj_setjmp: {
1621 // Two incoming args: GPR:$src, GPR:$val
1624 // str $val, [$src, #4]
1629 unsigned SrcReg = MI->getOperand(0).getReg();
1630 unsigned ValReg = MI->getOperand(1).getReg();
1631 MCSymbol *Label = GetARMSJLJEHLabel();
1634 TmpInst.setOpcode(ARM::tMOVr);
1635 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1636 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1638 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1639 TmpInst.addOperand(MCOperand::CreateReg(0));
1640 OutStreamer.AddComment("eh_setjmp begin");
1641 OutStreamer.EmitInstruction(TmpInst);
1645 TmpInst.setOpcode(ARM::tADDi3);
1646 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1648 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1649 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1650 TmpInst.addOperand(MCOperand::CreateImm(7));
1652 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1653 TmpInst.addOperand(MCOperand::CreateReg(0));
1654 OutStreamer.EmitInstruction(TmpInst);
1658 TmpInst.setOpcode(ARM::tSTRi);
1659 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1660 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1661 // The offset immediate is #4. The operand value is scaled by 4 for the
1662 // tSTR instruction.
1663 TmpInst.addOperand(MCOperand::CreateImm(1));
1665 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1666 TmpInst.addOperand(MCOperand::CreateReg(0));
1667 OutStreamer.EmitInstruction(TmpInst);
1671 TmpInst.setOpcode(ARM::tMOVi8);
1672 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1673 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1674 TmpInst.addOperand(MCOperand::CreateImm(0));
1676 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1677 TmpInst.addOperand(MCOperand::CreateReg(0));
1678 OutStreamer.EmitInstruction(TmpInst);
1681 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1683 TmpInst.setOpcode(ARM::tB);
1684 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1685 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1686 TmpInst.addOperand(MCOperand::CreateReg(0));
1687 OutStreamer.EmitInstruction(TmpInst);
1691 TmpInst.setOpcode(ARM::tMOVi8);
1692 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1693 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1694 TmpInst.addOperand(MCOperand::CreateImm(1));
1696 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1697 TmpInst.addOperand(MCOperand::CreateReg(0));
1698 OutStreamer.AddComment("eh_setjmp end");
1699 OutStreamer.EmitInstruction(TmpInst);
1701 OutStreamer.EmitLabel(Label);
1705 case ARM::Int_eh_sjlj_setjmp_nofp:
1706 case ARM::Int_eh_sjlj_setjmp: {
1707 // Two incoming args: GPR:$src, GPR:$val
1709 // str $val, [$src, #+4]
1713 unsigned SrcReg = MI->getOperand(0).getReg();
1714 unsigned ValReg = MI->getOperand(1).getReg();
1718 TmpInst.setOpcode(ARM::ADDri);
1719 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1720 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1721 TmpInst.addOperand(MCOperand::CreateImm(8));
1723 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1724 TmpInst.addOperand(MCOperand::CreateReg(0));
1725 // 's' bit operand (always reg0 for this).
1726 TmpInst.addOperand(MCOperand::CreateReg(0));
1727 OutStreamer.AddComment("eh_setjmp begin");
1728 OutStreamer.EmitInstruction(TmpInst);
1732 TmpInst.setOpcode(ARM::STRi12);
1733 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1734 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1735 TmpInst.addOperand(MCOperand::CreateImm(4));
1737 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1738 TmpInst.addOperand(MCOperand::CreateReg(0));
1739 OutStreamer.EmitInstruction(TmpInst);
1743 TmpInst.setOpcode(ARM::MOVi);
1744 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1745 TmpInst.addOperand(MCOperand::CreateImm(0));
1747 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1748 TmpInst.addOperand(MCOperand::CreateReg(0));
1749 // 's' bit operand (always reg0 for this).
1750 TmpInst.addOperand(MCOperand::CreateReg(0));
1751 OutStreamer.EmitInstruction(TmpInst);
1755 TmpInst.setOpcode(ARM::ADDri);
1756 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1757 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1758 TmpInst.addOperand(MCOperand::CreateImm(0));
1760 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1761 TmpInst.addOperand(MCOperand::CreateReg(0));
1762 // 's' bit operand (always reg0 for this).
1763 TmpInst.addOperand(MCOperand::CreateReg(0));
1764 OutStreamer.EmitInstruction(TmpInst);
1768 TmpInst.setOpcode(ARM::MOVi);
1769 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1770 TmpInst.addOperand(MCOperand::CreateImm(1));
1772 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1773 TmpInst.addOperand(MCOperand::CreateReg(0));
1774 // 's' bit operand (always reg0 for this).
1775 TmpInst.addOperand(MCOperand::CreateReg(0));
1776 OutStreamer.AddComment("eh_setjmp end");
1777 OutStreamer.EmitInstruction(TmpInst);
1781 case ARM::Int_eh_sjlj_longjmp: {
1782 // ldr sp, [$src, #8]
1783 // ldr $scratch, [$src, #4]
1786 unsigned SrcReg = MI->getOperand(0).getReg();
1787 unsigned ScratchReg = MI->getOperand(1).getReg();
1790 TmpInst.setOpcode(ARM::LDRi12);
1791 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1792 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1793 TmpInst.addOperand(MCOperand::CreateImm(8));
1795 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1796 TmpInst.addOperand(MCOperand::CreateReg(0));
1797 OutStreamer.EmitInstruction(TmpInst);
1801 TmpInst.setOpcode(ARM::LDRi12);
1802 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1803 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1804 TmpInst.addOperand(MCOperand::CreateImm(4));
1806 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1807 TmpInst.addOperand(MCOperand::CreateReg(0));
1808 OutStreamer.EmitInstruction(TmpInst);
1812 TmpInst.setOpcode(ARM::LDRi12);
1813 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1814 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1815 TmpInst.addOperand(MCOperand::CreateImm(0));
1817 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1818 TmpInst.addOperand(MCOperand::CreateReg(0));
1819 OutStreamer.EmitInstruction(TmpInst);
1823 TmpInst.setOpcode(ARM::BX);
1824 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1826 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1827 TmpInst.addOperand(MCOperand::CreateReg(0));
1828 OutStreamer.EmitInstruction(TmpInst);
1832 case ARM::tInt_eh_sjlj_longjmp: {
1833 // ldr $scratch, [$src, #8]
1835 // ldr $scratch, [$src, #4]
1838 unsigned SrcReg = MI->getOperand(0).getReg();
1839 unsigned ScratchReg = MI->getOperand(1).getReg();
1842 TmpInst.setOpcode(ARM::tLDRi);
1843 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1844 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1845 // The offset immediate is #8. The operand value is scaled by 4 for the
1846 // tLDR instruction.
1847 TmpInst.addOperand(MCOperand::CreateImm(2));
1849 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1850 TmpInst.addOperand(MCOperand::CreateReg(0));
1851 OutStreamer.EmitInstruction(TmpInst);
1855 TmpInst.setOpcode(ARM::tMOVr);
1856 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1857 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1859 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1860 TmpInst.addOperand(MCOperand::CreateReg(0));
1861 OutStreamer.EmitInstruction(TmpInst);
1865 TmpInst.setOpcode(ARM::tLDRi);
1866 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1867 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1868 TmpInst.addOperand(MCOperand::CreateImm(1));
1870 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1871 TmpInst.addOperand(MCOperand::CreateReg(0));
1872 OutStreamer.EmitInstruction(TmpInst);
1876 TmpInst.setOpcode(ARM::tLDRr);
1877 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1878 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1879 TmpInst.addOperand(MCOperand::CreateReg(0));
1881 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1882 TmpInst.addOperand(MCOperand::CreateReg(0));
1883 OutStreamer.EmitInstruction(TmpInst);
1887 TmpInst.setOpcode(ARM::tBX);
1888 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1890 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1891 TmpInst.addOperand(MCOperand::CreateReg(0));
1892 OutStreamer.EmitInstruction(TmpInst);
1899 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1901 OutStreamer.EmitInstruction(TmpInst);
1904 //===----------------------------------------------------------------------===//
1905 // Target Registry Stuff
1906 //===----------------------------------------------------------------------===//
1908 // Force static initialization.
1909 extern "C" void LLVMInitializeARMAsmPrinter() {
1910 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1911 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);