1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
57 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
58 cl::desc("enable experimental asmprinter gunk in the arm backend"));
70 class ARMAsmPrinter : public AsmPrinter {
72 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
73 /// make the right decision when printing asm code for different targets.
74 const ARMSubtarget *Subtarget;
76 /// AFI - Keep a pointer to ARMFunctionInfo for the current
80 /// MCP - Keep a pointer to constantpool entries of the current
82 const MachineConstantPool *MCP;
85 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
86 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
87 Subtarget = &TM.getSubtarget<ARMSubtarget>();
90 virtual const char *getPassName() const {
91 return "ARM Assembly Printer";
94 void EmitJumpTable(const MachineInstr *MI);
95 void EmitJump2Table(const MachineInstr *MI);
96 void printInstructionThroughMCStreamer(const MachineInstr *MI);
99 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
100 const char *Modifier = 0);
101 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
102 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
104 void printSORegOperand(const MachineInstr *MI, int OpNum,
106 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
108 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
110 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
112 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
114 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
115 const char *Modifier = 0);
116 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
117 const char *Modifier = 0);
118 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
120 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
122 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
124 const char *Modifier = 0);
125 void printBitfieldInvMaskImmOperand(const MachineInstr *MI, int OpNum,
127 void printMemBOption(const MachineInstr *MI, int OpNum,
129 void printShiftImmOperand(const MachineInstr *MI, int OpNum,
132 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
134 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
135 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
137 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
140 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
142 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
146 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
149 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
150 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
152 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
154 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
156 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
158 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
160 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
163 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
165 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
167 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
169 void printPredicateOperand(const MachineInstr *MI, int OpNum,
171 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
173 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
175 void printPCLabel(const MachineInstr *MI, int OpNum,
177 void printRegisterList(const MachineInstr *MI, int OpNum,
179 void printCPInstOperand(const MachineInstr *MI, int OpNum,
181 const char *Modifier);
182 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
184 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
186 void printTBAddrMode(const MachineInstr *MI, int OpNum,
188 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
190 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
192 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
194 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
197 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
198 unsigned AsmVariant, const char *ExtraCode,
200 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
202 const char *ExtraCode, raw_ostream &O);
204 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
205 static const char *getRegisterName(unsigned RegNo);
207 virtual void EmitInstruction(const MachineInstr *MI);
208 bool runOnMachineFunction(MachineFunction &F);
210 virtual void EmitConstantPool() {} // we emit constant pools customly!
211 virtual void EmitFunctionEntryLabel();
212 void EmitStartOfAsmFile(Module &M);
213 void EmitEndOfAsmFile(Module &M);
215 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
216 MachineLocation Location;
217 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
218 // Frame address. Currently handles register +- offset only.
219 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
220 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
222 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
227 virtual unsigned getISAEncoding() {
228 // ARM/Darwin adds ISA to the DWARF info for each function.
229 if (!Subtarget->isTargetDarwin())
231 return Subtarget->isThumb() ?
232 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
235 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
236 const MachineBasicBlock *MBB) const;
237 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
239 MCSymbol *GetARMSJLJEHLabel(void) const;
241 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
243 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
244 SmallString<128> Str;
245 raw_svector_ostream OS(Str);
246 EmitMachineConstantPoolValue(MCPV, OS);
247 OutStreamer.EmitRawText(OS.str());
250 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
252 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
253 case 1: O << MAI->getData8bitsDirective(0); break;
254 case 2: O << MAI->getData16bitsDirective(0); break;
255 case 4: O << MAI->getData32bitsDirective(0); break;
256 default: assert(0 && "Unknown CPV size");
259 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
261 if (ACPV->isLSDA()) {
262 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
263 } else if (ACPV->isBlockAddress()) {
264 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
265 } else if (ACPV->isGlobalValue()) {
266 const GlobalValue *GV = ACPV->getGV();
267 bool isIndirect = Subtarget->isTargetDarwin() &&
268 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
270 O << *Mang->getSymbol(GV);
272 // FIXME: Remove this when Darwin transition to @GOT like syntax.
273 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
276 MachineModuleInfoMachO &MMIMachO =
277 MMI->getObjFileInfo<MachineModuleInfoMachO>();
278 MachineModuleInfoImpl::StubValueTy &StubSym =
279 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
280 MMIMachO.getGVStubEntry(Sym);
281 if (StubSym.getPointer() == 0)
282 StubSym = MachineModuleInfoImpl::
283 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
286 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
287 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
290 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
291 if (ACPV->getPCAdjustment() != 0) {
292 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
293 << getFunctionNumber() << "_" << ACPV->getLabelId()
294 << "+" << (unsigned)ACPV->getPCAdjustment();
295 if (ACPV->mustAddCurrentAddress())
301 } // end of anonymous namespace
303 #include "ARMGenAsmWriter.inc"
305 void ARMAsmPrinter::EmitFunctionEntryLabel() {
306 if (AFI->isThumbFunction()) {
307 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
308 if (!Subtarget->isTargetDarwin())
309 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
311 // This needs to emit to a temporary string to get properly quoted
312 // MCSymbols when they have spaces in them.
313 SmallString<128> Tmp;
314 raw_svector_ostream OS(Tmp);
315 OS << "\t.thumb_func\t" << *CurrentFnSym;
316 OutStreamer.EmitRawText(OS.str());
320 OutStreamer.EmitLabel(CurrentFnSym);
323 /// runOnMachineFunction - This uses the printInstruction()
324 /// method to print assembly for each instruction.
326 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
327 AFI = MF.getInfo<ARMFunctionInfo>();
328 MCP = MF.getConstantPool();
330 return AsmPrinter::runOnMachineFunction(MF);
333 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
334 raw_ostream &O, const char *Modifier) {
335 const MachineOperand &MO = MI->getOperand(OpNum);
336 unsigned TF = MO.getTargetFlags();
338 switch (MO.getType()) {
340 assert(0 && "<unknown operand type>");
341 case MachineOperand::MO_Register: {
342 unsigned Reg = MO.getReg();
343 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
344 if (Modifier && strcmp(Modifier, "lane") == 0) {
345 unsigned RegNum = getARMRegisterNumbering(Reg);
347 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
348 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
349 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
351 assert(!MO.getSubReg() && "Subregs should be eliminated!");
352 O << getRegisterName(Reg);
356 case MachineOperand::MO_Immediate: {
357 int64_t Imm = MO.getImm();
359 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
360 (TF & ARMII::MO_LO16))
362 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
363 (TF & ARMII::MO_HI16))
368 case MachineOperand::MO_MachineBasicBlock:
369 O << *MO.getMBB()->getSymbol();
371 case MachineOperand::MO_GlobalAddress: {
372 bool isCallOp = Modifier && !strcmp(Modifier, "call");
373 const GlobalValue *GV = MO.getGlobal();
375 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
376 (TF & ARMII::MO_LO16))
378 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
379 (TF & ARMII::MO_HI16))
381 O << *Mang->getSymbol(GV);
383 printOffset(MO.getOffset(), O);
385 if (isCallOp && Subtarget->isTargetELF() &&
386 TM.getRelocationModel() == Reloc::PIC_)
390 case MachineOperand::MO_ExternalSymbol: {
391 bool isCallOp = Modifier && !strcmp(Modifier, "call");
392 O << *GetExternalSymbolSymbol(MO.getSymbolName());
394 if (isCallOp && Subtarget->isTargetELF() &&
395 TM.getRelocationModel() == Reloc::PIC_)
399 case MachineOperand::MO_ConstantPoolIndex:
400 O << *GetCPISymbol(MO.getIndex());
402 case MachineOperand::MO_JumpTableIndex:
403 O << *GetJTISymbol(MO.getIndex());
408 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
409 const MCAsmInfo *MAI) {
410 // Break it up into two parts that make up a shifter immediate.
411 V = ARM_AM::getSOImmVal(V);
412 assert(V != -1 && "Not a valid so_imm value!");
414 unsigned Imm = ARM_AM::getSOImmValImm(V);
415 unsigned Rot = ARM_AM::getSOImmValRot(V);
417 // Print low-level immediate formation info, per
418 // A5.1.3: "Data-processing operands - Immediate".
420 O << "#" << Imm << ", " << Rot;
421 // Pretty printed version.
423 O << "\t" << MAI->getCommentString() << ' ';
424 O << (int)ARM_AM::rotr32(Imm, Rot);
431 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
432 /// immediate in bits 0-7.
433 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
435 const MachineOperand &MO = MI->getOperand(OpNum);
436 assert(MO.isImm() && "Not a valid so_imm value!");
437 printSOImm(O, MO.getImm(), isVerbose(), MAI);
440 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
441 /// followed by an 'orr' to materialize.
442 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
444 const MachineOperand &MO = MI->getOperand(OpNum);
445 assert(MO.isImm() && "Not a valid so_imm value!");
446 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
447 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
448 printSOImm(O, V1, isVerbose(), MAI);
450 printPredicateOperand(MI, 2, O);
452 printOperand(MI, 0, O);
454 printOperand(MI, 0, O);
456 printSOImm(O, V2, isVerbose(), MAI);
459 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
460 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
462 // REG REG 0,SH_OPC - e.g. R5, ROR R3
463 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
464 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
466 const MachineOperand &MO1 = MI->getOperand(Op);
467 const MachineOperand &MO2 = MI->getOperand(Op+1);
468 const MachineOperand &MO3 = MI->getOperand(Op+2);
470 O << getRegisterName(MO1.getReg());
472 // Print the shift opc.
473 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
474 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
476 O << ' ' << getRegisterName(MO2.getReg());
477 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
478 } else if (ShOpc != ARM_AM::rrx) {
479 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
483 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
485 const MachineOperand &MO1 = MI->getOperand(Op);
486 const MachineOperand &MO2 = MI->getOperand(Op+1);
487 const MachineOperand &MO3 = MI->getOperand(Op+2);
489 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
490 printOperand(MI, Op, O);
494 O << "[" << getRegisterName(MO1.getReg());
497 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
499 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
500 << ARM_AM::getAM2Offset(MO3.getImm());
506 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
507 << getRegisterName(MO2.getReg());
509 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
511 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
516 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
518 const MachineOperand &MO1 = MI->getOperand(Op);
519 const MachineOperand &MO2 = MI->getOperand(Op+1);
522 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
524 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
529 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
530 << getRegisterName(MO1.getReg());
532 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
534 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
538 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
540 const MachineOperand &MO1 = MI->getOperand(Op);
541 const MachineOperand &MO2 = MI->getOperand(Op+1);
542 const MachineOperand &MO3 = MI->getOperand(Op+2);
544 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
545 O << "[" << getRegisterName(MO1.getReg());
549 << (char)ARM_AM::getAM3Op(MO3.getImm())
550 << getRegisterName(MO2.getReg())
555 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
557 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
562 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
564 const MachineOperand &MO1 = MI->getOperand(Op);
565 const MachineOperand &MO2 = MI->getOperand(Op+1);
568 O << (char)ARM_AM::getAM3Op(MO2.getImm())
569 << getRegisterName(MO1.getReg());
573 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
575 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
579 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
581 const char *Modifier) {
582 const MachineOperand &MO2 = MI->getOperand(Op+1);
583 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
584 if (Modifier && strcmp(Modifier, "submode") == 0) {
585 O << ARM_AM::getAMSubModeStr(Mode);
586 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
587 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
588 if (Mode == ARM_AM::ia)
591 printOperand(MI, Op, O);
595 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
597 const char *Modifier) {
598 const MachineOperand &MO1 = MI->getOperand(Op);
599 const MachineOperand &MO2 = MI->getOperand(Op+1);
601 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
602 printOperand(MI, Op, O);
606 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
608 O << "[" << getRegisterName(MO1.getReg());
610 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
612 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
618 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
620 const MachineOperand &MO1 = MI->getOperand(Op);
621 const MachineOperand &MO2 = MI->getOperand(Op+1);
623 O << "[" << getRegisterName(MO1.getReg());
625 // FIXME: Both darwin as and GNU as violate ARM docs here.
626 O << ", :" << (MO2.getImm() << 3);
631 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
633 const MachineOperand &MO = MI->getOperand(Op);
634 if (MO.getReg() == 0)
637 O << ", " << getRegisterName(MO.getReg());
640 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
642 const char *Modifier) {
643 if (Modifier && strcmp(Modifier, "label") == 0) {
644 printPCLabel(MI, Op+1, O);
648 const MachineOperand &MO1 = MI->getOperand(Op);
649 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
650 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
654 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
656 const MachineOperand &MO = MI->getOperand(Op);
657 uint32_t v = ~MO.getImm();
658 int32_t lsb = CountTrailingZeros_32(v);
659 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
660 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
661 O << "#" << lsb << ", #" << width;
665 ARMAsmPrinter::printMemBOption(const MachineInstr *MI, int OpNum,
667 unsigned val = MI->getOperand(OpNum).getImm();
668 O << ARM_MB::MemBOptToString(val);
671 void ARMAsmPrinter::printShiftImmOperand(const MachineInstr *MI, int OpNum,
673 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
674 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
676 case ARM_AM::no_shift:
685 assert(0 && "unexpected shift opcode for shift immediate operand");
687 O << ARM_AM::getSORegOffset(ShiftOp);
690 //===--------------------------------------------------------------------===//
692 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
694 O << "#" << MI->getOperand(Op).getImm() * 4;
698 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
700 // (3 - the number of trailing zeros) is the number of then / else.
701 unsigned Mask = MI->getOperand(Op).getImm();
702 unsigned CondBit0 = Mask >> 4 & 1;
703 unsigned NumTZ = CountTrailingZeros_32(Mask);
704 assert(NumTZ <= 3 && "Invalid IT mask!");
705 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
706 bool T = ((Mask >> Pos) & 1) == CondBit0;
715 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
717 const MachineOperand &MO1 = MI->getOperand(Op);
718 const MachineOperand &MO2 = MI->getOperand(Op+1);
719 O << "[" << getRegisterName(MO1.getReg());
720 O << ", " << getRegisterName(MO2.getReg()) << "]";
724 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
727 const MachineOperand &MO1 = MI->getOperand(Op);
728 const MachineOperand &MO2 = MI->getOperand(Op+1);
729 const MachineOperand &MO3 = MI->getOperand(Op+2);
731 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
732 printOperand(MI, Op, O);
736 O << "[" << getRegisterName(MO1.getReg());
738 O << ", " << getRegisterName(MO3.getReg());
739 else if (unsigned ImmOffs = MO2.getImm())
740 O << ", #" << ImmOffs * Scale;
745 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
747 printThumbAddrModeRI5Operand(MI, Op, O, 1);
750 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
752 printThumbAddrModeRI5Operand(MI, Op, O, 2);
755 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
757 printThumbAddrModeRI5Operand(MI, Op, O, 4);
760 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
762 const MachineOperand &MO1 = MI->getOperand(Op);
763 const MachineOperand &MO2 = MI->getOperand(Op+1);
764 O << "[" << getRegisterName(MO1.getReg());
765 if (unsigned ImmOffs = MO2.getImm())
766 O << ", #" << ImmOffs*4;
770 //===--------------------------------------------------------------------===//
772 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
773 // register with shift forms.
775 // REG IMM, SH_OPC - e.g. R5, LSL #3
776 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
778 const MachineOperand &MO1 = MI->getOperand(OpNum);
779 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
781 unsigned Reg = MO1.getReg();
782 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
783 O << getRegisterName(Reg);
785 // Print the shift opc.
786 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
787 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
788 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
789 if (ShOpc != ARM_AM::rrx)
790 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
793 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
796 const MachineOperand &MO1 = MI->getOperand(OpNum);
797 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
799 O << "[" << getRegisterName(MO1.getReg());
801 unsigned OffImm = MO2.getImm();
802 if (OffImm) // Don't print +0.
803 O << ", #" << OffImm;
807 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
810 const MachineOperand &MO1 = MI->getOperand(OpNum);
811 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
813 O << "[" << getRegisterName(MO1.getReg());
815 int32_t OffImm = (int32_t)MO2.getImm();
818 O << ", #-" << -OffImm;
820 O << ", #" << OffImm;
824 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
827 const MachineOperand &MO1 = MI->getOperand(OpNum);
828 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
830 O << "[" << getRegisterName(MO1.getReg());
832 int32_t OffImm = (int32_t)MO2.getImm() / 4;
835 O << ", #-" << -OffImm * 4;
837 O << ", #" << OffImm * 4;
841 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
844 const MachineOperand &MO1 = MI->getOperand(OpNum);
845 int32_t OffImm = (int32_t)MO1.getImm();
848 O << "#-" << -OffImm;
853 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
856 const MachineOperand &MO1 = MI->getOperand(OpNum);
857 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
858 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
860 O << "[" << getRegisterName(MO1.getReg());
862 assert(MO2.getReg() && "Invalid so_reg load / store address!");
863 O << ", " << getRegisterName(MO2.getReg());
865 unsigned ShAmt = MO3.getImm();
867 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
868 O << ", lsl #" << ShAmt;
874 //===--------------------------------------------------------------------===//
876 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
878 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
880 O << ARMCondCodeToString(CC);
883 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
886 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
887 O << ARMCondCodeToString(CC);
890 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
892 unsigned Reg = MI->getOperand(OpNum).getReg();
894 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
899 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
901 int Id = (int)MI->getOperand(OpNum).getImm();
902 O << MAI->getPrivateGlobalPrefix()
903 << "PC" << getFunctionNumber() << "_" << Id;
906 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
909 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
910 if (MI->getOperand(i).isImplicit())
912 if ((int)i != OpNum) O << ", ";
913 printOperand(MI, i, O);
918 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
919 raw_ostream &O, const char *Modifier) {
920 assert(Modifier && "This operand only works with a modifier!");
921 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
923 if (!strcmp(Modifier, "label")) {
924 unsigned ID = MI->getOperand(OpNum).getImm();
925 OutStreamer.EmitLabel(GetCPISymbol(ID));
927 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
928 unsigned CPI = MI->getOperand(OpNum).getIndex();
930 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
932 if (MCPE.isMachineConstantPoolEntry()) {
933 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
935 EmitGlobalConstant(MCPE.Val.ConstVal);
940 MCSymbol *ARMAsmPrinter::
941 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
942 const MachineBasicBlock *MBB) const {
943 SmallString<60> Name;
944 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
945 << getFunctionNumber() << '_' << uid << '_' << uid2
946 << "_set_" << MBB->getNumber();
947 return OutContext.GetOrCreateSymbol(Name.str());
950 MCSymbol *ARMAsmPrinter::
951 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
952 SmallString<60> Name;
953 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
954 << getFunctionNumber() << '_' << uid << '_' << uid2;
955 return OutContext.GetOrCreateSymbol(Name.str());
959 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
960 SmallString<60> Name;
961 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
962 << getFunctionNumber();
963 return OutContext.GetOrCreateSymbol(Name.str());
966 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
968 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
970 const MachineOperand &MO1 = MI->getOperand(OpNum);
971 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
973 unsigned JTI = MO1.getIndex();
974 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
975 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
977 O << "\n" << *JTISymbol << ":\n";
979 const char *JTEntryDirective = MAI->getData32bitsDirective();
981 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
982 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
983 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
984 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
985 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
986 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
987 MachineBasicBlock *MBB = JTBBs[i];
988 bool isNew = JTSets.insert(MBB);
990 if (UseSet && isNew) {
992 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
993 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
996 O << JTEntryDirective << ' ';
998 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
999 else if (TM.getRelocationModel() == Reloc::PIC_)
1000 O << *MBB->getSymbol() << '-' << *JTISymbol;
1002 O << *MBB->getSymbol();
1009 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
1011 const MachineOperand &MO1 = MI->getOperand(OpNum);
1012 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1013 unsigned JTI = MO1.getIndex();
1015 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1017 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
1019 O << "\n" << *JTISymbol << ":\n";
1021 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1022 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1023 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1024 bool ByteOffset = false, HalfWordOffset = false;
1025 if (MI->getOpcode() == ARM::t2TBB)
1027 else if (MI->getOpcode() == ARM::t2TBH)
1028 HalfWordOffset = true;
1030 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1031 MachineBasicBlock *MBB = JTBBs[i];
1033 O << MAI->getData8bitsDirective();
1034 else if (HalfWordOffset)
1035 O << MAI->getData16bitsDirective();
1037 if (ByteOffset || HalfWordOffset)
1038 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1040 O << "\tb.w " << *MBB->getSymbol();
1047 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1049 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1050 if (MI->getOpcode() == ARM::t2TBH)
1055 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1057 O << MI->getOperand(OpNum).getImm();
1060 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1062 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1063 O << '#' << FP->getValueAPF().convertToFloat();
1065 O << "\t\t" << MAI->getCommentString() << ' ';
1066 WriteAsOperand(O, FP, /*PrintType=*/false);
1070 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1072 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1073 O << '#' << FP->getValueAPF().convertToDouble();
1075 O << "\t\t" << MAI->getCommentString() << ' ';
1076 WriteAsOperand(O, FP, /*PrintType=*/false);
1080 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1082 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1084 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1085 O << "#0x" << utohexstr(Val);
1088 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1089 unsigned AsmVariant, const char *ExtraCode,
1091 // Does this asm operand have a single letter operand modifier?
1092 if (ExtraCode && ExtraCode[0]) {
1093 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1095 switch (ExtraCode[0]) {
1096 default: return true; // Unknown modifier.
1097 case 'a': // Print as a memory address.
1098 if (MI->getOperand(OpNum).isReg()) {
1099 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1103 case 'c': // Don't print "#" before an immediate operand.
1104 if (!MI->getOperand(OpNum).isImm())
1106 printNoHashImmediate(MI, OpNum, O);
1108 case 'P': // Print a VFP double precision register.
1109 case 'q': // Print a NEON quad precision register.
1110 printOperand(MI, OpNum, O);
1115 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1120 printOperand(MI, OpNum, O);
1124 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1125 unsigned OpNum, unsigned AsmVariant,
1126 const char *ExtraCode,
1128 if (ExtraCode && ExtraCode[0])
1129 return true; // Unknown modifier.
1131 const MachineOperand &MO = MI->getOperand(OpNum);
1132 assert(MO.isReg() && "unexpected inline asm memory operand");
1133 O << "[" << getRegisterName(MO.getReg()) << "]";
1137 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1139 printInstructionThroughMCStreamer(MI);
1143 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1146 SmallString<128> Str;
1147 raw_svector_ostream OS(Str);
1148 if (MI->getOpcode() == ARM::DBG_VALUE) {
1149 unsigned NOps = MI->getNumOperands();
1151 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1152 // cast away const; DIetc do not take const operands for some reason.
1153 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1156 // Frame address. Currently handles register +- offset only.
1157 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1158 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1161 printOperand(MI, NOps-2, OS);
1162 } else if (MI->getOpcode() == ARM::MOVs) {
1163 // FIXME: Thumb variants?
1164 const MachineOperand &Dst = MI->getOperand(0);
1165 const MachineOperand &MO1 = MI->getOperand(1);
1166 const MachineOperand &MO2 = MI->getOperand(2);
1167 const MachineOperand &MO3 = MI->getOperand(3);
1169 OS << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
1170 printSBitModifierOperand(MI, 6, OS);
1171 printPredicateOperand(MI, 4, OS);
1173 OS << '\t' << getRegisterName(Dst.getReg())
1174 << ", " << getRegisterName(MO1.getReg());
1176 if (ARM_AM::getSORegShOp(MO3.getImm()) != ARM_AM::rrx) {
1180 OS << getRegisterName(MO2.getReg());
1181 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
1183 OS << "#" << ARM_AM::getSORegOffset(MO3.getImm());
1188 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
1189 MI->getOperand(0).getReg() == ARM::SP &&
1190 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
1191 OS << '\t' << "push";
1192 printPredicateOperand(MI, 3, OS);
1194 printRegisterList(MI, 5, OS);
1197 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
1198 MI->getOperand(0).getReg() == ARM::SP &&
1199 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
1200 OS << '\t' << "pop";
1201 printPredicateOperand(MI, 3, OS);
1203 printRegisterList(MI, 5, OS);
1206 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
1207 MI->getOperand(0).getReg() == ARM::SP &&
1208 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::db) {
1209 OS << '\t' << "vpush";
1210 printPredicateOperand(MI, 3, OS);
1212 printRegisterList(MI, 5, OS);
1215 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
1216 MI->getOperand(0).getReg() == ARM::SP &&
1217 ARM_AM::getAM4SubMode(MI->getOperand(2).getImm()) == ARM_AM::ia) {
1218 OS << '\t' << "vpop";
1219 printPredicateOperand(MI, 3, OS);
1221 printRegisterList(MI, 5, OS);
1223 // TRAP and tTRAP need special handling for non-Darwin. The GNU binutils
1224 // don't (yet) support the 'trap' mnemonic. (Use decimal, not hex, to
1225 // be consistent with the MC instruction printer.)
1226 // FIXME: This really should be in AsmPrinter/ARMInstPrinter.cpp, not here.
1227 // Need a way to ask "isTargetDarwin()" there, first, though.
1228 if (MI->getOpcode() == ARM::TRAP && !Subtarget->isTargetDarwin()) {
1229 OS << "\t.long\t3892305662\t\t" << MAI->getCommentString() << "trap";
1230 } else if (MI->getOpcode() == ARM::tTRAP && !Subtarget->isTargetDarwin()) {
1231 OS << "\t.short\t57086\t\t\t" << MAI->getCommentString() << " trap";
1233 printInstruction(MI, OS);
1235 // Output the instruction to the stream
1236 OutStreamer.EmitRawText(OS.str());
1238 // Make sure the instruction that follows TBB is 2-byte aligned.
1239 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1240 if (MI->getOpcode() == ARM::t2TBB)
1244 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1245 if (Subtarget->isTargetDarwin()) {
1246 Reloc::Model RelocM = TM.getRelocationModel();
1247 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1248 // Declare all the text sections up front (before the DWARF sections
1249 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1250 // them together at the beginning of the object file. This helps
1251 // avoid out-of-range branches that are due a fundamental limitation of
1252 // the way symbol offsets are encoded with the current Darwin ARM
1254 const TargetLoweringObjectFileMachO &TLOFMacho =
1255 static_cast<const TargetLoweringObjectFileMachO &>(
1256 getObjFileLowering());
1257 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1258 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1259 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1260 if (RelocM == Reloc::DynamicNoPIC) {
1261 const MCSection *sect =
1262 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1263 MCSectionMachO::S_SYMBOL_STUBS,
1264 12, SectionKind::getText());
1265 OutStreamer.SwitchSection(sect);
1267 const MCSection *sect =
1268 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1269 MCSectionMachO::S_SYMBOL_STUBS,
1270 16, SectionKind::getText());
1271 OutStreamer.SwitchSection(sect);
1273 const MCSection *StaticInitSect =
1274 OutContext.getMachOSection("__TEXT", "__StaticInit",
1275 MCSectionMachO::S_REGULAR |
1276 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1277 SectionKind::getText());
1278 OutStreamer.SwitchSection(StaticInitSect);
1282 // Use unified assembler syntax.
1283 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1285 // Emit ARM Build Attributes
1286 if (Subtarget->isTargetELF()) {
1288 std::string CPUString = Subtarget->getCPUString();
1289 if (CPUString != "generic")
1290 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1292 // FIXME: Emit FPU type
1293 if (Subtarget->hasVFP2())
1294 OutStreamer.EmitRawText("\t.eabi_attribute " +
1295 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1297 // Signal various FP modes.
1298 if (!UnsafeFPMath) {
1299 OutStreamer.EmitRawText("\t.eabi_attribute " +
1300 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1301 OutStreamer.EmitRawText("\t.eabi_attribute " +
1302 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1305 if (NoInfsFPMath && NoNaNsFPMath)
1306 OutStreamer.EmitRawText("\t.eabi_attribute " +
1307 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1309 OutStreamer.EmitRawText("\t.eabi_attribute " +
1310 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1312 // 8-bytes alignment stuff.
1313 OutStreamer.EmitRawText("\t.eabi_attribute " +
1314 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1315 OutStreamer.EmitRawText("\t.eabi_attribute " +
1316 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1318 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1319 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1320 OutStreamer.EmitRawText("\t.eabi_attribute " +
1321 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1322 OutStreamer.EmitRawText("\t.eabi_attribute " +
1323 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1325 // FIXME: Should we signal R9 usage?
1330 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1331 if (Subtarget->isTargetDarwin()) {
1332 // All darwin targets use mach-o.
1333 const TargetLoweringObjectFileMachO &TLOFMacho =
1334 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1335 MachineModuleInfoMachO &MMIMacho =
1336 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1338 // Output non-lazy-pointers for external and common global variables.
1339 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1341 if (!Stubs.empty()) {
1342 // Switch with ".non_lazy_symbol_pointer" directive.
1343 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1345 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1347 OutStreamer.EmitLabel(Stubs[i].first);
1348 // .indirect_symbol _foo
1349 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1350 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1353 // External to current translation unit.
1354 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1356 // Internal to current translation unit.
1358 // When we place the LSDA into the TEXT section, the type info
1359 // pointers need to be indirect and pc-rel. We accomplish this by
1360 // using NLPs; however, sometimes the types are local to the file.
1361 // We need to fill in the value for the NLP in those cases.
1362 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1364 4/*size*/, 0/*addrspace*/);
1368 OutStreamer.AddBlankLine();
1371 Stubs = MMIMacho.GetHiddenGVStubList();
1372 if (!Stubs.empty()) {
1373 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1375 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1377 OutStreamer.EmitLabel(Stubs[i].first);
1379 OutStreamer.EmitValue(MCSymbolRefExpr::
1380 Create(Stubs[i].second.getPointer(),
1382 4/*size*/, 0/*addrspace*/);
1386 OutStreamer.AddBlankLine();
1389 // Funny Darwin hack: This flag tells the linker that no global symbols
1390 // contain code that falls through to other global symbols (e.g. the obvious
1391 // implementation of multiple entry points). If this doesn't occur, the
1392 // linker can safely perform dead code stripping. Since LLVM never
1393 // generates code that does this, it is always safe to set.
1394 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1398 //===----------------------------------------------------------------------===//
1400 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
1401 unsigned LabelId, MCContext &Ctx) {
1403 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
1404 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
1408 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
1409 unsigned Opcode = MI->getOpcode();
1411 if (Opcode == ARM::BR_JTadd)
1413 else if (Opcode == ARM::BR_JTm)
1416 const MachineOperand &MO1 = MI->getOperand(OpNum);
1417 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1418 unsigned JTI = MO1.getIndex();
1420 // Emit a label for the jump table.
1421 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1422 OutStreamer.EmitLabel(JTISymbol);
1424 // Emit each entry of the table.
1425 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1426 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1427 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1429 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1430 MachineBasicBlock *MBB = JTBBs[i];
1431 // Construct an MCExpr for the entry. We want a value of the form:
1432 // (BasicBlockAddr - TableBeginAddr)
1434 // For example, a table with entries jumping to basic blocks BB0 and BB1
1437 // .word (LBB0 - LJTI_0_0)
1438 // .word (LBB1 - LJTI_0_0)
1439 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1441 if (TM.getRelocationModel() == Reloc::PIC_)
1442 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1445 OutStreamer.EmitValue(Expr, 4);
1449 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1450 unsigned Opcode = MI->getOpcode();
1451 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1452 const MachineOperand &MO1 = MI->getOperand(OpNum);
1453 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1454 unsigned JTI = MO1.getIndex();
1456 // Emit a label for the jump table.
1457 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1458 OutStreamer.EmitLabel(JTISymbol);
1460 // Emit each entry of the table.
1461 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1462 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1463 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1464 unsigned OffsetWidth = 4;
1465 if (MI->getOpcode() == ARM::t2TBB)
1467 else if (MI->getOpcode() == ARM::t2TBH)
1470 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1471 MachineBasicBlock *MBB = JTBBs[i];
1472 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1474 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1475 if (OffsetWidth == 4) {
1477 BrInst.setOpcode(ARM::t2B);
1478 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1479 OutStreamer.EmitInstruction(BrInst);
1482 // Otherwise it's an offset from the dispatch instruction. Construct an
1483 // MCExpr for the entry. We want a value of the form:
1484 // (BasicBlockAddr - TableBeginAddr) / 2
1486 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1489 // .byte (LBB0 - LJTI_0_0) / 2
1490 // .byte (LBB1 - LJTI_0_0) / 2
1491 const MCExpr *Expr =
1492 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1493 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1495 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1497 OutStreamer.EmitValue(Expr, OffsetWidth);
1500 // Make sure the instruction that follows TBB is 2-byte aligned.
1501 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1502 if (MI->getOpcode() == ARM::t2TBB)
1506 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1507 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1508 switch (MI->getOpcode()) {
1509 case ARM::t2MOVi32imm:
1510 assert(0 && "Should be lowered by thumb2it pass");
1512 case ARM::tPICADD: {
1513 // This is a pseudo op for a label + instruction sequence, which looks like:
1516 // This adds the address of LPC0 to r0.
1519 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1520 getFunctionNumber(), MI->getOperand(2).getImm(),
1523 // Form and emit the add.
1525 AddInst.setOpcode(ARM::tADDhirr);
1526 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1527 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1528 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1529 // Add predicate operands.
1530 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1531 AddInst.addOperand(MCOperand::CreateReg(0));
1532 OutStreamer.EmitInstruction(AddInst);
1535 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1536 // This is a pseudo op for a label + instruction sequence, which looks like:
1539 // This adds the address of LPC0 to r0.
1542 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1543 getFunctionNumber(), MI->getOperand(2).getImm(),
1546 // Form and emit the add.
1548 AddInst.setOpcode(ARM::ADDrr);
1549 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1550 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1551 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1552 // Add predicate operands.
1553 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1554 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1555 // Add 's' bit operand (always reg0 for this)
1556 AddInst.addOperand(MCOperand::CreateReg(0));
1557 OutStreamer.EmitInstruction(AddInst);
1567 case ARM::PICLDRSH: {
1568 // This is a pseudo op for a label + instruction sequence, which looks like:
1571 // The LCP0 label is referenced by a constant pool entry in order to get
1572 // a PC-relative address at the ldr instruction.
1575 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1576 getFunctionNumber(), MI->getOperand(2).getImm(),
1579 // Form and emit the load
1581 switch (MI->getOpcode()) {
1583 llvm_unreachable("Unexpected opcode!");
1584 case ARM::PICSTR: Opcode = ARM::STR; break;
1585 case ARM::PICSTRB: Opcode = ARM::STRB; break;
1586 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1587 case ARM::PICLDR: Opcode = ARM::LDR; break;
1588 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
1589 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1590 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1591 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1594 LdStInst.setOpcode(Opcode);
1595 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1596 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1597 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1598 LdStInst.addOperand(MCOperand::CreateImm(0));
1599 // Add predicate operands.
1600 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1601 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1602 OutStreamer.EmitInstruction(LdStInst);
1606 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1607 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1608 /// in the function. The first operand is the ID# for this instruction, the
1609 /// second is the index into the MachineConstantPool that this is, the third
1610 /// is the size in bytes of this constant pool entry.
1611 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1612 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1615 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1617 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1618 if (MCPE.isMachineConstantPoolEntry())
1619 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1621 EmitGlobalConstant(MCPE.Val.ConstVal);
1625 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1626 // This is a hack that lowers as a two instruction sequence.
1627 unsigned DstReg = MI->getOperand(0).getReg();
1628 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1630 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1631 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1635 TmpInst.setOpcode(ARM::MOVi);
1636 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1637 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1640 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1641 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1643 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1644 OutStreamer.EmitInstruction(TmpInst);
1649 TmpInst.setOpcode(ARM::ORRri);
1650 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1651 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1652 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1654 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1655 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1657 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1658 OutStreamer.EmitInstruction(TmpInst);
1662 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1663 // This is a hack that lowers as a two instruction sequence.
1664 unsigned DstReg = MI->getOperand(0).getReg();
1665 const MachineOperand &MO = MI->getOperand(1);
1668 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1669 V1 = MCOperand::CreateImm(ImmVal & 65535);
1670 V2 = MCOperand::CreateImm(ImmVal >> 16);
1671 } else if (MO.isGlobal()) {
1672 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
1673 const MCSymbolRefExpr *SymRef1 =
1674 MCSymbolRefExpr::Create(Symbol,
1675 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1676 const MCSymbolRefExpr *SymRef2 =
1677 MCSymbolRefExpr::Create(Symbol,
1678 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1679 V1 = MCOperand::CreateExpr(SymRef1);
1680 V2 = MCOperand::CreateExpr(SymRef2);
1682 // FIXME: External symbol?
1684 llvm_unreachable("cannot handle this operand");
1689 TmpInst.setOpcode(ARM::MOVi16);
1690 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1691 TmpInst.addOperand(V1); // lower16(imm)
1694 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1695 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1697 OutStreamer.EmitInstruction(TmpInst);
1702 TmpInst.setOpcode(ARM::MOVTi16);
1703 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1704 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1705 TmpInst.addOperand(V2); // upper16(imm)
1708 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1709 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1711 OutStreamer.EmitInstruction(TmpInst);
1718 case ARM::t2BR_JT: {
1719 // Lower and emit the instruction itself, then the jump table following it.
1721 MCInstLowering.Lower(MI, TmpInst);
1722 OutStreamer.EmitInstruction(TmpInst);
1729 case ARM::BR_JTadd: {
1730 // Lower and emit the instruction itself, then the jump table following it.
1732 MCInstLowering.Lower(MI, TmpInst);
1733 OutStreamer.EmitInstruction(TmpInst);
1738 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1739 // FIXME: Remove this special case when they do.
1740 if (!Subtarget->isTargetDarwin()) {
1741 //.long 0xe7ffdefe ${:comment} trap
1742 uint32_t Val = 0xe7ffdefeUL;
1743 OutStreamer.AddComment("trap");
1744 OutStreamer.EmitIntValue(Val, 4);
1750 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1751 // FIXME: Remove this special case when they do.
1752 if (!Subtarget->isTargetDarwin()) {
1753 //.short 57086 ${:comment} trap
1754 uint16_t Val = 0xdefe;
1755 OutStreamer.AddComment("trap");
1756 OutStreamer.EmitIntValue(Val, 2);
1761 case ARM::t2Int_eh_sjlj_setjmp:
1762 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1763 case ARM::tInt_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
1764 // Two incoming args: GPR:$src, GPR:$val
1767 // str $val, [$src, #4]
1772 unsigned SrcReg = MI->getOperand(0).getReg();
1773 unsigned ValReg = MI->getOperand(1).getReg();
1774 MCSymbol *Label = GetARMSJLJEHLabel();
1777 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1778 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1779 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1781 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1782 OutStreamer.AddComment("eh_setjmp begin");
1783 OutStreamer.EmitInstruction(TmpInst);
1787 TmpInst.setOpcode(ARM::tADDi3);
1788 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1790 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1791 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1792 TmpInst.addOperand(MCOperand::CreateImm(7));
1794 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1795 TmpInst.addOperand(MCOperand::CreateReg(0));
1796 OutStreamer.EmitInstruction(TmpInst);
1800 TmpInst.setOpcode(ARM::tSTR);
1801 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1802 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1803 // The offset immediate is #4. The operand value is scaled by 4 for the
1804 // tSTR instruction.
1805 TmpInst.addOperand(MCOperand::CreateImm(1));
1806 TmpInst.addOperand(MCOperand::CreateReg(0));
1808 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1809 TmpInst.addOperand(MCOperand::CreateReg(0));
1810 OutStreamer.EmitInstruction(TmpInst);
1814 TmpInst.setOpcode(ARM::tMOVi8);
1815 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1816 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1817 TmpInst.addOperand(MCOperand::CreateImm(0));
1819 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1820 TmpInst.addOperand(MCOperand::CreateReg(0));
1821 OutStreamer.EmitInstruction(TmpInst);
1824 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1826 TmpInst.setOpcode(ARM::tB);
1827 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1828 OutStreamer.EmitInstruction(TmpInst);
1832 TmpInst.setOpcode(ARM::tMOVi8);
1833 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1834 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1835 TmpInst.addOperand(MCOperand::CreateImm(1));
1837 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1838 TmpInst.addOperand(MCOperand::CreateReg(0));
1839 OutStreamer.AddComment("eh_setjmp end");
1840 OutStreamer.EmitInstruction(TmpInst);
1842 OutStreamer.EmitLabel(Label);
1846 case ARM::Int_eh_sjlj_setjmp_nofp:
1847 case ARM::Int_eh_sjlj_setjmp: { // FIXME: Remove asmstring from td file.
1848 // Two incoming args: GPR:$src, GPR:$val
1850 // str $val, [$src, #+4]
1854 unsigned SrcReg = MI->getOperand(0).getReg();
1855 unsigned ValReg = MI->getOperand(1).getReg();
1859 TmpInst.setOpcode(ARM::ADDri);
1860 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1861 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1862 TmpInst.addOperand(MCOperand::CreateImm(8));
1864 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1865 TmpInst.addOperand(MCOperand::CreateReg(0));
1866 // 's' bit operand (always reg0 for this).
1867 TmpInst.addOperand(MCOperand::CreateReg(0));
1868 OutStreamer.AddComment("eh_setjmp begin");
1869 OutStreamer.EmitInstruction(TmpInst);
1873 TmpInst.setOpcode(ARM::STR);
1874 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1875 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1876 TmpInst.addOperand(MCOperand::CreateReg(0));
1877 TmpInst.addOperand(MCOperand::CreateImm(4));
1879 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1880 TmpInst.addOperand(MCOperand::CreateReg(0));
1881 OutStreamer.EmitInstruction(TmpInst);
1885 TmpInst.setOpcode(ARM::MOVi);
1886 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1887 TmpInst.addOperand(MCOperand::CreateImm(0));
1889 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1890 TmpInst.addOperand(MCOperand::CreateReg(0));
1891 // 's' bit operand (always reg0 for this).
1892 TmpInst.addOperand(MCOperand::CreateReg(0));
1893 OutStreamer.EmitInstruction(TmpInst);
1897 TmpInst.setOpcode(ARM::ADDri);
1898 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1899 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1900 TmpInst.addOperand(MCOperand::CreateImm(0));
1902 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1903 TmpInst.addOperand(MCOperand::CreateReg(0));
1904 // 's' bit operand (always reg0 for this).
1905 TmpInst.addOperand(MCOperand::CreateReg(0));
1906 OutStreamer.EmitInstruction(TmpInst);
1910 TmpInst.setOpcode(ARM::MOVi);
1911 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1912 TmpInst.addOperand(MCOperand::CreateImm(1));
1914 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1915 TmpInst.addOperand(MCOperand::CreateReg(0));
1916 // 's' bit operand (always reg0 for this).
1917 TmpInst.addOperand(MCOperand::CreateReg(0));
1918 OutStreamer.AddComment("eh_setjmp end");
1919 OutStreamer.EmitInstruction(TmpInst);
1926 MCInstLowering.Lower(MI, TmpInst);
1927 OutStreamer.EmitInstruction(TmpInst);
1930 //===----------------------------------------------------------------------===//
1931 // Target Registry Stuff
1932 //===----------------------------------------------------------------------===//
1934 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1935 unsigned SyntaxVariant,
1936 const MCAsmInfo &MAI) {
1937 if (SyntaxVariant == 0)
1938 return new ARMInstPrinter(MAI);
1942 // Force static initialization.
1943 extern "C" void LLVMInitializeARMAsmPrinter() {
1944 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1945 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1947 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1948 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);