1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/TargetRegistry.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 // This structure holds all attributes, accounting for
104 // their string/numeric value, so we can later emmit them
105 // in declaration order, keeping all in the same vector
106 struct AttributeItemType {
114 StringRef StringValue;
117 MCObjectStreamer &Streamer;
118 StringRef CurrentVendor;
119 SmallVector<AttributeItemType, 64> Contents;
121 // Account for the ULEB/String size of each item,
122 // not just the number of items
124 // FIXME: this should be in a more generic place, but
125 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
126 size_t getULEBSize(int Value) {
130 Size += sizeof(int8_t); // Is this really necessary?
136 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
137 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
139 void MaybeSwitchVendor(StringRef Vendor) {
140 assert(!Vendor.empty() && "Vendor cannot be empty.");
142 if (CurrentVendor.empty())
143 CurrentVendor = Vendor;
144 else if (CurrentVendor == Vendor)
149 CurrentVendor = Vendor;
151 assert(Contents.size() == 0);
154 void EmitAttribute(unsigned Attribute, unsigned Value) {
155 AttributeItemType attr = {
156 AttributeItemType::NumericAttribute,
161 ContentsSize += getULEBSize(Attribute);
162 ContentsSize += getULEBSize(Value);
163 Contents.push_back(attr);
166 void EmitTextAttribute(unsigned Attribute, StringRef String) {
167 AttributeItemType attr = {
168 AttributeItemType::TextAttribute,
173 ContentsSize += getULEBSize(Attribute);
175 ContentsSize += String.size()+1;
177 Contents.push_back(attr);
181 // Vendor size + Vendor name + '\0'
182 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
185 const size_t TagHeaderSize = 1 + 4;
187 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
188 Streamer.EmitBytes(CurrentVendor, 0);
189 Streamer.EmitIntValue(0, 1); // '\0'
191 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
192 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
194 // Size should have been accounted for already, now
195 // emit each field as its type (ULEB or String)
196 for (unsigned int i=0; i<Contents.size(); ++i) {
197 AttributeItemType item = Contents[i];
198 Streamer.EmitULEB128IntValue(item.Tag, 0);
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue, 0);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(UppercaseString(item.StringValue), 0);
205 Streamer.EmitIntValue(0, 1); // '\0'
208 assert(0 && "Invalid attribute type");
216 } // end of anonymous namespace
218 MachineLocation ARMAsmPrinter::
219 getDebugValueLocation(const MachineInstr *MI) const {
220 MachineLocation Location;
221 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
222 // Frame address. Currently handles register +- offset only.
223 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
224 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
226 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
231 /// EmitDwarfRegOp - Emit dwarf register operation.
232 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
233 const TargetRegisterInfo *RI = TM.getRegisterInfo();
234 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
235 AsmPrinter::EmitDwarfRegOp(MLoc);
237 unsigned Reg = MLoc.getReg();
238 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
239 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
240 // S registers are described as bit-pieces of a register
241 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
242 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
248 OutStreamer.AddComment("DW_OP_regx for S register");
249 EmitInt8(dwarf::DW_OP_regx);
251 OutStreamer.AddComment(Twine(SReg));
255 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
261 EmitInt8(dwarf::DW_OP_bit_piece);
265 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
266 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
267 // Q registers Q0-Q15 are described by composing two D registers together.
268 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
271 unsigned QReg = Reg - ARM::Q0;
272 unsigned D1 = 256 + 2 * QReg;
273 unsigned D2 = D1 + 1;
275 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
276 EmitInt8(dwarf::DW_OP_regx);
278 OutStreamer.AddComment("DW_OP_piece 8");
279 EmitInt8(dwarf::DW_OP_piece);
282 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
283 EmitInt8(dwarf::DW_OP_regx);
285 OutStreamer.AddComment("DW_OP_piece 8");
286 EmitInt8(dwarf::DW_OP_piece);
292 void ARMAsmPrinter::EmitFunctionEntryLabel() {
293 if (AFI->isThumbFunction()) {
294 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
295 OutStreamer.EmitThumbFunc(CurrentFnSym);
298 OutStreamer.EmitLabel(CurrentFnSym);
301 /// runOnMachineFunction - This uses the EmitInstruction()
302 /// method to print assembly for each instruction.
304 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
305 AFI = MF.getInfo<ARMFunctionInfo>();
306 MCP = MF.getConstantPool();
308 return AsmPrinter::runOnMachineFunction(MF);
311 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
312 raw_ostream &O, const char *Modifier) {
313 const MachineOperand &MO = MI->getOperand(OpNum);
314 unsigned TF = MO.getTargetFlags();
316 switch (MO.getType()) {
318 assert(0 && "<unknown operand type>");
319 case MachineOperand::MO_Register: {
320 unsigned Reg = MO.getReg();
321 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
322 assert(!MO.getSubReg() && "Subregs should be eliminated!");
323 O << ARMInstPrinter::getRegisterName(Reg);
326 case MachineOperand::MO_Immediate: {
327 int64_t Imm = MO.getImm();
329 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
330 (TF == ARMII::MO_LO16))
332 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
333 (TF == ARMII::MO_HI16))
338 case MachineOperand::MO_MachineBasicBlock:
339 O << *MO.getMBB()->getSymbol();
341 case MachineOperand::MO_GlobalAddress: {
342 const GlobalValue *GV = MO.getGlobal();
343 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
344 (TF & ARMII::MO_LO16))
346 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
347 (TF & ARMII::MO_HI16))
349 O << *Mang->getSymbol(GV);
351 printOffset(MO.getOffset(), O);
352 if (TF == ARMII::MO_PLT)
356 case MachineOperand::MO_ExternalSymbol: {
357 O << *GetExternalSymbolSymbol(MO.getSymbolName());
358 if (TF == ARMII::MO_PLT)
362 case MachineOperand::MO_ConstantPoolIndex:
363 O << *GetCPISymbol(MO.getIndex());
365 case MachineOperand::MO_JumpTableIndex:
366 O << *GetJTISymbol(MO.getIndex());
371 //===--------------------------------------------------------------------===//
373 MCSymbol *ARMAsmPrinter::
374 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
375 const MachineBasicBlock *MBB) const {
376 SmallString<60> Name;
377 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
378 << getFunctionNumber() << '_' << uid << '_' << uid2
379 << "_set_" << MBB->getNumber();
380 return OutContext.GetOrCreateSymbol(Name.str());
383 MCSymbol *ARMAsmPrinter::
384 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
385 SmallString<60> Name;
386 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
387 << getFunctionNumber() << '_' << uid << '_' << uid2;
388 return OutContext.GetOrCreateSymbol(Name.str());
392 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
393 SmallString<60> Name;
394 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
395 << getFunctionNumber();
396 return OutContext.GetOrCreateSymbol(Name.str());
399 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
400 unsigned AsmVariant, const char *ExtraCode,
402 // Does this asm operand have a single letter operand modifier?
403 if (ExtraCode && ExtraCode[0]) {
404 if (ExtraCode[1] != 0) return true; // Unknown modifier.
406 switch (ExtraCode[0]) {
407 default: return true; // Unknown modifier.
408 case 'a': // Print as a memory address.
409 if (MI->getOperand(OpNum).isReg()) {
411 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
416 case 'c': // Don't print "#" before an immediate operand.
417 if (!MI->getOperand(OpNum).isImm())
419 O << MI->getOperand(OpNum).getImm();
421 case 'P': // Print a VFP double precision register.
422 case 'q': // Print a NEON quad precision register.
423 printOperand(MI, OpNum, O);
425 case 'y': // Print a VFP single precision register as indexed double.
426 // This uses the ordering of the alias table to get the first 'd' register
427 // that overlaps the 's' register. Also, s0 is an odd register, hence the
428 // odd modulus check below.
429 if (MI->getOperand(OpNum).isReg()) {
430 unsigned Reg = MI->getOperand(OpNum).getReg();
431 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
432 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
433 (((Reg % 2) == 1) ? "[0]" : "[1]");
437 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
438 if (!MI->getOperand(OpNum).isImm())
440 O << ~(MI->getOperand(OpNum).getImm());
442 case 'L': // The low 16 bits of an immediate constant.
443 if (!MI->getOperand(OpNum).isImm())
445 O << (MI->getOperand(OpNum).getImm() & 0xffff);
447 case 'M': { // A register range suitable for LDM/STM.
448 if (!MI->getOperand(OpNum).isReg())
450 const MachineOperand &MO = MI->getOperand(OpNum);
451 unsigned RegBegin = MO.getReg();
452 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
453 // already got the operands in registers that are operands to the
454 // inline asm statement.
456 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
458 // FIXME: The register allocator not only may not have given us the
459 // registers in sequence, but may not be in ascending registers. This
460 // will require changes in the register allocator that'll need to be
461 // propagated down here if the operands change.
462 unsigned RegOps = OpNum + 1;
463 while (MI->getOperand(RegOps).isReg()) {
465 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
473 case 'R': // The most significant register of a pair.
474 case 'Q': { // The least significant register of a pair.
477 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
478 if (!FlagsOP.isImm())
480 unsigned Flags = FlagsOP.getImm();
481 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
484 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
485 if (RegOp >= MI->getNumOperands())
487 const MachineOperand &MO = MI->getOperand(RegOp);
490 unsigned Reg = MO.getReg();
491 O << ARMInstPrinter::getRegisterName(Reg);
495 // These modifiers are not yet supported.
496 case 'p': // The high single-precision register of a VFP double-precision
498 case 'e': // The low doubleword register of a NEON quad register.
499 case 'f': // The high doubleword register of a NEON quad register.
500 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
501 case 'H': // The highest-numbered register of a pair.
506 printOperand(MI, OpNum, O);
510 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
511 unsigned OpNum, unsigned AsmVariant,
512 const char *ExtraCode,
514 // Does this asm operand have a single letter operand modifier?
515 if (ExtraCode && ExtraCode[0]) {
516 if (ExtraCode[1] != 0) return true; // Unknown modifier.
518 switch (ExtraCode[0]) {
519 case 'A': // A memory operand for a VLD1/VST1 instruction.
520 default: return true; // Unknown modifier.
521 case 'm': // The base register of a memory operand.
522 if (!MI->getOperand(OpNum).isReg())
524 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
529 const MachineOperand &MO = MI->getOperand(OpNum);
530 assert(MO.isReg() && "unexpected inline asm memory operand");
531 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
535 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
536 if (Subtarget->isTargetDarwin()) {
537 Reloc::Model RelocM = TM.getRelocationModel();
538 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
539 // Declare all the text sections up front (before the DWARF sections
540 // emitted by AsmPrinter::doInitialization) so the assembler will keep
541 // them together at the beginning of the object file. This helps
542 // avoid out-of-range branches that are due a fundamental limitation of
543 // the way symbol offsets are encoded with the current Darwin ARM
545 const TargetLoweringObjectFileMachO &TLOFMacho =
546 static_cast<const TargetLoweringObjectFileMachO &>(
547 getObjFileLowering());
548 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
549 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
550 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
551 if (RelocM == Reloc::DynamicNoPIC) {
552 const MCSection *sect =
553 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
554 MCSectionMachO::S_SYMBOL_STUBS,
555 12, SectionKind::getText());
556 OutStreamer.SwitchSection(sect);
558 const MCSection *sect =
559 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
560 MCSectionMachO::S_SYMBOL_STUBS,
561 16, SectionKind::getText());
562 OutStreamer.SwitchSection(sect);
564 const MCSection *StaticInitSect =
565 OutContext.getMachOSection("__TEXT", "__StaticInit",
566 MCSectionMachO::S_REGULAR |
567 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
568 SectionKind::getText());
569 OutStreamer.SwitchSection(StaticInitSect);
573 // Use unified assembler syntax.
574 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
576 // Emit ARM Build Attributes
577 if (Subtarget->isTargetELF()) {
584 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
585 if (Subtarget->isTargetDarwin()) {
586 // All darwin targets use mach-o.
587 const TargetLoweringObjectFileMachO &TLOFMacho =
588 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
589 MachineModuleInfoMachO &MMIMacho =
590 MMI->getObjFileInfo<MachineModuleInfoMachO>();
592 // Output non-lazy-pointers for external and common global variables.
593 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
595 if (!Stubs.empty()) {
596 // Switch with ".non_lazy_symbol_pointer" directive.
597 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
599 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
601 OutStreamer.EmitLabel(Stubs[i].first);
602 // .indirect_symbol _foo
603 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
604 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
607 // External to current translation unit.
608 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
610 // Internal to current translation unit.
612 // When we place the LSDA into the TEXT section, the type info
613 // pointers need to be indirect and pc-rel. We accomplish this by
614 // using NLPs; however, sometimes the types are local to the file.
615 // We need to fill in the value for the NLP in those cases.
616 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
618 4/*size*/, 0/*addrspace*/);
622 OutStreamer.AddBlankLine();
625 Stubs = MMIMacho.GetHiddenGVStubList();
626 if (!Stubs.empty()) {
627 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
629 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
631 OutStreamer.EmitLabel(Stubs[i].first);
633 OutStreamer.EmitValue(MCSymbolRefExpr::
634 Create(Stubs[i].second.getPointer(),
636 4/*size*/, 0/*addrspace*/);
640 OutStreamer.AddBlankLine();
643 // Funny Darwin hack: This flag tells the linker that no global symbols
644 // contain code that falls through to other global symbols (e.g. the obvious
645 // implementation of multiple entry points). If this doesn't occur, the
646 // linker can safely perform dead code stripping. Since LLVM never
647 // generates code that does this, it is always safe to set.
648 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
652 //===----------------------------------------------------------------------===//
653 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
655 // The following seem like one-off assembler flags, but they actually need
656 // to appear in the .ARM.attributes section in ELF.
657 // Instead of subclassing the MCELFStreamer, we do the work here.
659 void ARMAsmPrinter::emitAttributes() {
661 emitARMAttributeSection();
663 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
664 bool emitFPU = false;
665 AttributeEmitter *AttrEmitter;
666 if (OutStreamer.hasRawTextSupport()) {
667 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
670 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
671 AttrEmitter = new ObjectAttributeEmitter(O);
674 AttrEmitter->MaybeSwitchVendor("aeabi");
676 std::string CPUString = Subtarget->getCPUString();
678 if (CPUString == "cortex-a8" ||
679 Subtarget->isCortexA8()) {
680 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
681 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
682 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
683 ARMBuildAttrs::ApplicationProfile);
684 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
685 ARMBuildAttrs::Allowed);
686 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
687 ARMBuildAttrs::AllowThumb32);
688 // Fixme: figure out when this is emitted.
689 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
690 // ARMBuildAttrs::AllowWMMXv1);
693 /// ADD additional Else-cases here!
694 } else if (CPUString == "xscale") {
695 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
696 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
697 ARMBuildAttrs::Allowed);
698 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
699 ARMBuildAttrs::Allowed);
700 } else if (CPUString == "generic") {
701 // FIXME: Why these defaults?
702 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
703 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
704 ARMBuildAttrs::Allowed);
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
706 ARMBuildAttrs::Allowed);
709 if (Subtarget->hasNEON() && emitFPU) {
710 /* NEON is not exactly a VFP architecture, but GAS emit one of
711 * neon/vfpv3/vfpv2 for .fpu parameters */
712 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
713 /* If emitted for NEON, omit from VFP below, since you can have both
714 * NEON and VFP in build attributes but only one .fpu */
719 if (Subtarget->hasVFP3()) {
720 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
721 ARMBuildAttrs::AllowFPv3A);
723 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
726 } else if (Subtarget->hasVFP2()) {
727 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
728 ARMBuildAttrs::AllowFPv2);
730 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
733 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
734 * since NEON can have 1 (allowed) or 2 (MAC operations) */
735 if (Subtarget->hasNEON()) {
736 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
737 ARMBuildAttrs::Allowed);
740 // Signal various FP modes.
742 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
743 ARMBuildAttrs::Allowed);
744 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
745 ARMBuildAttrs::Allowed);
748 if (NoInfsFPMath && NoNaNsFPMath)
749 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
750 ARMBuildAttrs::Allowed);
752 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
753 ARMBuildAttrs::AllowIEE754);
755 // FIXME: add more flags to ARMBuildAttrs.h
756 // 8-bytes alignment stuff.
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
758 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
760 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
761 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
762 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
763 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
765 // FIXME: Should we signal R9 usage?
767 if (Subtarget->hasDivide())
768 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
770 AttrEmitter->Finish();
774 void ARMAsmPrinter::emitARMAttributeSection() {
776 // [ <section-length> "vendor-name"
777 // [ <file-tag> <size> <attribute>*
778 // | <section-tag> <size> <section-number>* 0 <attribute>*
779 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
783 if (OutStreamer.hasRawTextSupport())
786 const ARMElfTargetObjectFile &TLOFELF =
787 static_cast<const ARMElfTargetObjectFile &>
788 (getObjFileLowering());
790 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
793 OutStreamer.EmitIntValue(0x41, 1);
796 //===----------------------------------------------------------------------===//
798 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
799 unsigned LabelId, MCContext &Ctx) {
801 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
802 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
806 static MCSymbolRefExpr::VariantKind
807 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
809 default: llvm_unreachable("Unknown modifier!");
810 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
811 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
812 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
813 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
814 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
815 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
817 return MCSymbolRefExpr::VK_None;
820 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
821 bool isIndirect = Subtarget->isTargetDarwin() &&
822 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
824 return Mang->getSymbol(GV);
826 // FIXME: Remove this when Darwin transition to @GOT like syntax.
827 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
828 MachineModuleInfoMachO &MMIMachO =
829 MMI->getObjFileInfo<MachineModuleInfoMachO>();
830 MachineModuleInfoImpl::StubValueTy &StubSym =
831 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
832 MMIMachO.getGVStubEntry(MCSym);
833 if (StubSym.getPointer() == 0)
834 StubSym = MachineModuleInfoImpl::
835 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
840 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
841 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
843 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
846 if (ACPV->isLSDA()) {
847 SmallString<128> Str;
848 raw_svector_ostream OS(Str);
849 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
850 MCSym = OutContext.GetOrCreateSymbol(OS.str());
851 } else if (ACPV->isBlockAddress()) {
852 const BlockAddress *BA =
853 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
854 MCSym = GetBlockAddressSymbol(BA);
855 } else if (ACPV->isGlobalValue()) {
856 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
857 MCSym = GetARMGVSymbol(GV);
858 } else if (ACPV->isMachineBasicBlock()) {
859 const MachineBasicBlock *MBB = ACPV->getMBB();
860 MCSym = MBB->getSymbol();
862 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
863 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
866 // Create an MCSymbol for the reference.
868 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
871 if (ACPV->getPCAdjustment()) {
872 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
876 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
878 MCBinaryExpr::CreateAdd(PCRelExpr,
879 MCConstantExpr::Create(ACPV->getPCAdjustment(),
882 if (ACPV->mustAddCurrentAddress()) {
883 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
884 // label, so just emit a local label end reference that instead.
885 MCSymbol *DotSym = OutContext.CreateTempSymbol();
886 OutStreamer.EmitLabel(DotSym);
887 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
888 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
890 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
892 OutStreamer.EmitValue(Expr, Size);
895 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
896 unsigned Opcode = MI->getOpcode();
898 if (Opcode == ARM::BR_JTadd)
900 else if (Opcode == ARM::BR_JTm)
903 const MachineOperand &MO1 = MI->getOperand(OpNum);
904 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
905 unsigned JTI = MO1.getIndex();
907 // Emit a label for the jump table.
908 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
909 OutStreamer.EmitLabel(JTISymbol);
911 // Emit each entry of the table.
912 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
913 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
914 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
916 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
917 MachineBasicBlock *MBB = JTBBs[i];
918 // Construct an MCExpr for the entry. We want a value of the form:
919 // (BasicBlockAddr - TableBeginAddr)
921 // For example, a table with entries jumping to basic blocks BB0 and BB1
924 // .word (LBB0 - LJTI_0_0)
925 // .word (LBB1 - LJTI_0_0)
926 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
928 if (TM.getRelocationModel() == Reloc::PIC_)
929 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
932 // If we're generating a table of Thumb addresses in static relocation
933 // model, we need to add one to keep interworking correctly.
934 else if (AFI->isThumbFunction())
935 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
937 OutStreamer.EmitValue(Expr, 4);
941 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
942 unsigned Opcode = MI->getOpcode();
943 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
944 const MachineOperand &MO1 = MI->getOperand(OpNum);
945 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
946 unsigned JTI = MO1.getIndex();
948 // Emit a label for the jump table.
949 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
950 OutStreamer.EmitLabel(JTISymbol);
952 // Emit each entry of the table.
953 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
954 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
955 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
956 unsigned OffsetWidth = 4;
957 if (MI->getOpcode() == ARM::t2TBB_JT)
959 else if (MI->getOpcode() == ARM::t2TBH_JT)
962 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
963 MachineBasicBlock *MBB = JTBBs[i];
964 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
966 // If this isn't a TBB or TBH, the entries are direct branch instructions.
967 if (OffsetWidth == 4) {
969 BrInst.setOpcode(ARM::t2B);
970 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
971 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
972 BrInst.addOperand(MCOperand::CreateReg(0));
973 OutStreamer.EmitInstruction(BrInst);
976 // Otherwise it's an offset from the dispatch instruction. Construct an
977 // MCExpr for the entry. We want a value of the form:
978 // (BasicBlockAddr - TableBeginAddr) / 2
980 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
983 // .byte (LBB0 - LJTI_0_0) / 2
984 // .byte (LBB1 - LJTI_0_0) / 2
986 MCBinaryExpr::CreateSub(MBBSymbolExpr,
987 MCSymbolRefExpr::Create(JTISymbol, OutContext),
989 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
991 OutStreamer.EmitValue(Expr, OffsetWidth);
995 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
997 unsigned NOps = MI->getNumOperands();
999 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1000 // cast away const; DIetc do not take const operands for some reason.
1001 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1004 // Frame address. Currently handles register +- offset only.
1005 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1006 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1009 printOperand(MI, NOps-2, OS);
1012 static void populateADROperands(MCInst &Inst, unsigned Dest,
1013 const MCSymbol *Label,
1014 unsigned pred, unsigned ccreg,
1016 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1017 Inst.addOperand(MCOperand::CreateReg(Dest));
1018 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1019 // Add predicate operands.
1020 Inst.addOperand(MCOperand::CreateImm(pred));
1021 Inst.addOperand(MCOperand::CreateReg(ccreg));
1024 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1028 // Emit the instruction as usual, just patch the opcode.
1029 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1030 TmpInst.setOpcode(Opcode);
1031 OutStreamer.EmitInstruction(TmpInst);
1034 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1035 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1036 "Only instruction which are involved into frame setup code are allowed");
1038 const MachineFunction &MF = *MI->getParent()->getParent();
1039 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1040 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1042 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1043 unsigned Opc = MI->getOpcode();
1044 unsigned SrcReg, DstReg;
1046 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1047 // Two special cases:
1048 // 1) tPUSH does not have src/dst regs.
1049 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1050 // load. Yes, this is pretty fragile, but for now I don't see better
1052 SrcReg = DstReg = ARM::SP;
1054 SrcReg = MI->getOperand(1).getReg();
1055 DstReg = MI->getOperand(0).getReg();
1058 // Try to figure out the unwinding opcode out of src / dst regs.
1059 if (MI->getDesc().mayStore()) {
1061 assert(DstReg == ARM::SP &&
1062 "Only stack pointer as a destination reg is supported");
1064 SmallVector<unsigned, 4> RegList;
1065 // Skip src & dst reg, and pred ops.
1066 unsigned StartOp = 2 + 2;
1067 // Use all the operands.
1068 unsigned NumOffset = 0;
1073 assert(0 && "Unsupported opcode for unwinding information");
1075 // Special case here: no src & dst reg, but two extra imp ops.
1076 StartOp = 2; NumOffset = 2;
1077 case ARM::STMDB_UPD:
1078 case ARM::t2STMDB_UPD:
1079 case ARM::VSTMDDB_UPD:
1080 assert(SrcReg == ARM::SP &&
1081 "Only stack pointer as a source reg is supported");
1082 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1084 RegList.push_back(MI->getOperand(i).getReg());
1086 case ARM::STR_PRE_IMM:
1087 case ARM::STR_PRE_REG:
1088 assert(MI->getOperand(2).getReg() == ARM::SP &&
1089 "Only stack pointer as a source reg is supported");
1090 RegList.push_back(SrcReg);
1093 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1095 // Changes of stack / frame pointer.
1096 if (SrcReg == ARM::SP) {
1101 assert(0 && "Unsupported opcode for unwinding information");
1106 Offset = -MI->getOperand(2).getImm();
1109 Offset = MI->getOperand(2).getImm();
1112 Offset = MI->getOperand(2).getImm()*4;
1116 Offset = -MI->getOperand(2).getImm()*4;
1118 case ARM::tLDRpci: {
1119 // Grab the constpool index and check, whether it corresponds to
1120 // original or cloned constpool entry.
1121 unsigned CPI = MI->getOperand(1).getIndex();
1122 const MachineConstantPool *MCP = MF.getConstantPool();
1123 if (CPI >= MCP->getConstants().size())
1124 CPI = AFI.getOriginalCPIdx(CPI);
1125 assert(CPI != -1U && "Invalid constpool index");
1127 // Derive the actual offset.
1128 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1129 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1130 // FIXME: Check for user, it should be "add" instruction!
1131 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1136 if (DstReg == FramePtr && FramePtr != ARM::SP)
1137 // Set-up of the frame pointer. Positive values correspond to "add"
1139 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1140 else if (DstReg == ARM::SP) {
1141 // Change of SP by an offset. Positive values correspond to "sub"
1143 OutStreamer.EmitPad(Offset);
1146 assert(0 && "Unsupported opcode for unwinding information");
1148 } else if (DstReg == ARM::SP) {
1149 // FIXME: .movsp goes here
1151 assert(0 && "Unsupported opcode for unwinding information");
1155 assert(0 && "Unsupported opcode for unwinding information");
1160 extern cl::opt<bool> EnableARMEHABI;
1162 // Simple pseudo-instructions have their lowering (with expansion to real
1163 // instructions) auto-generated.
1164 #include "ARMGenMCPseudoLowering.inc"
1166 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1167 // Emit unwinding stuff for frame-related instructions
1168 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1169 EmitUnwindingInstruction(MI);
1171 // Do any auto-generated pseudo lowerings.
1172 if (emitPseudoExpansionLowering(OutStreamer, MI))
1175 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1176 "Pseudo flag setting opcode should be expanded early");
1178 // Check for manual lowerings.
1179 unsigned Opc = MI->getOpcode();
1181 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1182 case ARM::DBG_VALUE: {
1183 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1184 SmallString<128> TmpStr;
1185 raw_svector_ostream OS(TmpStr);
1186 PrintDebugValueComment(MI, OS);
1187 OutStreamer.EmitRawText(StringRef(OS.str()));
1192 case ARM::tLEApcrel:
1193 case ARM::t2LEApcrel: {
1194 // FIXME: Need to also handle globals and externals
1196 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1197 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1199 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1200 GetCPISymbol(MI->getOperand(1).getIndex()),
1201 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1203 OutStreamer.EmitInstruction(TmpInst);
1206 case ARM::LEApcrelJT:
1207 case ARM::tLEApcrelJT:
1208 case ARM::t2LEApcrelJT: {
1210 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1211 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1213 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1214 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1215 MI->getOperand(2).getImm()),
1216 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1218 OutStreamer.EmitInstruction(TmpInst);
1221 // Darwin call instructions are just normal call instructions with different
1222 // clobber semantics (they clobber R9).
1223 case ARM::BXr9_CALL:
1224 case ARM::BX_CALL: {
1227 TmpInst.setOpcode(ARM::MOVr);
1228 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1229 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1230 // Add predicate operands.
1231 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1232 TmpInst.addOperand(MCOperand::CreateReg(0));
1233 // Add 's' bit operand (always reg0 for this)
1234 TmpInst.addOperand(MCOperand::CreateReg(0));
1235 OutStreamer.EmitInstruction(TmpInst);
1239 TmpInst.setOpcode(ARM::BX);
1240 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1241 OutStreamer.EmitInstruction(TmpInst);
1245 case ARM::tBXr9_CALL:
1246 case ARM::tBX_CALL: {
1249 TmpInst.setOpcode(ARM::tMOVr);
1250 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1251 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1252 // Add predicate operands.
1253 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1254 TmpInst.addOperand(MCOperand::CreateReg(0));
1255 OutStreamer.EmitInstruction(TmpInst);
1259 TmpInst.setOpcode(ARM::tBX);
1260 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1261 // Add predicate operands.
1262 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1263 TmpInst.addOperand(MCOperand::CreateReg(0));
1264 OutStreamer.EmitInstruction(TmpInst);
1268 case ARM::BMOVPCRXr9_CALL:
1269 case ARM::BMOVPCRX_CALL: {
1272 TmpInst.setOpcode(ARM::MOVr);
1273 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1274 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1275 // Add predicate operands.
1276 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1277 TmpInst.addOperand(MCOperand::CreateReg(0));
1278 // Add 's' bit operand (always reg0 for this)
1279 TmpInst.addOperand(MCOperand::CreateReg(0));
1280 OutStreamer.EmitInstruction(TmpInst);
1284 TmpInst.setOpcode(ARM::MOVr);
1285 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1286 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1287 // Add predicate operands.
1288 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1289 TmpInst.addOperand(MCOperand::CreateReg(0));
1290 // Add 's' bit operand (always reg0 for this)
1291 TmpInst.addOperand(MCOperand::CreateReg(0));
1292 OutStreamer.EmitInstruction(TmpInst);
1296 case ARM::MOVi16_ga_pcrel:
1297 case ARM::t2MOVi16_ga_pcrel: {
1299 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1300 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1302 unsigned TF = MI->getOperand(1).getTargetFlags();
1303 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1304 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1305 MCSymbol *GVSym = GetARMGVSymbol(GV);
1306 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1308 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1309 getFunctionNumber(),
1310 MI->getOperand(2).getImm(), OutContext);
1311 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1312 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1313 const MCExpr *PCRelExpr =
1314 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1315 MCBinaryExpr::CreateAdd(LabelSymExpr,
1316 MCConstantExpr::Create(PCAdj, OutContext),
1317 OutContext), OutContext), OutContext);
1318 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1320 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1321 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1324 // Add predicate operands.
1325 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1326 TmpInst.addOperand(MCOperand::CreateReg(0));
1327 // Add 's' bit operand (always reg0 for this)
1328 TmpInst.addOperand(MCOperand::CreateReg(0));
1329 OutStreamer.EmitInstruction(TmpInst);
1332 case ARM::MOVTi16_ga_pcrel:
1333 case ARM::t2MOVTi16_ga_pcrel: {
1335 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1336 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1337 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1338 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1340 unsigned TF = MI->getOperand(2).getTargetFlags();
1341 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1342 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1343 MCSymbol *GVSym = GetARMGVSymbol(GV);
1344 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1346 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1347 getFunctionNumber(),
1348 MI->getOperand(3).getImm(), OutContext);
1349 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1350 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1351 const MCExpr *PCRelExpr =
1352 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1353 MCBinaryExpr::CreateAdd(LabelSymExpr,
1354 MCConstantExpr::Create(PCAdj, OutContext),
1355 OutContext), OutContext), OutContext);
1356 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1358 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1359 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1361 // Add predicate operands.
1362 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1363 TmpInst.addOperand(MCOperand::CreateReg(0));
1364 // Add 's' bit operand (always reg0 for this)
1365 TmpInst.addOperand(MCOperand::CreateReg(0));
1366 OutStreamer.EmitInstruction(TmpInst);
1369 case ARM::tPICADD: {
1370 // This is a pseudo op for a label + instruction sequence, which looks like:
1373 // This adds the address of LPC0 to r0.
1376 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1377 getFunctionNumber(), MI->getOperand(2).getImm(),
1380 // Form and emit the add.
1382 AddInst.setOpcode(ARM::tADDhirr);
1383 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1384 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1385 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1386 // Add predicate operands.
1387 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1388 AddInst.addOperand(MCOperand::CreateReg(0));
1389 OutStreamer.EmitInstruction(AddInst);
1393 // This is a pseudo op for a label + instruction sequence, which looks like:
1396 // This adds the address of LPC0 to r0.
1399 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1400 getFunctionNumber(), MI->getOperand(2).getImm(),
1403 // Form and emit the add.
1405 AddInst.setOpcode(ARM::ADDrr);
1406 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1407 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1408 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1409 // Add predicate operands.
1410 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1411 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1412 // Add 's' bit operand (always reg0 for this)
1413 AddInst.addOperand(MCOperand::CreateReg(0));
1414 OutStreamer.EmitInstruction(AddInst);
1424 case ARM::PICLDRSH: {
1425 // This is a pseudo op for a label + instruction sequence, which looks like:
1428 // The LCP0 label is referenced by a constant pool entry in order to get
1429 // a PC-relative address at the ldr instruction.
1432 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1433 getFunctionNumber(), MI->getOperand(2).getImm(),
1436 // Form and emit the load
1438 switch (MI->getOpcode()) {
1440 llvm_unreachable("Unexpected opcode!");
1441 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1442 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1443 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1444 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1445 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1446 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1447 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1448 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1451 LdStInst.setOpcode(Opcode);
1452 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1453 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1454 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1455 LdStInst.addOperand(MCOperand::CreateImm(0));
1456 // Add predicate operands.
1457 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1458 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1459 OutStreamer.EmitInstruction(LdStInst);
1463 case ARM::CONSTPOOL_ENTRY: {
1464 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1465 /// in the function. The first operand is the ID# for this instruction, the
1466 /// second is the index into the MachineConstantPool that this is, the third
1467 /// is the size in bytes of this constant pool entry.
1468 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1469 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1472 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1474 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1475 if (MCPE.isMachineConstantPoolEntry())
1476 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1478 EmitGlobalConstant(MCPE.Val.ConstVal);
1482 case ARM::t2BR_JT: {
1483 // Lower and emit the instruction itself, then the jump table following it.
1485 TmpInst.setOpcode(ARM::tMOVr);
1486 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1487 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1488 // Add predicate operands.
1489 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1490 TmpInst.addOperand(MCOperand::CreateReg(0));
1491 OutStreamer.EmitInstruction(TmpInst);
1492 // Output the data for the jump table itself
1496 case ARM::t2TBB_JT: {
1497 // Lower and emit the instruction itself, then the jump table following it.
1500 TmpInst.setOpcode(ARM::t2TBB);
1501 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1502 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1503 // Add predicate operands.
1504 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1505 TmpInst.addOperand(MCOperand::CreateReg(0));
1506 OutStreamer.EmitInstruction(TmpInst);
1507 // Output the data for the jump table itself
1509 // Make sure the next instruction is 2-byte aligned.
1513 case ARM::t2TBH_JT: {
1514 // Lower and emit the instruction itself, then the jump table following it.
1517 TmpInst.setOpcode(ARM::t2TBH);
1518 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1519 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1520 // Add predicate operands.
1521 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1522 TmpInst.addOperand(MCOperand::CreateReg(0));
1523 OutStreamer.EmitInstruction(TmpInst);
1524 // Output the data for the jump table itself
1530 // Lower and emit the instruction itself, then the jump table following it.
1533 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1534 ARM::MOVr : ARM::tMOVr;
1535 TmpInst.setOpcode(Opc);
1536 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1537 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1538 // Add predicate operands.
1539 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1540 TmpInst.addOperand(MCOperand::CreateReg(0));
1541 // Add 's' bit operand (always reg0 for this)
1542 if (Opc == ARM::MOVr)
1543 TmpInst.addOperand(MCOperand::CreateReg(0));
1544 OutStreamer.EmitInstruction(TmpInst);
1546 // Make sure the Thumb jump table is 4-byte aligned.
1547 if (Opc == ARM::tMOVr)
1550 // Output the data for the jump table itself
1555 // Lower and emit the instruction itself, then the jump table following it.
1558 if (MI->getOperand(1).getReg() == 0) {
1560 TmpInst.setOpcode(ARM::LDRi12);
1561 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1562 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1563 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1565 TmpInst.setOpcode(ARM::LDRrs);
1566 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1567 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1568 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1569 TmpInst.addOperand(MCOperand::CreateImm(0));
1571 // Add predicate operands.
1572 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1573 TmpInst.addOperand(MCOperand::CreateReg(0));
1574 OutStreamer.EmitInstruction(TmpInst);
1576 // Output the data for the jump table itself
1580 case ARM::BR_JTadd: {
1581 // Lower and emit the instruction itself, then the jump table following it.
1582 // add pc, target, idx
1584 TmpInst.setOpcode(ARM::ADDrr);
1585 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1586 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1587 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1588 // Add predicate operands.
1589 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1590 TmpInst.addOperand(MCOperand::CreateReg(0));
1591 // Add 's' bit operand (always reg0 for this)
1592 TmpInst.addOperand(MCOperand::CreateReg(0));
1593 OutStreamer.EmitInstruction(TmpInst);
1595 // Output the data for the jump table itself
1600 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1601 // FIXME: Remove this special case when they do.
1602 if (!Subtarget->isTargetDarwin()) {
1603 //.long 0xe7ffdefe @ trap
1604 uint32_t Val = 0xe7ffdefeUL;
1605 OutStreamer.AddComment("trap");
1606 OutStreamer.EmitIntValue(Val, 4);
1612 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1613 // FIXME: Remove this special case when they do.
1614 if (!Subtarget->isTargetDarwin()) {
1615 //.short 57086 @ trap
1616 uint16_t Val = 0xdefe;
1617 OutStreamer.AddComment("trap");
1618 OutStreamer.EmitIntValue(Val, 2);
1623 case ARM::t2Int_eh_sjlj_setjmp:
1624 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1625 case ARM::tInt_eh_sjlj_setjmp: {
1626 // Two incoming args: GPR:$src, GPR:$val
1629 // str $val, [$src, #4]
1634 unsigned SrcReg = MI->getOperand(0).getReg();
1635 unsigned ValReg = MI->getOperand(1).getReg();
1636 MCSymbol *Label = GetARMSJLJEHLabel();
1639 TmpInst.setOpcode(ARM::tMOVr);
1640 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1641 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1643 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1644 TmpInst.addOperand(MCOperand::CreateReg(0));
1645 OutStreamer.AddComment("eh_setjmp begin");
1646 OutStreamer.EmitInstruction(TmpInst);
1650 TmpInst.setOpcode(ARM::tADDi3);
1651 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1653 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1654 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1655 TmpInst.addOperand(MCOperand::CreateImm(7));
1657 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1658 TmpInst.addOperand(MCOperand::CreateReg(0));
1659 OutStreamer.EmitInstruction(TmpInst);
1663 TmpInst.setOpcode(ARM::tSTRi);
1664 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1665 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1666 // The offset immediate is #4. The operand value is scaled by 4 for the
1667 // tSTR instruction.
1668 TmpInst.addOperand(MCOperand::CreateImm(1));
1670 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1671 TmpInst.addOperand(MCOperand::CreateReg(0));
1672 OutStreamer.EmitInstruction(TmpInst);
1676 TmpInst.setOpcode(ARM::tMOVi8);
1677 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1678 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1679 TmpInst.addOperand(MCOperand::CreateImm(0));
1681 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1682 TmpInst.addOperand(MCOperand::CreateReg(0));
1683 OutStreamer.EmitInstruction(TmpInst);
1686 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1688 TmpInst.setOpcode(ARM::tB);
1689 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1690 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1691 TmpInst.addOperand(MCOperand::CreateReg(0));
1692 OutStreamer.EmitInstruction(TmpInst);
1696 TmpInst.setOpcode(ARM::tMOVi8);
1697 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1698 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1699 TmpInst.addOperand(MCOperand::CreateImm(1));
1701 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1702 TmpInst.addOperand(MCOperand::CreateReg(0));
1703 OutStreamer.AddComment("eh_setjmp end");
1704 OutStreamer.EmitInstruction(TmpInst);
1706 OutStreamer.EmitLabel(Label);
1710 case ARM::Int_eh_sjlj_setjmp_nofp:
1711 case ARM::Int_eh_sjlj_setjmp: {
1712 // Two incoming args: GPR:$src, GPR:$val
1714 // str $val, [$src, #+4]
1718 unsigned SrcReg = MI->getOperand(0).getReg();
1719 unsigned ValReg = MI->getOperand(1).getReg();
1723 TmpInst.setOpcode(ARM::ADDri);
1724 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1725 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1726 TmpInst.addOperand(MCOperand::CreateImm(8));
1728 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1729 TmpInst.addOperand(MCOperand::CreateReg(0));
1730 // 's' bit operand (always reg0 for this).
1731 TmpInst.addOperand(MCOperand::CreateReg(0));
1732 OutStreamer.AddComment("eh_setjmp begin");
1733 OutStreamer.EmitInstruction(TmpInst);
1737 TmpInst.setOpcode(ARM::STRi12);
1738 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1739 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1740 TmpInst.addOperand(MCOperand::CreateImm(4));
1742 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1743 TmpInst.addOperand(MCOperand::CreateReg(0));
1744 OutStreamer.EmitInstruction(TmpInst);
1748 TmpInst.setOpcode(ARM::MOVi);
1749 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1750 TmpInst.addOperand(MCOperand::CreateImm(0));
1752 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1753 TmpInst.addOperand(MCOperand::CreateReg(0));
1754 // 's' bit operand (always reg0 for this).
1755 TmpInst.addOperand(MCOperand::CreateReg(0));
1756 OutStreamer.EmitInstruction(TmpInst);
1760 TmpInst.setOpcode(ARM::ADDri);
1761 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1762 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1763 TmpInst.addOperand(MCOperand::CreateImm(0));
1765 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1766 TmpInst.addOperand(MCOperand::CreateReg(0));
1767 // 's' bit operand (always reg0 for this).
1768 TmpInst.addOperand(MCOperand::CreateReg(0));
1769 OutStreamer.EmitInstruction(TmpInst);
1773 TmpInst.setOpcode(ARM::MOVi);
1774 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1775 TmpInst.addOperand(MCOperand::CreateImm(1));
1777 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1778 TmpInst.addOperand(MCOperand::CreateReg(0));
1779 // 's' bit operand (always reg0 for this).
1780 TmpInst.addOperand(MCOperand::CreateReg(0));
1781 OutStreamer.AddComment("eh_setjmp end");
1782 OutStreamer.EmitInstruction(TmpInst);
1786 case ARM::Int_eh_sjlj_longjmp: {
1787 // ldr sp, [$src, #8]
1788 // ldr $scratch, [$src, #4]
1791 unsigned SrcReg = MI->getOperand(0).getReg();
1792 unsigned ScratchReg = MI->getOperand(1).getReg();
1795 TmpInst.setOpcode(ARM::LDRi12);
1796 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1797 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1798 TmpInst.addOperand(MCOperand::CreateImm(8));
1800 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1801 TmpInst.addOperand(MCOperand::CreateReg(0));
1802 OutStreamer.EmitInstruction(TmpInst);
1806 TmpInst.setOpcode(ARM::LDRi12);
1807 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1808 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1809 TmpInst.addOperand(MCOperand::CreateImm(4));
1811 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1812 TmpInst.addOperand(MCOperand::CreateReg(0));
1813 OutStreamer.EmitInstruction(TmpInst);
1817 TmpInst.setOpcode(ARM::LDRi12);
1818 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1819 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1820 TmpInst.addOperand(MCOperand::CreateImm(0));
1822 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1823 TmpInst.addOperand(MCOperand::CreateReg(0));
1824 OutStreamer.EmitInstruction(TmpInst);
1828 TmpInst.setOpcode(ARM::BX);
1829 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1831 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1832 TmpInst.addOperand(MCOperand::CreateReg(0));
1833 OutStreamer.EmitInstruction(TmpInst);
1837 case ARM::tInt_eh_sjlj_longjmp: {
1838 // ldr $scratch, [$src, #8]
1840 // ldr $scratch, [$src, #4]
1843 unsigned SrcReg = MI->getOperand(0).getReg();
1844 unsigned ScratchReg = MI->getOperand(1).getReg();
1847 TmpInst.setOpcode(ARM::tLDRi);
1848 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1849 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1850 // The offset immediate is #8. The operand value is scaled by 4 for the
1851 // tLDR instruction.
1852 TmpInst.addOperand(MCOperand::CreateImm(2));
1854 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1855 TmpInst.addOperand(MCOperand::CreateReg(0));
1856 OutStreamer.EmitInstruction(TmpInst);
1860 TmpInst.setOpcode(ARM::tMOVr);
1861 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1862 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1864 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1865 TmpInst.addOperand(MCOperand::CreateReg(0));
1866 OutStreamer.EmitInstruction(TmpInst);
1870 TmpInst.setOpcode(ARM::tLDRi);
1871 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1872 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1873 TmpInst.addOperand(MCOperand::CreateImm(1));
1875 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1876 TmpInst.addOperand(MCOperand::CreateReg(0));
1877 OutStreamer.EmitInstruction(TmpInst);
1881 TmpInst.setOpcode(ARM::tLDRr);
1882 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1883 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1884 TmpInst.addOperand(MCOperand::CreateReg(0));
1886 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1887 TmpInst.addOperand(MCOperand::CreateReg(0));
1888 OutStreamer.EmitInstruction(TmpInst);
1892 TmpInst.setOpcode(ARM::tBX);
1893 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1895 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1896 TmpInst.addOperand(MCOperand::CreateReg(0));
1897 OutStreamer.EmitInstruction(TmpInst);
1904 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1906 OutStreamer.EmitInstruction(TmpInst);
1909 //===----------------------------------------------------------------------===//
1910 // Target Registry Stuff
1911 //===----------------------------------------------------------------------===//
1913 // Force static initialization.
1914 extern "C" void LLVMInitializeARMAsmPrinter() {
1915 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1916 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);