1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "AsmPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/raw_ostream.h"
56 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
57 cl::desc("enable experimental asmprinter gunk in the arm backend"));
69 class ARMAsmPrinter : public AsmPrinter {
71 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
72 /// make the right decision when printing asm code for different targets.
73 const ARMSubtarget *Subtarget;
75 /// AFI - Keep a pointer to ARMFunctionInfo for the current
79 /// MCP - Keep a pointer to constantpool entries of the current
81 const MachineConstantPool *MCP;
84 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
85 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
86 Subtarget = &TM.getSubtarget<ARMSubtarget>();
89 virtual const char *getPassName() const {
90 return "ARM Assembly Printer";
93 void printInstructionThroughMCStreamer(const MachineInstr *MI);
96 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
97 const char *Modifier = 0);
98 void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
99 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
101 void printSORegOperand(const MachineInstr *MI, int OpNum,
103 void printAddrMode2Operand(const MachineInstr *MI, int OpNum,
105 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum,
107 void printAddrMode3Operand(const MachineInstr *MI, int OpNum,
109 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum,
111 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
112 const char *Modifier = 0);
113 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O,
114 const char *Modifier = 0);
115 void printAddrMode6Operand(const MachineInstr *MI, int OpNum,
117 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum,
119 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
121 const char *Modifier = 0);
122 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum,
125 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum,
127 void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O);
128 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum,
130 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
133 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum,
135 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum,
137 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum,
139 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum,
142 void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
143 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum,
145 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum,
147 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum,
149 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum,
151 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum,
153 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum,
156 void printCPSOptionOperand(const MachineInstr *MI, int OpNum,
158 void printMSRMaskOperand(const MachineInstr *MI, int OpNum,
160 void printNegZeroOperand(const MachineInstr *MI, int OpNum,
162 void printPredicateOperand(const MachineInstr *MI, int OpNum,
164 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum,
166 void printSBitModifierOperand(const MachineInstr *MI, int OpNum,
168 void printPCLabel(const MachineInstr *MI, int OpNum,
170 void printRegisterList(const MachineInstr *MI, int OpNum,
172 void printCPInstOperand(const MachineInstr *MI, int OpNum,
174 const char *Modifier);
175 void printJTBlockOperand(const MachineInstr *MI, int OpNum,
177 void printJT2BlockOperand(const MachineInstr *MI, int OpNum,
179 void printTBAddrMode(const MachineInstr *MI, int OpNum,
181 void printNoHashImmediate(const MachineInstr *MI, int OpNum,
183 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
185 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
187 void printNEONModImmOperand(const MachineInstr *MI, int OpNum,
190 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
191 unsigned AsmVariant, const char *ExtraCode,
193 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
195 const char *ExtraCode, raw_ostream &O);
197 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen
198 static const char *getRegisterName(unsigned RegNo);
200 virtual void EmitInstruction(const MachineInstr *MI);
201 bool runOnMachineFunction(MachineFunction &F);
203 virtual void EmitConstantPool() {} // we emit constant pools customly!
204 virtual void EmitFunctionEntryLabel();
205 void EmitStartOfAsmFile(Module &M);
206 void EmitEndOfAsmFile(Module &M);
208 virtual unsigned getISAEncoding() {
209 // ARM/Darwin adds ISA to the DWARF info for each function.
210 if (!Subtarget->isTargetDarwin())
212 return Subtarget->isThumb() ?
213 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
216 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
217 const MachineBasicBlock *MBB) const;
218 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
220 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
222 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
223 SmallString<128> Str;
224 raw_svector_ostream OS(Str);
225 EmitMachineConstantPoolValue(MCPV, OS);
226 OutStreamer.EmitRawText(OS.str());
229 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
231 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
232 case 1: O << MAI->getData8bitsDirective(0); break;
233 case 2: O << MAI->getData16bitsDirective(0); break;
234 case 4: O << MAI->getData32bitsDirective(0); break;
235 default: assert(0 && "Unknown CPV size");
238 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
240 if (ACPV->isLSDA()) {
241 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
242 } else if (ACPV->isBlockAddress()) {
243 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
244 } else if (ACPV->isGlobalValue()) {
245 const GlobalValue *GV = ACPV->getGV();
246 bool isIndirect = Subtarget->isTargetDarwin() &&
247 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
249 O << *Mang->getSymbol(GV);
251 // FIXME: Remove this when Darwin transition to @GOT like syntax.
252 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
255 MachineModuleInfoMachO &MMIMachO =
256 MMI->getObjFileInfo<MachineModuleInfoMachO>();
257 MachineModuleInfoImpl::StubValueTy &StubSym =
258 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
259 MMIMachO.getGVStubEntry(Sym);
260 if (StubSym.getPointer() == 0)
261 StubSym = MachineModuleInfoImpl::
262 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
265 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
266 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
269 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
270 if (ACPV->getPCAdjustment() != 0) {
271 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
272 << getFunctionNumber() << "_" << ACPV->getLabelId()
273 << "+" << (unsigned)ACPV->getPCAdjustment();
274 if (ACPV->mustAddCurrentAddress())
280 } // end of anonymous namespace
282 #include "ARMGenAsmWriter.inc"
284 void ARMAsmPrinter::EmitFunctionEntryLabel() {
285 if (AFI->isThumbFunction()) {
286 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
287 if (!Subtarget->isTargetDarwin())
288 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
290 // This needs to emit to a temporary string to get properly quoted
291 // MCSymbols when they have spaces in them.
292 SmallString<128> Tmp;
293 raw_svector_ostream OS(Tmp);
294 OS << "\t.thumb_func\t" << *CurrentFnSym;
295 OutStreamer.EmitRawText(OS.str());
299 OutStreamer.EmitLabel(CurrentFnSym);
302 /// runOnMachineFunction - This uses the printInstruction()
303 /// method to print assembly for each instruction.
305 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
306 AFI = MF.getInfo<ARMFunctionInfo>();
307 MCP = MF.getConstantPool();
309 return AsmPrinter::runOnMachineFunction(MF);
312 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
313 raw_ostream &O, const char *Modifier) {
314 const MachineOperand &MO = MI->getOperand(OpNum);
315 unsigned TF = MO.getTargetFlags();
317 switch (MO.getType()) {
319 assert(0 && "<unknown operand type>");
320 case MachineOperand::MO_Register: {
321 unsigned Reg = MO.getReg();
322 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
323 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
324 unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_0);
325 unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, ARM::dsub_1);
327 << getRegisterName(DRegLo) << ", " << getRegisterName(DRegHi)
329 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
330 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
332 TM.getRegisterInfo()->getMatchingSuperReg(Reg,
333 RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
334 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
336 assert(!MO.getSubReg() && "Subregs should be eliminated!");
337 O << getRegisterName(Reg);
341 case MachineOperand::MO_Immediate: {
342 int64_t Imm = MO.getImm();
344 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
345 (TF & ARMII::MO_LO16))
347 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
348 (TF & ARMII::MO_HI16))
353 case MachineOperand::MO_MachineBasicBlock:
354 O << *MO.getMBB()->getSymbol();
356 case MachineOperand::MO_GlobalAddress: {
357 bool isCallOp = Modifier && !strcmp(Modifier, "call");
358 const GlobalValue *GV = MO.getGlobal();
360 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
361 (TF & ARMII::MO_LO16))
363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
364 (TF & ARMII::MO_HI16))
366 O << *Mang->getSymbol(GV);
368 printOffset(MO.getOffset(), O);
370 if (isCallOp && Subtarget->isTargetELF() &&
371 TM.getRelocationModel() == Reloc::PIC_)
375 case MachineOperand::MO_ExternalSymbol: {
376 bool isCallOp = Modifier && !strcmp(Modifier, "call");
377 O << *GetExternalSymbolSymbol(MO.getSymbolName());
379 if (isCallOp && Subtarget->isTargetELF() &&
380 TM.getRelocationModel() == Reloc::PIC_)
384 case MachineOperand::MO_ConstantPoolIndex:
385 O << *GetCPISymbol(MO.getIndex());
387 case MachineOperand::MO_JumpTableIndex:
388 O << *GetJTISymbol(MO.getIndex());
393 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
394 const MCAsmInfo *MAI) {
395 // Break it up into two parts that make up a shifter immediate.
396 V = ARM_AM::getSOImmVal(V);
397 assert(V != -1 && "Not a valid so_imm value!");
399 unsigned Imm = ARM_AM::getSOImmValImm(V);
400 unsigned Rot = ARM_AM::getSOImmValRot(V);
402 // Print low-level immediate formation info, per
403 // A5.1.3: "Data-processing operands - Immediate".
405 O << "#" << Imm << ", " << Rot;
406 // Pretty printed version.
408 O << "\t" << MAI->getCommentString() << ' ';
409 O << (int)ARM_AM::rotr32(Imm, Rot);
416 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
417 /// immediate in bits 0-7.
418 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum,
420 const MachineOperand &MO = MI->getOperand(OpNum);
421 assert(MO.isImm() && "Not a valid so_imm value!");
422 printSOImm(O, MO.getImm(), isVerbose(), MAI);
425 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
426 /// followed by an 'orr' to materialize.
427 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum,
429 const MachineOperand &MO = MI->getOperand(OpNum);
430 assert(MO.isImm() && "Not a valid so_imm value!");
431 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
432 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
433 printSOImm(O, V1, isVerbose(), MAI);
435 printPredicateOperand(MI, 2, O);
437 printOperand(MI, 0, O);
439 printOperand(MI, 0, O);
441 printSOImm(O, V2, isVerbose(), MAI);
444 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
445 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
447 // REG REG 0,SH_OPC - e.g. R5, ROR R3
448 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
449 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op,
451 const MachineOperand &MO1 = MI->getOperand(Op);
452 const MachineOperand &MO2 = MI->getOperand(Op+1);
453 const MachineOperand &MO3 = MI->getOperand(Op+2);
455 O << getRegisterName(MO1.getReg());
457 // Print the shift opc.
459 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
463 O << getRegisterName(MO2.getReg());
464 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
466 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
470 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op,
472 const MachineOperand &MO1 = MI->getOperand(Op);
473 const MachineOperand &MO2 = MI->getOperand(Op+1);
474 const MachineOperand &MO3 = MI->getOperand(Op+2);
476 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
477 printOperand(MI, Op, O);
481 O << "[" << getRegisterName(MO1.getReg());
484 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
486 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
487 << ARM_AM::getAM2Offset(MO3.getImm());
493 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
494 << getRegisterName(MO2.getReg());
496 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
498 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
503 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op,
505 const MachineOperand &MO1 = MI->getOperand(Op);
506 const MachineOperand &MO2 = MI->getOperand(Op+1);
509 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
511 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
516 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
517 << getRegisterName(MO1.getReg());
519 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
521 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
525 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op,
527 const MachineOperand &MO1 = MI->getOperand(Op);
528 const MachineOperand &MO2 = MI->getOperand(Op+1);
529 const MachineOperand &MO3 = MI->getOperand(Op+2);
531 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
532 O << "[" << getRegisterName(MO1.getReg());
536 << (char)ARM_AM::getAM3Op(MO3.getImm())
537 << getRegisterName(MO2.getReg())
542 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
544 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
549 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op,
551 const MachineOperand &MO1 = MI->getOperand(Op);
552 const MachineOperand &MO2 = MI->getOperand(Op+1);
555 O << (char)ARM_AM::getAM3Op(MO2.getImm())
556 << getRegisterName(MO1.getReg());
560 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
562 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
566 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
568 const char *Modifier) {
569 const MachineOperand &MO2 = MI->getOperand(Op+1);
570 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
571 if (Modifier && strcmp(Modifier, "submode") == 0) {
572 O << ARM_AM::getAMSubModeStr(Mode);
573 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
574 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
575 if (Mode == ARM_AM::ia)
578 printOperand(MI, Op, O);
582 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
584 const char *Modifier) {
585 const MachineOperand &MO1 = MI->getOperand(Op);
586 const MachineOperand &MO2 = MI->getOperand(Op+1);
588 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
589 printOperand(MI, Op, O);
593 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
595 if (Modifier && strcmp(Modifier, "submode") == 0) {
596 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
597 O << ARM_AM::getAMSubModeStr(Mode);
599 } else if (Modifier && strcmp(Modifier, "base") == 0) {
600 // Used for FSTM{D|S} and LSTM{D|S} operations.
601 O << getRegisterName(MO1.getReg());
605 O << "[" << getRegisterName(MO1.getReg());
607 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
609 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
615 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op,
617 const MachineOperand &MO1 = MI->getOperand(Op);
618 const MachineOperand &MO2 = MI->getOperand(Op+1);
620 O << "[" << getRegisterName(MO1.getReg());
622 // FIXME: Both darwin as and GNU as violate ARM docs here.
623 O << ", :" << (MO2.getImm() << 3);
628 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op,
630 const MachineOperand &MO = MI->getOperand(Op);
631 if (MO.getReg() == 0)
634 O << ", " << getRegisterName(MO.getReg());
637 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
639 const char *Modifier) {
640 if (Modifier && strcmp(Modifier, "label") == 0) {
641 printPCLabel(MI, Op+1, O);
645 const MachineOperand &MO1 = MI->getOperand(Op);
646 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
647 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
651 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op,
653 const MachineOperand &MO = MI->getOperand(Op);
654 uint32_t v = ~MO.getImm();
655 int32_t lsb = CountTrailingZeros_32(v);
656 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
657 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
658 O << "#" << lsb << ", #" << width;
661 //===--------------------------------------------------------------------===//
663 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op,
665 O << "#" << MI->getOperand(Op).getImm() * 4;
669 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op,
671 // (3 - the number of trailing zeros) is the number of then / else.
672 unsigned Mask = MI->getOperand(Op).getImm();
673 unsigned CondBit0 = Mask >> 4 & 1;
674 unsigned NumTZ = CountTrailingZeros_32(Mask);
675 assert(NumTZ <= 3 && "Invalid IT mask!");
676 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
677 bool T = ((Mask >> Pos) & 1) == CondBit0;
686 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op,
688 const MachineOperand &MO1 = MI->getOperand(Op);
689 const MachineOperand &MO2 = MI->getOperand(Op+1);
690 O << "[" << getRegisterName(MO1.getReg());
691 O << ", " << getRegisterName(MO2.getReg()) << "]";
695 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
698 const MachineOperand &MO1 = MI->getOperand(Op);
699 const MachineOperand &MO2 = MI->getOperand(Op+1);
700 const MachineOperand &MO3 = MI->getOperand(Op+2);
702 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
703 printOperand(MI, Op, O);
707 O << "[" << getRegisterName(MO1.getReg());
709 O << ", " << getRegisterName(MO3.getReg());
710 else if (unsigned ImmOffs = MO2.getImm())
711 O << ", #" << ImmOffs * Scale;
716 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op,
718 printThumbAddrModeRI5Operand(MI, Op, O, 1);
721 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op,
723 printThumbAddrModeRI5Operand(MI, Op, O, 2);
726 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op,
728 printThumbAddrModeRI5Operand(MI, Op, O, 4);
731 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op,
733 const MachineOperand &MO1 = MI->getOperand(Op);
734 const MachineOperand &MO2 = MI->getOperand(Op+1);
735 O << "[" << getRegisterName(MO1.getReg());
736 if (unsigned ImmOffs = MO2.getImm())
737 O << ", #" << ImmOffs*4;
741 //===--------------------------------------------------------------------===//
743 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
744 // register with shift forms.
746 // REG IMM, SH_OPC - e.g. R5, LSL #3
747 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum,
749 const MachineOperand &MO1 = MI->getOperand(OpNum);
750 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
752 unsigned Reg = MO1.getReg();
753 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
754 O << getRegisterName(Reg);
756 // Print the shift opc.
758 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
761 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
762 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
765 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
768 const MachineOperand &MO1 = MI->getOperand(OpNum);
769 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
771 O << "[" << getRegisterName(MO1.getReg());
773 unsigned OffImm = MO2.getImm();
774 if (OffImm) // Don't print +0.
775 O << ", #" << OffImm;
779 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
782 const MachineOperand &MO1 = MI->getOperand(OpNum);
783 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
785 O << "[" << getRegisterName(MO1.getReg());
787 int32_t OffImm = (int32_t)MO2.getImm();
790 O << ", #-" << -OffImm;
792 O << ", #" << OffImm;
796 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
799 const MachineOperand &MO1 = MI->getOperand(OpNum);
800 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
802 O << "[" << getRegisterName(MO1.getReg());
804 int32_t OffImm = (int32_t)MO2.getImm() / 4;
807 O << ", #-" << -OffImm * 4;
809 O << ", #" << OffImm * 4;
813 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
816 const MachineOperand &MO1 = MI->getOperand(OpNum);
817 int32_t OffImm = (int32_t)MO1.getImm();
820 O << "#-" << -OffImm;
825 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
828 const MachineOperand &MO1 = MI->getOperand(OpNum);
829 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
830 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
832 O << "[" << getRegisterName(MO1.getReg());
834 assert(MO2.getReg() && "Invalid so_reg load / store address!");
835 O << ", " << getRegisterName(MO2.getReg());
837 unsigned ShAmt = MO3.getImm();
839 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
840 O << ", lsl #" << ShAmt;
846 //===--------------------------------------------------------------------===//
848 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum,
850 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
852 O << ARMCondCodeToString(CC);
855 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
858 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
859 O << ARMCondCodeToString(CC);
862 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum,
864 unsigned Reg = MI->getOperand(OpNum).getReg();
866 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
871 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum,
873 int Id = (int)MI->getOperand(OpNum).getImm();
874 O << MAI->getPrivateGlobalPrefix()
875 << "PC" << getFunctionNumber() << "_" << Id;
878 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum,
881 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
882 if (MI->getOperand(i).isImplicit())
884 if ((int)i != OpNum) O << ", ";
885 printOperand(MI, i, O);
890 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
891 raw_ostream &O, const char *Modifier) {
892 assert(Modifier && "This operand only works with a modifier!");
893 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
895 if (!strcmp(Modifier, "label")) {
896 unsigned ID = MI->getOperand(OpNum).getImm();
897 OutStreamer.EmitLabel(GetCPISymbol(ID));
899 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
900 unsigned CPI = MI->getOperand(OpNum).getIndex();
902 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
904 if (MCPE.isMachineConstantPoolEntry()) {
905 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
907 EmitGlobalConstant(MCPE.Val.ConstVal);
912 MCSymbol *ARMAsmPrinter::
913 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
914 const MachineBasicBlock *MBB) const {
915 SmallString<60> Name;
916 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
917 << getFunctionNumber() << '_' << uid << '_' << uid2
918 << "_set_" << MBB->getNumber();
919 return OutContext.GetOrCreateSymbol(Name.str());
922 MCSymbol *ARMAsmPrinter::
923 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
924 SmallString<60> Name;
925 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
926 << getFunctionNumber() << '_' << uid << '_' << uid2;
927 return OutContext.GetOrCreateSymbol(Name.str());
930 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum,
932 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
934 const MachineOperand &MO1 = MI->getOperand(OpNum);
935 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
937 unsigned JTI = MO1.getIndex();
938 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
939 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
941 O << *JTISymbol << ":\n";
943 const char *JTEntryDirective = MAI->getData32bitsDirective();
945 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
948 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
949 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
950 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
951 MachineBasicBlock *MBB = JTBBs[i];
952 bool isNew = JTSets.insert(MBB);
954 if (UseSet && isNew) {
956 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
957 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
960 O << JTEntryDirective << ' ';
962 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
963 else if (TM.getRelocationModel() == Reloc::PIC_)
964 O << *MBB->getSymbol() << '-' << *JTISymbol;
966 O << *MBB->getSymbol();
973 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum,
975 const MachineOperand &MO1 = MI->getOperand(OpNum);
976 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
977 unsigned JTI = MO1.getIndex();
979 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
981 // Can't use EmitLabel until instprinter happens, label comes out in the wrong
983 O << *JTISymbol << ":\n";
985 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
986 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
987 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
988 bool ByteOffset = false, HalfWordOffset = false;
989 if (MI->getOpcode() == ARM::t2TBB)
991 else if (MI->getOpcode() == ARM::t2TBH)
992 HalfWordOffset = true;
994 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
995 MachineBasicBlock *MBB = JTBBs[i];
997 O << MAI->getData8bitsDirective();
998 else if (HalfWordOffset)
999 O << MAI->getData16bitsDirective();
1001 if (ByteOffset || HalfWordOffset)
1002 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
1004 O << "\tb.w " << *MBB->getSymbol();
1011 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum,
1013 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
1014 if (MI->getOpcode() == ARM::t2TBH)
1019 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum,
1021 O << MI->getOperand(OpNum).getImm();
1024 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum,
1026 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1027 O << '#' << FP->getValueAPF().convertToFloat();
1029 O << "\t\t" << MAI->getCommentString() << ' ';
1030 WriteAsOperand(O, FP, /*PrintType=*/false);
1034 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum,
1036 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1037 O << '#' << FP->getValueAPF().convertToDouble();
1039 O << "\t\t" << MAI->getCommentString() << ' ';
1040 WriteAsOperand(O, FP, /*PrintType=*/false);
1044 void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum,
1046 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1048 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1049 O << "#0x" << utohexstr(Val);
1052 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1053 unsigned AsmVariant, const char *ExtraCode,
1055 // Does this asm operand have a single letter operand modifier?
1056 if (ExtraCode && ExtraCode[0]) {
1057 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1059 switch (ExtraCode[0]) {
1060 default: return true; // Unknown modifier.
1061 case 'a': // Print as a memory address.
1062 if (MI->getOperand(OpNum).isReg()) {
1063 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1067 case 'c': // Don't print "#" before an immediate operand.
1068 if (!MI->getOperand(OpNum).isImm())
1070 printNoHashImmediate(MI, OpNum, O);
1072 case 'P': // Print a VFP double precision register.
1073 case 'q': // Print a NEON quad precision register.
1074 printOperand(MI, OpNum, O);
1079 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
1084 printOperand(MI, OpNum, O);
1088 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1089 unsigned OpNum, unsigned AsmVariant,
1090 const char *ExtraCode,
1092 if (ExtraCode && ExtraCode[0])
1093 return true; // Unknown modifier.
1095 const MachineOperand &MO = MI->getOperand(OpNum);
1096 assert(MO.isReg() && "unexpected inline asm memory operand");
1097 O << "[" << getRegisterName(MO.getReg()) << "]";
1101 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1103 printInstructionThroughMCStreamer(MI);
1107 if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY)
1110 SmallString<128> Str;
1111 raw_svector_ostream OS(Str);
1112 if (MI->getOpcode() == ARM::DBG_VALUE) {
1113 unsigned NOps = MI->getNumOperands();
1115 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1116 // cast away const; DIetc do not take const operands for some reason.
1117 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1120 // Frame address. Currently handles register +- offset only.
1121 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1122 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1125 printOperand(MI, NOps-2, OS);
1126 OutStreamer.EmitRawText(OS.str());
1130 printInstruction(MI, OS);
1131 OutStreamer.EmitRawText(OS.str());
1133 // Make sure the instruction that follows TBB is 2-byte aligned.
1134 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
1135 if (MI->getOpcode() == ARM::t2TBB)
1139 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1140 if (Subtarget->isTargetDarwin()) {
1141 Reloc::Model RelocM = TM.getRelocationModel();
1142 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1143 // Declare all the text sections up front (before the DWARF sections
1144 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1145 // them together at the beginning of the object file. This helps
1146 // avoid out-of-range branches that are due a fundamental limitation of
1147 // the way symbol offsets are encoded with the current Darwin ARM
1149 const TargetLoweringObjectFileMachO &TLOFMacho =
1150 static_cast<const TargetLoweringObjectFileMachO &>(
1151 getObjFileLowering());
1152 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1153 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1154 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1155 if (RelocM == Reloc::DynamicNoPIC) {
1156 const MCSection *sect =
1157 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
1158 MCSectionMachO::S_SYMBOL_STUBS,
1159 12, SectionKind::getText());
1160 OutStreamer.SwitchSection(sect);
1162 const MCSection *sect =
1163 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
1164 MCSectionMachO::S_SYMBOL_STUBS,
1165 16, SectionKind::getText());
1166 OutStreamer.SwitchSection(sect);
1168 const MCSection *StaticInitSect =
1169 OutContext.getMachOSection("__TEXT", "__StaticInit",
1170 MCSectionMachO::S_REGULAR |
1171 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
1172 SectionKind::getText());
1173 OutStreamer.SwitchSection(StaticInitSect);
1177 // Use unified assembler syntax.
1178 OutStreamer.EmitRawText(StringRef("\t.syntax unified"));
1180 // Emit ARM Build Attributes
1181 if (Subtarget->isTargetELF()) {
1183 std::string CPUString = Subtarget->getCPUString();
1184 if (CPUString != "generic")
1185 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
1187 // FIXME: Emit FPU type
1188 if (Subtarget->hasVFP2())
1189 OutStreamer.EmitRawText("\t.eabi_attribute " +
1190 Twine(ARMBuildAttrs::VFP_arch) + ", 2");
1192 // Signal various FP modes.
1193 if (!UnsafeFPMath) {
1194 OutStreamer.EmitRawText("\t.eabi_attribute " +
1195 Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1");
1196 OutStreamer.EmitRawText("\t.eabi_attribute " +
1197 Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1");
1200 if (NoInfsFPMath && NoNaNsFPMath)
1201 OutStreamer.EmitRawText("\t.eabi_attribute " +
1202 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1");
1204 OutStreamer.EmitRawText("\t.eabi_attribute " +
1205 Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3");
1207 // 8-bytes alignment stuff.
1208 OutStreamer.EmitRawText("\t.eabi_attribute " +
1209 Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1");
1210 OutStreamer.EmitRawText("\t.eabi_attribute " +
1211 Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1");
1213 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1214 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
1215 OutStreamer.EmitRawText("\t.eabi_attribute " +
1216 Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3");
1217 OutStreamer.EmitRawText("\t.eabi_attribute " +
1218 Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1");
1220 // FIXME: Should we signal R9 usage?
1225 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1226 if (Subtarget->isTargetDarwin()) {
1227 // All darwin targets use mach-o.
1228 const TargetLoweringObjectFileMachO &TLOFMacho =
1229 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
1230 MachineModuleInfoMachO &MMIMacho =
1231 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1233 // Output non-lazy-pointers for external and common global variables.
1234 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1236 if (!Stubs.empty()) {
1237 // Switch with ".non_lazy_symbol_pointer" directive.
1238 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1240 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1242 OutStreamer.EmitLabel(Stubs[i].first);
1243 // .indirect_symbol _foo
1244 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1245 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1248 // External to current translation unit.
1249 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1251 // Internal to current translation unit.
1253 // When we place the LSDA into the TEXT section, the type info pointers
1254 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1255 // However, sometimes the types are local to the file. So we need to
1256 // fill in the value for the NLP in those cases.
1257 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1259 4/*size*/, 0/*addrspace*/);
1263 OutStreamer.AddBlankLine();
1266 Stubs = MMIMacho.GetHiddenGVStubList();
1267 if (!Stubs.empty()) {
1268 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1270 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1272 OutStreamer.EmitLabel(Stubs[i].first);
1274 OutStreamer.EmitValue(MCSymbolRefExpr::
1275 Create(Stubs[i].second.getPointer(),
1277 4/*size*/, 0/*addrspace*/);
1281 OutStreamer.AddBlankLine();
1284 // Funny Darwin hack: This flag tells the linker that no global symbols
1285 // contain code that falls through to other global symbols (e.g. the obvious
1286 // implementation of multiple entry points). If this doesn't occur, the
1287 // linker can safely perform dead code stripping. Since LLVM never
1288 // generates code that does this, it is always safe to set.
1289 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1293 //===----------------------------------------------------------------------===//
1295 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1296 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1297 switch (MI->getOpcode()) {
1298 case ARM::t2MOVi32imm:
1299 assert(0 && "Should be lowered by thumb2it pass");
1301 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1302 // This is a pseudo op for a label + instruction sequence, which looks like:
1305 // This adds the address of LPC0 to r0.
1308 // FIXME: MOVE TO SHARED PLACE.
1309 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1310 const char *Prefix = MAI->getPrivateGlobalPrefix();
1311 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1312 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1313 OutStreamer.EmitLabel(Label);
1316 // Form and emit tha dd.
1318 AddInst.setOpcode(ARM::ADDrr);
1319 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1320 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1321 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1322 OutStreamer.EmitInstruction(AddInst);
1325 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1326 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1327 /// in the function. The first operand is the ID# for this instruction, the
1328 /// second is the index into the MachineConstantPool that this is, the third
1329 /// is the size in bytes of this constant pool entry.
1330 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1331 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1334 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1336 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1337 if (MCPE.isMachineConstantPoolEntry())
1338 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1340 EmitGlobalConstant(MCPE.Val.ConstVal);
1344 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1345 // This is a hack that lowers as a two instruction sequence.
1346 unsigned DstReg = MI->getOperand(0).getReg();
1347 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1349 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1350 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1354 TmpInst.setOpcode(ARM::MOVi);
1355 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1356 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1359 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1360 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1362 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1363 OutStreamer.EmitInstruction(TmpInst);
1368 TmpInst.setOpcode(ARM::ORRri);
1369 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1370 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1371 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1373 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1374 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1376 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1377 OutStreamer.EmitInstruction(TmpInst);
1381 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1382 // This is a hack that lowers as a two instruction sequence.
1383 unsigned DstReg = MI->getOperand(0).getReg();
1384 const MachineOperand &MO = MI->getOperand(1);
1387 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1388 V1 = MCOperand::CreateImm(ImmVal & 65535);
1389 V2 = MCOperand::CreateImm(ImmVal >> 16);
1390 } else if (MO.isGlobal()) {
1391 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO);
1392 const MCSymbolRefExpr *SymRef1 =
1393 MCSymbolRefExpr::Create(Symbol,
1394 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
1395 const MCSymbolRefExpr *SymRef2 =
1396 MCSymbolRefExpr::Create(Symbol,
1397 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
1398 V1 = MCOperand::CreateExpr(SymRef1);
1399 V2 = MCOperand::CreateExpr(SymRef2);
1402 llvm_unreachable("cannot handle this operand");
1407 TmpInst.setOpcode(ARM::MOVi16);
1408 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1409 TmpInst.addOperand(V1); // lower16(imm)
1412 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1413 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1415 OutStreamer.EmitInstruction(TmpInst);
1420 TmpInst.setOpcode(ARM::MOVTi16);
1421 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1422 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1423 TmpInst.addOperand(V2); // upper16(imm)
1426 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1427 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1429 OutStreamer.EmitInstruction(TmpInst);
1437 MCInstLowering.Lower(MI, TmpInst);
1438 OutStreamer.EmitInstruction(TmpInst);
1441 //===----------------------------------------------------------------------===//
1442 // Target Registry Stuff
1443 //===----------------------------------------------------------------------===//
1445 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1446 unsigned SyntaxVariant,
1447 const MCAsmInfo &MAI) {
1448 if (SyntaxVariant == 0)
1449 return new ARMInstPrinter(MAI, false);
1453 // Force static initialization.
1454 extern "C" void LLVMInitializeARMAsmPrinter() {
1455 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1456 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1458 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1459 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);