1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "InstPrinter/ARMInstPrinter.h"
24 #include "MCTargetDesc/ARMAddressingModes.h"
25 #include "MCTargetDesc/ARMMCExpr.h"
26 #include "llvm/Analysis/DebugInfo.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Module.h"
29 #include "llvm/Type.h"
30 #include "llvm/Assembly/Writer.h"
31 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCAssembler.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCObjectStreamer.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Target/Mangler.h"
43 #include "llvm/Target/TargetData.h"
44 #include "llvm/Target/TargetMachine.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
56 // Per section and per symbol attributes are not supported.
57 // To implement them we would need the ability to delay this emission
58 // until the assembly file is fully parsed/generated as only then do we
59 // know the symbol and section numbers.
60 class AttributeEmitter {
62 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
63 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
64 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
65 virtual void Finish() = 0;
66 virtual ~AttributeEmitter() {}
69 class AsmAttributeEmitter : public AttributeEmitter {
73 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
74 void MaybeSwitchVendor(StringRef Vendor) { }
76 void EmitAttribute(unsigned Attribute, unsigned Value) {
77 Streamer.EmitRawText("\t.eabi_attribute " +
78 Twine(Attribute) + ", " + Twine(Value));
81 void EmitTextAttribute(unsigned Attribute, StringRef String) {
83 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
84 case ARMBuildAttrs::CPU_name:
85 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
87 /* GAS requires .fpu to be emitted regardless of EABI attribute */
88 case ARMBuildAttrs::Advanced_SIMD_arch:
89 case ARMBuildAttrs::VFP_arch:
90 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
97 class ObjectAttributeEmitter : public AttributeEmitter {
98 // This structure holds all attributes, accounting for
99 // their string/numeric value, so we can later emmit them
100 // in declaration order, keeping all in the same vector
101 struct AttributeItemType {
109 StringRef StringValue;
112 MCObjectStreamer &Streamer;
113 StringRef CurrentVendor;
114 SmallVector<AttributeItemType, 64> Contents;
116 // Account for the ULEB/String size of each item,
117 // not just the number of items
119 // FIXME: this should be in a more generic place, but
120 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
121 size_t getULEBSize(int Value) {
125 Size += sizeof(int8_t); // Is this really necessary?
131 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
132 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
134 void MaybeSwitchVendor(StringRef Vendor) {
135 assert(!Vendor.empty() && "Vendor cannot be empty.");
137 if (CurrentVendor.empty())
138 CurrentVendor = Vendor;
139 else if (CurrentVendor == Vendor)
144 CurrentVendor = Vendor;
146 assert(Contents.size() == 0);
149 void EmitAttribute(unsigned Attribute, unsigned Value) {
150 AttributeItemType attr = {
151 AttributeItemType::NumericAttribute,
156 ContentsSize += getULEBSize(Attribute);
157 ContentsSize += getULEBSize(Value);
158 Contents.push_back(attr);
161 void EmitTextAttribute(unsigned Attribute, StringRef String) {
162 AttributeItemType attr = {
163 AttributeItemType::TextAttribute,
168 ContentsSize += getULEBSize(Attribute);
170 ContentsSize += String.size()+1;
172 Contents.push_back(attr);
176 // Vendor size + Vendor name + '\0'
177 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
180 const size_t TagHeaderSize = 1 + 4;
182 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
183 Streamer.EmitBytes(CurrentVendor, 0);
184 Streamer.EmitIntValue(0, 1); // '\0'
186 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
187 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
189 // Size should have been accounted for already, now
190 // emit each field as its type (ULEB or String)
191 for (unsigned int i=0; i<Contents.size(); ++i) {
192 AttributeItemType item = Contents[i];
193 Streamer.EmitULEB128IntValue(item.Tag, 0);
195 default: llvm_unreachable("Invalid attribute type");
196 case AttributeItemType::NumericAttribute:
197 Streamer.EmitULEB128IntValue(item.IntValue, 0);
199 case AttributeItemType::TextAttribute:
200 Streamer.EmitBytes(item.StringValue.upper(), 0);
201 Streamer.EmitIntValue(0, 1); // '\0'
210 } // end of anonymous namespace
212 MachineLocation ARMAsmPrinter::
213 getDebugValueLocation(const MachineInstr *MI) const {
214 MachineLocation Location;
215 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
216 // Frame address. Currently handles register +- offset only.
217 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
218 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
220 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
225 /// EmitDwarfRegOp - Emit dwarf register operation.
226 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
227 const TargetRegisterInfo *RI = TM.getRegisterInfo();
228 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
229 AsmPrinter::EmitDwarfRegOp(MLoc);
231 unsigned Reg = MLoc.getReg();
232 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
234 // S registers are described as bit-pieces of a register
235 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
236 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
238 unsigned SReg = Reg - ARM::S0;
239 bool odd = SReg & 0x1;
240 unsigned Rx = 256 + (SReg >> 1);
242 OutStreamer.AddComment("DW_OP_regx for S register");
243 EmitInt8(dwarf::DW_OP_regx);
245 OutStreamer.AddComment(Twine(SReg));
249 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
250 EmitInt8(dwarf::DW_OP_bit_piece);
254 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
255 EmitInt8(dwarf::DW_OP_bit_piece);
259 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
261 // Q registers Q0-Q15 are described by composing two D registers together.
262 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
265 unsigned QReg = Reg - ARM::Q0;
266 unsigned D1 = 256 + 2 * QReg;
267 unsigned D2 = D1 + 1;
269 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
270 EmitInt8(dwarf::DW_OP_regx);
272 OutStreamer.AddComment("DW_OP_piece 8");
273 EmitInt8(dwarf::DW_OP_piece);
276 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
277 EmitInt8(dwarf::DW_OP_regx);
279 OutStreamer.AddComment("DW_OP_piece 8");
280 EmitInt8(dwarf::DW_OP_piece);
286 void ARMAsmPrinter::EmitFunctionEntryLabel() {
287 OutStreamer.ForceCodeRegion();
289 if (AFI->isThumbFunction()) {
290 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
291 OutStreamer.EmitThumbFunc(CurrentFnSym);
294 OutStreamer.EmitLabel(CurrentFnSym);
297 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
298 uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType());
299 assert(Size && "C++ constructor pointer had zero size!");
301 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
302 assert(GV && "C++ constructor pointer was not a GlobalValue!");
304 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
305 (Subtarget->isTargetDarwin()
306 ? MCSymbolRefExpr::VK_None
307 : MCSymbolRefExpr::VK_ARM_TARGET1),
310 OutStreamer.EmitValue(E, Size);
313 /// runOnMachineFunction - This uses the EmitInstruction()
314 /// method to print assembly for each instruction.
316 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
317 AFI = MF.getInfo<ARMFunctionInfo>();
318 MCP = MF.getConstantPool();
320 return AsmPrinter::runOnMachineFunction(MF);
323 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
324 raw_ostream &O, const char *Modifier) {
325 const MachineOperand &MO = MI->getOperand(OpNum);
326 unsigned TF = MO.getTargetFlags();
328 switch (MO.getType()) {
329 default: llvm_unreachable("<unknown operand type>");
330 case MachineOperand::MO_Register: {
331 unsigned Reg = MO.getReg();
332 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
333 assert(!MO.getSubReg() && "Subregs should be eliminated!");
334 O << ARMInstPrinter::getRegisterName(Reg);
337 case MachineOperand::MO_Immediate: {
338 int64_t Imm = MO.getImm();
340 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
341 (TF == ARMII::MO_LO16))
343 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
344 (TF == ARMII::MO_HI16))
349 case MachineOperand::MO_MachineBasicBlock:
350 O << *MO.getMBB()->getSymbol();
352 case MachineOperand::MO_GlobalAddress: {
353 const GlobalValue *GV = MO.getGlobal();
354 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
355 (TF & ARMII::MO_LO16))
357 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
358 (TF & ARMII::MO_HI16))
360 O << *Mang->getSymbol(GV);
362 printOffset(MO.getOffset(), O);
363 if (TF == ARMII::MO_PLT)
367 case MachineOperand::MO_ExternalSymbol: {
368 O << *GetExternalSymbolSymbol(MO.getSymbolName());
369 if (TF == ARMII::MO_PLT)
373 case MachineOperand::MO_ConstantPoolIndex:
374 O << *GetCPISymbol(MO.getIndex());
376 case MachineOperand::MO_JumpTableIndex:
377 O << *GetJTISymbol(MO.getIndex());
382 //===--------------------------------------------------------------------===//
384 MCSymbol *ARMAsmPrinter::
385 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
386 const MachineBasicBlock *MBB) const {
387 SmallString<60> Name;
388 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
389 << getFunctionNumber() << '_' << uid << '_' << uid2
390 << "_set_" << MBB->getNumber();
391 return OutContext.GetOrCreateSymbol(Name.str());
394 MCSymbol *ARMAsmPrinter::
395 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
396 SmallString<60> Name;
397 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
398 << getFunctionNumber() << '_' << uid << '_' << uid2;
399 return OutContext.GetOrCreateSymbol(Name.str());
403 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
404 SmallString<60> Name;
405 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
406 << getFunctionNumber();
407 return OutContext.GetOrCreateSymbol(Name.str());
410 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
411 unsigned AsmVariant, const char *ExtraCode,
413 // Does this asm operand have a single letter operand modifier?
414 if (ExtraCode && ExtraCode[0]) {
415 if (ExtraCode[1] != 0) return true; // Unknown modifier.
417 switch (ExtraCode[0]) {
418 default: return true; // Unknown modifier.
419 case 'a': // Print as a memory address.
420 if (MI->getOperand(OpNum).isReg()) {
422 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
427 case 'c': // Don't print "#" before an immediate operand.
428 if (!MI->getOperand(OpNum).isImm())
430 O << MI->getOperand(OpNum).getImm();
432 case 'P': // Print a VFP double precision register.
433 case 'q': // Print a NEON quad precision register.
434 printOperand(MI, OpNum, O);
436 case 'y': // Print a VFP single precision register as indexed double.
437 // This uses the ordering of the alias table to get the first 'd' register
438 // that overlaps the 's' register. Also, s0 is an odd register, hence the
439 // odd modulus check below.
440 if (MI->getOperand(OpNum).isReg()) {
441 unsigned Reg = MI->getOperand(OpNum).getReg();
442 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
443 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
444 (((Reg % 2) == 1) ? "[0]" : "[1]");
448 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
449 if (!MI->getOperand(OpNum).isImm())
451 O << ~(MI->getOperand(OpNum).getImm());
453 case 'L': // The low 16 bits of an immediate constant.
454 if (!MI->getOperand(OpNum).isImm())
456 O << (MI->getOperand(OpNum).getImm() & 0xffff);
458 case 'M': { // A register range suitable for LDM/STM.
459 if (!MI->getOperand(OpNum).isReg())
461 const MachineOperand &MO = MI->getOperand(OpNum);
462 unsigned RegBegin = MO.getReg();
463 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
464 // already got the operands in registers that are operands to the
465 // inline asm statement.
467 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
469 // FIXME: The register allocator not only may not have given us the
470 // registers in sequence, but may not be in ascending registers. This
471 // will require changes in the register allocator that'll need to be
472 // propagated down here if the operands change.
473 unsigned RegOps = OpNum + 1;
474 while (MI->getOperand(RegOps).isReg()) {
476 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
484 case 'R': // The most significant register of a pair.
485 case 'Q': { // The least significant register of a pair.
488 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
489 if (!FlagsOP.isImm())
491 unsigned Flags = FlagsOP.getImm();
492 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
495 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
496 if (RegOp >= MI->getNumOperands())
498 const MachineOperand &MO = MI->getOperand(RegOp);
501 unsigned Reg = MO.getReg();
502 O << ARMInstPrinter::getRegisterName(Reg);
506 case 'e': // The low doubleword register of a NEON quad register.
507 case 'f': { // The high doubleword register of a NEON quad register.
508 if (!MI->getOperand(OpNum).isReg())
510 unsigned Reg = MI->getOperand(OpNum).getReg();
511 if (!ARM::QPRRegClass.contains(Reg))
513 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
514 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
515 ARM::dsub_0 : ARM::dsub_1);
516 O << ARMInstPrinter::getRegisterName(SubReg);
520 // These modifiers are not yet supported.
521 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
522 case 'H': // The highest-numbered register of a pair.
527 printOperand(MI, OpNum, O);
531 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
532 unsigned OpNum, unsigned AsmVariant,
533 const char *ExtraCode,
535 // Does this asm operand have a single letter operand modifier?
536 if (ExtraCode && ExtraCode[0]) {
537 if (ExtraCode[1] != 0) return true; // Unknown modifier.
539 switch (ExtraCode[0]) {
540 case 'A': // A memory operand for a VLD1/VST1 instruction.
541 default: return true; // Unknown modifier.
542 case 'm': // The base register of a memory operand.
543 if (!MI->getOperand(OpNum).isReg())
545 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
550 const MachineOperand &MO = MI->getOperand(OpNum);
551 assert(MO.isReg() && "unexpected inline asm memory operand");
552 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
556 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
557 if (Subtarget->isTargetDarwin()) {
558 Reloc::Model RelocM = TM.getRelocationModel();
559 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
560 // Declare all the text sections up front (before the DWARF sections
561 // emitted by AsmPrinter::doInitialization) so the assembler will keep
562 // them together at the beginning of the object file. This helps
563 // avoid out-of-range branches that are due a fundamental limitation of
564 // the way symbol offsets are encoded with the current Darwin ARM
566 const TargetLoweringObjectFileMachO &TLOFMacho =
567 static_cast<const TargetLoweringObjectFileMachO &>(
568 getObjFileLowering());
569 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
570 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
571 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
572 if (RelocM == Reloc::DynamicNoPIC) {
573 const MCSection *sect =
574 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
575 MCSectionMachO::S_SYMBOL_STUBS,
576 12, SectionKind::getText());
577 OutStreamer.SwitchSection(sect);
579 const MCSection *sect =
580 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
581 MCSectionMachO::S_SYMBOL_STUBS,
582 16, SectionKind::getText());
583 OutStreamer.SwitchSection(sect);
585 const MCSection *StaticInitSect =
586 OutContext.getMachOSection("__TEXT", "__StaticInit",
587 MCSectionMachO::S_REGULAR |
588 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
589 SectionKind::getText());
590 OutStreamer.SwitchSection(StaticInitSect);
594 // Use unified assembler syntax.
595 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
597 // Emit ARM Build Attributes
598 if (Subtarget->isTargetELF())
603 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
604 if (Subtarget->isTargetDarwin()) {
605 // All darwin targets use mach-o.
606 const TargetLoweringObjectFileMachO &TLOFMacho =
607 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
608 MachineModuleInfoMachO &MMIMacho =
609 MMI->getObjFileInfo<MachineModuleInfoMachO>();
611 // Output non-lazy-pointers for external and common global variables.
612 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
614 if (!Stubs.empty()) {
615 // Switch with ".non_lazy_symbol_pointer" directive.
616 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
618 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
620 OutStreamer.EmitLabel(Stubs[i].first);
621 // .indirect_symbol _foo
622 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
623 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
626 // External to current translation unit.
627 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
629 // Internal to current translation unit.
631 // When we place the LSDA into the TEXT section, the type info
632 // pointers need to be indirect and pc-rel. We accomplish this by
633 // using NLPs; however, sometimes the types are local to the file.
634 // We need to fill in the value for the NLP in those cases.
635 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
637 4/*size*/, 0/*addrspace*/);
641 OutStreamer.AddBlankLine();
644 Stubs = MMIMacho.GetHiddenGVStubList();
645 if (!Stubs.empty()) {
646 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
648 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
650 OutStreamer.EmitLabel(Stubs[i].first);
652 OutStreamer.EmitValue(MCSymbolRefExpr::
653 Create(Stubs[i].second.getPointer(),
655 4/*size*/, 0/*addrspace*/);
659 OutStreamer.AddBlankLine();
662 // Funny Darwin hack: This flag tells the linker that no global symbols
663 // contain code that falls through to other global symbols (e.g. the obvious
664 // implementation of multiple entry points). If this doesn't occur, the
665 // linker can safely perform dead code stripping. Since LLVM never
666 // generates code that does this, it is always safe to set.
667 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
671 //===----------------------------------------------------------------------===//
672 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
674 // The following seem like one-off assembler flags, but they actually need
675 // to appear in the .ARM.attributes section in ELF.
676 // Instead of subclassing the MCELFStreamer, we do the work here.
678 void ARMAsmPrinter::emitAttributes() {
680 emitARMAttributeSection();
682 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
683 bool emitFPU = false;
684 AttributeEmitter *AttrEmitter;
685 if (OutStreamer.hasRawTextSupport()) {
686 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
689 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
690 AttrEmitter = new ObjectAttributeEmitter(O);
693 AttrEmitter->MaybeSwitchVendor("aeabi");
695 std::string CPUString = Subtarget->getCPUString();
697 if (CPUString == "cortex-a8" ||
698 Subtarget->isCortexA8()) {
699 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
700 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
701 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
702 ARMBuildAttrs::ApplicationProfile);
703 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
704 ARMBuildAttrs::Allowed);
705 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
706 ARMBuildAttrs::AllowThumb32);
707 // Fixme: figure out when this is emitted.
708 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
709 // ARMBuildAttrs::AllowWMMXv1);
712 /// ADD additional Else-cases here!
713 } else if (CPUString == "xscale") {
714 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
715 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
716 ARMBuildAttrs::Allowed);
717 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
718 ARMBuildAttrs::Allowed);
719 } else if (CPUString == "generic") {
720 // FIXME: Why these defaults?
721 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
722 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
723 ARMBuildAttrs::Allowed);
724 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
725 ARMBuildAttrs::Allowed);
728 if (Subtarget->hasNEON() && emitFPU) {
729 /* NEON is not exactly a VFP architecture, but GAS emit one of
730 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
731 if (Subtarget->hasNEON2())
732 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
735 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
736 /* If emitted for NEON, omit from VFP below, since you can have both
737 * NEON and VFP in build attributes but only one .fpu */
742 if (Subtarget->hasVFP4()) {
743 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
744 ARMBuildAttrs::AllowFPv4A);
746 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
749 } else if (Subtarget->hasVFP3()) {
750 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
751 ARMBuildAttrs::AllowFPv3A);
753 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
756 } else if (Subtarget->hasVFP2()) {
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
758 ARMBuildAttrs::AllowFPv2);
760 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
763 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
764 * since NEON can have 1 (allowed) or 2 (MAC operations) */
765 if (Subtarget->hasNEON()) {
766 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
767 ARMBuildAttrs::Allowed);
770 // Signal various FP modes.
771 if (!TM.Options.UnsafeFPMath) {
772 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
773 ARMBuildAttrs::Allowed);
774 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
775 ARMBuildAttrs::Allowed);
778 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
779 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
780 ARMBuildAttrs::Allowed);
782 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
783 ARMBuildAttrs::AllowIEE754);
785 // FIXME: add more flags to ARMBuildAttrs.h
786 // 8-bytes alignment stuff.
787 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
788 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
790 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
791 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
792 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
793 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
795 // FIXME: Should we signal R9 usage?
797 if (Subtarget->hasDivide())
798 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
800 AttrEmitter->Finish();
804 void ARMAsmPrinter::emitARMAttributeSection() {
806 // [ <section-length> "vendor-name"
807 // [ <file-tag> <size> <attribute>*
808 // | <section-tag> <size> <section-number>* 0 <attribute>*
809 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
813 if (OutStreamer.hasRawTextSupport())
816 const ARMElfTargetObjectFile &TLOFELF =
817 static_cast<const ARMElfTargetObjectFile &>
818 (getObjFileLowering());
820 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
823 OutStreamer.EmitIntValue(0x41, 1);
826 //===----------------------------------------------------------------------===//
828 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
829 unsigned LabelId, MCContext &Ctx) {
831 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
832 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
836 static MCSymbolRefExpr::VariantKind
837 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
839 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
840 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
841 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
842 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
843 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
844 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
846 llvm_unreachable("Invalid ARMCPModifier!");
849 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
850 bool isIndirect = Subtarget->isTargetDarwin() &&
851 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
853 return Mang->getSymbol(GV);
855 // FIXME: Remove this when Darwin transition to @GOT like syntax.
856 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
857 MachineModuleInfoMachO &MMIMachO =
858 MMI->getObjFileInfo<MachineModuleInfoMachO>();
859 MachineModuleInfoImpl::StubValueTy &StubSym =
860 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
861 MMIMachO.getGVStubEntry(MCSym);
862 if (StubSym.getPointer() == 0)
863 StubSym = MachineModuleInfoImpl::
864 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
869 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
870 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
872 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
875 if (ACPV->isLSDA()) {
876 SmallString<128> Str;
877 raw_svector_ostream OS(Str);
878 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
879 MCSym = OutContext.GetOrCreateSymbol(OS.str());
880 } else if (ACPV->isBlockAddress()) {
881 const BlockAddress *BA =
882 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
883 MCSym = GetBlockAddressSymbol(BA);
884 } else if (ACPV->isGlobalValue()) {
885 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
886 MCSym = GetARMGVSymbol(GV);
887 } else if (ACPV->isMachineBasicBlock()) {
888 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
889 MCSym = MBB->getSymbol();
891 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
892 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
893 MCSym = GetExternalSymbolSymbol(Sym);
896 // Create an MCSymbol for the reference.
898 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
901 if (ACPV->getPCAdjustment()) {
902 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
906 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
908 MCBinaryExpr::CreateAdd(PCRelExpr,
909 MCConstantExpr::Create(ACPV->getPCAdjustment(),
912 if (ACPV->mustAddCurrentAddress()) {
913 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
914 // label, so just emit a local label end reference that instead.
915 MCSymbol *DotSym = OutContext.CreateTempSymbol();
916 OutStreamer.EmitLabel(DotSym);
917 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
918 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
920 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
922 OutStreamer.EmitValue(Expr, Size);
925 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
926 unsigned Opcode = MI->getOpcode();
928 if (Opcode == ARM::BR_JTadd)
930 else if (Opcode == ARM::BR_JTm)
933 const MachineOperand &MO1 = MI->getOperand(OpNum);
934 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
935 unsigned JTI = MO1.getIndex();
937 // Tag the jump table appropriately for precise disassembly.
938 OutStreamer.EmitJumpTable32Region();
940 // Emit a label for the jump table.
941 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
942 OutStreamer.EmitLabel(JTISymbol);
944 // Emit each entry of the table.
945 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
949 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
950 MachineBasicBlock *MBB = JTBBs[i];
951 // Construct an MCExpr for the entry. We want a value of the form:
952 // (BasicBlockAddr - TableBeginAddr)
954 // For example, a table with entries jumping to basic blocks BB0 and BB1
957 // .word (LBB0 - LJTI_0_0)
958 // .word (LBB1 - LJTI_0_0)
959 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
961 if (TM.getRelocationModel() == Reloc::PIC_)
962 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
965 // If we're generating a table of Thumb addresses in static relocation
966 // model, we need to add one to keep interworking correctly.
967 else if (AFI->isThumbFunction())
968 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
970 OutStreamer.EmitValue(Expr, 4);
974 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
975 unsigned Opcode = MI->getOpcode();
976 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
977 const MachineOperand &MO1 = MI->getOperand(OpNum);
978 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
979 unsigned JTI = MO1.getIndex();
981 // Emit a label for the jump table.
982 if (MI->getOpcode() == ARM::t2TBB_JT) {
983 OutStreamer.EmitJumpTable8Region();
984 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
985 OutStreamer.EmitJumpTable16Region();
987 OutStreamer.EmitJumpTable32Region();
990 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
991 OutStreamer.EmitLabel(JTISymbol);
993 // Emit each entry of the table.
994 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
995 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
996 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
997 unsigned OffsetWidth = 4;
998 if (MI->getOpcode() == ARM::t2TBB_JT)
1000 else if (MI->getOpcode() == ARM::t2TBH_JT)
1003 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1004 MachineBasicBlock *MBB = JTBBs[i];
1005 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1007 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1008 if (OffsetWidth == 4) {
1010 BrInst.setOpcode(ARM::t2B);
1011 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
1012 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1013 BrInst.addOperand(MCOperand::CreateReg(0));
1014 OutStreamer.EmitInstruction(BrInst);
1017 // Otherwise it's an offset from the dispatch instruction. Construct an
1018 // MCExpr for the entry. We want a value of the form:
1019 // (BasicBlockAddr - TableBeginAddr) / 2
1021 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1024 // .byte (LBB0 - LJTI_0_0) / 2
1025 // .byte (LBB1 - LJTI_0_0) / 2
1026 const MCExpr *Expr =
1027 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1028 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1030 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1032 OutStreamer.EmitValue(Expr, OffsetWidth);
1036 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1038 unsigned NOps = MI->getNumOperands();
1040 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
1041 // cast away const; DIetc do not take const operands for some reason.
1042 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
1045 // Frame address. Currently handles register +- offset only.
1046 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
1047 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1050 printOperand(MI, NOps-2, OS);
1053 static void populateADROperands(MCInst &Inst, unsigned Dest,
1054 const MCSymbol *Label,
1055 unsigned pred, unsigned ccreg,
1057 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1058 Inst.addOperand(MCOperand::CreateReg(Dest));
1059 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1060 // Add predicate operands.
1061 Inst.addOperand(MCOperand::CreateImm(pred));
1062 Inst.addOperand(MCOperand::CreateReg(ccreg));
1065 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1069 // Emit the instruction as usual, just patch the opcode.
1070 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1071 TmpInst.setOpcode(Opcode);
1072 OutStreamer.EmitInstruction(TmpInst);
1075 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1076 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1077 "Only instruction which are involved into frame setup code are allowed");
1079 const MachineFunction &MF = *MI->getParent()->getParent();
1080 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1081 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1083 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1084 unsigned Opc = MI->getOpcode();
1085 unsigned SrcReg, DstReg;
1087 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1088 // Two special cases:
1089 // 1) tPUSH does not have src/dst regs.
1090 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1091 // load. Yes, this is pretty fragile, but for now I don't see better
1093 SrcReg = DstReg = ARM::SP;
1095 SrcReg = MI->getOperand(1).getReg();
1096 DstReg = MI->getOperand(0).getReg();
1099 // Try to figure out the unwinding opcode out of src / dst regs.
1100 if (MI->mayStore()) {
1102 assert(DstReg == ARM::SP &&
1103 "Only stack pointer as a destination reg is supported");
1105 SmallVector<unsigned, 4> RegList;
1106 // Skip src & dst reg, and pred ops.
1107 unsigned StartOp = 2 + 2;
1108 // Use all the operands.
1109 unsigned NumOffset = 0;
1114 llvm_unreachable("Unsupported opcode for unwinding information");
1116 // Special case here: no src & dst reg, but two extra imp ops.
1117 StartOp = 2; NumOffset = 2;
1118 case ARM::STMDB_UPD:
1119 case ARM::t2STMDB_UPD:
1120 case ARM::VSTMDDB_UPD:
1121 assert(SrcReg == ARM::SP &&
1122 "Only stack pointer as a source reg is supported");
1123 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1125 RegList.push_back(MI->getOperand(i).getReg());
1127 case ARM::STR_PRE_IMM:
1128 case ARM::STR_PRE_REG:
1129 case ARM::t2STR_PRE:
1130 assert(MI->getOperand(2).getReg() == ARM::SP &&
1131 "Only stack pointer as a source reg is supported");
1132 RegList.push_back(SrcReg);
1135 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1137 // Changes of stack / frame pointer.
1138 if (SrcReg == ARM::SP) {
1143 llvm_unreachable("Unsupported opcode for unwinding information");
1149 Offset = -MI->getOperand(2).getImm();
1153 Offset = MI->getOperand(2).getImm();
1156 Offset = MI->getOperand(2).getImm()*4;
1160 Offset = -MI->getOperand(2).getImm()*4;
1162 case ARM::tLDRpci: {
1163 // Grab the constpool index and check, whether it corresponds to
1164 // original or cloned constpool entry.
1165 unsigned CPI = MI->getOperand(1).getIndex();
1166 const MachineConstantPool *MCP = MF.getConstantPool();
1167 if (CPI >= MCP->getConstants().size())
1168 CPI = AFI.getOriginalCPIdx(CPI);
1169 assert(CPI != -1U && "Invalid constpool index");
1171 // Derive the actual offset.
1172 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1173 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1174 // FIXME: Check for user, it should be "add" instruction!
1175 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1180 if (DstReg == FramePtr && FramePtr != ARM::SP)
1181 // Set-up of the frame pointer. Positive values correspond to "add"
1183 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1184 else if (DstReg == ARM::SP) {
1185 // Change of SP by an offset. Positive values correspond to "sub"
1187 OutStreamer.EmitPad(Offset);
1190 llvm_unreachable("Unsupported opcode for unwinding information");
1192 } else if (DstReg == ARM::SP) {
1193 // FIXME: .movsp goes here
1195 llvm_unreachable("Unsupported opcode for unwinding information");
1199 llvm_unreachable("Unsupported opcode for unwinding information");
1204 extern cl::opt<bool> EnableARMEHABI;
1206 // Simple pseudo-instructions have their lowering (with expansion to real
1207 // instructions) auto-generated.
1208 #include "ARMGenMCPseudoLowering.inc"
1210 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1211 if (MI->getOpcode() != ARM::CONSTPOOL_ENTRY)
1212 OutStreamer.EmitCodeRegion();
1214 // Emit unwinding stuff for frame-related instructions
1215 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1216 EmitUnwindingInstruction(MI);
1218 // Do any auto-generated pseudo lowerings.
1219 if (emitPseudoExpansionLowering(OutStreamer, MI))
1222 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1223 "Pseudo flag setting opcode should be expanded early");
1225 // Check for manual lowerings.
1226 unsigned Opc = MI->getOpcode();
1228 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1229 case ARM::DBG_VALUE: {
1230 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1231 SmallString<128> TmpStr;
1232 raw_svector_ostream OS(TmpStr);
1233 PrintDebugValueComment(MI, OS);
1234 OutStreamer.EmitRawText(StringRef(OS.str()));
1239 case ARM::tLEApcrel:
1240 case ARM::t2LEApcrel: {
1241 // FIXME: Need to also handle globals and externals
1243 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1244 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1246 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1247 GetCPISymbol(MI->getOperand(1).getIndex()),
1248 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1250 OutStreamer.EmitInstruction(TmpInst);
1253 case ARM::LEApcrelJT:
1254 case ARM::tLEApcrelJT:
1255 case ARM::t2LEApcrelJT: {
1257 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1258 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1260 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1261 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1262 MI->getOperand(2).getImm()),
1263 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1265 OutStreamer.EmitInstruction(TmpInst);
1268 // Darwin call instructions are just normal call instructions with different
1269 // clobber semantics (they clobber R9).
1270 case ARM::BX_CALL: {
1273 TmpInst.setOpcode(ARM::MOVr);
1274 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1275 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1276 // Add predicate operands.
1277 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1278 TmpInst.addOperand(MCOperand::CreateReg(0));
1279 // Add 's' bit operand (always reg0 for this)
1280 TmpInst.addOperand(MCOperand::CreateReg(0));
1281 OutStreamer.EmitInstruction(TmpInst);
1285 TmpInst.setOpcode(ARM::BX);
1286 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1287 OutStreamer.EmitInstruction(TmpInst);
1291 case ARM::tBX_CALL: {
1294 TmpInst.setOpcode(ARM::tMOVr);
1295 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1296 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1297 // Add predicate operands.
1298 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1299 TmpInst.addOperand(MCOperand::CreateReg(0));
1300 OutStreamer.EmitInstruction(TmpInst);
1304 TmpInst.setOpcode(ARM::tBX);
1305 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1306 // Add predicate operands.
1307 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1308 TmpInst.addOperand(MCOperand::CreateReg(0));
1309 OutStreamer.EmitInstruction(TmpInst);
1313 case ARM::BMOVPCRX_CALL: {
1316 TmpInst.setOpcode(ARM::MOVr);
1317 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1318 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1319 // Add predicate operands.
1320 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1321 TmpInst.addOperand(MCOperand::CreateReg(0));
1322 // Add 's' bit operand (always reg0 for this)
1323 TmpInst.addOperand(MCOperand::CreateReg(0));
1324 OutStreamer.EmitInstruction(TmpInst);
1328 TmpInst.setOpcode(ARM::MOVr);
1329 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1330 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1331 // Add predicate operands.
1332 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 // Add 's' bit operand (always reg0 for this)
1335 TmpInst.addOperand(MCOperand::CreateReg(0));
1336 OutStreamer.EmitInstruction(TmpInst);
1340 case ARM::BMOVPCB_CALL: {
1343 TmpInst.setOpcode(ARM::MOVr);
1344 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1345 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1346 // Add predicate operands.
1347 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1348 TmpInst.addOperand(MCOperand::CreateReg(0));
1349 // Add 's' bit operand (always reg0 for this)
1350 TmpInst.addOperand(MCOperand::CreateReg(0));
1351 OutStreamer.EmitInstruction(TmpInst);
1355 TmpInst.setOpcode(ARM::Bcc);
1356 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1357 MCSymbol *GVSym = Mang->getSymbol(GV);
1358 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1359 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1360 // Add predicate operands.
1361 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1362 TmpInst.addOperand(MCOperand::CreateReg(0));
1363 OutStreamer.EmitInstruction(TmpInst);
1367 case ARM::t2BMOVPCB_CALL: {
1370 TmpInst.setOpcode(ARM::tMOVr);
1371 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1372 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1373 // Add predicate operands.
1374 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1375 TmpInst.addOperand(MCOperand::CreateReg(0));
1376 OutStreamer.EmitInstruction(TmpInst);
1380 TmpInst.setOpcode(ARM::t2B);
1381 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1382 MCSymbol *GVSym = Mang->getSymbol(GV);
1383 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1384 TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
1385 // Add predicate operands.
1386 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1387 TmpInst.addOperand(MCOperand::CreateReg(0));
1388 OutStreamer.EmitInstruction(TmpInst);
1392 case ARM::MOVi16_ga_pcrel:
1393 case ARM::t2MOVi16_ga_pcrel: {
1395 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1396 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1398 unsigned TF = MI->getOperand(1).getTargetFlags();
1399 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1400 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1401 MCSymbol *GVSym = GetARMGVSymbol(GV);
1402 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1404 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1405 getFunctionNumber(),
1406 MI->getOperand(2).getImm(), OutContext);
1407 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1408 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1409 const MCExpr *PCRelExpr =
1410 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1411 MCBinaryExpr::CreateAdd(LabelSymExpr,
1412 MCConstantExpr::Create(PCAdj, OutContext),
1413 OutContext), OutContext), OutContext);
1414 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1416 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1417 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1420 // Add predicate operands.
1421 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1422 TmpInst.addOperand(MCOperand::CreateReg(0));
1423 // Add 's' bit operand (always reg0 for this)
1424 TmpInst.addOperand(MCOperand::CreateReg(0));
1425 OutStreamer.EmitInstruction(TmpInst);
1428 case ARM::MOVTi16_ga_pcrel:
1429 case ARM::t2MOVTi16_ga_pcrel: {
1431 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1432 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1433 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1434 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1436 unsigned TF = MI->getOperand(2).getTargetFlags();
1437 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1438 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1439 MCSymbol *GVSym = GetARMGVSymbol(GV);
1440 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1442 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1443 getFunctionNumber(),
1444 MI->getOperand(3).getImm(), OutContext);
1445 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1446 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1447 const MCExpr *PCRelExpr =
1448 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1449 MCBinaryExpr::CreateAdd(LabelSymExpr,
1450 MCConstantExpr::Create(PCAdj, OutContext),
1451 OutContext), OutContext), OutContext);
1452 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1454 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1455 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1457 // Add predicate operands.
1458 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1459 TmpInst.addOperand(MCOperand::CreateReg(0));
1460 // Add 's' bit operand (always reg0 for this)
1461 TmpInst.addOperand(MCOperand::CreateReg(0));
1462 OutStreamer.EmitInstruction(TmpInst);
1465 case ARM::tPICADD: {
1466 // This is a pseudo op for a label + instruction sequence, which looks like:
1469 // This adds the address of LPC0 to r0.
1472 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1473 getFunctionNumber(), MI->getOperand(2).getImm(),
1476 // Form and emit the add.
1478 AddInst.setOpcode(ARM::tADDhirr);
1479 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1480 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1481 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1482 // Add predicate operands.
1483 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1484 AddInst.addOperand(MCOperand::CreateReg(0));
1485 OutStreamer.EmitInstruction(AddInst);
1489 // This is a pseudo op for a label + instruction sequence, which looks like:
1492 // This adds the address of LPC0 to r0.
1495 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1496 getFunctionNumber(), MI->getOperand(2).getImm(),
1499 // Form and emit the add.
1501 AddInst.setOpcode(ARM::ADDrr);
1502 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1503 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1504 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1505 // Add predicate operands.
1506 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1507 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1508 // Add 's' bit operand (always reg0 for this)
1509 AddInst.addOperand(MCOperand::CreateReg(0));
1510 OutStreamer.EmitInstruction(AddInst);
1520 case ARM::PICLDRSH: {
1521 // This is a pseudo op for a label + instruction sequence, which looks like:
1524 // The LCP0 label is referenced by a constant pool entry in order to get
1525 // a PC-relative address at the ldr instruction.
1528 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1529 getFunctionNumber(), MI->getOperand(2).getImm(),
1532 // Form and emit the load
1534 switch (MI->getOpcode()) {
1536 llvm_unreachable("Unexpected opcode!");
1537 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1538 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1539 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1540 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1541 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1542 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1543 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1544 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1547 LdStInst.setOpcode(Opcode);
1548 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1549 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1550 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1551 LdStInst.addOperand(MCOperand::CreateImm(0));
1552 // Add predicate operands.
1553 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1554 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1555 OutStreamer.EmitInstruction(LdStInst);
1559 case ARM::CONSTPOOL_ENTRY: {
1560 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1561 /// in the function. The first operand is the ID# for this instruction, the
1562 /// second is the index into the MachineConstantPool that this is, the third
1563 /// is the size in bytes of this constant pool entry.
1564 /// The required alignment is specified on the basic block holding this MI.
1565 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1566 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1568 // Mark the constant pool entry as data if we're not already in a data
1570 OutStreamer.EmitDataRegion();
1571 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1573 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1574 if (MCPE.isMachineConstantPoolEntry())
1575 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1577 EmitGlobalConstant(MCPE.Val.ConstVal);
1580 case ARM::t2BR_JT: {
1581 // Lower and emit the instruction itself, then the jump table following it.
1583 TmpInst.setOpcode(ARM::tMOVr);
1584 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1585 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1586 // Add predicate operands.
1587 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1588 TmpInst.addOperand(MCOperand::CreateReg(0));
1589 OutStreamer.EmitInstruction(TmpInst);
1590 // Output the data for the jump table itself
1594 case ARM::t2TBB_JT: {
1595 // Lower and emit the instruction itself, then the jump table following it.
1598 TmpInst.setOpcode(ARM::t2TBB);
1599 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1600 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1601 // Add predicate operands.
1602 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1603 TmpInst.addOperand(MCOperand::CreateReg(0));
1604 OutStreamer.EmitInstruction(TmpInst);
1605 // Output the data for the jump table itself
1607 // Make sure the next instruction is 2-byte aligned.
1611 case ARM::t2TBH_JT: {
1612 // Lower and emit the instruction itself, then the jump table following it.
1615 TmpInst.setOpcode(ARM::t2TBH);
1616 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1617 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1618 // Add predicate operands.
1619 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1620 TmpInst.addOperand(MCOperand::CreateReg(0));
1621 OutStreamer.EmitInstruction(TmpInst);
1622 // Output the data for the jump table itself
1628 // Lower and emit the instruction itself, then the jump table following it.
1631 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1632 ARM::MOVr : ARM::tMOVr;
1633 TmpInst.setOpcode(Opc);
1634 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1635 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1636 // Add predicate operands.
1637 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1638 TmpInst.addOperand(MCOperand::CreateReg(0));
1639 // Add 's' bit operand (always reg0 for this)
1640 if (Opc == ARM::MOVr)
1641 TmpInst.addOperand(MCOperand::CreateReg(0));
1642 OutStreamer.EmitInstruction(TmpInst);
1644 // Make sure the Thumb jump table is 4-byte aligned.
1645 if (Opc == ARM::tMOVr)
1648 // Output the data for the jump table itself
1653 // Lower and emit the instruction itself, then the jump table following it.
1656 if (MI->getOperand(1).getReg() == 0) {
1658 TmpInst.setOpcode(ARM::LDRi12);
1659 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1660 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1661 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1663 TmpInst.setOpcode(ARM::LDRrs);
1664 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1665 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1666 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1667 TmpInst.addOperand(MCOperand::CreateImm(0));
1669 // Add predicate operands.
1670 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1671 TmpInst.addOperand(MCOperand::CreateReg(0));
1672 OutStreamer.EmitInstruction(TmpInst);
1674 // Output the data for the jump table itself
1678 case ARM::BR_JTadd: {
1679 // Lower and emit the instruction itself, then the jump table following it.
1680 // add pc, target, idx
1682 TmpInst.setOpcode(ARM::ADDrr);
1683 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1684 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1685 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1686 // Add predicate operands.
1687 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1688 TmpInst.addOperand(MCOperand::CreateReg(0));
1689 // Add 's' bit operand (always reg0 for this)
1690 TmpInst.addOperand(MCOperand::CreateReg(0));
1691 OutStreamer.EmitInstruction(TmpInst);
1693 // Output the data for the jump table itself
1698 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1699 // FIXME: Remove this special case when they do.
1700 if (!Subtarget->isTargetDarwin()) {
1701 //.long 0xe7ffdefe @ trap
1702 uint32_t Val = 0xe7ffdefeUL;
1703 OutStreamer.AddComment("trap");
1704 OutStreamer.EmitIntValue(Val, 4);
1710 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1711 // FIXME: Remove this special case when they do.
1712 if (!Subtarget->isTargetDarwin()) {
1713 //.short 57086 @ trap
1714 uint16_t Val = 0xdefe;
1715 OutStreamer.AddComment("trap");
1716 OutStreamer.EmitIntValue(Val, 2);
1721 case ARM::t2Int_eh_sjlj_setjmp:
1722 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1723 case ARM::tInt_eh_sjlj_setjmp: {
1724 // Two incoming args: GPR:$src, GPR:$val
1727 // str $val, [$src, #4]
1732 unsigned SrcReg = MI->getOperand(0).getReg();
1733 unsigned ValReg = MI->getOperand(1).getReg();
1734 MCSymbol *Label = GetARMSJLJEHLabel();
1737 TmpInst.setOpcode(ARM::tMOVr);
1738 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1739 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1741 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1742 TmpInst.addOperand(MCOperand::CreateReg(0));
1743 OutStreamer.AddComment("eh_setjmp begin");
1744 OutStreamer.EmitInstruction(TmpInst);
1748 TmpInst.setOpcode(ARM::tADDi3);
1749 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1751 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1752 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1753 TmpInst.addOperand(MCOperand::CreateImm(7));
1755 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1756 TmpInst.addOperand(MCOperand::CreateReg(0));
1757 OutStreamer.EmitInstruction(TmpInst);
1761 TmpInst.setOpcode(ARM::tSTRi);
1762 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1763 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1764 // The offset immediate is #4. The operand value is scaled by 4 for the
1765 // tSTR instruction.
1766 TmpInst.addOperand(MCOperand::CreateImm(1));
1768 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1769 TmpInst.addOperand(MCOperand::CreateReg(0));
1770 OutStreamer.EmitInstruction(TmpInst);
1774 TmpInst.setOpcode(ARM::tMOVi8);
1775 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1776 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1777 TmpInst.addOperand(MCOperand::CreateImm(0));
1779 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1780 TmpInst.addOperand(MCOperand::CreateReg(0));
1781 OutStreamer.EmitInstruction(TmpInst);
1784 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1786 TmpInst.setOpcode(ARM::tB);
1787 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1788 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1789 TmpInst.addOperand(MCOperand::CreateReg(0));
1790 OutStreamer.EmitInstruction(TmpInst);
1794 TmpInst.setOpcode(ARM::tMOVi8);
1795 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1796 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1797 TmpInst.addOperand(MCOperand::CreateImm(1));
1799 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1800 TmpInst.addOperand(MCOperand::CreateReg(0));
1801 OutStreamer.AddComment("eh_setjmp end");
1802 OutStreamer.EmitInstruction(TmpInst);
1804 OutStreamer.EmitLabel(Label);
1808 case ARM::Int_eh_sjlj_setjmp_nofp:
1809 case ARM::Int_eh_sjlj_setjmp: {
1810 // Two incoming args: GPR:$src, GPR:$val
1812 // str $val, [$src, #+4]
1816 unsigned SrcReg = MI->getOperand(0).getReg();
1817 unsigned ValReg = MI->getOperand(1).getReg();
1821 TmpInst.setOpcode(ARM::ADDri);
1822 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1823 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1824 TmpInst.addOperand(MCOperand::CreateImm(8));
1826 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1827 TmpInst.addOperand(MCOperand::CreateReg(0));
1828 // 's' bit operand (always reg0 for this).
1829 TmpInst.addOperand(MCOperand::CreateReg(0));
1830 OutStreamer.AddComment("eh_setjmp begin");
1831 OutStreamer.EmitInstruction(TmpInst);
1835 TmpInst.setOpcode(ARM::STRi12);
1836 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1837 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1838 TmpInst.addOperand(MCOperand::CreateImm(4));
1840 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1841 TmpInst.addOperand(MCOperand::CreateReg(0));
1842 OutStreamer.EmitInstruction(TmpInst);
1846 TmpInst.setOpcode(ARM::MOVi);
1847 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1848 TmpInst.addOperand(MCOperand::CreateImm(0));
1850 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1851 TmpInst.addOperand(MCOperand::CreateReg(0));
1852 // 's' bit operand (always reg0 for this).
1853 TmpInst.addOperand(MCOperand::CreateReg(0));
1854 OutStreamer.EmitInstruction(TmpInst);
1858 TmpInst.setOpcode(ARM::ADDri);
1859 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1860 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1861 TmpInst.addOperand(MCOperand::CreateImm(0));
1863 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1864 TmpInst.addOperand(MCOperand::CreateReg(0));
1865 // 's' bit operand (always reg0 for this).
1866 TmpInst.addOperand(MCOperand::CreateReg(0));
1867 OutStreamer.EmitInstruction(TmpInst);
1871 TmpInst.setOpcode(ARM::MOVi);
1872 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1873 TmpInst.addOperand(MCOperand::CreateImm(1));
1875 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1876 TmpInst.addOperand(MCOperand::CreateReg(0));
1877 // 's' bit operand (always reg0 for this).
1878 TmpInst.addOperand(MCOperand::CreateReg(0));
1879 OutStreamer.AddComment("eh_setjmp end");
1880 OutStreamer.EmitInstruction(TmpInst);
1884 case ARM::Int_eh_sjlj_longjmp: {
1885 // ldr sp, [$src, #8]
1886 // ldr $scratch, [$src, #4]
1889 unsigned SrcReg = MI->getOperand(0).getReg();
1890 unsigned ScratchReg = MI->getOperand(1).getReg();
1893 TmpInst.setOpcode(ARM::LDRi12);
1894 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1895 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1896 TmpInst.addOperand(MCOperand::CreateImm(8));
1898 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1899 TmpInst.addOperand(MCOperand::CreateReg(0));
1900 OutStreamer.EmitInstruction(TmpInst);
1904 TmpInst.setOpcode(ARM::LDRi12);
1905 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1906 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1907 TmpInst.addOperand(MCOperand::CreateImm(4));
1909 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1910 TmpInst.addOperand(MCOperand::CreateReg(0));
1911 OutStreamer.EmitInstruction(TmpInst);
1915 TmpInst.setOpcode(ARM::LDRi12);
1916 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1917 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1918 TmpInst.addOperand(MCOperand::CreateImm(0));
1920 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1921 TmpInst.addOperand(MCOperand::CreateReg(0));
1922 OutStreamer.EmitInstruction(TmpInst);
1926 TmpInst.setOpcode(ARM::BX);
1927 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1929 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1930 TmpInst.addOperand(MCOperand::CreateReg(0));
1931 OutStreamer.EmitInstruction(TmpInst);
1935 case ARM::tInt_eh_sjlj_longjmp: {
1936 // ldr $scratch, [$src, #8]
1938 // ldr $scratch, [$src, #4]
1941 unsigned SrcReg = MI->getOperand(0).getReg();
1942 unsigned ScratchReg = MI->getOperand(1).getReg();
1945 TmpInst.setOpcode(ARM::tLDRi);
1946 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1947 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1948 // The offset immediate is #8. The operand value is scaled by 4 for the
1949 // tLDR instruction.
1950 TmpInst.addOperand(MCOperand::CreateImm(2));
1952 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1953 TmpInst.addOperand(MCOperand::CreateReg(0));
1954 OutStreamer.EmitInstruction(TmpInst);
1958 TmpInst.setOpcode(ARM::tMOVr);
1959 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1960 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1962 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1963 TmpInst.addOperand(MCOperand::CreateReg(0));
1964 OutStreamer.EmitInstruction(TmpInst);
1968 TmpInst.setOpcode(ARM::tLDRi);
1969 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1970 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1971 TmpInst.addOperand(MCOperand::CreateImm(1));
1973 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1974 TmpInst.addOperand(MCOperand::CreateReg(0));
1975 OutStreamer.EmitInstruction(TmpInst);
1979 TmpInst.setOpcode(ARM::tLDRr);
1980 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1981 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1982 TmpInst.addOperand(MCOperand::CreateReg(0));
1984 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1985 TmpInst.addOperand(MCOperand::CreateReg(0));
1986 OutStreamer.EmitInstruction(TmpInst);
1990 TmpInst.setOpcode(ARM::tBX);
1991 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1993 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1994 TmpInst.addOperand(MCOperand::CreateReg(0));
1995 OutStreamer.EmitInstruction(TmpInst);
2002 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2004 OutStreamer.EmitInstruction(TmpInst);
2007 //===----------------------------------------------------------------------===//
2008 // Target Registry Stuff
2009 //===----------------------------------------------------------------------===//
2011 // Force static initialization.
2012 extern "C" void LLVMInitializeARMAsmPrinter() {
2013 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
2014 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);