1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMAsmPrinter.h"
18 #include "ARMBuildAttrs.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "InstPrinter/ARMInstPrinter.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "MCTargetDesc/ARMMCExpr.h"
27 #include "llvm/Analysis/DebugInfo.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Module.h"
30 #include "llvm/Type.h"
31 #include "llvm/Assembly/Writer.h"
32 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCExpr.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCSectionMachO.h"
41 #include "llvm/MC/MCObjectStreamer.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/Target/Mangler.h"
45 #include "llvm/Target/TargetData.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetOptions.h"
48 #include "llvm/ADT/SmallPtrSet.h"
49 #include "llvm/ADT/SmallString.h"
50 #include "llvm/ADT/StringExtras.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/TargetRegistry.h"
55 #include "llvm/Support/raw_ostream.h"
61 // Per section and per symbol attributes are not supported.
62 // To implement them we would need the ability to delay this emission
63 // until the assembly file is fully parsed/generated as only then do we
64 // know the symbol and section numbers.
65 class AttributeEmitter {
67 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
68 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
69 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
70 virtual void Finish() = 0;
71 virtual ~AttributeEmitter() {}
74 class AsmAttributeEmitter : public AttributeEmitter {
78 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
79 void MaybeSwitchVendor(StringRef Vendor) { }
81 void EmitAttribute(unsigned Attribute, unsigned Value) {
82 Streamer.EmitRawText("\t.eabi_attribute " +
83 Twine(Attribute) + ", " + Twine(Value));
86 void EmitTextAttribute(unsigned Attribute, StringRef String) {
88 case ARMBuildAttrs::CPU_name:
89 Streamer.EmitRawText(StringRef("\t.cpu ") + LowercaseString(String));
91 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
93 case ARMBuildAttrs::VFP_arch:
94 Streamer.EmitRawText(StringRef("\t.fpu ") + LowercaseString(String));
96 default: assert(0 && "Unsupported Text attribute in ASM Mode"); break;
102 class ObjectAttributeEmitter : public AttributeEmitter {
103 // This structure holds all attributes, accounting for
104 // their string/numeric value, so we can later emmit them
105 // in declaration order, keeping all in the same vector
106 struct AttributeItemType {
114 StringRef StringValue;
117 MCObjectStreamer &Streamer;
118 StringRef CurrentVendor;
119 SmallVector<AttributeItemType, 64> Contents;
121 // Account for the ULEB/String size of each item,
122 // not just the number of items
124 // FIXME: this should be in a more generic place, but
125 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
126 size_t getULEBSize(int Value) {
130 Size += sizeof(int8_t); // Is this really necessary?
136 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
137 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
139 void MaybeSwitchVendor(StringRef Vendor) {
140 assert(!Vendor.empty() && "Vendor cannot be empty.");
142 if (CurrentVendor.empty())
143 CurrentVendor = Vendor;
144 else if (CurrentVendor == Vendor)
149 CurrentVendor = Vendor;
151 assert(Contents.size() == 0);
154 void EmitAttribute(unsigned Attribute, unsigned Value) {
155 AttributeItemType attr = {
156 AttributeItemType::NumericAttribute,
161 ContentsSize += getULEBSize(Attribute);
162 ContentsSize += getULEBSize(Value);
163 Contents.push_back(attr);
166 void EmitTextAttribute(unsigned Attribute, StringRef String) {
167 AttributeItemType attr = {
168 AttributeItemType::TextAttribute,
173 ContentsSize += getULEBSize(Attribute);
175 ContentsSize += String.size()+1;
177 Contents.push_back(attr);
181 // Vendor size + Vendor name + '\0'
182 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
185 const size_t TagHeaderSize = 1 + 4;
187 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
188 Streamer.EmitBytes(CurrentVendor, 0);
189 Streamer.EmitIntValue(0, 1); // '\0'
191 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
192 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
194 // Size should have been accounted for already, now
195 // emit each field as its type (ULEB or String)
196 for (unsigned int i=0; i<Contents.size(); ++i) {
197 AttributeItemType item = Contents[i];
198 Streamer.EmitULEB128IntValue(item.Tag, 0);
200 case AttributeItemType::NumericAttribute:
201 Streamer.EmitULEB128IntValue(item.IntValue, 0);
203 case AttributeItemType::TextAttribute:
204 Streamer.EmitBytes(UppercaseString(item.StringValue), 0);
205 Streamer.EmitIntValue(0, 1); // '\0'
208 assert(0 && "Invalid attribute type");
216 } // end of anonymous namespace
218 MachineLocation ARMAsmPrinter::
219 getDebugValueLocation(const MachineInstr *MI) const {
220 MachineLocation Location;
221 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
222 // Frame address. Currently handles register +- offset only.
223 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
224 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
226 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
231 /// EmitDwarfRegOp - Emit dwarf register operation.
232 void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
233 const TargetRegisterInfo *RI = TM.getRegisterInfo();
234 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
235 AsmPrinter::EmitDwarfRegOp(MLoc);
237 unsigned Reg = MLoc.getReg();
238 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
239 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
240 // S registers are described as bit-pieces of a register
241 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
242 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
244 unsigned SReg = Reg - ARM::S0;
245 bool odd = SReg & 0x1;
246 unsigned Rx = 256 + (SReg >> 1);
248 OutStreamer.AddComment("DW_OP_regx for S register");
249 EmitInt8(dwarf::DW_OP_regx);
251 OutStreamer.AddComment(Twine(SReg));
255 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
256 EmitInt8(dwarf::DW_OP_bit_piece);
260 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
261 EmitInt8(dwarf::DW_OP_bit_piece);
265 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
266 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
267 // Q registers Q0-Q15 are described by composing two D registers together.
268 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)
270 unsigned QReg = Reg - ARM::Q0;
271 unsigned D1 = 256 + 2 * QReg;
272 unsigned D2 = D1 + 1;
274 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
275 EmitInt8(dwarf::DW_OP_regx);
277 OutStreamer.AddComment("DW_OP_piece 8");
278 EmitInt8(dwarf::DW_OP_piece);
281 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
282 EmitInt8(dwarf::DW_OP_regx);
284 OutStreamer.AddComment("DW_OP_piece 8");
285 EmitInt8(dwarf::DW_OP_piece);
291 void ARMAsmPrinter::EmitFunctionEntryLabel() {
292 if (AFI->isThumbFunction()) {
293 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
294 OutStreamer.EmitThumbFunc(CurrentFnSym);
297 OutStreamer.EmitLabel(CurrentFnSym);
300 /// runOnMachineFunction - This uses the EmitInstruction()
301 /// method to print assembly for each instruction.
303 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
304 AFI = MF.getInfo<ARMFunctionInfo>();
305 MCP = MF.getConstantPool();
307 return AsmPrinter::runOnMachineFunction(MF);
310 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
311 raw_ostream &O, const char *Modifier) {
312 const MachineOperand &MO = MI->getOperand(OpNum);
313 unsigned TF = MO.getTargetFlags();
315 switch (MO.getType()) {
317 assert(0 && "<unknown operand type>");
318 case MachineOperand::MO_Register: {
319 unsigned Reg = MO.getReg();
320 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
321 assert(!MO.getSubReg() && "Subregs should be eliminated!");
322 O << ARMInstPrinter::getRegisterName(Reg);
325 case MachineOperand::MO_Immediate: {
326 int64_t Imm = MO.getImm();
328 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
329 (TF == ARMII::MO_LO16))
331 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
332 (TF == ARMII::MO_HI16))
337 case MachineOperand::MO_MachineBasicBlock:
338 O << *MO.getMBB()->getSymbol();
340 case MachineOperand::MO_GlobalAddress: {
341 const GlobalValue *GV = MO.getGlobal();
342 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
343 (TF & ARMII::MO_LO16))
345 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
346 (TF & ARMII::MO_HI16))
348 O << *Mang->getSymbol(GV);
350 printOffset(MO.getOffset(), O);
351 if (TF == ARMII::MO_PLT)
355 case MachineOperand::MO_ExternalSymbol: {
356 O << *GetExternalSymbolSymbol(MO.getSymbolName());
357 if (TF == ARMII::MO_PLT)
361 case MachineOperand::MO_ConstantPoolIndex:
362 O << *GetCPISymbol(MO.getIndex());
364 case MachineOperand::MO_JumpTableIndex:
365 O << *GetJTISymbol(MO.getIndex());
370 //===--------------------------------------------------------------------===//
372 MCSymbol *ARMAsmPrinter::
373 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
374 const MachineBasicBlock *MBB) const {
375 SmallString<60> Name;
376 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
377 << getFunctionNumber() << '_' << uid << '_' << uid2
378 << "_set_" << MBB->getNumber();
379 return OutContext.GetOrCreateSymbol(Name.str());
382 MCSymbol *ARMAsmPrinter::
383 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
384 SmallString<60> Name;
385 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
386 << getFunctionNumber() << '_' << uid << '_' << uid2;
387 return OutContext.GetOrCreateSymbol(Name.str());
391 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
392 SmallString<60> Name;
393 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
394 << getFunctionNumber();
395 return OutContext.GetOrCreateSymbol(Name.str());
398 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
399 unsigned AsmVariant, const char *ExtraCode,
401 // Does this asm operand have a single letter operand modifier?
402 if (ExtraCode && ExtraCode[0]) {
403 if (ExtraCode[1] != 0) return true; // Unknown modifier.
405 switch (ExtraCode[0]) {
406 default: return true; // Unknown modifier.
407 case 'a': // Print as a memory address.
408 if (MI->getOperand(OpNum).isReg()) {
410 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
415 case 'c': // Don't print "#" before an immediate operand.
416 if (!MI->getOperand(OpNum).isImm())
418 O << MI->getOperand(OpNum).getImm();
420 case 'P': // Print a VFP double precision register.
421 case 'q': // Print a NEON quad precision register.
422 printOperand(MI, OpNum, O);
424 case 'y': // Print a VFP single precision register as indexed double.
425 // This uses the ordering of the alias table to get the first 'd' register
426 // that overlaps the 's' register. Also, s0 is an odd register, hence the
427 // odd modulus check below.
428 if (MI->getOperand(OpNum).isReg()) {
429 unsigned Reg = MI->getOperand(OpNum).getReg();
430 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
431 O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
432 (((Reg % 2) == 1) ? "[0]" : "[1]");
436 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
437 if (!MI->getOperand(OpNum).isImm())
439 O << ~(MI->getOperand(OpNum).getImm());
441 case 'L': // The low 16 bits of an immediate constant.
442 if (!MI->getOperand(OpNum).isImm())
444 O << (MI->getOperand(OpNum).getImm() & 0xffff);
446 case 'M': { // A register range suitable for LDM/STM.
447 if (!MI->getOperand(OpNum).isReg())
449 const MachineOperand &MO = MI->getOperand(OpNum);
450 unsigned RegBegin = MO.getReg();
451 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
452 // already got the operands in registers that are operands to the
453 // inline asm statement.
455 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
457 // FIXME: The register allocator not only may not have given us the
458 // registers in sequence, but may not be in ascending registers. This
459 // will require changes in the register allocator that'll need to be
460 // propagated down here if the operands change.
461 unsigned RegOps = OpNum + 1;
462 while (MI->getOperand(RegOps).isReg()) {
464 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
472 case 'R': // The most significant register of a pair.
473 case 'Q': { // The least significant register of a pair.
476 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
477 if (!FlagsOP.isImm())
479 unsigned Flags = FlagsOP.getImm();
480 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
483 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
484 if (RegOp >= MI->getNumOperands())
486 const MachineOperand &MO = MI->getOperand(RegOp);
489 unsigned Reg = MO.getReg();
490 O << ARMInstPrinter::getRegisterName(Reg);
494 // These modifiers are not yet supported.
495 case 'p': // The high single-precision register of a VFP double-precision
497 case 'e': // The low doubleword register of a NEON quad register.
498 case 'f': // The high doubleword register of a NEON quad register.
499 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
500 case 'H': // The highest-numbered register of a pair.
505 printOperand(MI, OpNum, O);
509 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
510 unsigned OpNum, unsigned AsmVariant,
511 const char *ExtraCode,
513 // Does this asm operand have a single letter operand modifier?
514 if (ExtraCode && ExtraCode[0]) {
515 if (ExtraCode[1] != 0) return true; // Unknown modifier.
517 switch (ExtraCode[0]) {
518 case 'A': // A memory operand for a VLD1/VST1 instruction.
519 default: return true; // Unknown modifier.
520 case 'm': // The base register of a memory operand.
521 if (!MI->getOperand(OpNum).isReg())
523 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
528 const MachineOperand &MO = MI->getOperand(OpNum);
529 assert(MO.isReg() && "unexpected inline asm memory operand");
530 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
534 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
535 if (Subtarget->isTargetDarwin()) {
536 Reloc::Model RelocM = TM.getRelocationModel();
537 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
538 // Declare all the text sections up front (before the DWARF sections
539 // emitted by AsmPrinter::doInitialization) so the assembler will keep
540 // them together at the beginning of the object file. This helps
541 // avoid out-of-range branches that are due a fundamental limitation of
542 // the way symbol offsets are encoded with the current Darwin ARM
544 const TargetLoweringObjectFileMachO &TLOFMacho =
545 static_cast<const TargetLoweringObjectFileMachO &>(
546 getObjFileLowering());
547 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
548 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
549 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
550 if (RelocM == Reloc::DynamicNoPIC) {
551 const MCSection *sect =
552 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
553 MCSectionMachO::S_SYMBOL_STUBS,
554 12, SectionKind::getText());
555 OutStreamer.SwitchSection(sect);
557 const MCSection *sect =
558 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
559 MCSectionMachO::S_SYMBOL_STUBS,
560 16, SectionKind::getText());
561 OutStreamer.SwitchSection(sect);
563 const MCSection *StaticInitSect =
564 OutContext.getMachOSection("__TEXT", "__StaticInit",
565 MCSectionMachO::S_REGULAR |
566 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
567 SectionKind::getText());
568 OutStreamer.SwitchSection(StaticInitSect);
572 // Use unified assembler syntax.
573 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
575 // Emit ARM Build Attributes
576 if (Subtarget->isTargetELF()) {
583 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
584 if (Subtarget->isTargetDarwin()) {
585 // All darwin targets use mach-o.
586 const TargetLoweringObjectFileMachO &TLOFMacho =
587 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
588 MachineModuleInfoMachO &MMIMacho =
589 MMI->getObjFileInfo<MachineModuleInfoMachO>();
591 // Output non-lazy-pointers for external and common global variables.
592 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
594 if (!Stubs.empty()) {
595 // Switch with ".non_lazy_symbol_pointer" directive.
596 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
598 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
600 OutStreamer.EmitLabel(Stubs[i].first);
601 // .indirect_symbol _foo
602 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
603 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
606 // External to current translation unit.
607 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
609 // Internal to current translation unit.
611 // When we place the LSDA into the TEXT section, the type info
612 // pointers need to be indirect and pc-rel. We accomplish this by
613 // using NLPs; however, sometimes the types are local to the file.
614 // We need to fill in the value for the NLP in those cases.
615 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
617 4/*size*/, 0/*addrspace*/);
621 OutStreamer.AddBlankLine();
624 Stubs = MMIMacho.GetHiddenGVStubList();
625 if (!Stubs.empty()) {
626 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
628 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
630 OutStreamer.EmitLabel(Stubs[i].first);
632 OutStreamer.EmitValue(MCSymbolRefExpr::
633 Create(Stubs[i].second.getPointer(),
635 4/*size*/, 0/*addrspace*/);
639 OutStreamer.AddBlankLine();
642 // Funny Darwin hack: This flag tells the linker that no global symbols
643 // contain code that falls through to other global symbols (e.g. the obvious
644 // implementation of multiple entry points). If this doesn't occur, the
645 // linker can safely perform dead code stripping. Since LLVM never
646 // generates code that does this, it is always safe to set.
647 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
651 //===----------------------------------------------------------------------===//
652 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
654 // The following seem like one-off assembler flags, but they actually need
655 // to appear in the .ARM.attributes section in ELF.
656 // Instead of subclassing the MCELFStreamer, we do the work here.
658 void ARMAsmPrinter::emitAttributes() {
660 emitARMAttributeSection();
662 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
663 bool emitFPU = false;
664 AttributeEmitter *AttrEmitter;
665 if (OutStreamer.hasRawTextSupport()) {
666 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
669 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
670 AttrEmitter = new ObjectAttributeEmitter(O);
673 AttrEmitter->MaybeSwitchVendor("aeabi");
675 std::string CPUString = Subtarget->getCPUString();
677 if (CPUString == "cortex-a8" ||
678 Subtarget->isCortexA8()) {
679 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
680 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
681 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
682 ARMBuildAttrs::ApplicationProfile);
683 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
684 ARMBuildAttrs::Allowed);
685 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
686 ARMBuildAttrs::AllowThumb32);
687 // Fixme: figure out when this is emitted.
688 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
689 // ARMBuildAttrs::AllowWMMXv1);
692 /// ADD additional Else-cases here!
693 } else if (CPUString == "xscale") {
694 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
695 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
696 ARMBuildAttrs::Allowed);
697 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
698 ARMBuildAttrs::Allowed);
699 } else if (CPUString == "generic") {
700 // FIXME: Why these defaults?
701 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
702 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
703 ARMBuildAttrs::Allowed);
704 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
705 ARMBuildAttrs::Allowed);
708 if (Subtarget->hasNEON() && emitFPU) {
709 /* NEON is not exactly a VFP architecture, but GAS emit one of
710 * neon/vfpv3/vfpv2 for .fpu parameters */
711 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
712 /* If emitted for NEON, omit from VFP below, since you can have both
713 * NEON and VFP in build attributes but only one .fpu */
718 if (Subtarget->hasVFP3()) {
719 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
720 ARMBuildAttrs::AllowFPv3A);
722 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
725 } else if (Subtarget->hasVFP2()) {
726 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
727 ARMBuildAttrs::AllowFPv2);
729 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
732 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
733 * since NEON can have 1 (allowed) or 2 (MAC operations) */
734 if (Subtarget->hasNEON()) {
735 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
736 ARMBuildAttrs::Allowed);
739 // Signal various FP modes.
741 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
742 ARMBuildAttrs::Allowed);
743 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
744 ARMBuildAttrs::Allowed);
747 if (NoInfsFPMath && NoNaNsFPMath)
748 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
749 ARMBuildAttrs::Allowed);
751 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
752 ARMBuildAttrs::AllowIEE754);
754 // FIXME: add more flags to ARMBuildAttrs.h
755 // 8-bytes alignment stuff.
756 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
757 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
759 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
760 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
761 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
762 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
764 // FIXME: Should we signal R9 usage?
766 if (Subtarget->hasDivide())
767 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
769 AttrEmitter->Finish();
773 void ARMAsmPrinter::emitARMAttributeSection() {
775 // [ <section-length> "vendor-name"
776 // [ <file-tag> <size> <attribute>*
777 // | <section-tag> <size> <section-number>* 0 <attribute>*
778 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
782 if (OutStreamer.hasRawTextSupport())
785 const ARMElfTargetObjectFile &TLOFELF =
786 static_cast<const ARMElfTargetObjectFile &>
787 (getObjFileLowering());
789 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
792 OutStreamer.EmitIntValue(0x41, 1);
795 //===----------------------------------------------------------------------===//
797 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
798 unsigned LabelId, MCContext &Ctx) {
800 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
801 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
805 static MCSymbolRefExpr::VariantKind
806 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
808 default: llvm_unreachable("Unknown modifier!");
809 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
810 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
811 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
812 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
813 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
814 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
816 return MCSymbolRefExpr::VK_None;
819 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
820 bool isIndirect = Subtarget->isTargetDarwin() &&
821 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
823 return Mang->getSymbol(GV);
825 // FIXME: Remove this when Darwin transition to @GOT like syntax.
826 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
827 MachineModuleInfoMachO &MMIMachO =
828 MMI->getObjFileInfo<MachineModuleInfoMachO>();
829 MachineModuleInfoImpl::StubValueTy &StubSym =
830 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
831 MMIMachO.getGVStubEntry(MCSym);
832 if (StubSym.getPointer() == 0)
833 StubSym = MachineModuleInfoImpl::
834 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
839 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
840 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
842 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
845 if (ACPV->isLSDA()) {
846 SmallString<128> Str;
847 raw_svector_ostream OS(Str);
848 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
849 MCSym = OutContext.GetOrCreateSymbol(OS.str());
850 } else if (ACPV->isBlockAddress()) {
851 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
852 } else if (ACPV->isGlobalValue()) {
853 const GlobalValue *GV = ACPV->getGV();
854 MCSym = GetARMGVSymbol(GV);
856 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
857 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
860 // Create an MCSymbol for the reference.
862 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
865 if (ACPV->getPCAdjustment()) {
866 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
870 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
872 MCBinaryExpr::CreateAdd(PCRelExpr,
873 MCConstantExpr::Create(ACPV->getPCAdjustment(),
876 if (ACPV->mustAddCurrentAddress()) {
877 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
878 // label, so just emit a local label end reference that instead.
879 MCSymbol *DotSym = OutContext.CreateTempSymbol();
880 OutStreamer.EmitLabel(DotSym);
881 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
882 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
884 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
886 OutStreamer.EmitValue(Expr, Size);
889 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
890 unsigned Opcode = MI->getOpcode();
892 if (Opcode == ARM::BR_JTadd)
894 else if (Opcode == ARM::BR_JTm)
897 const MachineOperand &MO1 = MI->getOperand(OpNum);
898 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
899 unsigned JTI = MO1.getIndex();
901 // Emit a label for the jump table.
902 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
903 OutStreamer.EmitLabel(JTISymbol);
905 // Emit each entry of the table.
906 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
907 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
908 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
910 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
911 MachineBasicBlock *MBB = JTBBs[i];
912 // Construct an MCExpr for the entry. We want a value of the form:
913 // (BasicBlockAddr - TableBeginAddr)
915 // For example, a table with entries jumping to basic blocks BB0 and BB1
918 // .word (LBB0 - LJTI_0_0)
919 // .word (LBB1 - LJTI_0_0)
920 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
922 if (TM.getRelocationModel() == Reloc::PIC_)
923 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
926 // If we're generating a table of Thumb addresses in static relocation
927 // model, we need to add one to keep interworking correctly.
928 else if (AFI->isThumbFunction())
929 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
931 OutStreamer.EmitValue(Expr, 4);
935 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
936 unsigned Opcode = MI->getOpcode();
937 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
938 const MachineOperand &MO1 = MI->getOperand(OpNum);
939 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
940 unsigned JTI = MO1.getIndex();
942 // Emit a label for the jump table.
943 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
944 OutStreamer.EmitLabel(JTISymbol);
946 // Emit each entry of the table.
947 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
948 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
949 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
950 unsigned OffsetWidth = 4;
951 if (MI->getOpcode() == ARM::t2TBB_JT)
953 else if (MI->getOpcode() == ARM::t2TBH_JT)
956 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
957 MachineBasicBlock *MBB = JTBBs[i];
958 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
960 // If this isn't a TBB or TBH, the entries are direct branch instructions.
961 if (OffsetWidth == 4) {
963 BrInst.setOpcode(ARM::t2B);
964 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
965 OutStreamer.EmitInstruction(BrInst);
968 // Otherwise it's an offset from the dispatch instruction. Construct an
969 // MCExpr for the entry. We want a value of the form:
970 // (BasicBlockAddr - TableBeginAddr) / 2
972 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
975 // .byte (LBB0 - LJTI_0_0) / 2
976 // .byte (LBB1 - LJTI_0_0) / 2
978 MCBinaryExpr::CreateSub(MBBSymbolExpr,
979 MCSymbolRefExpr::Create(JTISymbol, OutContext),
981 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
983 OutStreamer.EmitValue(Expr, OffsetWidth);
987 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
989 unsigned NOps = MI->getNumOperands();
991 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
992 // cast away const; DIetc do not take const operands for some reason.
993 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
996 // Frame address. Currently handles register +- offset only.
997 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
998 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
1001 printOperand(MI, NOps-2, OS);
1004 static void populateADROperands(MCInst &Inst, unsigned Dest,
1005 const MCSymbol *Label,
1006 unsigned pred, unsigned ccreg,
1008 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
1009 Inst.addOperand(MCOperand::CreateReg(Dest));
1010 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1011 // Add predicate operands.
1012 Inst.addOperand(MCOperand::CreateImm(pred));
1013 Inst.addOperand(MCOperand::CreateReg(ccreg));
1016 void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI,
1020 // Emit the instruction as usual, just patch the opcode.
1021 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1022 TmpInst.setOpcode(Opcode);
1023 OutStreamer.EmitInstruction(TmpInst);
1026 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1027 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1028 "Only instruction which are involved into frame setup code are allowed");
1030 const MachineFunction &MF = *MI->getParent()->getParent();
1031 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
1032 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1034 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1035 unsigned Opc = MI->getOpcode();
1036 unsigned SrcReg, DstReg;
1038 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1039 // Two special cases:
1040 // 1) tPUSH does not have src/dst regs.
1041 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1042 // load. Yes, this is pretty fragile, but for now I don't see better
1044 SrcReg = DstReg = ARM::SP;
1046 SrcReg = MI->getOperand(1).getReg();
1047 DstReg = MI->getOperand(0).getReg();
1050 // Try to figure out the unwinding opcode out of src / dst regs.
1051 if (MI->getDesc().mayStore()) {
1053 assert(DstReg == ARM::SP &&
1054 "Only stack pointer as a destination reg is supported");
1056 SmallVector<unsigned, 4> RegList;
1057 // Skip src & dst reg, and pred ops.
1058 unsigned StartOp = 2 + 2;
1059 // Use all the operands.
1060 unsigned NumOffset = 0;
1065 assert(0 && "Unsupported opcode for unwinding information");
1067 // Special case here: no src & dst reg, but two extra imp ops.
1068 StartOp = 2; NumOffset = 2;
1069 case ARM::STMDB_UPD:
1070 case ARM::t2STMDB_UPD:
1071 case ARM::VSTMDDB_UPD:
1072 assert(SrcReg == ARM::SP &&
1073 "Only stack pointer as a source reg is supported");
1074 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1076 RegList.push_back(MI->getOperand(i).getReg());
1078 case ARM::STR_PRE_IMM:
1079 case ARM::STR_PRE_REG:
1080 assert(MI->getOperand(2).getReg() == ARM::SP &&
1081 "Only stack pointer as a source reg is supported");
1082 RegList.push_back(SrcReg);
1085 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1087 // Changes of stack / frame pointer.
1088 if (SrcReg == ARM::SP) {
1093 assert(0 && "Unsupported opcode for unwinding information");
1098 Offset = -MI->getOperand(2).getImm();
1101 Offset = MI->getOperand(2).getImm();
1104 Offset = MI->getOperand(2).getImm()*4;
1108 Offset = -MI->getOperand(2).getImm()*4;
1110 case ARM::tLDRpci: {
1111 // Grab the constpool index and check, whether it corresponds to
1112 // original or cloned constpool entry.
1113 unsigned CPI = MI->getOperand(1).getIndex();
1114 const MachineConstantPool *MCP = MF.getConstantPool();
1115 if (CPI >= MCP->getConstants().size())
1116 CPI = AFI.getOriginalCPIdx(CPI);
1117 assert(CPI != -1U && "Invalid constpool index");
1119 // Derive the actual offset.
1120 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1121 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1122 // FIXME: Check for user, it should be "add" instruction!
1123 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1128 if (DstReg == FramePtr && FramePtr != ARM::SP)
1129 // Set-up of the frame pointer. Positive values correspond to "add"
1131 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
1132 else if (DstReg == ARM::SP) {
1133 // Change of SP by an offset. Positive values correspond to "sub"
1135 OutStreamer.EmitPad(Offset);
1138 assert(0 && "Unsupported opcode for unwinding information");
1140 } else if (DstReg == ARM::SP) {
1141 // FIXME: .movsp goes here
1143 assert(0 && "Unsupported opcode for unwinding information");
1147 assert(0 && "Unsupported opcode for unwinding information");
1152 extern cl::opt<bool> EnableARMEHABI;
1154 // Simple pseudo-instructions have their lowering (with expansion to real
1155 // instructions) auto-generated.
1156 #include "ARMGenMCPseudoLowering.inc"
1158 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1159 // Emit unwinding stuff for frame-related instructions
1160 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
1161 EmitUnwindingInstruction(MI);
1163 // Do any auto-generated pseudo lowerings.
1164 if (emitPseudoExpansionLowering(OutStreamer, MI))
1167 // Check for manual lowerings.
1168 unsigned Opc = MI->getOpcode();
1170 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
1171 case ARM::DBG_VALUE: {
1172 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
1173 SmallString<128> TmpStr;
1174 raw_svector_ostream OS(TmpStr);
1175 PrintDebugValueComment(MI, OS);
1176 OutStreamer.EmitRawText(StringRef(OS.str()));
1181 case ARM::tLEApcrel:
1182 case ARM::t2LEApcrel: {
1183 // FIXME: Need to also handle globals and externals
1185 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
1186 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1188 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1189 GetCPISymbol(MI->getOperand(1).getIndex()),
1190 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
1192 OutStreamer.EmitInstruction(TmpInst);
1195 case ARM::LEApcrelJT:
1196 case ARM::tLEApcrelJT:
1197 case ARM::t2LEApcrelJT: {
1199 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
1200 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1202 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
1203 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1204 MI->getOperand(2).getImm()),
1205 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
1207 OutStreamer.EmitInstruction(TmpInst);
1210 // Darwin call instructions are just normal call instructions with different
1211 // clobber semantics (they clobber R9).
1212 case ARM::BXr9_CALL:
1213 case ARM::BX_CALL: {
1216 TmpInst.setOpcode(ARM::MOVr);
1217 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1218 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1219 // Add predicate operands.
1220 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1221 TmpInst.addOperand(MCOperand::CreateReg(0));
1222 // Add 's' bit operand (always reg0 for this)
1223 TmpInst.addOperand(MCOperand::CreateReg(0));
1224 OutStreamer.EmitInstruction(TmpInst);
1228 TmpInst.setOpcode(ARM::BX);
1229 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1230 OutStreamer.EmitInstruction(TmpInst);
1234 case ARM::tBXr9_CALL:
1235 case ARM::tBX_CALL: {
1238 TmpInst.setOpcode(ARM::tMOVr);
1239 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1240 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1241 // Add predicate operands.
1242 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1243 TmpInst.addOperand(MCOperand::CreateReg(0));
1244 OutStreamer.EmitInstruction(TmpInst);
1248 TmpInst.setOpcode(ARM::tBX);
1249 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1250 // Add predicate operands.
1251 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1252 TmpInst.addOperand(MCOperand::CreateReg(0));
1253 OutStreamer.EmitInstruction(TmpInst);
1257 case ARM::BMOVPCRXr9_CALL:
1258 case ARM::BMOVPCRX_CALL: {
1261 TmpInst.setOpcode(ARM::MOVr);
1262 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
1263 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1264 // Add predicate operands.
1265 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1266 TmpInst.addOperand(MCOperand::CreateReg(0));
1267 // Add 's' bit operand (always reg0 for this)
1268 TmpInst.addOperand(MCOperand::CreateReg(0));
1269 OutStreamer.EmitInstruction(TmpInst);
1273 TmpInst.setOpcode(ARM::MOVr);
1274 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1275 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1276 // Add predicate operands.
1277 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1278 TmpInst.addOperand(MCOperand::CreateReg(0));
1279 // Add 's' bit operand (always reg0 for this)
1280 TmpInst.addOperand(MCOperand::CreateReg(0));
1281 OutStreamer.EmitInstruction(TmpInst);
1285 case ARM::MOVi16_ga_pcrel:
1286 case ARM::t2MOVi16_ga_pcrel: {
1288 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1289 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1291 unsigned TF = MI->getOperand(1).getTargetFlags();
1292 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
1293 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1294 MCSymbol *GVSym = GetARMGVSymbol(GV);
1295 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1297 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1298 getFunctionNumber(),
1299 MI->getOperand(2).getImm(), OutContext);
1300 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1301 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1302 const MCExpr *PCRelExpr =
1303 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1304 MCBinaryExpr::CreateAdd(LabelSymExpr,
1305 MCConstantExpr::Create(PCAdj, OutContext),
1306 OutContext), OutContext), OutContext);
1307 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1309 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1310 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1313 // Add predicate operands.
1314 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1315 TmpInst.addOperand(MCOperand::CreateReg(0));
1316 // Add 's' bit operand (always reg0 for this)
1317 TmpInst.addOperand(MCOperand::CreateReg(0));
1318 OutStreamer.EmitInstruction(TmpInst);
1321 case ARM::MOVTi16_ga_pcrel:
1322 case ARM::t2MOVTi16_ga_pcrel: {
1324 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1325 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1326 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1327 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1329 unsigned TF = MI->getOperand(2).getTargetFlags();
1330 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
1331 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1332 MCSymbol *GVSym = GetARMGVSymbol(GV);
1333 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
1335 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1336 getFunctionNumber(),
1337 MI->getOperand(3).getImm(), OutContext);
1338 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1339 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1340 const MCExpr *PCRelExpr =
1341 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1342 MCBinaryExpr::CreateAdd(LabelSymExpr,
1343 MCConstantExpr::Create(PCAdj, OutContext),
1344 OutContext), OutContext), OutContext);
1345 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1347 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1348 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1350 // Add predicate operands.
1351 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1352 TmpInst.addOperand(MCOperand::CreateReg(0));
1353 // Add 's' bit operand (always reg0 for this)
1354 TmpInst.addOperand(MCOperand::CreateReg(0));
1355 OutStreamer.EmitInstruction(TmpInst);
1358 case ARM::tPICADD: {
1359 // This is a pseudo op for a label + instruction sequence, which looks like:
1362 // This adds the address of LPC0 to r0.
1365 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1366 getFunctionNumber(), MI->getOperand(2).getImm(),
1369 // Form and emit the add.
1371 AddInst.setOpcode(ARM::tADDhirr);
1372 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1373 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1374 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1375 // Add predicate operands.
1376 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1377 AddInst.addOperand(MCOperand::CreateReg(0));
1378 OutStreamer.EmitInstruction(AddInst);
1382 // This is a pseudo op for a label + instruction sequence, which looks like:
1385 // This adds the address of LPC0 to r0.
1388 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1389 getFunctionNumber(), MI->getOperand(2).getImm(),
1392 // Form and emit the add.
1394 AddInst.setOpcode(ARM::ADDrr);
1395 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1396 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1397 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1398 // Add predicate operands.
1399 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1400 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1401 // Add 's' bit operand (always reg0 for this)
1402 AddInst.addOperand(MCOperand::CreateReg(0));
1403 OutStreamer.EmitInstruction(AddInst);
1413 case ARM::PICLDRSH: {
1414 // This is a pseudo op for a label + instruction sequence, which looks like:
1417 // The LCP0 label is referenced by a constant pool entry in order to get
1418 // a PC-relative address at the ldr instruction.
1421 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1422 getFunctionNumber(), MI->getOperand(2).getImm(),
1425 // Form and emit the load
1427 switch (MI->getOpcode()) {
1429 llvm_unreachable("Unexpected opcode!");
1430 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1431 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1432 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1433 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1434 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1435 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1436 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1437 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1440 LdStInst.setOpcode(Opcode);
1441 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1442 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
1443 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1444 LdStInst.addOperand(MCOperand::CreateImm(0));
1445 // Add predicate operands.
1446 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
1447 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
1448 OutStreamer.EmitInstruction(LdStInst);
1452 case ARM::CONSTPOOL_ENTRY: {
1453 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1454 /// in the function. The first operand is the ID# for this instruction, the
1455 /// second is the index into the MachineConstantPool that this is, the third
1456 /// is the size in bytes of this constant pool entry.
1457 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1458 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1461 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1463 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1464 if (MCPE.isMachineConstantPoolEntry())
1465 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1467 EmitGlobalConstant(MCPE.Val.ConstVal);
1471 case ARM::t2BR_JT: {
1472 // Lower and emit the instruction itself, then the jump table following it.
1474 TmpInst.setOpcode(ARM::tMOVr);
1475 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1476 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1477 // Add predicate operands.
1478 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1479 TmpInst.addOperand(MCOperand::CreateReg(0));
1480 OutStreamer.EmitInstruction(TmpInst);
1481 // Output the data for the jump table itself
1485 case ARM::t2TBB_JT: {
1486 // Lower and emit the instruction itself, then the jump table following it.
1489 TmpInst.setOpcode(ARM::t2TBB);
1490 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1491 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1492 // Add predicate operands.
1493 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1494 TmpInst.addOperand(MCOperand::CreateReg(0));
1495 OutStreamer.EmitInstruction(TmpInst);
1496 // Output the data for the jump table itself
1498 // Make sure the next instruction is 2-byte aligned.
1502 case ARM::t2TBH_JT: {
1503 // Lower and emit the instruction itself, then the jump table following it.
1506 TmpInst.setOpcode(ARM::t2TBH);
1507 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1508 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1509 // Add predicate operands.
1510 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1511 TmpInst.addOperand(MCOperand::CreateReg(0));
1512 OutStreamer.EmitInstruction(TmpInst);
1513 // Output the data for the jump table itself
1519 // Lower and emit the instruction itself, then the jump table following it.
1522 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1523 ARM::MOVr : ARM::tMOVr;
1524 TmpInst.setOpcode(Opc);
1525 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1526 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1527 // Add predicate operands.
1528 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1529 TmpInst.addOperand(MCOperand::CreateReg(0));
1530 // Add 's' bit operand (always reg0 for this)
1531 if (Opc == ARM::MOVr)
1532 TmpInst.addOperand(MCOperand::CreateReg(0));
1533 OutStreamer.EmitInstruction(TmpInst);
1535 // Make sure the Thumb jump table is 4-byte aligned.
1536 if (Opc == ARM::tMOVr)
1539 // Output the data for the jump table itself
1544 // Lower and emit the instruction itself, then the jump table following it.
1547 if (MI->getOperand(1).getReg() == 0) {
1549 TmpInst.setOpcode(ARM::LDRi12);
1550 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1551 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1552 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1554 TmpInst.setOpcode(ARM::LDRrs);
1555 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1556 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1557 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1558 TmpInst.addOperand(MCOperand::CreateImm(0));
1560 // Add predicate operands.
1561 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1562 TmpInst.addOperand(MCOperand::CreateReg(0));
1563 OutStreamer.EmitInstruction(TmpInst);
1565 // Output the data for the jump table itself
1569 case ARM::BR_JTadd: {
1570 // Lower and emit the instruction itself, then the jump table following it.
1571 // add pc, target, idx
1573 TmpInst.setOpcode(ARM::ADDrr);
1574 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1575 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1576 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1577 // Add predicate operands.
1578 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1579 TmpInst.addOperand(MCOperand::CreateReg(0));
1580 // Add 's' bit operand (always reg0 for this)
1581 TmpInst.addOperand(MCOperand::CreateReg(0));
1582 OutStreamer.EmitInstruction(TmpInst);
1584 // Output the data for the jump table itself
1589 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1590 // FIXME: Remove this special case when they do.
1591 if (!Subtarget->isTargetDarwin()) {
1592 //.long 0xe7ffdefe @ trap
1593 uint32_t Val = 0xe7ffdefeUL;
1594 OutStreamer.AddComment("trap");
1595 OutStreamer.EmitIntValue(Val, 4);
1601 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1602 // FIXME: Remove this special case when they do.
1603 if (!Subtarget->isTargetDarwin()) {
1604 //.short 57086 @ trap
1605 uint16_t Val = 0xdefe;
1606 OutStreamer.AddComment("trap");
1607 OutStreamer.EmitIntValue(Val, 2);
1612 case ARM::t2Int_eh_sjlj_setjmp:
1613 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1614 case ARM::tInt_eh_sjlj_setjmp: {
1615 // Two incoming args: GPR:$src, GPR:$val
1618 // str $val, [$src, #4]
1623 unsigned SrcReg = MI->getOperand(0).getReg();
1624 unsigned ValReg = MI->getOperand(1).getReg();
1625 MCSymbol *Label = GetARMSJLJEHLabel();
1628 TmpInst.setOpcode(ARM::tMOVr);
1629 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1630 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1632 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1633 TmpInst.addOperand(MCOperand::CreateReg(0));
1634 OutStreamer.AddComment("eh_setjmp begin");
1635 OutStreamer.EmitInstruction(TmpInst);
1639 TmpInst.setOpcode(ARM::tADDi3);
1640 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1642 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1643 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1644 TmpInst.addOperand(MCOperand::CreateImm(7));
1646 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1647 TmpInst.addOperand(MCOperand::CreateReg(0));
1648 OutStreamer.EmitInstruction(TmpInst);
1652 TmpInst.setOpcode(ARM::tSTRi);
1653 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1654 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1655 // The offset immediate is #4. The operand value is scaled by 4 for the
1656 // tSTR instruction.
1657 TmpInst.addOperand(MCOperand::CreateImm(1));
1659 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1660 TmpInst.addOperand(MCOperand::CreateReg(0));
1661 OutStreamer.EmitInstruction(TmpInst);
1665 TmpInst.setOpcode(ARM::tMOVi8);
1666 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1667 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1668 TmpInst.addOperand(MCOperand::CreateImm(0));
1670 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1671 TmpInst.addOperand(MCOperand::CreateReg(0));
1672 OutStreamer.EmitInstruction(TmpInst);
1675 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1677 TmpInst.setOpcode(ARM::tB);
1678 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1679 OutStreamer.EmitInstruction(TmpInst);
1683 TmpInst.setOpcode(ARM::tMOVi8);
1684 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1685 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1686 TmpInst.addOperand(MCOperand::CreateImm(1));
1688 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1689 TmpInst.addOperand(MCOperand::CreateReg(0));
1690 OutStreamer.AddComment("eh_setjmp end");
1691 OutStreamer.EmitInstruction(TmpInst);
1693 OutStreamer.EmitLabel(Label);
1697 case ARM::Int_eh_sjlj_setjmp_nofp:
1698 case ARM::Int_eh_sjlj_setjmp: {
1699 // Two incoming args: GPR:$src, GPR:$val
1701 // str $val, [$src, #+4]
1705 unsigned SrcReg = MI->getOperand(0).getReg();
1706 unsigned ValReg = MI->getOperand(1).getReg();
1710 TmpInst.setOpcode(ARM::ADDri);
1711 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1712 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1713 TmpInst.addOperand(MCOperand::CreateImm(8));
1715 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1716 TmpInst.addOperand(MCOperand::CreateReg(0));
1717 // 's' bit operand (always reg0 for this).
1718 TmpInst.addOperand(MCOperand::CreateReg(0));
1719 OutStreamer.AddComment("eh_setjmp begin");
1720 OutStreamer.EmitInstruction(TmpInst);
1724 TmpInst.setOpcode(ARM::STRi12);
1725 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1726 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1727 TmpInst.addOperand(MCOperand::CreateImm(4));
1729 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1730 TmpInst.addOperand(MCOperand::CreateReg(0));
1731 OutStreamer.EmitInstruction(TmpInst);
1735 TmpInst.setOpcode(ARM::MOVi);
1736 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1737 TmpInst.addOperand(MCOperand::CreateImm(0));
1739 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1740 TmpInst.addOperand(MCOperand::CreateReg(0));
1741 // 's' bit operand (always reg0 for this).
1742 TmpInst.addOperand(MCOperand::CreateReg(0));
1743 OutStreamer.EmitInstruction(TmpInst);
1747 TmpInst.setOpcode(ARM::ADDri);
1748 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1749 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1750 TmpInst.addOperand(MCOperand::CreateImm(0));
1752 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1753 TmpInst.addOperand(MCOperand::CreateReg(0));
1754 // 's' bit operand (always reg0 for this).
1755 TmpInst.addOperand(MCOperand::CreateReg(0));
1756 OutStreamer.EmitInstruction(TmpInst);
1760 TmpInst.setOpcode(ARM::MOVi);
1761 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1762 TmpInst.addOperand(MCOperand::CreateImm(1));
1764 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1765 TmpInst.addOperand(MCOperand::CreateReg(0));
1766 // 's' bit operand (always reg0 for this).
1767 TmpInst.addOperand(MCOperand::CreateReg(0));
1768 OutStreamer.AddComment("eh_setjmp end");
1769 OutStreamer.EmitInstruction(TmpInst);
1773 case ARM::Int_eh_sjlj_longjmp: {
1774 // ldr sp, [$src, #8]
1775 // ldr $scratch, [$src, #4]
1778 unsigned SrcReg = MI->getOperand(0).getReg();
1779 unsigned ScratchReg = MI->getOperand(1).getReg();
1782 TmpInst.setOpcode(ARM::LDRi12);
1783 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1784 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1785 TmpInst.addOperand(MCOperand::CreateImm(8));
1787 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1788 TmpInst.addOperand(MCOperand::CreateReg(0));
1789 OutStreamer.EmitInstruction(TmpInst);
1793 TmpInst.setOpcode(ARM::LDRi12);
1794 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1795 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1796 TmpInst.addOperand(MCOperand::CreateImm(4));
1798 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1799 TmpInst.addOperand(MCOperand::CreateReg(0));
1800 OutStreamer.EmitInstruction(TmpInst);
1804 TmpInst.setOpcode(ARM::LDRi12);
1805 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1806 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1807 TmpInst.addOperand(MCOperand::CreateImm(0));
1809 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1810 TmpInst.addOperand(MCOperand::CreateReg(0));
1811 OutStreamer.EmitInstruction(TmpInst);
1815 TmpInst.setOpcode(ARM::BX);
1816 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1818 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1819 TmpInst.addOperand(MCOperand::CreateReg(0));
1820 OutStreamer.EmitInstruction(TmpInst);
1824 case ARM::tInt_eh_sjlj_longjmp: {
1825 // ldr $scratch, [$src, #8]
1827 // ldr $scratch, [$src, #4]
1830 unsigned SrcReg = MI->getOperand(0).getReg();
1831 unsigned ScratchReg = MI->getOperand(1).getReg();
1834 TmpInst.setOpcode(ARM::tLDRi);
1835 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1836 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1837 // The offset immediate is #8. The operand value is scaled by 4 for the
1838 // tLDR instruction.
1839 TmpInst.addOperand(MCOperand::CreateImm(2));
1841 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1842 TmpInst.addOperand(MCOperand::CreateReg(0));
1843 OutStreamer.EmitInstruction(TmpInst);
1847 TmpInst.setOpcode(ARM::tMOVr);
1848 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1849 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1851 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1852 TmpInst.addOperand(MCOperand::CreateReg(0));
1853 OutStreamer.EmitInstruction(TmpInst);
1857 TmpInst.setOpcode(ARM::tLDRi);
1858 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1859 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1860 TmpInst.addOperand(MCOperand::CreateImm(1));
1862 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1863 TmpInst.addOperand(MCOperand::CreateReg(0));
1864 OutStreamer.EmitInstruction(TmpInst);
1868 TmpInst.setOpcode(ARM::tLDRr);
1869 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1870 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1871 TmpInst.addOperand(MCOperand::CreateReg(0));
1873 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1874 TmpInst.addOperand(MCOperand::CreateReg(0));
1875 OutStreamer.EmitInstruction(TmpInst);
1879 TmpInst.setOpcode(ARM::tBX);
1880 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1882 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1883 TmpInst.addOperand(MCOperand::CreateReg(0));
1884 OutStreamer.EmitInstruction(TmpInst);
1891 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1893 OutStreamer.EmitInstruction(TmpInst);
1896 //===----------------------------------------------------------------------===//
1897 // Target Registry Stuff
1898 //===----------------------------------------------------------------------===//
1900 // Force static initialization.
1901 extern "C" void LLVMInitializeARMAsmPrinter() {
1902 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1903 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);