1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "InstPrinter/ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Analysis/DebugInfo.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Module.h"
27 #include "llvm/Type.h"
28 #include "llvm/Assembly/Writer.h"
29 #include "llvm/CodeGen/AsmPrinter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/raw_ostream.h"
66 class ARMAsmPrinter : public AsmPrinter {
68 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
69 /// make the right decision when printing asm code for different targets.
70 const ARMSubtarget *Subtarget;
72 /// AFI - Keep a pointer to ARMFunctionInfo for the current
76 /// MCP - Keep a pointer to constantpool entries of the current
78 const MachineConstantPool *MCP;
81 explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
82 : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) {
83 Subtarget = &TM.getSubtarget<ARMSubtarget>();
86 virtual const char *getPassName() const {
87 return "ARM Assembly Printer";
90 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
91 const char *Modifier = 0);
93 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
94 unsigned AsmVariant, const char *ExtraCode,
96 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
98 const char *ExtraCode, raw_ostream &O);
100 void EmitJumpTable(const MachineInstr *MI);
101 void EmitJump2Table(const MachineInstr *MI);
102 virtual void EmitInstruction(const MachineInstr *MI);
103 bool runOnMachineFunction(MachineFunction &F);
105 virtual void EmitConstantPool() {} // we emit constant pools customly!
106 virtual void EmitFunctionEntryLabel();
107 void EmitStartOfAsmFile(Module &M);
108 void EmitEndOfAsmFile(Module &M);
111 // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile()
112 void emitAttributes();
113 void emitAttribute(ARMBuildAttrs::AttrType attr, int v);
116 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
118 MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
119 MachineLocation Location;
120 assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
121 // Frame address. Currently handles register +- offset only.
122 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
123 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
125 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
130 virtual unsigned getISAEncoding() {
131 // ARM/Darwin adds ISA to the DWARF info for each function.
132 if (!Subtarget->isTargetDarwin())
134 return Subtarget->isThumb() ?
135 llvm::ARM::DW_ISA_ARM_thumb : llvm::ARM::DW_ISA_ARM_arm;
138 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
139 const MachineBasicBlock *MBB) const;
140 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
142 MCSymbol *GetARMSJLJEHLabel(void) const;
144 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
146 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
147 SmallString<128> Str;
148 raw_svector_ostream OS(Str);
149 EmitMachineConstantPoolValue(MCPV, OS);
150 OutStreamer.EmitRawText(OS.str());
153 void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV,
155 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
156 case 1: O << MAI->getData8bitsDirective(0); break;
157 case 2: O << MAI->getData16bitsDirective(0); break;
158 case 4: O << MAI->getData32bitsDirective(0); break;
159 default: assert(0 && "Unknown CPV size");
162 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
164 if (ACPV->isLSDA()) {
165 O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
166 } else if (ACPV->isBlockAddress()) {
167 O << *GetBlockAddressSymbol(ACPV->getBlockAddress());
168 } else if (ACPV->isGlobalValue()) {
169 const GlobalValue *GV = ACPV->getGV();
170 bool isIndirect = Subtarget->isTargetDarwin() &&
171 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
173 O << *Mang->getSymbol(GV);
175 // FIXME: Remove this when Darwin transition to @GOT like syntax.
176 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
179 MachineModuleInfoMachO &MMIMachO =
180 MMI->getObjFileInfo<MachineModuleInfoMachO>();
181 MachineModuleInfoImpl::StubValueTy &StubSym =
182 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
183 MMIMachO.getGVStubEntry(Sym);
184 if (StubSym.getPointer() == 0)
185 StubSym = MachineModuleInfoImpl::
186 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
189 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
190 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
193 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
194 if (ACPV->getPCAdjustment() != 0) {
195 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
196 << getFunctionNumber() << "_" << ACPV->getLabelId()
197 << "+" << (unsigned)ACPV->getPCAdjustment();
198 if (ACPV->mustAddCurrentAddress())
204 } // end of anonymous namespace
206 void ARMAsmPrinter::EmitFunctionEntryLabel() {
207 if (AFI->isThumbFunction()) {
208 OutStreamer.EmitRawText(StringRef("\t.code\t16"));
209 if (!Subtarget->isTargetDarwin())
210 OutStreamer.EmitRawText(StringRef("\t.thumb_func"));
212 // This needs to emit to a temporary string to get properly quoted
213 // MCSymbols when they have spaces in them.
214 SmallString<128> Tmp;
215 raw_svector_ostream OS(Tmp);
216 OS << "\t.thumb_func\t" << *CurrentFnSym;
217 OutStreamer.EmitRawText(OS.str());
221 OutStreamer.EmitLabel(CurrentFnSym);
224 /// runOnMachineFunction - This uses the EmitInstruction()
225 /// method to print assembly for each instruction.
227 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
228 AFI = MF.getInfo<ARMFunctionInfo>();
229 MCP = MF.getConstantPool();
231 return AsmPrinter::runOnMachineFunction(MF);
234 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
235 raw_ostream &O, const char *Modifier) {
236 const MachineOperand &MO = MI->getOperand(OpNum);
237 unsigned TF = MO.getTargetFlags();
239 switch (MO.getType()) {
241 assert(0 && "<unknown operand type>");
242 case MachineOperand::MO_Register: {
243 unsigned Reg = MO.getReg();
244 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
245 assert(!MO.getSubReg() && "Subregs should be eliminated!");
246 O << ARMInstPrinter::getRegisterName(Reg);
249 case MachineOperand::MO_Immediate: {
250 int64_t Imm = MO.getImm();
252 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
253 (TF == ARMII::MO_LO16))
255 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
256 (TF == ARMII::MO_HI16))
261 case MachineOperand::MO_MachineBasicBlock:
262 O << *MO.getMBB()->getSymbol();
264 case MachineOperand::MO_GlobalAddress: {
265 const GlobalValue *GV = MO.getGlobal();
266 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
267 (TF & ARMII::MO_LO16))
269 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
270 (TF & ARMII::MO_HI16))
272 O << *Mang->getSymbol(GV);
274 printOffset(MO.getOffset(), O);
275 if (TF == ARMII::MO_PLT)
279 case MachineOperand::MO_ExternalSymbol: {
280 O << *GetExternalSymbolSymbol(MO.getSymbolName());
281 if (TF == ARMII::MO_PLT)
285 case MachineOperand::MO_ConstantPoolIndex:
286 O << *GetCPISymbol(MO.getIndex());
288 case MachineOperand::MO_JumpTableIndex:
289 O << *GetJTISymbol(MO.getIndex());
294 //===--------------------------------------------------------------------===//
296 MCSymbol *ARMAsmPrinter::
297 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
298 const MachineBasicBlock *MBB) const {
299 SmallString<60> Name;
300 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
301 << getFunctionNumber() << '_' << uid << '_' << uid2
302 << "_set_" << MBB->getNumber();
303 return OutContext.GetOrCreateSymbol(Name.str());
306 MCSymbol *ARMAsmPrinter::
307 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
308 SmallString<60> Name;
309 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
310 << getFunctionNumber() << '_' << uid << '_' << uid2;
311 return OutContext.GetOrCreateSymbol(Name.str());
315 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
316 SmallString<60> Name;
317 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
318 << getFunctionNumber();
319 return OutContext.GetOrCreateSymbol(Name.str());
322 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
323 unsigned AsmVariant, const char *ExtraCode,
325 // Does this asm operand have a single letter operand modifier?
326 if (ExtraCode && ExtraCode[0]) {
327 if (ExtraCode[1] != 0) return true; // Unknown modifier.
329 switch (ExtraCode[0]) {
330 default: return true; // Unknown modifier.
331 case 'a': // Print as a memory address.
332 if (MI->getOperand(OpNum).isReg()) {
334 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
339 case 'c': // Don't print "#" before an immediate operand.
340 if (!MI->getOperand(OpNum).isImm())
342 O << MI->getOperand(OpNum).getImm();
344 case 'P': // Print a VFP double precision register.
345 case 'q': // Print a NEON quad precision register.
346 printOperand(MI, OpNum, O);
351 report_fatal_error("llvm does not support 'Q', 'R', and 'H' modifiers!");
356 printOperand(MI, OpNum, O);
360 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
361 unsigned OpNum, unsigned AsmVariant,
362 const char *ExtraCode,
364 if (ExtraCode && ExtraCode[0])
365 return true; // Unknown modifier.
367 const MachineOperand &MO = MI->getOperand(OpNum);
368 assert(MO.isReg() && "unexpected inline asm memory operand");
369 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
373 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
374 if (Subtarget->isTargetDarwin()) {
375 Reloc::Model RelocM = TM.getRelocationModel();
376 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
377 // Declare all the text sections up front (before the DWARF sections
378 // emitted by AsmPrinter::doInitialization) so the assembler will keep
379 // them together at the beginning of the object file. This helps
380 // avoid out-of-range branches that are due a fundamental limitation of
381 // the way symbol offsets are encoded with the current Darwin ARM
383 const TargetLoweringObjectFileMachO &TLOFMacho =
384 static_cast<const TargetLoweringObjectFileMachO &>(
385 getObjFileLowering());
386 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
387 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
388 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
389 if (RelocM == Reloc::DynamicNoPIC) {
390 const MCSection *sect =
391 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
392 MCSectionMachO::S_SYMBOL_STUBS,
393 12, SectionKind::getText());
394 OutStreamer.SwitchSection(sect);
396 const MCSection *sect =
397 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
398 MCSectionMachO::S_SYMBOL_STUBS,
399 16, SectionKind::getText());
400 OutStreamer.SwitchSection(sect);
402 const MCSection *StaticInitSect =
403 OutContext.getMachOSection("__TEXT", "__StaticInit",
404 MCSectionMachO::S_REGULAR |
405 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
406 SectionKind::getText());
407 OutStreamer.SwitchSection(StaticInitSect);
411 // Use unified assembler syntax.
412 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
414 // Emit ARM Build Attributes
415 if (Subtarget->isTargetELF()) {
422 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
423 if (Subtarget->isTargetDarwin()) {
424 // All darwin targets use mach-o.
425 const TargetLoweringObjectFileMachO &TLOFMacho =
426 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
427 MachineModuleInfoMachO &MMIMacho =
428 MMI->getObjFileInfo<MachineModuleInfoMachO>();
430 // Output non-lazy-pointers for external and common global variables.
431 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
433 if (!Stubs.empty()) {
434 // Switch with ".non_lazy_symbol_pointer" directive.
435 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
437 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
439 OutStreamer.EmitLabel(Stubs[i].first);
440 // .indirect_symbol _foo
441 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
442 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
445 // External to current translation unit.
446 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
448 // Internal to current translation unit.
450 // When we place the LSDA into the TEXT section, the type info
451 // pointers need to be indirect and pc-rel. We accomplish this by
452 // using NLPs; however, sometimes the types are local to the file.
453 // We need to fill in the value for the NLP in those cases.
454 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
456 4/*size*/, 0/*addrspace*/);
460 OutStreamer.AddBlankLine();
463 Stubs = MMIMacho.GetHiddenGVStubList();
464 if (!Stubs.empty()) {
465 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
467 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
469 OutStreamer.EmitLabel(Stubs[i].first);
471 OutStreamer.EmitValue(MCSymbolRefExpr::
472 Create(Stubs[i].second.getPointer(),
474 4/*size*/, 0/*addrspace*/);
478 OutStreamer.AddBlankLine();
481 // Funny Darwin hack: This flag tells the linker that no global symbols
482 // contain code that falls through to other global symbols (e.g. the obvious
483 // implementation of multiple entry points). If this doesn't occur, the
484 // linker can safely perform dead code stripping. Since LLVM never
485 // generates code that does this, it is always safe to set.
486 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
490 //===----------------------------------------------------------------------===//
491 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
493 // The following seem like one-off assembler flags, but they actually need
494 // to appear in the .ARM.attributes section in ELF.
495 // Instead of subclassing the MCELFStreamer, we do the work here.
497 void ARMAsmPrinter::emitAttributes() {
498 // FIXME: Add in ELF specific section handling here.
500 // FIXME: unify this: .cpu and CPUString with enum attributes
501 std::string CPUString = Subtarget->getCPUString();
502 if (CPUString != "generic")
503 OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString));
505 // FIXME: Emit FPU type
506 if (Subtarget->hasVFP2())
507 emitAttribute(ARMBuildAttrs::VFP_arch, 2);
509 // Signal various FP modes.
511 emitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
512 emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
515 if (NoInfsFPMath && NoNaNsFPMath)
516 emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
518 emitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
520 // 8-bytes alignment stuff.
521 emitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
522 emitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
524 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
525 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
526 emitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
527 emitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
529 // FIXME: Should we signal R9 usage?
532 void ARMAsmPrinter::emitAttribute(ARMBuildAttrs::AttrType attr, int v) {
533 if (OutStreamer.hasRawTextSupport()) {
534 OutStreamer.EmitRawText("\t.eabi_attribute " +
535 Twine(attr) + ", " + Twine(v));
538 assert(0 && "ELF .ARM.attributes unimplemented");
542 //===----------------------------------------------------------------------===//
544 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
545 unsigned LabelId, MCContext &Ctx) {
547 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
548 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
552 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
553 unsigned Opcode = MI->getOpcode();
555 if (Opcode == ARM::BR_JTadd)
557 else if (Opcode == ARM::BR_JTm)
560 const MachineOperand &MO1 = MI->getOperand(OpNum);
561 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
562 unsigned JTI = MO1.getIndex();
564 // Emit a label for the jump table.
565 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
566 OutStreamer.EmitLabel(JTISymbol);
568 // Emit each entry of the table.
569 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
570 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
571 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
573 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
574 MachineBasicBlock *MBB = JTBBs[i];
575 // Construct an MCExpr for the entry. We want a value of the form:
576 // (BasicBlockAddr - TableBeginAddr)
578 // For example, a table with entries jumping to basic blocks BB0 and BB1
581 // .word (LBB0 - LJTI_0_0)
582 // .word (LBB1 - LJTI_0_0)
583 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
585 if (TM.getRelocationModel() == Reloc::PIC_)
586 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
589 OutStreamer.EmitValue(Expr, 4);
593 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
594 unsigned Opcode = MI->getOpcode();
595 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
596 const MachineOperand &MO1 = MI->getOperand(OpNum);
597 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
598 unsigned JTI = MO1.getIndex();
600 // Emit a label for the jump table.
601 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
602 OutStreamer.EmitLabel(JTISymbol);
604 // Emit each entry of the table.
605 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
606 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
607 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
608 unsigned OffsetWidth = 4;
609 if (MI->getOpcode() == ARM::t2TBB)
611 else if (MI->getOpcode() == ARM::t2TBH)
614 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
615 MachineBasicBlock *MBB = JTBBs[i];
616 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
618 // If this isn't a TBB or TBH, the entries are direct branch instructions.
619 if (OffsetWidth == 4) {
621 BrInst.setOpcode(ARM::t2B);
622 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
623 OutStreamer.EmitInstruction(BrInst);
626 // Otherwise it's an offset from the dispatch instruction. Construct an
627 // MCExpr for the entry. We want a value of the form:
628 // (BasicBlockAddr - TableBeginAddr) / 2
630 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
633 // .byte (LBB0 - LJTI_0_0) / 2
634 // .byte (LBB1 - LJTI_0_0) / 2
636 MCBinaryExpr::CreateSub(MBBSymbolExpr,
637 MCSymbolRefExpr::Create(JTISymbol, OutContext),
639 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
641 OutStreamer.EmitValue(Expr, OffsetWidth);
644 // Make sure the instruction that follows TBB is 2-byte aligned.
645 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
646 if (MI->getOpcode() == ARM::t2TBB)
650 void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
652 unsigned NOps = MI->getNumOperands();
654 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
655 // cast away const; DIetc do not take const operands for some reason.
656 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
659 // Frame address. Currently handles register +- offset only.
660 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
661 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
664 printOperand(MI, NOps-2, OS);
667 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
668 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
669 switch (MI->getOpcode()) {
670 case ARM::t2MOVi32imm:
671 assert(0 && "Should be lowered by thumb2it pass");
673 case ARM::DBG_VALUE: {
674 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
675 SmallString<128> TmpStr;
676 raw_svector_ostream OS(TmpStr);
677 PrintDebugValueComment(MI, OS);
678 OutStreamer.EmitRawText(StringRef(OS.str()));
683 // This is a pseudo op for a label + instruction sequence, which looks like:
686 // This adds the address of LPC0 to r0.
689 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
690 getFunctionNumber(), MI->getOperand(2).getImm(),
693 // Form and emit the add.
695 AddInst.setOpcode(ARM::tADDhirr);
696 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
697 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
698 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
699 // Add predicate operands.
700 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
701 AddInst.addOperand(MCOperand::CreateReg(0));
702 OutStreamer.EmitInstruction(AddInst);
706 // This is a pseudo op for a label + instruction sequence, which looks like:
709 // This adds the address of LPC0 to r0.
712 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
713 getFunctionNumber(), MI->getOperand(2).getImm(),
716 // Form and emit the add.
718 AddInst.setOpcode(ARM::ADDrr);
719 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
720 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
721 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
722 // Add predicate operands.
723 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
724 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
725 // Add 's' bit operand (always reg0 for this)
726 AddInst.addOperand(MCOperand::CreateReg(0));
727 OutStreamer.EmitInstruction(AddInst);
737 case ARM::PICLDRSH: {
738 // This is a pseudo op for a label + instruction sequence, which looks like:
741 // The LCP0 label is referenced by a constant pool entry in order to get
742 // a PC-relative address at the ldr instruction.
745 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
746 getFunctionNumber(), MI->getOperand(2).getImm(),
749 // Form and emit the load
751 switch (MI->getOpcode()) {
753 llvm_unreachable("Unexpected opcode!");
754 case ARM::PICSTR: Opcode = ARM::STR; break;
755 case ARM::PICSTRB: Opcode = ARM::STRB; break;
756 case ARM::PICSTRH: Opcode = ARM::STRH; break;
757 case ARM::PICLDR: Opcode = ARM::LDR; break;
758 case ARM::PICLDRB: Opcode = ARM::LDRB; break;
759 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
760 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
761 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
764 LdStInst.setOpcode(Opcode);
765 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
766 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
767 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
768 LdStInst.addOperand(MCOperand::CreateImm(0));
769 // Add predicate operands.
770 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
771 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
772 OutStreamer.EmitInstruction(LdStInst);
776 case ARM::CONSTPOOL_ENTRY: {
777 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
778 /// in the function. The first operand is the ID# for this instruction, the
779 /// second is the index into the MachineConstantPool that this is, the third
780 /// is the size in bytes of this constant pool entry.
781 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
782 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
785 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
787 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
788 if (MCPE.isMachineConstantPoolEntry())
789 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
791 EmitGlobalConstant(MCPE.Val.ConstVal);
795 case ARM::MOVi2pieces: {
796 // FIXME: We'd like to remove the asm string in the .td file, but the
797 // This is a hack that lowers as a two instruction sequence.
798 unsigned DstReg = MI->getOperand(0).getReg();
799 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
801 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
802 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
806 TmpInst.setOpcode(ARM::MOVi);
807 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
808 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
811 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
812 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
814 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
815 OutStreamer.EmitInstruction(TmpInst);
820 TmpInst.setOpcode(ARM::ORRri);
821 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
822 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
823 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
825 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
826 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
828 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
829 OutStreamer.EmitInstruction(TmpInst);
833 case ARM::MOVi32imm: {
834 // FIXME: We'd like to remove the asm string in the .td file, but the
835 // This is a hack that lowers as a two instruction sequence.
836 unsigned DstReg = MI->getOperand(0).getReg();
837 const MachineOperand &MO = MI->getOperand(1);
840 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
841 V1 = MCOperand::CreateImm(ImmVal & 65535);
842 V2 = MCOperand::CreateImm(ImmVal >> 16);
843 } else if (MO.isGlobal()) {
844 MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
845 const MCSymbolRefExpr *SymRef1 =
846 MCSymbolRefExpr::Create(Symbol,
847 MCSymbolRefExpr::VK_ARM_LO16, OutContext);
848 const MCSymbolRefExpr *SymRef2 =
849 MCSymbolRefExpr::Create(Symbol,
850 MCSymbolRefExpr::VK_ARM_HI16, OutContext);
851 V1 = MCOperand::CreateExpr(SymRef1);
852 V2 = MCOperand::CreateExpr(SymRef2);
854 // FIXME: External symbol?
856 llvm_unreachable("cannot handle this operand");
861 TmpInst.setOpcode(ARM::MOVi16);
862 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
863 TmpInst.addOperand(V1); // lower16(imm)
866 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
867 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
869 OutStreamer.EmitInstruction(TmpInst);
874 TmpInst.setOpcode(ARM::MOVTi16);
875 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
876 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
877 TmpInst.addOperand(V2); // upper16(imm)
880 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
881 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
883 OutStreamer.EmitInstruction(TmpInst);
891 // Lower and emit the instruction itself, then the jump table following it.
893 MCInstLowering.Lower(MI, TmpInst);
894 OutStreamer.EmitInstruction(TmpInst);
901 case ARM::BR_JTadd: {
902 // Lower and emit the instruction itself, then the jump table following it.
904 MCInstLowering.Lower(MI, TmpInst);
905 OutStreamer.EmitInstruction(TmpInst);
910 // Non-Darwin binutils don't yet support the "trap" mnemonic.
911 // FIXME: Remove this special case when they do.
912 if (!Subtarget->isTargetDarwin()) {
913 //.long 0xe7ffdefe @ trap
914 uint32_t Val = 0xe7ffdefeUL;
915 OutStreamer.AddComment("trap");
916 OutStreamer.EmitIntValue(Val, 4);
922 // Non-Darwin binutils don't yet support the "trap" mnemonic.
923 // FIXME: Remove this special case when they do.
924 if (!Subtarget->isTargetDarwin()) {
925 //.short 57086 @ trap
926 uint16_t Val = 0xdefe;
927 OutStreamer.AddComment("trap");
928 OutStreamer.EmitIntValue(Val, 2);
933 case ARM::t2Int_eh_sjlj_setjmp:
934 case ARM::t2Int_eh_sjlj_setjmp_nofp:
935 case ARM::tInt_eh_sjlj_setjmp: {
936 // Two incoming args: GPR:$src, GPR:$val
939 // str $val, [$src, #4]
944 unsigned SrcReg = MI->getOperand(0).getReg();
945 unsigned ValReg = MI->getOperand(1).getReg();
946 MCSymbol *Label = GetARMSJLJEHLabel();
949 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
950 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
951 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
953 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
954 OutStreamer.AddComment("eh_setjmp begin");
955 OutStreamer.EmitInstruction(TmpInst);
959 TmpInst.setOpcode(ARM::tADDi3);
960 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
962 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
963 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
964 TmpInst.addOperand(MCOperand::CreateImm(7));
966 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
967 TmpInst.addOperand(MCOperand::CreateReg(0));
968 OutStreamer.EmitInstruction(TmpInst);
972 TmpInst.setOpcode(ARM::tSTR);
973 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
974 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
975 // The offset immediate is #4. The operand value is scaled by 4 for the
977 TmpInst.addOperand(MCOperand::CreateImm(1));
978 TmpInst.addOperand(MCOperand::CreateReg(0));
980 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
981 TmpInst.addOperand(MCOperand::CreateReg(0));
982 OutStreamer.EmitInstruction(TmpInst);
986 TmpInst.setOpcode(ARM::tMOVi8);
987 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
988 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
989 TmpInst.addOperand(MCOperand::CreateImm(0));
991 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
992 TmpInst.addOperand(MCOperand::CreateReg(0));
993 OutStreamer.EmitInstruction(TmpInst);
996 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
998 TmpInst.setOpcode(ARM::tB);
999 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1000 OutStreamer.EmitInstruction(TmpInst);
1004 TmpInst.setOpcode(ARM::tMOVi8);
1005 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1006 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1007 TmpInst.addOperand(MCOperand::CreateImm(1));
1009 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1010 TmpInst.addOperand(MCOperand::CreateReg(0));
1011 OutStreamer.AddComment("eh_setjmp end");
1012 OutStreamer.EmitInstruction(TmpInst);
1014 OutStreamer.EmitLabel(Label);
1018 case ARM::Int_eh_sjlj_setjmp_nofp:
1019 case ARM::Int_eh_sjlj_setjmp: {
1020 // Two incoming args: GPR:$src, GPR:$val
1022 // str $val, [$src, #+4]
1026 unsigned SrcReg = MI->getOperand(0).getReg();
1027 unsigned ValReg = MI->getOperand(1).getReg();
1031 TmpInst.setOpcode(ARM::ADDri);
1032 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1033 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1034 TmpInst.addOperand(MCOperand::CreateImm(8));
1036 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1037 TmpInst.addOperand(MCOperand::CreateReg(0));
1038 // 's' bit operand (always reg0 for this).
1039 TmpInst.addOperand(MCOperand::CreateReg(0));
1040 OutStreamer.AddComment("eh_setjmp begin");
1041 OutStreamer.EmitInstruction(TmpInst);
1045 TmpInst.setOpcode(ARM::STR);
1046 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1047 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1048 TmpInst.addOperand(MCOperand::CreateReg(0));
1049 TmpInst.addOperand(MCOperand::CreateImm(4));
1051 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1052 TmpInst.addOperand(MCOperand::CreateReg(0));
1053 OutStreamer.EmitInstruction(TmpInst);
1057 TmpInst.setOpcode(ARM::MOVi);
1058 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1059 TmpInst.addOperand(MCOperand::CreateImm(0));
1061 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1062 TmpInst.addOperand(MCOperand::CreateReg(0));
1063 // 's' bit operand (always reg0 for this).
1064 TmpInst.addOperand(MCOperand::CreateReg(0));
1065 OutStreamer.EmitInstruction(TmpInst);
1069 TmpInst.setOpcode(ARM::ADDri);
1070 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1071 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1072 TmpInst.addOperand(MCOperand::CreateImm(0));
1074 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1075 TmpInst.addOperand(MCOperand::CreateReg(0));
1076 // 's' bit operand (always reg0 for this).
1077 TmpInst.addOperand(MCOperand::CreateReg(0));
1078 OutStreamer.EmitInstruction(TmpInst);
1082 TmpInst.setOpcode(ARM::MOVi);
1083 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1084 TmpInst.addOperand(MCOperand::CreateImm(1));
1086 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1087 TmpInst.addOperand(MCOperand::CreateReg(0));
1088 // 's' bit operand (always reg0 for this).
1089 TmpInst.addOperand(MCOperand::CreateReg(0));
1090 OutStreamer.AddComment("eh_setjmp end");
1091 OutStreamer.EmitInstruction(TmpInst);
1095 case ARM::Int_eh_sjlj_longjmp: {
1096 // ldr sp, [$src, #8]
1097 // ldr $scratch, [$src, #4]
1100 unsigned SrcReg = MI->getOperand(0).getReg();
1101 unsigned ScratchReg = MI->getOperand(1).getReg();
1104 TmpInst.setOpcode(ARM::LDR);
1105 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1106 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1107 TmpInst.addOperand(MCOperand::CreateReg(0));
1108 TmpInst.addOperand(MCOperand::CreateImm(8));
1110 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1111 TmpInst.addOperand(MCOperand::CreateReg(0));
1112 OutStreamer.EmitInstruction(TmpInst);
1116 TmpInst.setOpcode(ARM::LDR);
1117 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1118 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1119 TmpInst.addOperand(MCOperand::CreateReg(0));
1120 TmpInst.addOperand(MCOperand::CreateImm(4));
1122 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1123 TmpInst.addOperand(MCOperand::CreateReg(0));
1124 OutStreamer.EmitInstruction(TmpInst);
1128 TmpInst.setOpcode(ARM::LDR);
1129 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1130 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1131 TmpInst.addOperand(MCOperand::CreateReg(0));
1132 TmpInst.addOperand(MCOperand::CreateImm(0));
1134 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1135 TmpInst.addOperand(MCOperand::CreateReg(0));
1136 OutStreamer.EmitInstruction(TmpInst);
1140 TmpInst.setOpcode(ARM::BRIND);
1141 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1143 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1144 TmpInst.addOperand(MCOperand::CreateReg(0));
1145 OutStreamer.EmitInstruction(TmpInst);
1149 case ARM::tInt_eh_sjlj_longjmp: {
1150 // ldr $scratch, [$src, #8]
1152 // ldr $scratch, [$src, #4]
1155 unsigned SrcReg = MI->getOperand(0).getReg();
1156 unsigned ScratchReg = MI->getOperand(1).getReg();
1159 TmpInst.setOpcode(ARM::tLDR);
1160 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1161 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1162 // The offset immediate is #8. The operand value is scaled by 4 for the
1163 // tSTR instruction.
1164 TmpInst.addOperand(MCOperand::CreateImm(2));
1165 TmpInst.addOperand(MCOperand::CreateReg(0));
1167 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1168 TmpInst.addOperand(MCOperand::CreateReg(0));
1169 OutStreamer.EmitInstruction(TmpInst);
1173 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1174 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1175 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1177 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1178 TmpInst.addOperand(MCOperand::CreateReg(0));
1179 OutStreamer.EmitInstruction(TmpInst);
1183 TmpInst.setOpcode(ARM::tLDR);
1184 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1185 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1186 TmpInst.addOperand(MCOperand::CreateImm(1));
1187 TmpInst.addOperand(MCOperand::CreateReg(0));
1189 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1190 TmpInst.addOperand(MCOperand::CreateReg(0));
1191 OutStreamer.EmitInstruction(TmpInst);
1195 TmpInst.setOpcode(ARM::tLDR);
1196 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1197 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1198 TmpInst.addOperand(MCOperand::CreateImm(0));
1199 TmpInst.addOperand(MCOperand::CreateReg(0));
1201 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1202 TmpInst.addOperand(MCOperand::CreateReg(0));
1203 OutStreamer.EmitInstruction(TmpInst);
1207 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1208 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1210 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1211 TmpInst.addOperand(MCOperand::CreateReg(0));
1212 OutStreamer.EmitInstruction(TmpInst);
1219 MCInstLowering.Lower(MI, TmpInst);
1220 OutStreamer.EmitInstruction(TmpInst);
1223 //===----------------------------------------------------------------------===//
1224 // Target Registry Stuff
1225 //===----------------------------------------------------------------------===//
1227 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1228 unsigned SyntaxVariant,
1229 const MCAsmInfo &MAI) {
1230 if (SyntaxVariant == 0)
1231 return new ARMInstPrinter(MAI);
1235 // Force static initialization.
1236 extern "C" void LLVMInitializeARMAsmPrinter() {
1237 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1238 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1240 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1241 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);