1 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the ARM target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
20 #include "llvm/Support/ErrorHandling.h"
22 // Note that the following auto-generated files only defined enum types, and
23 // so are safe to include here.
25 // Defines symbolic names for ARM registers. This defines a mapping from
26 // register name to register number.
28 #include "ARMGenRegisterNames.inc"
30 // Defines symbolic names for the ARM instructions.
32 #include "ARMGenInstrNames.inc"
36 // Enums corresponding to ARM condition codes
38 // The CondCodes constants map directly to the 4-bit encoding of the
39 // condition field for predicated instructions.
40 enum CondCodes { // Meaning (integer) Meaning (floating-point)
42 NE, // Not equal Not equal, or unordered
43 HS, // Carry set >, ==, or unordered
44 LO, // Carry clear Less than
45 MI, // Minus, negative Less than
46 PL, // Plus, positive or zero >, ==, or unordered
47 VS, // Overflow Unordered
48 VC, // No overflow Not unordered
49 HI, // Unsigned higher Greater than, or unordered
50 LS, // Unsigned lower or same Less than or equal
51 GE, // Greater than or equal Greater than or equal
52 LT, // Less than Less than, or unordered
53 GT, // Greater than Greater than
54 LE, // Less than or equal <, ==, or unordered
55 AL // Always (unconditional) Always (unconditional)
58 inline static CondCodes getOppositeCondition(CondCodes CC) {
60 default: llvm_unreachable("Unknown condition code");
79 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
81 default: llvm_unreachable("Unknown condition code");
82 case ARMCC::EQ: return "eq";
83 case ARMCC::NE: return "ne";
84 case ARMCC::HS: return "hs";
85 case ARMCC::LO: return "lo";
86 case ARMCC::MI: return "mi";
87 case ARMCC::PL: return "pl";
88 case ARMCC::VS: return "vs";
89 case ARMCC::VC: return "vc";
90 case ARMCC::HI: return "hi";
91 case ARMCC::LS: return "ls";
92 case ARMCC::GE: return "ge";
93 case ARMCC::LT: return "lt";
94 case ARMCC::GT: return "gt";
95 case ARMCC::LE: return "le";
96 case ARMCC::AL: return "al";
101 // The Memory Barrier Option constants map directly to the 4-bit encoding of
102 // the option field for memory barrier operations.
114 inline static const char *MemBOptToString(unsigned val) {
116 default: llvm_unreachable("Unknown memory operation");
117 case SY: return "sy";
118 case ST: return "st";
119 case ISH: return "ish";
120 case ISHST: return "ishst";
121 case NSH: return "nsh";
122 case NSHST: return "nshst";
123 case OSH: return "osh";
124 case OSHST: return "oshst";
127 } // namespace ARM_MB
129 /// getARMRegisterNumbering - Given the enum value for some register, e.g.
130 /// ARM::LR, return the number that it corresponds to (e.g. 14).
131 inline static unsigned getARMRegisterNumbering(unsigned Reg) {
135 llvm_unreachable("Unknown ARM register!");
136 case R0: case S0: case D0: case Q0: return 0;
137 case R1: case S1: case D1: case Q1: return 1;
138 case R2: case S2: case D2: case Q2: return 2;
139 case R3: case S3: case D3: case Q3: return 3;
140 case R4: case S4: case D4: case Q4: return 4;
141 case R5: case S5: case D5: case Q5: return 5;
142 case R6: case S6: case D6: case Q6: return 6;
143 case R7: case S7: case D7: case Q7: return 7;
144 case R8: case S8: case D8: case Q8: return 8;
145 case R9: case S9: case D9: case Q9: return 9;
146 case R10: case S10: case D10: case Q10: return 10;
147 case R11: case S11: case D11: case Q11: return 11;
148 case R12: case S12: case D12: case Q12: return 12;
149 case SP: case S13: case D13: case Q13: return 13;
150 case LR: case S14: case D14: case Q14: return 14;
151 case PC: case S15: case D15: case Q15: return 15;
153 case S16: case D16: return 16;
154 case S17: case D17: return 17;
155 case S18: case D18: return 18;
156 case S19: case D19: return 19;
157 case S20: case D20: return 20;
158 case S21: case D21: return 21;
159 case S22: case D22: return 22;
160 case S23: case D23: return 23;
161 case S24: case D24: return 24;
162 case S25: case D25: return 25;
163 case S26: case D26: return 26;
164 case S27: case D27: return 27;
165 case S28: case D28: return 28;
166 case S29: case D29: return 29;
167 case S30: case D30: return 30;
168 case S31: case D31: return 31;
173 /// Target Operand Flag enum.
175 //===------------------------------------------------------------------===//
176 // ARM Specific MachineOperand flags.
180 /// MO_LO16 - On a symbol operand, this represents a relocation containing
181 /// lower 16 bit of the address. Used only via movw instruction.
184 /// MO_HI16 - On a symbol operand, this represents a relocation containing
185 /// higher 16 bit of the address. Used only via movt instruction.
188 /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
192 } // end namespace ARMII
194 } // end namespace llvm;