1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/BranchProbability.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
40 #define GET_INSTRINFO_CTOR_DTOR
41 #include "ARMGenInstrInfo.inc"
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
50 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
51 cl::desc("Widen ARM vmovs to vmovd when possible"));
53 static cl::opt<unsigned>
54 SwiftPartialUpdateClearance("swift-partial-update-clearance",
55 cl::Hidden, cl::init(12),
56 cl::desc("Clearance before partial register updates"));
58 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
60 uint16_t MLxOpc; // MLA / MLS opcode
61 uint16_t MulOpc; // Expanded multiplication opcode
62 uint16_t AddSubOpc; // Expanded add / sub opcode
63 bool NegAcc; // True if the acc is negated before the add / sub.
64 bool HasLane; // True if instruction has an extra "lane" operand.
67 static const ARM_MLxEntry ARM_MLxTable[] = {
68 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
70 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
71 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
72 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
73 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
74 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
75 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
76 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
77 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
80 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
81 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
82 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
83 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
84 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
85 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
86 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
87 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
90 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
91 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
93 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
94 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
95 assert(false && "Duplicated entries?");
96 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
97 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
101 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
102 // currently defaults to no prepass hazard recognizer.
103 ScheduleHazardRecognizer *ARMBaseInstrInfo::
104 CreateTargetHazardRecognizer(const TargetMachine *TM,
105 const ScheduleDAG *DAG) const {
106 if (usePreRAHazardRecognizer()) {
107 const InstrItineraryData *II = TM->getInstrItineraryData();
108 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
110 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
113 ScheduleHazardRecognizer *ARMBaseInstrInfo::
114 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
115 const ScheduleDAG *DAG) const {
116 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
117 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
118 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
122 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
123 MachineBasicBlock::iterator &MBBI,
124 LiveVariables *LV) const {
125 // FIXME: Thumb2 support.
130 MachineInstr *MI = MBBI;
131 MachineFunction &MF = *MI->getParent()->getParent();
132 uint64_t TSFlags = MI->getDesc().TSFlags;
134 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
135 default: return NULL;
136 case ARMII::IndexModePre:
139 case ARMII::IndexModePost:
143 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
149 MachineInstr *UpdateMI = NULL;
150 MachineInstr *MemMI = NULL;
151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
152 const MCInstrDesc &MCID = MI->getDesc();
153 unsigned NumOps = MCID.getNumOperands();
154 bool isLoad = !MI->mayStore();
155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156 const MachineOperand &Base = MI->getOperand(2);
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
158 unsigned WBReg = WB.getReg();
159 unsigned BaseReg = Base.getReg();
160 unsigned OffReg = Offset.getReg();
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
164 default: llvm_unreachable("Unknown indexed op!");
165 case ARMII::AddrMode2: {
166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
167 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
169 if (ARM_AM::getSOImmVal(Amt) == -1)
170 // Can't encode it in a so_imm operand. This transformation will
171 // add more than 1 instruction. Abandon!
173 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
175 .addReg(BaseReg).addImm(Amt)
176 .addImm(Pred).addReg(0).addReg(0);
177 } else if (Amt != 0) {
178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
183 .addImm(Pred).addReg(0).addReg(0);
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187 .addReg(BaseReg).addReg(OffReg)
188 .addImm(Pred).addReg(0).addReg(0);
191 case ARMII::AddrMode3 : {
192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
193 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
195 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
198 .addReg(BaseReg).addImm(Amt)
199 .addImm(Pred).addReg(0).addReg(0);
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
203 .addReg(BaseReg).addReg(OffReg)
204 .addImm(Pred).addReg(0).addReg(0);
209 std::vector<MachineInstr*> NewMIs;
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
214 .addReg(WBReg).addImm(0).addImm(Pred);
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
218 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
219 NewMIs.push_back(MemMI);
220 NewMIs.push_back(UpdateMI);
223 MemMI = BuildMI(MF, MI->getDebugLoc(),
224 get(MemOpc), MI->getOperand(0).getReg())
225 .addReg(BaseReg).addImm(0).addImm(Pred);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc)).addReg(MI->getOperand(1).getReg())
229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
231 UpdateMI->getOperand(0).setIsDead();
232 NewMIs.push_back(UpdateMI);
233 NewMIs.push_back(MemMI);
236 // Transfer LiveVariables states, kill / dead info.
238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = MI->getOperand(i);
240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
241 unsigned Reg = MO.getReg();
243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
247 LV->addVirtualRegisterDead(Reg, NewMI);
249 if (MO.isUse() && MO.isKill()) {
250 for (unsigned j = 0; j < 2; ++j) {
251 // Look at the two new MI's in reverse order.
252 MachineInstr *NewMI = NewMIs[j];
253 if (!NewMI->readsRegister(Reg))
255 LV->addVirtualRegisterKilled(Reg, NewMI);
256 if (VI.removeKill(MI))
257 VI.Kills.push_back(NewMI);
265 MFI->insert(MBBI, NewMIs[1]);
266 MFI->insert(MBBI, NewMIs[0]);
272 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
273 MachineBasicBlock *&FBB,
274 SmallVectorImpl<MachineOperand> &Cond,
275 bool AllowModify) const {
279 MachineBasicBlock::iterator I = MBB.end();
280 if (I == MBB.begin())
281 return false; // Empty blocks are easy.
284 // Walk backwards from the end of the basic block until the branch is
285 // analyzed or we give up.
286 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
288 // Flag to be raised on unanalyzeable instructions. This is useful in cases
289 // where we want to clean up on the end of the basic block before we bail
291 bool CantAnalyze = false;
293 // Skip over DEBUG values and predicated nonterminators.
294 while (I->isDebugValue() || !I->isTerminator()) {
295 if (I == MBB.begin())
300 if (isIndirectBranchOpcode(I->getOpcode()) ||
301 isJumpTableBranchOpcode(I->getOpcode())) {
302 // Indirect branches and jump tables can't be analyzed, but we still want
303 // to clean up any instructions at the tail of the basic block.
305 } else if (isUncondBranchOpcode(I->getOpcode())) {
306 TBB = I->getOperand(0).getMBB();
307 } else if (isCondBranchOpcode(I->getOpcode())) {
308 // Bail out if we encounter multiple conditional branches.
312 assert(!FBB && "FBB should have been null.");
314 TBB = I->getOperand(0).getMBB();
315 Cond.push_back(I->getOperand(1));
316 Cond.push_back(I->getOperand(2));
317 } else if (I->isReturn()) {
318 // Returns can't be analyzed, but we should run cleanup.
319 CantAnalyze = !isPredicated(I);
321 // We encountered other unrecognized terminator. Bail out immediately.
325 // Cleanup code - to be run for unpredicated unconditional branches and
327 if (!isPredicated(I) &&
328 (isUncondBranchOpcode(I->getOpcode()) ||
329 isIndirectBranchOpcode(I->getOpcode()) ||
330 isJumpTableBranchOpcode(I->getOpcode()) ||
332 // Forget any previous condition branch information - it no longer applies.
336 // If we can modify the function, delete everything below this
337 // unconditional branch.
339 MachineBasicBlock::iterator DI = llvm::next(I);
340 while (DI != MBB.end()) {
341 MachineInstr *InstToDelete = DI;
343 InstToDelete->eraseFromParent();
351 if (I == MBB.begin())
357 // We made it past the terminators without bailing out - we must have
358 // analyzed this branch successfully.
363 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
364 MachineBasicBlock::iterator I = MBB.end();
365 if (I == MBB.begin()) return 0;
367 while (I->isDebugValue()) {
368 if (I == MBB.begin())
372 if (!isUncondBranchOpcode(I->getOpcode()) &&
373 !isCondBranchOpcode(I->getOpcode()))
376 // Remove the branch.
377 I->eraseFromParent();
381 if (I == MBB.begin()) return 1;
383 if (!isCondBranchOpcode(I->getOpcode()))
386 // Remove the branch.
387 I->eraseFromParent();
392 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
393 MachineBasicBlock *FBB,
394 const SmallVectorImpl<MachineOperand> &Cond,
396 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
397 int BOpc = !AFI->isThumbFunction()
398 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
399 int BccOpc = !AFI->isThumbFunction()
400 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
401 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
403 // Shouldn't be a fall through.
404 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
405 assert((Cond.size() == 2 || Cond.size() == 0) &&
406 "ARM branch conditions have two components!");
409 if (Cond.empty()) { // Unconditional branch?
411 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
413 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
415 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
416 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
420 // Two-way conditional branch.
421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
424 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
426 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
430 bool ARMBaseInstrInfo::
431 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
432 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
433 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
437 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
438 if (MI->isBundle()) {
439 MachineBasicBlock::const_instr_iterator I = MI;
440 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
441 while (++I != E && I->isInsideBundle()) {
442 int PIdx = I->findFirstPredOperandIdx();
443 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
449 int PIdx = MI->findFirstPredOperandIdx();
450 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
453 bool ARMBaseInstrInfo::
454 PredicateInstruction(MachineInstr *MI,
455 const SmallVectorImpl<MachineOperand> &Pred) const {
456 unsigned Opc = MI->getOpcode();
457 if (isUncondBranchOpcode(Opc)) {
458 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
459 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
460 .addImm(Pred[0].getImm())
461 .addReg(Pred[1].getReg());
465 int PIdx = MI->findFirstPredOperandIdx();
467 MachineOperand &PMO = MI->getOperand(PIdx);
468 PMO.setImm(Pred[0].getImm());
469 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
475 bool ARMBaseInstrInfo::
476 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
477 const SmallVectorImpl<MachineOperand> &Pred2) const {
478 if (Pred1.size() > 2 || Pred2.size() > 2)
481 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
482 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
492 return CC2 == ARMCC::HI;
494 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
496 return CC2 == ARMCC::GT;
498 return CC2 == ARMCC::LT;
502 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
503 std::vector<MachineOperand> &Pred) const {
505 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
506 const MachineOperand &MO = MI->getOperand(i);
507 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
508 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
517 /// isPredicable - Return true if the specified instruction can be predicated.
518 /// By default, this returns true for every instruction with a
519 /// PredicateOperand.
520 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
521 if (!MI->isPredicable())
524 ARMFunctionInfo *AFI =
525 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
527 if (AFI->isThumb2Function()) {
528 if (getSubtarget().restrictIT())
529 return isV8EligibleForIT(MI);
530 } else { // non-Thumb
531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
538 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
539 LLVM_ATTRIBUTE_NOINLINE
540 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
542 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
544 assert(JTI < JT.size());
545 return JT[JTI].MBBs.size();
548 /// GetInstSize - Return the size of the specified MachineInstr.
550 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
551 const MachineBasicBlock &MBB = *MI->getParent();
552 const MachineFunction *MF = MBB.getParent();
553 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
555 const MCInstrDesc &MCID = MI->getDesc();
557 return MCID.getSize();
559 // If this machine instr is an inline asm, measure it.
560 if (MI->getOpcode() == ARM::INLINEASM)
561 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
564 unsigned Opc = MI->getOpcode();
566 case TargetOpcode::IMPLICIT_DEF:
567 case TargetOpcode::KILL:
568 case TargetOpcode::PROLOG_LABEL:
569 case TargetOpcode::EH_LABEL:
570 case TargetOpcode::DBG_VALUE:
572 case TargetOpcode::BUNDLE:
573 return getInstBundleLength(MI);
574 case ARM::MOVi16_ga_pcrel:
575 case ARM::MOVTi16_ga_pcrel:
576 case ARM::t2MOVi16_ga_pcrel:
577 case ARM::t2MOVTi16_ga_pcrel:
580 case ARM::t2MOVi32imm:
582 case ARM::CONSTPOOL_ENTRY:
583 // If this machine instr is a constant pool entry, its size is recorded as
585 return MI->getOperand(2).getImm();
586 case ARM::Int_eh_sjlj_longjmp:
588 case ARM::tInt_eh_sjlj_longjmp:
590 case ARM::Int_eh_sjlj_setjmp:
591 case ARM::Int_eh_sjlj_setjmp_nofp:
593 case ARM::tInt_eh_sjlj_setjmp:
594 case ARM::t2Int_eh_sjlj_setjmp:
595 case ARM::t2Int_eh_sjlj_setjmp_nofp:
603 case ARM::t2TBH_JT: {
604 // These are jumptable branches, i.e. a branch followed by an inlined
605 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
606 // entry is one byte; TBH two byte each.
607 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
608 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
609 unsigned NumOps = MCID.getNumOperands();
610 MachineOperand JTOP =
611 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
612 unsigned JTI = JTOP.getIndex();
613 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
615 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
616 assert(JTI < JT.size());
617 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
618 // 4 aligned. The assembler / linker may add 2 byte padding just before
619 // the JT entries. The size does not include this padding; the
620 // constant islands pass does separate bookkeeping for it.
621 // FIXME: If we know the size of the function is less than (1 << 16) *2
622 // bytes, we can use 16-bit entries instead. Then there won't be an
624 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
625 unsigned NumEntries = getNumJTEntries(JT, JTI);
626 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
627 // Make sure the instruction that follows TBB is 2-byte aligned.
628 // FIXME: Constant island pass should insert an "ALIGN" instruction
631 return NumEntries * EntrySize + InstSize;
634 // Otherwise, pseudo-instruction sizes are zero.
639 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
641 MachineBasicBlock::const_instr_iterator I = MI;
642 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
643 while (++I != E && I->isInsideBundle()) {
644 assert(!I->isBundle() && "No nested bundle!");
645 Size += GetInstSizeInBytes(&*I);
650 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator I, DebugLoc DL,
652 unsigned DestReg, unsigned SrcReg,
653 bool KillSrc) const {
654 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
655 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
657 if (GPRDest && GPRSrc) {
658 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
659 .addReg(SrcReg, getKillRegState(KillSrc))));
663 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
664 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
667 if (SPRDest && SPRSrc)
669 else if (GPRDest && SPRSrc)
671 else if (SPRDest && GPRSrc)
673 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
675 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
679 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
680 MIB.addReg(SrcReg, getKillRegState(KillSrc));
681 if (Opc == ARM::VORRq)
682 MIB.addReg(SrcReg, getKillRegState(KillSrc));
687 // Handle register classes that require multiple instructions.
688 unsigned BeginIdx = 0;
689 unsigned SubRegs = 0;
692 // Use VORRq when possible.
693 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
695 BeginIdx = ARM::qsub_0;
697 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
699 BeginIdx = ARM::qsub_0;
701 // Fall back to VMOVD.
702 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
704 BeginIdx = ARM::dsub_0;
706 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
708 BeginIdx = ARM::dsub_0;
710 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
712 BeginIdx = ARM::dsub_0;
714 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
715 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
716 BeginIdx = ARM::gsub_0;
718 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
720 BeginIdx = ARM::dsub_0;
723 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
725 BeginIdx = ARM::dsub_0;
728 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
730 BeginIdx = ARM::dsub_0;
735 assert(Opc && "Impossible reg-to-reg copy");
737 const TargetRegisterInfo *TRI = &getRegisterInfo();
738 MachineInstrBuilder Mov;
740 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
741 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
742 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
746 SmallSet<unsigned, 4> DstRegs;
748 for (unsigned i = 0; i != SubRegs; ++i) {
749 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
750 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
751 assert(Dst && Src && "Bad sub-register");
753 assert(!DstRegs.count(Src) && "destructive vector copy");
756 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
757 // VORR takes two source operands.
758 if (Opc == ARM::VORRq)
760 Mov = AddDefaultPred(Mov);
762 if (Opc == ARM::MOVr)
763 Mov = AddDefaultCC(Mov);
765 // Add implicit super-register defs and kills to the last instruction.
766 Mov->addRegisterDefined(DestReg, TRI);
768 Mov->addRegisterKilled(SrcReg, TRI);
771 const MachineInstrBuilder &
772 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
773 unsigned SubIdx, unsigned State,
774 const TargetRegisterInfo *TRI) const {
776 return MIB.addReg(Reg, State);
778 if (TargetRegisterInfo::isPhysicalRegister(Reg))
779 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
780 return MIB.addReg(Reg, State, SubIdx);
783 void ARMBaseInstrInfo::
784 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
785 unsigned SrcReg, bool isKill, int FI,
786 const TargetRegisterClass *RC,
787 const TargetRegisterInfo *TRI) const {
789 if (I != MBB.end()) DL = I->getDebugLoc();
790 MachineFunction &MF = *MBB.getParent();
791 MachineFrameInfo &MFI = *MF.getFrameInfo();
792 unsigned Align = MFI.getObjectAlignment(FI);
794 MachineMemOperand *MMO =
795 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
796 MachineMemOperand::MOStore,
797 MFI.getObjectSize(FI),
800 switch (RC->getSize()) {
802 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
803 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
804 .addReg(SrcReg, getKillRegState(isKill))
805 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
806 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
807 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
808 .addReg(SrcReg, getKillRegState(isKill))
809 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
811 llvm_unreachable("Unknown reg class!");
814 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
815 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
816 .addReg(SrcReg, getKillRegState(isKill))
817 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
818 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
819 if (Subtarget.hasV5TEOps()) {
820 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
821 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
822 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
823 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
827 // Fallback to STM instruction, which has existed since the dawn of
829 MachineInstrBuilder MIB =
830 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
831 .addFrameIndex(FI).addMemOperand(MMO));
832 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
833 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
836 llvm_unreachable("Unknown reg class!");
839 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
840 // Use aligned spills if the stack can be realigned.
841 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
842 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
843 .addFrameIndex(FI).addImm(16)
844 .addReg(SrcReg, getKillRegState(isKill))
845 .addMemOperand(MMO));
847 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
848 .addReg(SrcReg, getKillRegState(isKill))
850 .addMemOperand(MMO));
853 llvm_unreachable("Unknown reg class!");
856 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
857 // Use aligned spills if the stack can be realigned.
858 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
859 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
860 .addFrameIndex(FI).addImm(16)
861 .addReg(SrcReg, getKillRegState(isKill))
862 .addMemOperand(MMO));
864 MachineInstrBuilder MIB =
865 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
868 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
869 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
870 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
873 llvm_unreachable("Unknown reg class!");
876 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
877 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
878 // FIXME: It's possible to only store part of the QQ register if the
879 // spilled def has a sub-register index.
880 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
881 .addFrameIndex(FI).addImm(16)
882 .addReg(SrcReg, getKillRegState(isKill))
883 .addMemOperand(MMO));
885 MachineInstrBuilder MIB =
886 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
889 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
890 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
891 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
892 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
895 llvm_unreachable("Unknown reg class!");
898 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
899 MachineInstrBuilder MIB =
900 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
903 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
904 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
905 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
906 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
907 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
908 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
909 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
910 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
912 llvm_unreachable("Unknown reg class!");
915 llvm_unreachable("Unknown reg class!");
920 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
921 int &FrameIndex) const {
922 switch (MI->getOpcode()) {
925 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
926 if (MI->getOperand(1).isFI() &&
927 MI->getOperand(2).isReg() &&
928 MI->getOperand(3).isImm() &&
929 MI->getOperand(2).getReg() == 0 &&
930 MI->getOperand(3).getImm() == 0) {
931 FrameIndex = MI->getOperand(1).getIndex();
932 return MI->getOperand(0).getReg();
940 if (MI->getOperand(1).isFI() &&
941 MI->getOperand(2).isImm() &&
942 MI->getOperand(2).getImm() == 0) {
943 FrameIndex = MI->getOperand(1).getIndex();
944 return MI->getOperand(0).getReg();
948 case ARM::VST1d64TPseudo:
949 case ARM::VST1d64QPseudo:
950 if (MI->getOperand(0).isFI() &&
951 MI->getOperand(2).getSubReg() == 0) {
952 FrameIndex = MI->getOperand(0).getIndex();
953 return MI->getOperand(2).getReg();
957 if (MI->getOperand(1).isFI() &&
958 MI->getOperand(0).getSubReg() == 0) {
959 FrameIndex = MI->getOperand(1).getIndex();
960 return MI->getOperand(0).getReg();
968 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
969 int &FrameIndex) const {
970 const MachineMemOperand *Dummy;
971 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
974 void ARMBaseInstrInfo::
975 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
976 unsigned DestReg, int FI,
977 const TargetRegisterClass *RC,
978 const TargetRegisterInfo *TRI) const {
980 if (I != MBB.end()) DL = I->getDebugLoc();
981 MachineFunction &MF = *MBB.getParent();
982 MachineFrameInfo &MFI = *MF.getFrameInfo();
983 unsigned Align = MFI.getObjectAlignment(FI);
984 MachineMemOperand *MMO =
985 MF.getMachineMemOperand(
986 MachinePointerInfo::getFixedStack(FI),
987 MachineMemOperand::MOLoad,
988 MFI.getObjectSize(FI),
991 switch (RC->getSize()) {
993 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
994 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
995 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
997 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
998 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
999 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1001 llvm_unreachable("Unknown reg class!");
1004 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1005 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1006 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1007 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1008 MachineInstrBuilder MIB;
1010 if (Subtarget.hasV5TEOps()) {
1011 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1012 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1013 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1014 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1016 AddDefaultPred(MIB);
1018 // Fallback to LDM instruction, which has existed since the dawn of
1020 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1021 .addFrameIndex(FI).addMemOperand(MMO));
1022 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1023 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1026 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1027 MIB.addReg(DestReg, RegState::ImplicitDefine);
1029 llvm_unreachable("Unknown reg class!");
1032 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1033 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1034 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1035 .addFrameIndex(FI).addImm(16)
1036 .addMemOperand(MMO));
1038 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1040 .addMemOperand(MMO));
1043 llvm_unreachable("Unknown reg class!");
1046 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1047 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1048 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1049 .addFrameIndex(FI).addImm(16)
1050 .addMemOperand(MMO));
1052 MachineInstrBuilder MIB =
1053 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1055 .addMemOperand(MMO));
1056 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1057 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1058 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1059 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1060 MIB.addReg(DestReg, RegState::ImplicitDefine);
1063 llvm_unreachable("Unknown reg class!");
1066 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1067 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1068 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1069 .addFrameIndex(FI).addImm(16)
1070 .addMemOperand(MMO));
1072 MachineInstrBuilder MIB =
1073 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1075 .addMemOperand(MMO);
1076 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1077 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1078 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1079 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1080 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1081 MIB.addReg(DestReg, RegState::ImplicitDefine);
1084 llvm_unreachable("Unknown reg class!");
1087 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1088 MachineInstrBuilder MIB =
1089 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1091 .addMemOperand(MMO);
1092 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1093 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1094 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1095 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1096 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1097 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1098 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1099 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1100 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1101 MIB.addReg(DestReg, RegState::ImplicitDefine);
1103 llvm_unreachable("Unknown reg class!");
1106 llvm_unreachable("Unknown regclass!");
1111 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1112 int &FrameIndex) const {
1113 switch (MI->getOpcode()) {
1116 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1117 if (MI->getOperand(1).isFI() &&
1118 MI->getOperand(2).isReg() &&
1119 MI->getOperand(3).isImm() &&
1120 MI->getOperand(2).getReg() == 0 &&
1121 MI->getOperand(3).getImm() == 0) {
1122 FrameIndex = MI->getOperand(1).getIndex();
1123 return MI->getOperand(0).getReg();
1131 if (MI->getOperand(1).isFI() &&
1132 MI->getOperand(2).isImm() &&
1133 MI->getOperand(2).getImm() == 0) {
1134 FrameIndex = MI->getOperand(1).getIndex();
1135 return MI->getOperand(0).getReg();
1139 case ARM::VLD1d64TPseudo:
1140 case ARM::VLD1d64QPseudo:
1141 if (MI->getOperand(1).isFI() &&
1142 MI->getOperand(0).getSubReg() == 0) {
1143 FrameIndex = MI->getOperand(1).getIndex();
1144 return MI->getOperand(0).getReg();
1148 if (MI->getOperand(1).isFI() &&
1149 MI->getOperand(0).getSubReg() == 0) {
1150 FrameIndex = MI->getOperand(1).getIndex();
1151 return MI->getOperand(0).getReg();
1159 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1160 int &FrameIndex) const {
1161 const MachineMemOperand *Dummy;
1162 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1165 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1166 // This hook gets to expand COPY instructions before they become
1167 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1168 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1169 // changed into a VORR that can go down the NEON pipeline.
1170 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1173 // Look for a copy between even S-registers. That is where we keep floats
1174 // when using NEON v2f32 instructions for f32 arithmetic.
1175 unsigned DstRegS = MI->getOperand(0).getReg();
1176 unsigned SrcRegS = MI->getOperand(1).getReg();
1177 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1180 const TargetRegisterInfo *TRI = &getRegisterInfo();
1181 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1183 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1185 if (!DstRegD || !SrcRegD)
1188 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1189 // legal if the COPY already defines the full DstRegD, and it isn't a
1190 // sub-register insertion.
1191 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1194 // A dead copy shouldn't show up here, but reject it just in case.
1195 if (MI->getOperand(0).isDead())
1198 // All clear, widen the COPY.
1199 DEBUG(dbgs() << "widening: " << *MI);
1200 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1202 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1203 // or some other super-register.
1204 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1205 if (ImpDefIdx != -1)
1206 MI->RemoveOperand(ImpDefIdx);
1208 // Change the opcode and operands.
1209 MI->setDesc(get(ARM::VMOVD));
1210 MI->getOperand(0).setReg(DstRegD);
1211 MI->getOperand(1).setReg(SrcRegD);
1212 AddDefaultPred(MIB);
1214 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1215 // register scavenger and machine verifier, so we need to indicate that we
1216 // are reading an undefined value from SrcRegD, but a proper value from
1218 MI->getOperand(1).setIsUndef();
1219 MIB.addReg(SrcRegS, RegState::Implicit);
1221 // SrcRegD may actually contain an unrelated value in the ssub_1
1222 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1223 if (MI->getOperand(1).isKill()) {
1224 MI->getOperand(1).setIsKill(false);
1225 MI->addRegisterKilled(SrcRegS, TRI, true);
1228 DEBUG(dbgs() << "replaced by: " << *MI);
1232 /// Create a copy of a const pool value. Update CPI to the new index and return
1234 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1235 MachineConstantPool *MCP = MF.getConstantPool();
1236 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1238 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1239 assert(MCPE.isMachineConstantPoolEntry() &&
1240 "Expecting a machine constantpool entry!");
1241 ARMConstantPoolValue *ACPV =
1242 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1244 unsigned PCLabelId = AFI->createPICLabelUId();
1245 ARMConstantPoolValue *NewCPV = 0;
1246 // FIXME: The below assumes PIC relocation model and that the function
1247 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1248 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1249 // instructions, so that's probably OK, but is PIC always correct when
1251 if (ACPV->isGlobalValue())
1252 NewCPV = ARMConstantPoolConstant::
1253 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1255 else if (ACPV->isExtSymbol())
1256 NewCPV = ARMConstantPoolSymbol::
1257 Create(MF.getFunction()->getContext(),
1258 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1259 else if (ACPV->isBlockAddress())
1260 NewCPV = ARMConstantPoolConstant::
1261 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1262 ARMCP::CPBlockAddress, 4);
1263 else if (ACPV->isLSDA())
1264 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1266 else if (ACPV->isMachineBasicBlock())
1267 NewCPV = ARMConstantPoolMBB::
1268 Create(MF.getFunction()->getContext(),
1269 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1271 llvm_unreachable("Unexpected ARM constantpool value type!!");
1272 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1276 void ARMBaseInstrInfo::
1277 reMaterialize(MachineBasicBlock &MBB,
1278 MachineBasicBlock::iterator I,
1279 unsigned DestReg, unsigned SubIdx,
1280 const MachineInstr *Orig,
1281 const TargetRegisterInfo &TRI) const {
1282 unsigned Opcode = Orig->getOpcode();
1285 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1286 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1290 case ARM::tLDRpci_pic:
1291 case ARM::t2LDRpci_pic: {
1292 MachineFunction &MF = *MBB.getParent();
1293 unsigned CPI = Orig->getOperand(1).getIndex();
1294 unsigned PCLabelId = duplicateCPV(MF, CPI);
1295 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1297 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1298 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1305 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1306 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1307 switch(Orig->getOpcode()) {
1308 case ARM::tLDRpci_pic:
1309 case ARM::t2LDRpci_pic: {
1310 unsigned CPI = Orig->getOperand(1).getIndex();
1311 unsigned PCLabelId = duplicateCPV(MF, CPI);
1312 Orig->getOperand(1).setIndex(CPI);
1313 Orig->getOperand(2).setImm(PCLabelId);
1320 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1321 const MachineInstr *MI1,
1322 const MachineRegisterInfo *MRI) const {
1323 int Opcode = MI0->getOpcode();
1324 if (Opcode == ARM::t2LDRpci ||
1325 Opcode == ARM::t2LDRpci_pic ||
1326 Opcode == ARM::tLDRpci ||
1327 Opcode == ARM::tLDRpci_pic ||
1328 Opcode == ARM::LDRLIT_ga_pcrel ||
1329 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1330 Opcode == ARM::tLDRLIT_ga_pcrel ||
1331 Opcode == ARM::MOV_ga_pcrel ||
1332 Opcode == ARM::MOV_ga_pcrel_ldr ||
1333 Opcode == ARM::t2MOV_ga_pcrel) {
1334 if (MI1->getOpcode() != Opcode)
1336 if (MI0->getNumOperands() != MI1->getNumOperands())
1339 const MachineOperand &MO0 = MI0->getOperand(1);
1340 const MachineOperand &MO1 = MI1->getOperand(1);
1341 if (MO0.getOffset() != MO1.getOffset())
1344 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1345 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1346 Opcode == ARM::tLDRLIT_ga_pcrel ||
1347 Opcode == ARM::MOV_ga_pcrel ||
1348 Opcode == ARM::MOV_ga_pcrel_ldr ||
1349 Opcode == ARM::t2MOV_ga_pcrel)
1350 // Ignore the PC labels.
1351 return MO0.getGlobal() == MO1.getGlobal();
1353 const MachineFunction *MF = MI0->getParent()->getParent();
1354 const MachineConstantPool *MCP = MF->getConstantPool();
1355 int CPI0 = MO0.getIndex();
1356 int CPI1 = MO1.getIndex();
1357 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1358 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1359 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1360 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1361 if (isARMCP0 && isARMCP1) {
1362 ARMConstantPoolValue *ACPV0 =
1363 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1364 ARMConstantPoolValue *ACPV1 =
1365 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1366 return ACPV0->hasSameValue(ACPV1);
1367 } else if (!isARMCP0 && !isARMCP1) {
1368 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1371 } else if (Opcode == ARM::PICLDR) {
1372 if (MI1->getOpcode() != Opcode)
1374 if (MI0->getNumOperands() != MI1->getNumOperands())
1377 unsigned Addr0 = MI0->getOperand(1).getReg();
1378 unsigned Addr1 = MI1->getOperand(1).getReg();
1379 if (Addr0 != Addr1) {
1381 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1382 !TargetRegisterInfo::isVirtualRegister(Addr1))
1385 // This assumes SSA form.
1386 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1387 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1388 // Check if the loaded value, e.g. a constantpool of a global address, are
1390 if (!produceSameValue(Def0, Def1, MRI))
1394 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1395 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1396 const MachineOperand &MO0 = MI0->getOperand(i);
1397 const MachineOperand &MO1 = MI1->getOperand(i);
1398 if (!MO0.isIdenticalTo(MO1))
1404 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1407 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1408 /// determine if two loads are loading from the same base address. It should
1409 /// only return true if the base pointers are the same and the only differences
1410 /// between the two addresses is the offset. It also returns the offsets by
1413 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1414 /// is permanently disabled.
1415 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1417 int64_t &Offset2) const {
1418 // Don't worry about Thumb: just ARM and Thumb2.
1419 if (Subtarget.isThumb1Only()) return false;
1421 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1424 switch (Load1->getMachineOpcode()) {
1438 case ARM::t2LDRSHi8:
1440 case ARM::t2LDRBi12:
1441 case ARM::t2LDRSHi12:
1445 switch (Load2->getMachineOpcode()) {
1458 case ARM::t2LDRSHi8:
1460 case ARM::t2LDRBi12:
1461 case ARM::t2LDRSHi12:
1465 // Check if base addresses and chain operands match.
1466 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1467 Load1->getOperand(4) != Load2->getOperand(4))
1470 // Index should be Reg0.
1471 if (Load1->getOperand(3) != Load2->getOperand(3))
1474 // Determine the offsets.
1475 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1476 isa<ConstantSDNode>(Load2->getOperand(1))) {
1477 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1478 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1485 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1486 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1487 /// be scheduled togther. On some targets if two loads are loading from
1488 /// addresses in the same cache line, it's better if they are scheduled
1489 /// together. This function takes two integers that represent the load offsets
1490 /// from the common base address. It returns true if it decides it's desirable
1491 /// to schedule the two loads together. "NumLoads" is the number of loads that
1492 /// have already been scheduled after Load1.
1494 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1495 /// is permanently disabled.
1496 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1497 int64_t Offset1, int64_t Offset2,
1498 unsigned NumLoads) const {
1499 // Don't worry about Thumb: just ARM and Thumb2.
1500 if (Subtarget.isThumb1Only()) return false;
1502 assert(Offset2 > Offset1);
1504 if ((Offset2 - Offset1) / 8 > 64)
1507 // Check if the machine opcodes are different. If they are different
1508 // then we consider them to not be of the same base address,
1509 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1510 // In this case, they are considered to be the same because they are different
1511 // encoding forms of the same basic instruction.
1512 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1513 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1514 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1515 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1516 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1517 return false; // FIXME: overly conservative?
1519 // Four loads in a row should be sufficient.
1526 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1527 const MachineBasicBlock *MBB,
1528 const MachineFunction &MF) const {
1529 // Debug info is never a scheduling boundary. It's necessary to be explicit
1530 // due to the special treatment of IT instructions below, otherwise a
1531 // dbg_value followed by an IT will result in the IT instruction being
1532 // considered a scheduling hazard, which is wrong. It should be the actual
1533 // instruction preceding the dbg_value instruction(s), just like it is
1534 // when debug info is not present.
1535 if (MI->isDebugValue())
1538 // Terminators and labels can't be scheduled around.
1539 if (MI->isTerminator() || MI->isLabel())
1542 // Treat the start of the IT block as a scheduling boundary, but schedule
1543 // t2IT along with all instructions following it.
1544 // FIXME: This is a big hammer. But the alternative is to add all potential
1545 // true and anti dependencies to IT block instructions as implicit operands
1546 // to the t2IT instruction. The added compile time and complexity does not
1548 MachineBasicBlock::const_iterator I = MI;
1549 // Make sure to skip any dbg_value instructions
1550 while (++I != MBB->end() && I->isDebugValue())
1552 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1555 // Don't attempt to schedule around any instruction that defines
1556 // a stack-oriented pointer, as it's unlikely to be profitable. This
1557 // saves compile time, because it doesn't require every single
1558 // stack slot reference to depend on the instruction that does the
1560 // Calls don't actually change the stack pointer, even if they have imp-defs.
1561 // No ARM calling conventions change the stack pointer. (X86 calling
1562 // conventions sometimes do).
1563 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1569 bool ARMBaseInstrInfo::
1570 isProfitableToIfCvt(MachineBasicBlock &MBB,
1571 unsigned NumCycles, unsigned ExtraPredCycles,
1572 const BranchProbability &Probability) const {
1576 // Attempt to estimate the relative costs of predication versus branching.
1577 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1578 UnpredCost /= Probability.getDenominator();
1579 UnpredCost += 1; // The branch itself
1580 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1582 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1585 bool ARMBaseInstrInfo::
1586 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1587 unsigned TCycles, unsigned TExtra,
1588 MachineBasicBlock &FMBB,
1589 unsigned FCycles, unsigned FExtra,
1590 const BranchProbability &Probability) const {
1591 if (!TCycles || !FCycles)
1594 // Attempt to estimate the relative costs of predication versus branching.
1595 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1596 TUnpredCost /= Probability.getDenominator();
1598 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1599 unsigned FUnpredCost = Comp * FCycles;
1600 FUnpredCost /= Probability.getDenominator();
1602 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1603 UnpredCost += 1; // The branch itself
1604 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1606 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1610 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1611 MachineBasicBlock &FMBB) const {
1612 // Reduce false anti-dependencies to let Swift's out-of-order execution
1613 // engine do its thing.
1614 return Subtarget.isSwift();
1617 /// getInstrPredicate - If instruction is predicated, returns its predicate
1618 /// condition, otherwise returns AL. It also returns the condition code
1619 /// register by reference.
1621 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1622 int PIdx = MI->findFirstPredOperandIdx();
1628 PredReg = MI->getOperand(PIdx+1).getReg();
1629 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1633 int llvm::getMatchingCondBranchOpcode(int Opc) {
1638 if (Opc == ARM::t2B)
1641 llvm_unreachable("Unknown unconditional branch opcode!");
1644 /// commuteInstruction - Handle commutable instructions.
1646 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1647 switch (MI->getOpcode()) {
1649 case ARM::t2MOVCCr: {
1650 // MOVCC can be commuted by inverting the condition.
1651 unsigned PredReg = 0;
1652 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1653 // MOVCC AL can't be inverted. Shouldn't happen.
1654 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1656 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1659 // After swapping the MOVCC operands, also invert the condition.
1660 MI->getOperand(MI->findFirstPredOperandIdx())
1661 .setImm(ARMCC::getOppositeCondition(CC));
1665 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1668 /// Identify instructions that can be folded into a MOVCC instruction, and
1669 /// return the defining instruction.
1670 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1671 const MachineRegisterInfo &MRI,
1672 const TargetInstrInfo *TII) {
1673 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1675 if (!MRI.hasOneNonDBGUse(Reg))
1677 MachineInstr *MI = MRI.getVRegDef(Reg);
1680 // MI is folded into the MOVCC by predicating it.
1681 if (!MI->isPredicable())
1683 // Check if MI has any non-dead defs or physreg uses. This also detects
1684 // predicated instructions which will be reading CPSR.
1685 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1686 const MachineOperand &MO = MI->getOperand(i);
1687 // Reject frame index operands, PEI can't handle the predicated pseudos.
1688 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1692 // MI can't have any tied operands, that would conflict with predication.
1695 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1697 if (MO.isDef() && !MO.isDead())
1700 bool DontMoveAcrossStores = true;
1701 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1706 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1707 SmallVectorImpl<MachineOperand> &Cond,
1708 unsigned &TrueOp, unsigned &FalseOp,
1709 bool &Optimizable) const {
1710 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1711 "Unknown select instruction");
1716 // 3: Condition code.
1720 Cond.push_back(MI->getOperand(3));
1721 Cond.push_back(MI->getOperand(4));
1722 // We can always fold a def.
1727 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1728 bool PreferFalse) const {
1729 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1730 "Unknown select instruction");
1731 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1732 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1733 bool Invert = !DefMI;
1735 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1739 // Find new register class to use.
1740 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1741 unsigned DestReg = MI->getOperand(0).getReg();
1742 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1743 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1746 // Create a new predicated version of DefMI.
1747 // Rfalse is the first use.
1748 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1749 DefMI->getDesc(), DestReg);
1751 // Copy all the DefMI operands, excluding its (null) predicate.
1752 const MCInstrDesc &DefDesc = DefMI->getDesc();
1753 for (unsigned i = 1, e = DefDesc.getNumOperands();
1754 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1755 NewMI.addOperand(DefMI->getOperand(i));
1757 unsigned CondCode = MI->getOperand(3).getImm();
1759 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1761 NewMI.addImm(CondCode);
1762 NewMI.addOperand(MI->getOperand(4));
1764 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1765 if (NewMI->hasOptionalDef())
1766 AddDefaultCC(NewMI);
1768 // The output register value when the predicate is false is an implicit
1769 // register operand tied to the first def.
1770 // The tie makes the register allocator ensure the FalseReg is allocated the
1771 // same register as operand 0.
1772 FalseReg.setImplicit();
1773 NewMI.addOperand(FalseReg);
1774 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1776 // The caller will erase MI, but not DefMI.
1777 DefMI->eraseFromParent();
1781 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1782 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1785 /// This will go away once we can teach tblgen how to set the optional CPSR def
1787 struct AddSubFlagsOpcodePair {
1789 uint16_t MachineOpc;
1792 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1793 {ARM::ADDSri, ARM::ADDri},
1794 {ARM::ADDSrr, ARM::ADDrr},
1795 {ARM::ADDSrsi, ARM::ADDrsi},
1796 {ARM::ADDSrsr, ARM::ADDrsr},
1798 {ARM::SUBSri, ARM::SUBri},
1799 {ARM::SUBSrr, ARM::SUBrr},
1800 {ARM::SUBSrsi, ARM::SUBrsi},
1801 {ARM::SUBSrsr, ARM::SUBrsr},
1803 {ARM::RSBSri, ARM::RSBri},
1804 {ARM::RSBSrsi, ARM::RSBrsi},
1805 {ARM::RSBSrsr, ARM::RSBrsr},
1807 {ARM::t2ADDSri, ARM::t2ADDri},
1808 {ARM::t2ADDSrr, ARM::t2ADDrr},
1809 {ARM::t2ADDSrs, ARM::t2ADDrs},
1811 {ARM::t2SUBSri, ARM::t2SUBri},
1812 {ARM::t2SUBSrr, ARM::t2SUBrr},
1813 {ARM::t2SUBSrs, ARM::t2SUBrs},
1815 {ARM::t2RSBSri, ARM::t2RSBri},
1816 {ARM::t2RSBSrs, ARM::t2RSBrs},
1819 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1820 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1821 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1822 return AddSubFlagsOpcodeMap[i].MachineOpc;
1826 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1827 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1828 unsigned DestReg, unsigned BaseReg, int NumBytes,
1829 ARMCC::CondCodes Pred, unsigned PredReg,
1830 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1831 if (NumBytes == 0 && DestReg != BaseReg) {
1832 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1833 .addReg(BaseReg, RegState::Kill)
1834 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1835 .setMIFlags(MIFlags);
1839 bool isSub = NumBytes < 0;
1840 if (isSub) NumBytes = -NumBytes;
1843 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1844 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1845 assert(ThisVal && "Didn't extract field correctly");
1847 // We will handle these bits from offset, clear them.
1848 NumBytes &= ~ThisVal;
1850 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1852 // Build the new ADD / SUB.
1853 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1854 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1855 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1856 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1857 .setMIFlags(MIFlags);
1862 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1863 MachineFunction &MF, MachineInstr *MI,
1864 unsigned NumBytes) {
1865 // This optimisation potentially adds lots of load and store
1866 // micro-operations, it's only really a great benefit to code-size.
1867 if (!Subtarget.isMinSize())
1870 // If only one register is pushed/popped, LLVM can use an LDR/STR
1871 // instead. We can't modify those so make sure we're dealing with an
1872 // instruction we understand.
1873 bool IsPop = isPopOpcode(MI->getOpcode());
1874 bool IsPush = isPushOpcode(MI->getOpcode());
1875 if (!IsPush && !IsPop)
1878 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1879 MI->getOpcode() == ARM::VLDMDIA_UPD;
1880 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
1881 MI->getOpcode() == ARM::tPOP ||
1882 MI->getOpcode() == ARM::tPOP_RET;
1884 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
1885 MI->getOperand(1).getReg() == ARM::SP)) &&
1886 "trying to fold sp update into non-sp-updating push/pop");
1888 // The VFP push & pop act on D-registers, so we can only fold an adjustment
1889 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
1890 // if this is violated.
1891 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
1894 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
1895 // pred) so the list starts at 4. Thumb1 starts after the predicate.
1896 int RegListIdx = IsT1PushPop ? 2 : 4;
1898 // Calculate the space we'll need in terms of registers.
1899 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
1900 unsigned RD0Reg, RegsNeeded;
1903 RegsNeeded = NumBytes / 8;
1906 RegsNeeded = NumBytes / 4;
1909 // We're going to have to strip all list operands off before
1910 // re-adding them since the order matters, so save the existing ones
1912 SmallVector<MachineOperand, 4> RegList;
1913 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1914 RegList.push_back(MI->getOperand(i));
1916 MachineBasicBlock *MBB = MI->getParent();
1917 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
1918 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
1920 // Now try to find enough space in the reglist to allocate NumBytes.
1921 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
1924 // Pushing any register is completely harmless, mark the
1925 // register involved as undef since we don't care about it in
1927 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
1928 false, false, true));
1933 // However, we can only pop an extra register if it's not live. For
1934 // registers live within the function we might clobber a return value
1935 // register; the other way a register can be live here is if it's
1937 if (isCalleeSavedRegister(CurReg, CSRegs) ||
1938 MBB->computeRegisterLiveness(TRI, CurReg, MI) !=
1939 MachineBasicBlock::LQR_Dead) {
1940 // VFP pops don't allow holes in the register list, so any skip is fatal
1941 // for our transformation. GPR pops do, so we should just keep looking.
1948 // Mark the unimportant registers as <def,dead> in the POP.
1949 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
1957 // Finally we know we can profitably perform the optimisation so go
1958 // ahead: strip all existing registers off and add them back again
1959 // in the right order.
1960 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1961 MI->RemoveOperand(i);
1963 // Add the complete list back in.
1964 MachineInstrBuilder MIB(MF, &*MI);
1965 for (int i = RegList.size() - 1; i >= 0; --i)
1966 MIB.addOperand(RegList[i]);
1971 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1972 unsigned FrameReg, int &Offset,
1973 const ARMBaseInstrInfo &TII) {
1974 unsigned Opcode = MI.getOpcode();
1975 const MCInstrDesc &Desc = MI.getDesc();
1976 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1979 // Memory operands in inline assembly always use AddrMode2.
1980 if (Opcode == ARM::INLINEASM)
1981 AddrMode = ARMII::AddrMode2;
1983 if (Opcode == ARM::ADDri) {
1984 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1986 // Turn it into a move.
1987 MI.setDesc(TII.get(ARM::MOVr));
1988 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1989 MI.RemoveOperand(FrameRegIdx+1);
1992 } else if (Offset < 0) {
1995 MI.setDesc(TII.get(ARM::SUBri));
1998 // Common case: small offset, fits into instruction.
1999 if (ARM_AM::getSOImmVal(Offset) != -1) {
2000 // Replace the FrameIndex with sp / fp
2001 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2002 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2007 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2009 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2010 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2012 // We will handle these bits from offset, clear them.
2013 Offset &= ~ThisImmVal;
2015 // Get the properly encoded SOImmVal field.
2016 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2017 "Bit extraction didn't work?");
2018 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2020 unsigned ImmIdx = 0;
2022 unsigned NumBits = 0;
2025 case ARMII::AddrMode_i12: {
2026 ImmIdx = FrameRegIdx + 1;
2027 InstrOffs = MI.getOperand(ImmIdx).getImm();
2031 case ARMII::AddrMode2: {
2032 ImmIdx = FrameRegIdx+2;
2033 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2034 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2039 case ARMII::AddrMode3: {
2040 ImmIdx = FrameRegIdx+2;
2041 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2042 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2047 case ARMII::AddrMode4:
2048 case ARMII::AddrMode6:
2049 // Can't fold any offset even if it's zero.
2051 case ARMII::AddrMode5: {
2052 ImmIdx = FrameRegIdx+1;
2053 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2054 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2061 llvm_unreachable("Unsupported addressing mode!");
2064 Offset += InstrOffs * Scale;
2065 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2071 // Attempt to fold address comp. if opcode has offset bits
2073 // Common case: small offset, fits into instruction.
2074 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2075 int ImmedOffset = Offset / Scale;
2076 unsigned Mask = (1 << NumBits) - 1;
2077 if ((unsigned)Offset <= Mask * Scale) {
2078 // Replace the FrameIndex with sp
2079 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2080 // FIXME: When addrmode2 goes away, this will simplify (like the
2081 // T2 version), as the LDR.i12 versions don't need the encoding
2082 // tricks for the offset value.
2084 if (AddrMode == ARMII::AddrMode_i12)
2085 ImmedOffset = -ImmedOffset;
2087 ImmedOffset |= 1 << NumBits;
2089 ImmOp.ChangeToImmediate(ImmedOffset);
2094 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2095 ImmedOffset = ImmedOffset & Mask;
2097 if (AddrMode == ARMII::AddrMode_i12)
2098 ImmedOffset = -ImmedOffset;
2100 ImmedOffset |= 1 << NumBits;
2102 ImmOp.ChangeToImmediate(ImmedOffset);
2103 Offset &= ~(Mask*Scale);
2107 Offset = (isSub) ? -Offset : Offset;
2111 /// analyzeCompare - For a comparison instruction, return the source registers
2112 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2113 /// compares against in CmpValue. Return true if the comparison instruction
2114 /// can be analyzed.
2115 bool ARMBaseInstrInfo::
2116 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2117 int &CmpMask, int &CmpValue) const {
2118 switch (MI->getOpcode()) {
2122 SrcReg = MI->getOperand(0).getReg();
2125 CmpValue = MI->getOperand(1).getImm();
2129 SrcReg = MI->getOperand(0).getReg();
2130 SrcReg2 = MI->getOperand(1).getReg();
2136 SrcReg = MI->getOperand(0).getReg();
2138 CmpMask = MI->getOperand(1).getImm();
2146 /// isSuitableForMask - Identify a suitable 'and' instruction that
2147 /// operates on the given source register and applies the same mask
2148 /// as a 'tst' instruction. Provide a limited look-through for copies.
2149 /// When successful, MI will hold the found instruction.
2150 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2151 int CmpMask, bool CommonUse) {
2152 switch (MI->getOpcode()) {
2155 if (CmpMask != MI->getOperand(2).getImm())
2157 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2161 // Walk down one instruction which is potentially an 'and'.
2162 const MachineInstr &Copy = *MI;
2163 MachineBasicBlock::iterator AND(
2164 llvm::next(MachineBasicBlock::iterator(MI)));
2165 if (AND == MI->getParent()->end()) return false;
2167 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2175 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2176 /// the condition code if we modify the instructions such that flags are
2178 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2180 default: return ARMCC::AL;
2181 case ARMCC::EQ: return ARMCC::EQ;
2182 case ARMCC::NE: return ARMCC::NE;
2183 case ARMCC::HS: return ARMCC::LS;
2184 case ARMCC::LO: return ARMCC::HI;
2185 case ARMCC::HI: return ARMCC::LO;
2186 case ARMCC::LS: return ARMCC::HS;
2187 case ARMCC::GE: return ARMCC::LE;
2188 case ARMCC::LT: return ARMCC::GT;
2189 case ARMCC::GT: return ARMCC::LT;
2190 case ARMCC::LE: return ARMCC::GE;
2194 /// isRedundantFlagInstr - check whether the first instruction, whose only
2195 /// purpose is to update flags, can be made redundant.
2196 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2197 /// CMPri can be made redundant by SUBri if the operands are the same.
2198 /// This function can be extended later on.
2199 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2200 unsigned SrcReg2, int ImmValue,
2202 if ((CmpI->getOpcode() == ARM::CMPrr ||
2203 CmpI->getOpcode() == ARM::t2CMPrr) &&
2204 (OI->getOpcode() == ARM::SUBrr ||
2205 OI->getOpcode() == ARM::t2SUBrr) &&
2206 ((OI->getOperand(1).getReg() == SrcReg &&
2207 OI->getOperand(2).getReg() == SrcReg2) ||
2208 (OI->getOperand(1).getReg() == SrcReg2 &&
2209 OI->getOperand(2).getReg() == SrcReg)))
2212 if ((CmpI->getOpcode() == ARM::CMPri ||
2213 CmpI->getOpcode() == ARM::t2CMPri) &&
2214 (OI->getOpcode() == ARM::SUBri ||
2215 OI->getOpcode() == ARM::t2SUBri) &&
2216 OI->getOperand(1).getReg() == SrcReg &&
2217 OI->getOperand(2).getImm() == ImmValue)
2222 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2223 /// comparison into one that sets the zero bit in the flags register;
2224 /// Remove a redundant Compare instruction if an earlier instruction can set the
2225 /// flags in the same way as Compare.
2226 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2227 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2228 /// condition code of instructions which use the flags.
2229 bool ARMBaseInstrInfo::
2230 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2231 int CmpMask, int CmpValue,
2232 const MachineRegisterInfo *MRI) const {
2233 // Get the unique definition of SrcReg.
2234 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2235 if (!MI) return false;
2237 // Masked compares sometimes use the same register as the corresponding 'and'.
2238 if (CmpMask != ~0) {
2239 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2241 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2242 UE = MRI->use_end(); UI != UE; ++UI) {
2243 if (UI->getParent() != CmpInstr->getParent()) continue;
2244 MachineInstr *PotentialAND = &*UI;
2245 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2246 isPredicated(PotentialAND))
2251 if (!MI) return false;
2255 // Get ready to iterate backward from CmpInstr.
2256 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2257 B = CmpInstr->getParent()->begin();
2259 // Early exit if CmpInstr is at the beginning of the BB.
2260 if (I == B) return false;
2262 // There are two possible candidates which can be changed to set CPSR:
2263 // One is MI, the other is a SUB instruction.
2264 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2265 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2266 MachineInstr *Sub = NULL;
2268 // MI is not a candidate for CMPrr.
2270 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2271 // Conservatively refuse to convert an instruction which isn't in the same
2272 // BB as the comparison.
2273 // For CMPri, we need to check Sub, thus we can't return here.
2274 if (CmpInstr->getOpcode() == ARM::CMPri ||
2275 CmpInstr->getOpcode() == ARM::t2CMPri)
2281 // Check that CPSR isn't set between the comparison instruction and the one we
2282 // want to change. At the same time, search for Sub.
2283 const TargetRegisterInfo *TRI = &getRegisterInfo();
2285 for (; I != E; --I) {
2286 const MachineInstr &Instr = *I;
2288 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2289 Instr.readsRegister(ARM::CPSR, TRI))
2290 // This instruction modifies or uses CPSR after the one we want to
2291 // change. We can't do this transformation.
2294 // Check whether CmpInstr can be made redundant by the current instruction.
2295 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2301 // The 'and' is below the comparison instruction.
2305 // Return false if no candidates exist.
2309 // The single candidate is called MI.
2312 // We can't use a predicated instruction - it doesn't always write the flags.
2313 if (isPredicated(MI))
2316 switch (MI->getOpcode()) {
2350 case ARM::t2EORri: {
2351 // Scan forward for the use of CPSR
2352 // When checking against MI: if it's a conditional code requires
2353 // checking of V bit, then this is not safe to do.
2354 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2355 // If we are done with the basic block, we need to check whether CPSR is
2357 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2359 bool isSafe = false;
2361 E = CmpInstr->getParent()->end();
2362 while (!isSafe && ++I != E) {
2363 const MachineInstr &Instr = *I;
2364 for (unsigned IO = 0, EO = Instr.getNumOperands();
2365 !isSafe && IO != EO; ++IO) {
2366 const MachineOperand &MO = Instr.getOperand(IO);
2367 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2371 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2377 // Condition code is after the operand before CPSR except for VSELs.
2378 ARMCC::CondCodes CC;
2379 bool IsInstrVSel = true;
2380 switch (Instr.getOpcode()) {
2382 IsInstrVSel = false;
2383 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2404 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2405 if (NewCC == ARMCC::AL)
2407 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2408 // on CMP needs to be updated to be based on SUB.
2409 // Push the condition code operands to OperandsToUpdate.
2410 // If it is safe to remove CmpInstr, the condition code of these
2411 // operands will be modified.
2412 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2413 Sub->getOperand(2).getReg() == SrcReg) {
2414 // VSel doesn't support condition code update.
2417 OperandsToUpdate.push_back(
2418 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2423 // CPSR can be used multiple times, we should continue.
2436 // If CPSR is not killed nor re-defined, we should check whether it is
2437 // live-out. If it is live-out, do not optimize.
2439 MachineBasicBlock *MBB = CmpInstr->getParent();
2440 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2441 SE = MBB->succ_end(); SI != SE; ++SI)
2442 if ((*SI)->isLiveIn(ARM::CPSR))
2446 // Toggle the optional operand to CPSR.
2447 MI->getOperand(5).setReg(ARM::CPSR);
2448 MI->getOperand(5).setIsDef(true);
2449 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2450 CmpInstr->eraseFromParent();
2452 // Modify the condition code of operands in OperandsToUpdate.
2453 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2454 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2455 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2456 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2464 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2465 MachineInstr *DefMI, unsigned Reg,
2466 MachineRegisterInfo *MRI) const {
2467 // Fold large immediates into add, sub, or, xor.
2468 unsigned DefOpc = DefMI->getOpcode();
2469 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2471 if (!DefMI->getOperand(1).isImm())
2472 // Could be t2MOVi32imm <ga:xx>
2475 if (!MRI->hasOneNonDBGUse(Reg))
2478 const MCInstrDesc &DefMCID = DefMI->getDesc();
2479 if (DefMCID.hasOptionalDef()) {
2480 unsigned NumOps = DefMCID.getNumOperands();
2481 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2482 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2483 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2488 const MCInstrDesc &UseMCID = UseMI->getDesc();
2489 if (UseMCID.hasOptionalDef()) {
2490 unsigned NumOps = UseMCID.getNumOperands();
2491 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2492 // If the instruction sets the flag, do not attempt this optimization
2493 // since it may change the semantics of the code.
2497 unsigned UseOpc = UseMI->getOpcode();
2498 unsigned NewUseOpc = 0;
2499 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2500 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2501 bool Commute = false;
2503 default: return false;
2511 case ARM::t2EORrr: {
2512 Commute = UseMI->getOperand(2).getReg() != Reg;
2519 NewUseOpc = ARM::SUBri;
2525 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2527 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2528 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2531 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2532 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2533 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2537 case ARM::t2SUBrr: {
2541 NewUseOpc = ARM::t2SUBri;
2546 case ARM::t2EORrr: {
2547 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2549 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2550 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2553 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2554 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2555 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2563 unsigned OpIdx = Commute ? 2 : 1;
2564 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2565 bool isKill = UseMI->getOperand(OpIdx).isKill();
2566 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2567 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2568 UseMI, UseMI->getDebugLoc(),
2569 get(NewUseOpc), NewReg)
2570 .addReg(Reg1, getKillRegState(isKill))
2571 .addImm(SOImmValV1)));
2572 UseMI->setDesc(get(NewUseOpc));
2573 UseMI->getOperand(1).setReg(NewReg);
2574 UseMI->getOperand(1).setIsKill();
2575 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2576 DefMI->eraseFromParent();
2580 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2581 const MachineInstr *MI) {
2582 switch (MI->getOpcode()) {
2584 const MCInstrDesc &Desc = MI->getDesc();
2585 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2586 assert(UOps >= 0 && "bad # UOps");
2594 unsigned ShOpVal = MI->getOperand(3).getImm();
2595 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2596 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2599 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2600 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2607 if (!MI->getOperand(2).getReg())
2610 unsigned ShOpVal = MI->getOperand(3).getImm();
2611 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2612 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2615 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2616 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2623 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2625 case ARM::LDRSB_POST:
2626 case ARM::LDRSH_POST: {
2627 unsigned Rt = MI->getOperand(0).getReg();
2628 unsigned Rm = MI->getOperand(3).getReg();
2629 return (Rt == Rm) ? 4 : 3;
2632 case ARM::LDR_PRE_REG:
2633 case ARM::LDRB_PRE_REG: {
2634 unsigned Rt = MI->getOperand(0).getReg();
2635 unsigned Rm = MI->getOperand(3).getReg();
2638 unsigned ShOpVal = MI->getOperand(4).getImm();
2639 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2640 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2643 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2644 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2649 case ARM::STR_PRE_REG:
2650 case ARM::STRB_PRE_REG: {
2651 unsigned ShOpVal = MI->getOperand(4).getImm();
2652 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2653 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2656 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2657 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2663 case ARM::STRH_PRE: {
2664 unsigned Rt = MI->getOperand(0).getReg();
2665 unsigned Rm = MI->getOperand(3).getReg();
2670 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2674 case ARM::LDR_POST_REG:
2675 case ARM::LDRB_POST_REG:
2676 case ARM::LDRH_POST: {
2677 unsigned Rt = MI->getOperand(0).getReg();
2678 unsigned Rm = MI->getOperand(3).getReg();
2679 return (Rt == Rm) ? 3 : 2;
2682 case ARM::LDR_PRE_IMM:
2683 case ARM::LDRB_PRE_IMM:
2684 case ARM::LDR_POST_IMM:
2685 case ARM::LDRB_POST_IMM:
2686 case ARM::STRB_POST_IMM:
2687 case ARM::STRB_POST_REG:
2688 case ARM::STRB_PRE_IMM:
2689 case ARM::STRH_POST:
2690 case ARM::STR_POST_IMM:
2691 case ARM::STR_POST_REG:
2692 case ARM::STR_PRE_IMM:
2695 case ARM::LDRSB_PRE:
2696 case ARM::LDRSH_PRE: {
2697 unsigned Rm = MI->getOperand(3).getReg();
2700 unsigned Rt = MI->getOperand(0).getReg();
2703 unsigned ShOpVal = MI->getOperand(4).getImm();
2704 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2705 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2708 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2709 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2715 unsigned Rt = MI->getOperand(0).getReg();
2716 unsigned Rn = MI->getOperand(2).getReg();
2717 unsigned Rm = MI->getOperand(3).getReg();
2719 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2720 return (Rt == Rn) ? 3 : 2;
2724 unsigned Rm = MI->getOperand(3).getReg();
2726 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2730 case ARM::LDRD_POST:
2731 case ARM::t2LDRD_POST:
2734 case ARM::STRD_POST:
2735 case ARM::t2STRD_POST:
2738 case ARM::LDRD_PRE: {
2739 unsigned Rt = MI->getOperand(0).getReg();
2740 unsigned Rn = MI->getOperand(3).getReg();
2741 unsigned Rm = MI->getOperand(4).getReg();
2743 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2744 return (Rt == Rn) ? 4 : 3;
2747 case ARM::t2LDRD_PRE: {
2748 unsigned Rt = MI->getOperand(0).getReg();
2749 unsigned Rn = MI->getOperand(3).getReg();
2750 return (Rt == Rn) ? 4 : 3;
2753 case ARM::STRD_PRE: {
2754 unsigned Rm = MI->getOperand(4).getReg();
2756 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2760 case ARM::t2STRD_PRE:
2763 case ARM::t2LDR_POST:
2764 case ARM::t2LDRB_POST:
2765 case ARM::t2LDRB_PRE:
2766 case ARM::t2LDRSBi12:
2767 case ARM::t2LDRSBi8:
2768 case ARM::t2LDRSBpci:
2770 case ARM::t2LDRH_POST:
2771 case ARM::t2LDRH_PRE:
2773 case ARM::t2LDRSB_POST:
2774 case ARM::t2LDRSB_PRE:
2775 case ARM::t2LDRSH_POST:
2776 case ARM::t2LDRSH_PRE:
2777 case ARM::t2LDRSHi12:
2778 case ARM::t2LDRSHi8:
2779 case ARM::t2LDRSHpci:
2783 case ARM::t2LDRDi8: {
2784 unsigned Rt = MI->getOperand(0).getReg();
2785 unsigned Rn = MI->getOperand(2).getReg();
2786 return (Rt == Rn) ? 3 : 2;
2789 case ARM::t2STRB_POST:
2790 case ARM::t2STRB_PRE:
2793 case ARM::t2STRH_POST:
2794 case ARM::t2STRH_PRE:
2796 case ARM::t2STR_POST:
2797 case ARM::t2STR_PRE:
2803 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2804 // can't be easily determined return 0 (missing MachineMemOperand).
2806 // FIXME: The current MachineInstr design does not support relying on machine
2807 // mem operands to determine the width of a memory access. Instead, we expect
2808 // the target to provide this information based on the instruction opcode and
2809 // operands. However, using MachineMemOperand is a the best solution now for
2812 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2813 // operands. This is much more dangerous than using the MachineMemOperand
2814 // sizes because CodeGen passes can insert/remove optional machine operands. In
2815 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2816 // postRA passes as well.
2818 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2819 // machine model that calls this should handle the unknown (zero size) case.
2821 // Long term, we should require a target hook that verifies MachineMemOperand
2822 // sizes during MC lowering. That target hook should be local to MC lowering
2823 // because we can't ensure that it is aware of other MI forms. Doing this will
2824 // ensure that MachineMemOperands are correctly propagated through all passes.
2825 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2827 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2828 E = MI->memoperands_end(); I != E; ++I) {
2829 Size += (*I)->getSize();
2835 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2836 const MachineInstr *MI) const {
2837 if (!ItinData || ItinData->isEmpty())
2840 const MCInstrDesc &Desc = MI->getDesc();
2841 unsigned Class = Desc.getSchedClass();
2842 int ItinUOps = ItinData->getNumMicroOps(Class);
2843 if (ItinUOps >= 0) {
2844 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2845 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2850 unsigned Opc = MI->getOpcode();
2853 llvm_unreachable("Unexpected multi-uops instruction!");
2858 // The number of uOps for load / store multiple are determined by the number
2861 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2862 // same cycle. The scheduling for the first load / store must be done
2863 // separately by assuming the address is not 64-bit aligned.
2865 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2866 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2867 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2869 case ARM::VLDMDIA_UPD:
2870 case ARM::VLDMDDB_UPD:
2872 case ARM::VLDMSIA_UPD:
2873 case ARM::VLDMSDB_UPD:
2875 case ARM::VSTMDIA_UPD:
2876 case ARM::VSTMDDB_UPD:
2878 case ARM::VSTMSIA_UPD:
2879 case ARM::VSTMSDB_UPD: {
2880 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2881 return (NumRegs / 2) + (NumRegs % 2) + 1;
2884 case ARM::LDMIA_RET:
2889 case ARM::LDMIA_UPD:
2890 case ARM::LDMDA_UPD:
2891 case ARM::LDMDB_UPD:
2892 case ARM::LDMIB_UPD:
2897 case ARM::STMIA_UPD:
2898 case ARM::STMDA_UPD:
2899 case ARM::STMDB_UPD:
2900 case ARM::STMIB_UPD:
2902 case ARM::tLDMIA_UPD:
2903 case ARM::tSTMIA_UPD:
2907 case ARM::t2LDMIA_RET:
2910 case ARM::t2LDMIA_UPD:
2911 case ARM::t2LDMDB_UPD:
2914 case ARM::t2STMIA_UPD:
2915 case ARM::t2STMDB_UPD: {
2916 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2917 if (Subtarget.isSwift()) {
2918 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2921 case ARM::VLDMDIA_UPD:
2922 case ARM::VLDMDDB_UPD:
2923 case ARM::VLDMSIA_UPD:
2924 case ARM::VLDMSDB_UPD:
2925 case ARM::VSTMDIA_UPD:
2926 case ARM::VSTMDDB_UPD:
2927 case ARM::VSTMSIA_UPD:
2928 case ARM::VSTMSDB_UPD:
2929 case ARM::LDMIA_UPD:
2930 case ARM::LDMDA_UPD:
2931 case ARM::LDMDB_UPD:
2932 case ARM::LDMIB_UPD:
2933 case ARM::STMIA_UPD:
2934 case ARM::STMDA_UPD:
2935 case ARM::STMDB_UPD:
2936 case ARM::STMIB_UPD:
2937 case ARM::tLDMIA_UPD:
2938 case ARM::tSTMIA_UPD:
2939 case ARM::t2LDMIA_UPD:
2940 case ARM::t2LDMDB_UPD:
2941 case ARM::t2STMIA_UPD:
2942 case ARM::t2STMDB_UPD:
2943 ++UOps; // One for base register writeback.
2945 case ARM::LDMIA_RET:
2947 case ARM::t2LDMIA_RET:
2948 UOps += 2; // One for base reg wb, one for write to pc.
2952 } else if (Subtarget.isCortexA8()) {
2955 // 4 registers would be issued: 2, 2.
2956 // 5 registers would be issued: 2, 2, 1.
2957 int A8UOps = (NumRegs / 2);
2961 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2962 int A9UOps = (NumRegs / 2);
2963 // If there are odd number of registers or if it's not 64-bit aligned,
2964 // then it takes an extra AGU (Address Generation Unit) cycle.
2965 if ((NumRegs % 2) ||
2966 !MI->hasOneMemOperand() ||
2967 (*MI->memoperands_begin())->getAlignment() < 8)
2971 // Assume the worst.
2979 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2980 const MCInstrDesc &DefMCID,
2982 unsigned DefIdx, unsigned DefAlign) const {
2983 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2985 // Def is the address writeback.
2986 return ItinData->getOperandCycle(DefClass, DefIdx);
2989 if (Subtarget.isCortexA8()) {
2990 // (regno / 2) + (regno % 2) + 1
2991 DefCycle = RegNo / 2 + 1;
2994 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2996 bool isSLoad = false;
2998 switch (DefMCID.getOpcode()) {
3001 case ARM::VLDMSIA_UPD:
3002 case ARM::VLDMSDB_UPD:
3007 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3008 // then it takes an extra cycle.
3009 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3012 // Assume the worst.
3013 DefCycle = RegNo + 2;
3020 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3021 const MCInstrDesc &DefMCID,
3023 unsigned DefIdx, unsigned DefAlign) const {
3024 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3026 // Def is the address writeback.
3027 return ItinData->getOperandCycle(DefClass, DefIdx);
3030 if (Subtarget.isCortexA8()) {
3031 // 4 registers would be issued: 1, 2, 1.
3032 // 5 registers would be issued: 1, 2, 2.
3033 DefCycle = RegNo / 2;
3036 // Result latency is issue cycle + 2: E2.
3038 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3039 DefCycle = (RegNo / 2);
3040 // If there are odd number of registers or if it's not 64-bit aligned,
3041 // then it takes an extra AGU (Address Generation Unit) cycle.
3042 if ((RegNo % 2) || DefAlign < 8)
3044 // Result latency is AGU cycles + 2.
3047 // Assume the worst.
3048 DefCycle = RegNo + 2;
3055 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3056 const MCInstrDesc &UseMCID,
3058 unsigned UseIdx, unsigned UseAlign) const {
3059 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3061 return ItinData->getOperandCycle(UseClass, UseIdx);
3064 if (Subtarget.isCortexA8()) {
3065 // (regno / 2) + (regno % 2) + 1
3066 UseCycle = RegNo / 2 + 1;
3069 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3071 bool isSStore = false;
3073 switch (UseMCID.getOpcode()) {
3076 case ARM::VSTMSIA_UPD:
3077 case ARM::VSTMSDB_UPD:
3082 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3083 // then it takes an extra cycle.
3084 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3087 // Assume the worst.
3088 UseCycle = RegNo + 2;
3095 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3096 const MCInstrDesc &UseMCID,
3098 unsigned UseIdx, unsigned UseAlign) const {
3099 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3101 return ItinData->getOperandCycle(UseClass, UseIdx);
3104 if (Subtarget.isCortexA8()) {
3105 UseCycle = RegNo / 2;
3110 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3111 UseCycle = (RegNo / 2);
3112 // If there are odd number of registers or if it's not 64-bit aligned,
3113 // then it takes an extra AGU (Address Generation Unit) cycle.
3114 if ((RegNo % 2) || UseAlign < 8)
3117 // Assume the worst.
3124 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3125 const MCInstrDesc &DefMCID,
3126 unsigned DefIdx, unsigned DefAlign,
3127 const MCInstrDesc &UseMCID,
3128 unsigned UseIdx, unsigned UseAlign) const {
3129 unsigned DefClass = DefMCID.getSchedClass();
3130 unsigned UseClass = UseMCID.getSchedClass();
3132 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3133 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3135 // This may be a def / use of a variable_ops instruction, the operand
3136 // latency might be determinable dynamically. Let the target try to
3139 bool LdmBypass = false;
3140 switch (DefMCID.getOpcode()) {
3142 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3146 case ARM::VLDMDIA_UPD:
3147 case ARM::VLDMDDB_UPD:
3149 case ARM::VLDMSIA_UPD:
3150 case ARM::VLDMSDB_UPD:
3151 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3154 case ARM::LDMIA_RET:
3159 case ARM::LDMIA_UPD:
3160 case ARM::LDMDA_UPD:
3161 case ARM::LDMDB_UPD:
3162 case ARM::LDMIB_UPD:
3164 case ARM::tLDMIA_UPD:
3166 case ARM::t2LDMIA_RET:
3169 case ARM::t2LDMIA_UPD:
3170 case ARM::t2LDMDB_UPD:
3172 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3177 // We can't seem to determine the result latency of the def, assume it's 2.
3181 switch (UseMCID.getOpcode()) {
3183 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3187 case ARM::VSTMDIA_UPD:
3188 case ARM::VSTMDDB_UPD:
3190 case ARM::VSTMSIA_UPD:
3191 case ARM::VSTMSDB_UPD:
3192 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3199 case ARM::STMIA_UPD:
3200 case ARM::STMDA_UPD:
3201 case ARM::STMDB_UPD:
3202 case ARM::STMIB_UPD:
3203 case ARM::tSTMIA_UPD:
3208 case ARM::t2STMIA_UPD:
3209 case ARM::t2STMDB_UPD:
3210 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3215 // Assume it's read in the first stage.
3218 UseCycle = DefCycle - UseCycle + 1;
3221 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3222 // first def operand.
3223 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3226 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3227 UseClass, UseIdx)) {
3235 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3236 const MachineInstr *MI, unsigned Reg,
3237 unsigned &DefIdx, unsigned &Dist) {
3240 MachineBasicBlock::const_iterator I = MI; ++I;
3241 MachineBasicBlock::const_instr_iterator II =
3242 llvm::prior(I.getInstrIterator());
3243 assert(II->isInsideBundle() && "Empty bundle?");
3246 while (II->isInsideBundle()) {
3247 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3254 assert(Idx != -1 && "Cannot find bundled definition!");
3259 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3260 const MachineInstr *MI, unsigned Reg,
3261 unsigned &UseIdx, unsigned &Dist) {
3264 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3265 assert(II->isInsideBundle() && "Empty bundle?");
3266 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3268 // FIXME: This doesn't properly handle multiple uses.
3270 while (II != E && II->isInsideBundle()) {
3271 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3274 if (II->getOpcode() != ARM::t2IT)
3288 /// Return the number of cycles to add to (or subtract from) the static
3289 /// itinerary based on the def opcode and alignment. The caller will ensure that
3290 /// adjusted latency is at least one cycle.
3291 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3292 const MachineInstr *DefMI,
3293 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3295 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) {
3296 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3297 // variants are one cycle cheaper.
3298 switch (DefMCID->getOpcode()) {
3302 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3303 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3305 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3312 case ARM::t2LDRSHs: {
3313 // Thumb2 mode: lsl only.
3314 unsigned ShAmt = DefMI->getOperand(3).getImm();
3315 if (ShAmt == 0 || ShAmt == 2)
3320 } else if (Subtarget.isSwift()) {
3321 // FIXME: Properly handle all of the latency adjustments for address
3323 switch (DefMCID->getOpcode()) {
3327 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3328 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3329 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3332 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3333 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3336 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3343 case ARM::t2LDRSHs: {
3344 // Thumb2 mode: lsl only.
3345 unsigned ShAmt = DefMI->getOperand(3).getImm();
3346 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3353 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3354 switch (DefMCID->getOpcode()) {
3360 case ARM::VLD1q8wb_fixed:
3361 case ARM::VLD1q16wb_fixed:
3362 case ARM::VLD1q32wb_fixed:
3363 case ARM::VLD1q64wb_fixed:
3364 case ARM::VLD1q8wb_register:
3365 case ARM::VLD1q16wb_register:
3366 case ARM::VLD1q32wb_register:
3367 case ARM::VLD1q64wb_register:
3374 case ARM::VLD2d8wb_fixed:
3375 case ARM::VLD2d16wb_fixed:
3376 case ARM::VLD2d32wb_fixed:
3377 case ARM::VLD2q8wb_fixed:
3378 case ARM::VLD2q16wb_fixed:
3379 case ARM::VLD2q32wb_fixed:
3380 case ARM::VLD2d8wb_register:
3381 case ARM::VLD2d16wb_register:
3382 case ARM::VLD2d32wb_register:
3383 case ARM::VLD2q8wb_register:
3384 case ARM::VLD2q16wb_register:
3385 case ARM::VLD2q32wb_register:
3390 case ARM::VLD3d8_UPD:
3391 case ARM::VLD3d16_UPD:
3392 case ARM::VLD3d32_UPD:
3393 case ARM::VLD1d64Twb_fixed:
3394 case ARM::VLD1d64Twb_register:
3395 case ARM::VLD3q8_UPD:
3396 case ARM::VLD3q16_UPD:
3397 case ARM::VLD3q32_UPD:
3402 case ARM::VLD4d8_UPD:
3403 case ARM::VLD4d16_UPD:
3404 case ARM::VLD4d32_UPD:
3405 case ARM::VLD1d64Qwb_fixed:
3406 case ARM::VLD1d64Qwb_register:
3407 case ARM::VLD4q8_UPD:
3408 case ARM::VLD4q16_UPD:
3409 case ARM::VLD4q32_UPD:
3410 case ARM::VLD1DUPq8:
3411 case ARM::VLD1DUPq16:
3412 case ARM::VLD1DUPq32:
3413 case ARM::VLD1DUPq8wb_fixed:
3414 case ARM::VLD1DUPq16wb_fixed:
3415 case ARM::VLD1DUPq32wb_fixed:
3416 case ARM::VLD1DUPq8wb_register:
3417 case ARM::VLD1DUPq16wb_register:
3418 case ARM::VLD1DUPq32wb_register:
3419 case ARM::VLD2DUPd8:
3420 case ARM::VLD2DUPd16:
3421 case ARM::VLD2DUPd32:
3422 case ARM::VLD2DUPd8wb_fixed:
3423 case ARM::VLD2DUPd16wb_fixed:
3424 case ARM::VLD2DUPd32wb_fixed:
3425 case ARM::VLD2DUPd8wb_register:
3426 case ARM::VLD2DUPd16wb_register:
3427 case ARM::VLD2DUPd32wb_register:
3428 case ARM::VLD4DUPd8:
3429 case ARM::VLD4DUPd16:
3430 case ARM::VLD4DUPd32:
3431 case ARM::VLD4DUPd8_UPD:
3432 case ARM::VLD4DUPd16_UPD:
3433 case ARM::VLD4DUPd32_UPD:
3435 case ARM::VLD1LNd16:
3436 case ARM::VLD1LNd32:
3437 case ARM::VLD1LNd8_UPD:
3438 case ARM::VLD1LNd16_UPD:
3439 case ARM::VLD1LNd32_UPD:
3441 case ARM::VLD2LNd16:
3442 case ARM::VLD2LNd32:
3443 case ARM::VLD2LNq16:
3444 case ARM::VLD2LNq32:
3445 case ARM::VLD2LNd8_UPD:
3446 case ARM::VLD2LNd16_UPD:
3447 case ARM::VLD2LNd32_UPD:
3448 case ARM::VLD2LNq16_UPD:
3449 case ARM::VLD2LNq32_UPD:
3451 case ARM::VLD4LNd16:
3452 case ARM::VLD4LNd32:
3453 case ARM::VLD4LNq16:
3454 case ARM::VLD4LNq32:
3455 case ARM::VLD4LNd8_UPD:
3456 case ARM::VLD4LNd16_UPD:
3457 case ARM::VLD4LNd32_UPD:
3458 case ARM::VLD4LNq16_UPD:
3459 case ARM::VLD4LNq32_UPD:
3460 // If the address is not 64-bit aligned, the latencies of these
3461 // instructions increases by one.
3472 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3473 const MachineInstr *DefMI, unsigned DefIdx,
3474 const MachineInstr *UseMI,
3475 unsigned UseIdx) const {
3476 // No operand latency. The caller may fall back to getInstrLatency.
3477 if (!ItinData || ItinData->isEmpty())
3480 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3481 unsigned Reg = DefMO.getReg();
3482 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3483 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3485 unsigned DefAdj = 0;
3486 if (DefMI->isBundle()) {
3487 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3488 DefMCID = &DefMI->getDesc();
3490 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3491 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3495 unsigned UseAdj = 0;
3496 if (UseMI->isBundle()) {
3498 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3499 Reg, NewUseIdx, UseAdj);
3505 UseMCID = &UseMI->getDesc();
3508 if (Reg == ARM::CPSR) {
3509 if (DefMI->getOpcode() == ARM::FMSTAT) {
3510 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3511 return Subtarget.isLikeA9() ? 1 : 20;
3514 // CPSR set and branch can be paired in the same cycle.
3515 if (UseMI->isBranch())
3518 // Otherwise it takes the instruction latency (generally one).
3519 unsigned Latency = getInstrLatency(ItinData, DefMI);
3521 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3522 // its uses. Instructions which are otherwise scheduled between them may
3523 // incur a code size penalty (not able to use the CPSR setting 16-bit
3525 if (Latency > 0 && Subtarget.isThumb2()) {
3526 const MachineFunction *MF = DefMI->getParent()->getParent();
3527 if (MF->getFunction()->getAttributes().
3528 hasAttribute(AttributeSet::FunctionIndex,
3529 Attribute::OptimizeForSize))
3535 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3538 unsigned DefAlign = DefMI->hasOneMemOperand()
3539 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3540 unsigned UseAlign = UseMI->hasOneMemOperand()
3541 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3543 // Get the itinerary's latency if possible, and handle variable_ops.
3544 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3545 *UseMCID, UseIdx, UseAlign);
3546 // Unable to find operand latency. The caller may resort to getInstrLatency.
3550 // Adjust for IT block position.
3551 int Adj = DefAdj + UseAdj;
3553 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3554 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3555 if (Adj >= 0 || (int)Latency > -Adj) {
3556 return Latency + Adj;
3558 // Return the itinerary latency, which may be zero but not less than zero.
3563 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3564 SDNode *DefNode, unsigned DefIdx,
3565 SDNode *UseNode, unsigned UseIdx) const {
3566 if (!DefNode->isMachineOpcode())
3569 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3571 if (isZeroCost(DefMCID.Opcode))
3574 if (!ItinData || ItinData->isEmpty())
3575 return DefMCID.mayLoad() ? 3 : 1;
3577 if (!UseNode->isMachineOpcode()) {
3578 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3579 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3580 return Latency <= 2 ? 1 : Latency - 1;
3582 return Latency <= 3 ? 1 : Latency - 2;
3585 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3586 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3587 unsigned DefAlign = !DefMN->memoperands_empty()
3588 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3589 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3590 unsigned UseAlign = !UseMN->memoperands_empty()
3591 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3592 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3593 UseMCID, UseIdx, UseAlign);
3596 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) {
3597 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3598 // variants are one cycle cheaper.
3599 switch (DefMCID.getOpcode()) {
3604 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3605 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3607 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3614 case ARM::t2LDRSHs: {
3615 // Thumb2 mode: lsl only.
3617 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3618 if (ShAmt == 0 || ShAmt == 2)
3623 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3624 // FIXME: Properly handle all of the latency adjustments for address
3626 switch (DefMCID.getOpcode()) {
3631 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3632 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3634 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3635 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3637 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3644 case ARM::t2LDRSHs: {
3645 // Thumb2 mode: lsl 0-3 only.
3652 if (DefAlign < 8 && Subtarget.isLikeA9())
3653 switch (DefMCID.getOpcode()) {
3659 case ARM::VLD1q8wb_register:
3660 case ARM::VLD1q16wb_register:
3661 case ARM::VLD1q32wb_register:
3662 case ARM::VLD1q64wb_register:
3663 case ARM::VLD1q8wb_fixed:
3664 case ARM::VLD1q16wb_fixed:
3665 case ARM::VLD1q32wb_fixed:
3666 case ARM::VLD1q64wb_fixed:
3670 case ARM::VLD2q8Pseudo:
3671 case ARM::VLD2q16Pseudo:
3672 case ARM::VLD2q32Pseudo:
3673 case ARM::VLD2d8wb_fixed:
3674 case ARM::VLD2d16wb_fixed:
3675 case ARM::VLD2d32wb_fixed:
3676 case ARM::VLD2q8PseudoWB_fixed:
3677 case ARM::VLD2q16PseudoWB_fixed:
3678 case ARM::VLD2q32PseudoWB_fixed:
3679 case ARM::VLD2d8wb_register:
3680 case ARM::VLD2d16wb_register:
3681 case ARM::VLD2d32wb_register:
3682 case ARM::VLD2q8PseudoWB_register:
3683 case ARM::VLD2q16PseudoWB_register:
3684 case ARM::VLD2q32PseudoWB_register:
3685 case ARM::VLD3d8Pseudo:
3686 case ARM::VLD3d16Pseudo:
3687 case ARM::VLD3d32Pseudo:
3688 case ARM::VLD1d64TPseudo:
3689 case ARM::VLD1d64TPseudoWB_fixed:
3690 case ARM::VLD3d8Pseudo_UPD:
3691 case ARM::VLD3d16Pseudo_UPD:
3692 case ARM::VLD3d32Pseudo_UPD:
3693 case ARM::VLD3q8Pseudo_UPD:
3694 case ARM::VLD3q16Pseudo_UPD:
3695 case ARM::VLD3q32Pseudo_UPD:
3696 case ARM::VLD3q8oddPseudo:
3697 case ARM::VLD3q16oddPseudo:
3698 case ARM::VLD3q32oddPseudo:
3699 case ARM::VLD3q8oddPseudo_UPD:
3700 case ARM::VLD3q16oddPseudo_UPD:
3701 case ARM::VLD3q32oddPseudo_UPD:
3702 case ARM::VLD4d8Pseudo:
3703 case ARM::VLD4d16Pseudo:
3704 case ARM::VLD4d32Pseudo:
3705 case ARM::VLD1d64QPseudo:
3706 case ARM::VLD1d64QPseudoWB_fixed:
3707 case ARM::VLD4d8Pseudo_UPD:
3708 case ARM::VLD4d16Pseudo_UPD:
3709 case ARM::VLD4d32Pseudo_UPD:
3710 case ARM::VLD4q8Pseudo_UPD:
3711 case ARM::VLD4q16Pseudo_UPD:
3712 case ARM::VLD4q32Pseudo_UPD:
3713 case ARM::VLD4q8oddPseudo:
3714 case ARM::VLD4q16oddPseudo:
3715 case ARM::VLD4q32oddPseudo:
3716 case ARM::VLD4q8oddPseudo_UPD:
3717 case ARM::VLD4q16oddPseudo_UPD:
3718 case ARM::VLD4q32oddPseudo_UPD:
3719 case ARM::VLD1DUPq8:
3720 case ARM::VLD1DUPq16:
3721 case ARM::VLD1DUPq32:
3722 case ARM::VLD1DUPq8wb_fixed:
3723 case ARM::VLD1DUPq16wb_fixed:
3724 case ARM::VLD1DUPq32wb_fixed:
3725 case ARM::VLD1DUPq8wb_register:
3726 case ARM::VLD1DUPq16wb_register:
3727 case ARM::VLD1DUPq32wb_register:
3728 case ARM::VLD2DUPd8:
3729 case ARM::VLD2DUPd16:
3730 case ARM::VLD2DUPd32:
3731 case ARM::VLD2DUPd8wb_fixed:
3732 case ARM::VLD2DUPd16wb_fixed:
3733 case ARM::VLD2DUPd32wb_fixed:
3734 case ARM::VLD2DUPd8wb_register:
3735 case ARM::VLD2DUPd16wb_register:
3736 case ARM::VLD2DUPd32wb_register:
3737 case ARM::VLD4DUPd8Pseudo:
3738 case ARM::VLD4DUPd16Pseudo:
3739 case ARM::VLD4DUPd32Pseudo:
3740 case ARM::VLD4DUPd8Pseudo_UPD:
3741 case ARM::VLD4DUPd16Pseudo_UPD:
3742 case ARM::VLD4DUPd32Pseudo_UPD:
3743 case ARM::VLD1LNq8Pseudo:
3744 case ARM::VLD1LNq16Pseudo:
3745 case ARM::VLD1LNq32Pseudo:
3746 case ARM::VLD1LNq8Pseudo_UPD:
3747 case ARM::VLD1LNq16Pseudo_UPD:
3748 case ARM::VLD1LNq32Pseudo_UPD:
3749 case ARM::VLD2LNd8Pseudo:
3750 case ARM::VLD2LNd16Pseudo:
3751 case ARM::VLD2LNd32Pseudo:
3752 case ARM::VLD2LNq16Pseudo:
3753 case ARM::VLD2LNq32Pseudo:
3754 case ARM::VLD2LNd8Pseudo_UPD:
3755 case ARM::VLD2LNd16Pseudo_UPD:
3756 case ARM::VLD2LNd32Pseudo_UPD:
3757 case ARM::VLD2LNq16Pseudo_UPD:
3758 case ARM::VLD2LNq32Pseudo_UPD:
3759 case ARM::VLD4LNd8Pseudo:
3760 case ARM::VLD4LNd16Pseudo:
3761 case ARM::VLD4LNd32Pseudo:
3762 case ARM::VLD4LNq16Pseudo:
3763 case ARM::VLD4LNq32Pseudo:
3764 case ARM::VLD4LNd8Pseudo_UPD:
3765 case ARM::VLD4LNd16Pseudo_UPD:
3766 case ARM::VLD4LNd32Pseudo_UPD:
3767 case ARM::VLD4LNq16Pseudo_UPD:
3768 case ARM::VLD4LNq32Pseudo_UPD:
3769 // If the address is not 64-bit aligned, the latencies of these
3770 // instructions increases by one.
3778 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3779 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3780 MI->isRegSequence() || MI->isImplicitDef())
3786 const MCInstrDesc &MCID = MI->getDesc();
3788 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3789 // When predicated, CPSR is an additional source operand for CPSR updating
3790 // instructions, this apparently increases their latencies.
3796 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3797 const MachineInstr *MI,
3798 unsigned *PredCost) const {
3799 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3800 MI->isRegSequence() || MI->isImplicitDef())
3803 // An instruction scheduler typically runs on unbundled instructions, however
3804 // other passes may query the latency of a bundled instruction.
3805 if (MI->isBundle()) {
3806 unsigned Latency = 0;
3807 MachineBasicBlock::const_instr_iterator I = MI;
3808 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3809 while (++I != E && I->isInsideBundle()) {
3810 if (I->getOpcode() != ARM::t2IT)
3811 Latency += getInstrLatency(ItinData, I, PredCost);
3816 const MCInstrDesc &MCID = MI->getDesc();
3817 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3818 // When predicated, CPSR is an additional source operand for CPSR updating
3819 // instructions, this apparently increases their latencies.
3822 // Be sure to call getStageLatency for an empty itinerary in case it has a
3823 // valid MinLatency property.
3825 return MI->mayLoad() ? 3 : 1;
3827 unsigned Class = MCID.getSchedClass();
3829 // For instructions with variable uops, use uops as latency.
3830 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3831 return getNumMicroOps(ItinData, MI);
3833 // For the common case, fall back on the itinerary's latency.
3834 unsigned Latency = ItinData->getStageLatency(Class);
3836 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3837 unsigned DefAlign = MI->hasOneMemOperand()
3838 ? (*MI->memoperands_begin())->getAlignment() : 0;
3839 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3840 if (Adj >= 0 || (int)Latency > -Adj) {
3841 return Latency + Adj;
3846 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3847 SDNode *Node) const {
3848 if (!Node->isMachineOpcode())
3851 if (!ItinData || ItinData->isEmpty())
3854 unsigned Opcode = Node->getMachineOpcode();
3857 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3864 bool ARMBaseInstrInfo::
3865 hasHighOperandLatency(const InstrItineraryData *ItinData,
3866 const MachineRegisterInfo *MRI,
3867 const MachineInstr *DefMI, unsigned DefIdx,
3868 const MachineInstr *UseMI, unsigned UseIdx) const {
3869 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3870 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3871 if (Subtarget.isCortexA8() &&
3872 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3873 // CortexA8 VFP instructions are not pipelined.
3876 // Hoist VFP / NEON instructions with 4 or higher latency.
3877 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3879 Latency = getInstrLatency(ItinData, DefMI);
3882 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3883 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3886 bool ARMBaseInstrInfo::
3887 hasLowDefLatency(const InstrItineraryData *ItinData,
3888 const MachineInstr *DefMI, unsigned DefIdx) const {
3889 if (!ItinData || ItinData->isEmpty())
3892 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3893 if (DDomain == ARMII::DomainGeneral) {
3894 unsigned DefClass = DefMI->getDesc().getSchedClass();
3895 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3896 return (DefCycle != -1 && DefCycle <= 2);
3901 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3902 StringRef &ErrInfo) const {
3903 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3904 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3911 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3912 unsigned &AddSubOpc,
3913 bool &NegAcc, bool &HasLane) const {
3914 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3915 if (I == MLxEntryMap.end())
3918 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3919 MulOpc = Entry.MulOpc;
3920 AddSubOpc = Entry.AddSubOpc;
3921 NegAcc = Entry.NegAcc;
3922 HasLane = Entry.HasLane;
3926 //===----------------------------------------------------------------------===//
3927 // Execution domains.
3928 //===----------------------------------------------------------------------===//
3930 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3931 // and some can go down both. The vmov instructions go down the VFP pipeline,
3932 // but they can be changed to vorr equivalents that are executed by the NEON
3935 // We use the following execution domain numbering:
3943 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3945 std::pair<uint16_t, uint16_t>
3946 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3947 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3948 // if they are not predicated.
3949 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3950 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3952 // CortexA9 is particularly picky about mixing the two and wants these
3954 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3955 (MI->getOpcode() == ARM::VMOVRS ||
3956 MI->getOpcode() == ARM::VMOVSR ||
3957 MI->getOpcode() == ARM::VMOVS))
3958 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3960 // No other instructions can be swizzled, so just determine their domain.
3961 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3963 if (Domain & ARMII::DomainNEON)
3964 return std::make_pair(ExeNEON, 0);
3966 // Certain instructions can go either way on Cortex-A8.
3967 // Treat them as NEON instructions.
3968 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3969 return std::make_pair(ExeNEON, 0);
3971 if (Domain & ARMII::DomainVFP)
3972 return std::make_pair(ExeVFP, 0);
3974 return std::make_pair(ExeGeneric, 0);
3977 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
3978 unsigned SReg, unsigned &Lane) {
3979 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3982 if (DReg != ARM::NoRegister)
3986 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
3988 assert(DReg && "S-register with no D super-register?");
3992 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
3993 /// set ImplicitSReg to a register number that must be marked as implicit-use or
3994 /// zero if no register needs to be defined as implicit-use.
3996 /// If the function cannot determine if an SPR should be marked implicit use or
3997 /// not, it returns false.
3999 /// This function handles cases where an instruction is being modified from taking
4000 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4001 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4002 /// lane of the DPR).
4004 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4005 /// (including the case where the DPR itself is defined), it should not.
4007 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4009 unsigned DReg, unsigned Lane,
4010 unsigned &ImplicitSReg) {
4011 // If the DPR is defined or used already, the other SPR lane will be chained
4012 // correctly, so there is nothing to be done.
4013 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4018 // Otherwise we need to go searching to see if the SPR is set explicitly.
4019 ImplicitSReg = TRI->getSubReg(DReg,
4020 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4021 MachineBasicBlock::LivenessQueryResult LQR =
4022 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4024 if (LQR == MachineBasicBlock::LQR_Live)
4026 else if (LQR == MachineBasicBlock::LQR_Unknown)
4029 // If the register is known not to be live, there is no need to add an
4036 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4037 unsigned DstReg, SrcReg, DReg;
4039 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4040 const TargetRegisterInfo *TRI = &getRegisterInfo();
4041 switch (MI->getOpcode()) {
4043 llvm_unreachable("cannot handle opcode!");
4046 if (Domain != ExeNEON)
4049 // Zap the predicate operands.
4050 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4052 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4053 DstReg = MI->getOperand(0).getReg();
4054 SrcReg = MI->getOperand(1).getReg();
4056 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4057 MI->RemoveOperand(i-1);
4059 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4060 MI->setDesc(get(ARM::VORRd));
4061 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4066 if (Domain != ExeNEON)
4068 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4070 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4071 DstReg = MI->getOperand(0).getReg();
4072 SrcReg = MI->getOperand(1).getReg();
4074 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4075 MI->RemoveOperand(i-1);
4077 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4079 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4080 // Note that DSrc has been widened and the other lane may be undef, which
4081 // contaminates the entire register.
4082 MI->setDesc(get(ARM::VGETLNi32));
4083 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4084 .addReg(DReg, RegState::Undef)
4087 // The old source should be an implicit use, otherwise we might think it
4088 // was dead before here.
4089 MIB.addReg(SrcReg, RegState::Implicit);
4092 if (Domain != ExeNEON)
4094 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4096 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4097 DstReg = MI->getOperand(0).getReg();
4098 SrcReg = MI->getOperand(1).getReg();
4100 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4102 unsigned ImplicitSReg;
4103 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4106 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4107 MI->RemoveOperand(i-1);
4109 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4110 // Again DDst may be undefined at the beginning of this instruction.
4111 MI->setDesc(get(ARM::VSETLNi32));
4112 MIB.addReg(DReg, RegState::Define)
4113 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4116 AddDefaultPred(MIB);
4118 // The narrower destination must be marked as set to keep previous chains
4120 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4121 if (ImplicitSReg != 0)
4122 MIB.addReg(ImplicitSReg, RegState::Implicit);
4126 if (Domain != ExeNEON)
4129 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4130 DstReg = MI->getOperand(0).getReg();
4131 SrcReg = MI->getOperand(1).getReg();
4133 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4134 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4135 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4137 unsigned ImplicitSReg;
4138 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4141 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4142 MI->RemoveOperand(i-1);
4145 // Destination can be:
4146 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4147 MI->setDesc(get(ARM::VDUPLN32d));
4148 MIB.addReg(DDst, RegState::Define)
4149 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4151 AddDefaultPred(MIB);
4153 // Neither the source or the destination are naturally represented any
4154 // more, so add them in manually.
4155 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4156 MIB.addReg(SrcReg, RegState::Implicit);
4157 if (ImplicitSReg != 0)
4158 MIB.addReg(ImplicitSReg, RegState::Implicit);
4162 // In general there's no single instruction that can perform an S <-> S
4163 // move in NEON space, but a pair of VEXT instructions *can* do the
4164 // job. It turns out that the VEXTs needed will only use DSrc once, with
4165 // the position based purely on the combination of lane-0 and lane-1
4166 // involved. For example
4167 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4168 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4169 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4170 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4172 // Pattern of the MachineInstrs is:
4173 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4174 MachineInstrBuilder NewMIB;
4175 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4176 get(ARM::VEXTd32), DDst);
4178 // On the first instruction, both DSrc and DDst may be <undef> if present.
4179 // Specifically when the original instruction didn't have them as an
4181 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4182 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4183 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4185 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4186 CurUndef = !MI->readsRegister(CurReg, TRI);
4187 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4190 AddDefaultPred(NewMIB);
4192 if (SrcLane == DstLane)
4193 NewMIB.addReg(SrcReg, RegState::Implicit);
4195 MI->setDesc(get(ARM::VEXTd32));
4196 MIB.addReg(DDst, RegState::Define);
4198 // On the second instruction, DDst has definitely been defined above, so
4199 // it is not <undef>. DSrc, if present, can be <undef> as above.
4200 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4201 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4202 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4204 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4205 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4206 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4209 AddDefaultPred(MIB);
4211 if (SrcLane != DstLane)
4212 MIB.addReg(SrcReg, RegState::Implicit);
4214 // As before, the original destination is no longer represented, add it
4216 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4217 if (ImplicitSReg != 0)
4218 MIB.addReg(ImplicitSReg, RegState::Implicit);
4225 //===----------------------------------------------------------------------===//
4226 // Partial register updates
4227 //===----------------------------------------------------------------------===//
4229 // Swift renames NEON registers with 64-bit granularity. That means any
4230 // instruction writing an S-reg implicitly reads the containing D-reg. The
4231 // problem is mostly avoided by translating f32 operations to v2f32 operations
4232 // on D-registers, but f32 loads are still a problem.
4234 // These instructions can load an f32 into a NEON register:
4236 // VLDRS - Only writes S, partial D update.
4237 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4238 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4240 // FCONSTD can be used as a dependency-breaking instruction.
4241 unsigned ARMBaseInstrInfo::
4242 getPartialRegUpdateClearance(const MachineInstr *MI,
4244 const TargetRegisterInfo *TRI) const {
4245 if (!SwiftPartialUpdateClearance ||
4246 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4249 assert(TRI && "Need TRI instance");
4251 const MachineOperand &MO = MI->getOperand(OpNum);
4254 unsigned Reg = MO.getReg();
4257 switch(MI->getOpcode()) {
4258 // Normal instructions writing only an S-register.
4263 case ARM::VMOVv4i16:
4264 case ARM::VMOVv2i32:
4265 case ARM::VMOVv2f32:
4266 case ARM::VMOVv1i64:
4267 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4270 // Explicitly reads the dependency.
4271 case ARM::VLD1LNd32:
4278 // If this instruction actually reads a value from Reg, there is no unwanted
4280 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4283 // We must be able to clobber the whole D-reg.
4284 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4285 // Virtual register must be a foo:ssub_0<def,undef> operand.
4286 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4288 } else if (ARM::SPRRegClass.contains(Reg)) {
4289 // Physical register: MI must define the full D-reg.
4290 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4292 if (!DReg || !MI->definesRegister(DReg, TRI))
4296 // MI has an unwanted D-register dependency.
4297 // Avoid defs in the previous N instructrions.
4298 return SwiftPartialUpdateClearance;
4301 // Break a partial register dependency after getPartialRegUpdateClearance
4302 // returned non-zero.
4303 void ARMBaseInstrInfo::
4304 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4306 const TargetRegisterInfo *TRI) const {
4307 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4308 assert(TRI && "Need TRI instance");
4310 const MachineOperand &MO = MI->getOperand(OpNum);
4311 unsigned Reg = MO.getReg();
4312 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4313 "Can't break virtual register dependencies.");
4314 unsigned DReg = Reg;
4316 // If MI defines an S-reg, find the corresponding D super-register.
4317 if (ARM::SPRRegClass.contains(Reg)) {
4318 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4319 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4322 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4323 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4325 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4326 // the full D-register by loading the same value to both lanes. The
4327 // instruction is micro-coded with 2 uops, so don't do this until we can
4328 // properly schedule micro-coded instructions. The dispatcher stalls cause
4329 // too big regressions.
4331 // Insert the dependency-breaking FCONSTD before MI.
4332 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4333 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4334 get(ARM::FCONSTD), DReg).addImm(96));
4335 MI->addRegisterKilled(DReg, TRI, true);
4338 bool ARMBaseInstrInfo::hasNOP() const {
4339 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4342 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4343 if (MI->getNumOperands() < 4)
4345 unsigned ShOpVal = MI->getOperand(3).getImm();
4346 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4347 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4348 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4349 ((ShImm == 1 || ShImm == 2) &&
4350 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))