1 //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMHazardRecognizer.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMRegisterInfo.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGNodes.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Support/BranchProbability.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/ADT/STLExtras.h"
39 #define GET_INSTRINFO_CTOR
40 #include "ARMGenInstrInfo.inc"
45 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
46 cl::desc("Enable ARM 2-addr to 3-addr conv"));
49 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
50 cl::desc("Widen ARM vmovs to vmovd when possible"));
52 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
54 unsigned MLxOpc; // MLA / MLS opcode
55 unsigned MulOpc; // Expanded multiplication opcode
56 unsigned AddSubOpc; // Expanded add / sub opcode
57 bool NegAcc; // True if the acc is negated before the add / sub.
58 bool HasLane; // True if instruction has an extra "lane" operand.
61 static const ARM_MLxEntry ARM_MLxTable[] = {
62 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
64 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
65 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
66 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
67 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
68 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
69 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
71 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
74 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
75 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
76 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
77 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
78 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
79 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
80 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
81 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
84 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
85 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
87 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
88 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
89 assert(false && "Duplicated entries?");
90 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
91 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
95 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
96 // currently defaults to no prepass hazard recognizer.
97 ScheduleHazardRecognizer *ARMBaseInstrInfo::
98 CreateTargetHazardRecognizer(const TargetMachine *TM,
99 const ScheduleDAG *DAG) const {
100 if (usePreRAHazardRecognizer()) {
101 const InstrItineraryData *II = TM->getInstrItineraryData();
102 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
107 ScheduleHazardRecognizer *ARMBaseInstrInfo::
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const {
110 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
111 return (ScheduleHazardRecognizer *)
112 new ARMHazardRecognizer(II, *this, getRegisterInfo(), Subtarget, DAG);
113 return TargetInstrInfoImpl::CreateTargetPostRAHazardRecognizer(II, DAG);
117 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
118 MachineBasicBlock::iterator &MBBI,
119 LiveVariables *LV) const {
120 // FIXME: Thumb2 support.
125 MachineInstr *MI = MBBI;
126 MachineFunction &MF = *MI->getParent()->getParent();
127 uint64_t TSFlags = MI->getDesc().TSFlags;
129 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
130 default: return NULL;
131 case ARMII::IndexModePre:
134 case ARMII::IndexModePost:
138 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
140 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
144 MachineInstr *UpdateMI = NULL;
145 MachineInstr *MemMI = NULL;
146 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
147 const MCInstrDesc &MCID = MI->getDesc();
148 unsigned NumOps = MCID.getNumOperands();
149 bool isLoad = !MI->mayStore();
150 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
151 const MachineOperand &Base = MI->getOperand(2);
152 const MachineOperand &Offset = MI->getOperand(NumOps-3);
153 unsigned WBReg = WB.getReg();
154 unsigned BaseReg = Base.getReg();
155 unsigned OffReg = Offset.getReg();
156 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
160 assert(false && "Unknown indexed op!");
162 case ARMII::AddrMode2: {
163 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
164 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
166 if (ARM_AM::getSOImmVal(Amt) == -1)
167 // Can't encode it in a so_imm operand. This transformation will
168 // add more than 1 instruction. Abandon!
170 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
171 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
172 .addReg(BaseReg).addImm(Amt)
173 .addImm(Pred).addReg(0).addReg(0);
174 } else if (Amt != 0) {
175 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
176 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
179 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
180 .addImm(Pred).addReg(0).addReg(0);
182 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
183 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
184 .addReg(BaseReg).addReg(OffReg)
185 .addImm(Pred).addReg(0).addReg(0);
188 case ARMII::AddrMode3 : {
189 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
190 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
192 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
193 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
194 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
195 .addReg(BaseReg).addImm(Amt)
196 .addImm(Pred).addReg(0).addReg(0);
198 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
199 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
200 .addReg(BaseReg).addReg(OffReg)
201 .addImm(Pred).addReg(0).addReg(0);
206 std::vector<MachineInstr*> NewMIs;
209 MemMI = BuildMI(MF, MI->getDebugLoc(),
210 get(MemOpc), MI->getOperand(0).getReg())
211 .addReg(WBReg).addImm(0).addImm(Pred);
213 MemMI = BuildMI(MF, MI->getDebugLoc(),
214 get(MemOpc)).addReg(MI->getOperand(1).getReg())
215 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
216 NewMIs.push_back(MemMI);
217 NewMIs.push_back(UpdateMI);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc), MI->getOperand(0).getReg())
222 .addReg(BaseReg).addImm(0).addImm(Pred);
224 MemMI = BuildMI(MF, MI->getDebugLoc(),
225 get(MemOpc)).addReg(MI->getOperand(1).getReg())
226 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
228 UpdateMI->getOperand(0).setIsDead();
229 NewMIs.push_back(UpdateMI);
230 NewMIs.push_back(MemMI);
233 // Transfer LiveVariables states, kill / dead info.
235 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236 MachineOperand &MO = MI->getOperand(i);
237 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
238 unsigned Reg = MO.getReg();
240 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
242 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
244 LV->addVirtualRegisterDead(Reg, NewMI);
246 if (MO.isUse() && MO.isKill()) {
247 for (unsigned j = 0; j < 2; ++j) {
248 // Look at the two new MI's in reverse order.
249 MachineInstr *NewMI = NewMIs[j];
250 if (!NewMI->readsRegister(Reg))
252 LV->addVirtualRegisterKilled(Reg, NewMI);
253 if (VI.removeKill(MI))
254 VI.Kills.push_back(NewMI);
262 MFI->insert(MBBI, NewMIs[1]);
263 MFI->insert(MBBI, NewMIs[0]);
269 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
270 MachineBasicBlock *&FBB,
271 SmallVectorImpl<MachineOperand> &Cond,
272 bool AllowModify) const {
273 // If the block has no terminators, it just falls into the block after it.
274 MachineBasicBlock::iterator I = MBB.end();
275 if (I == MBB.begin())
278 while (I->isDebugValue()) {
279 if (I == MBB.begin())
283 if (!isUnpredicatedTerminator(I))
286 // Get the last instruction in the block.
287 MachineInstr *LastInst = I;
289 // If there is only one terminator instruction, process it.
290 unsigned LastOpc = LastInst->getOpcode();
291 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
292 if (isUncondBranchOpcode(LastOpc)) {
293 TBB = LastInst->getOperand(0).getMBB();
296 if (isCondBranchOpcode(LastOpc)) {
297 // Block ends with fall-through condbranch.
298 TBB = LastInst->getOperand(0).getMBB();
299 Cond.push_back(LastInst->getOperand(1));
300 Cond.push_back(LastInst->getOperand(2));
303 return true; // Can't handle indirect branch.
306 // Get the instruction before it if it is a terminator.
307 MachineInstr *SecondLastInst = I;
308 unsigned SecondLastOpc = SecondLastInst->getOpcode();
310 // If AllowModify is true and the block ends with two or more unconditional
311 // branches, delete all but the first unconditional branch.
312 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
313 while (isUncondBranchOpcode(SecondLastOpc)) {
314 LastInst->eraseFromParent();
315 LastInst = SecondLastInst;
316 LastOpc = LastInst->getOpcode();
317 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
318 // Return now the only terminator is an unconditional branch.
319 TBB = LastInst->getOperand(0).getMBB();
323 SecondLastOpc = SecondLastInst->getOpcode();
328 // If there are three terminators, we don't know what sort of block this is.
329 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
332 // If the block ends with a B and a Bcc, handle it.
333 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
334 TBB = SecondLastInst->getOperand(0).getMBB();
335 Cond.push_back(SecondLastInst->getOperand(1));
336 Cond.push_back(SecondLastInst->getOperand(2));
337 FBB = LastInst->getOperand(0).getMBB();
341 // If the block ends with two unconditional branches, handle it. The second
342 // one is not executed, so remove it.
343 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
344 TBB = SecondLastInst->getOperand(0).getMBB();
347 I->eraseFromParent();
351 // ...likewise if it ends with a branch table followed by an unconditional
352 // branch. The branch folder can create these, and we must get rid of them for
353 // correctness of Thumb constant islands.
354 if ((isJumpTableBranchOpcode(SecondLastOpc) ||
355 isIndirectBranchOpcode(SecondLastOpc)) &&
356 isUncondBranchOpcode(LastOpc)) {
359 I->eraseFromParent();
363 // Otherwise, can't handle this.
368 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
369 MachineBasicBlock::iterator I = MBB.end();
370 if (I == MBB.begin()) return 0;
372 while (I->isDebugValue()) {
373 if (I == MBB.begin())
377 if (!isUncondBranchOpcode(I->getOpcode()) &&
378 !isCondBranchOpcode(I->getOpcode()))
381 // Remove the branch.
382 I->eraseFromParent();
386 if (I == MBB.begin()) return 1;
388 if (!isCondBranchOpcode(I->getOpcode()))
391 // Remove the branch.
392 I->eraseFromParent();
397 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
398 MachineBasicBlock *FBB,
399 const SmallVectorImpl<MachineOperand> &Cond,
401 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
402 int BOpc = !AFI->isThumbFunction()
403 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
404 int BccOpc = !AFI->isThumbFunction()
405 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
406 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
408 // Shouldn't be a fall through.
409 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
410 assert((Cond.size() == 2 || Cond.size() == 0) &&
411 "ARM branch conditions have two components!");
414 if (Cond.empty()) { // Unconditional branch?
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
418 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
420 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
425 // Two-way conditional branch.
426 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
427 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
431 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
435 bool ARMBaseInstrInfo::
436 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
437 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
438 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
442 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
443 if (MI->isBundle()) {
444 MachineBasicBlock::const_instr_iterator I = MI;
445 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
446 while (++I != E && I->isInsideBundle()) {
447 int PIdx = I->findFirstPredOperandIdx();
448 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
454 int PIdx = MI->findFirstPredOperandIdx();
455 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
458 bool ARMBaseInstrInfo::
459 PredicateInstruction(MachineInstr *MI,
460 const SmallVectorImpl<MachineOperand> &Pred) const {
461 unsigned Opc = MI->getOpcode();
462 if (isUncondBranchOpcode(Opc)) {
463 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
464 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
465 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
469 int PIdx = MI->findFirstPredOperandIdx();
471 MachineOperand &PMO = MI->getOperand(PIdx);
472 PMO.setImm(Pred[0].getImm());
473 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
479 bool ARMBaseInstrInfo::
480 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
481 const SmallVectorImpl<MachineOperand> &Pred2) const {
482 if (Pred1.size() > 2 || Pred2.size() > 2)
485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
496 return CC2 == ARMCC::HI;
498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
500 return CC2 == ARMCC::GT;
502 return CC2 == ARMCC::LT;
506 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
507 std::vector<MachineOperand> &Pred) const {
508 // FIXME: This confuses implicit_def with optional CPSR def.
509 const MCInstrDesc &MCID = MI->getDesc();
510 if (!MCID.getImplicitDefs() && !MI->hasOptionalDef())
514 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
515 const MachineOperand &MO = MI->getOperand(i);
516 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
525 /// isPredicable - Return true if the specified instruction can be predicated.
526 /// By default, this returns true for every instruction with a
527 /// PredicateOperand.
528 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
529 if (!MI->isPredicable())
532 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
533 ARMFunctionInfo *AFI =
534 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
535 return AFI->isThumb2Function();
540 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
541 LLVM_ATTRIBUTE_NOINLINE
542 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
544 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
546 assert(JTI < JT.size());
547 return JT[JTI].MBBs.size();
550 /// GetInstSize - Return the size of the specified MachineInstr.
552 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
553 const MachineBasicBlock &MBB = *MI->getParent();
554 const MachineFunction *MF = MBB.getParent();
555 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
557 const MCInstrDesc &MCID = MI->getDesc();
559 return MCID.getSize();
561 // If this machine instr is an inline asm, measure it.
562 if (MI->getOpcode() == ARM::INLINEASM)
563 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
566 unsigned Opc = MI->getOpcode();
568 case TargetOpcode::IMPLICIT_DEF:
569 case TargetOpcode::KILL:
570 case TargetOpcode::PROLOG_LABEL:
571 case TargetOpcode::EH_LABEL:
572 case TargetOpcode::DBG_VALUE:
574 case TargetOpcode::BUNDLE:
575 return getInstBundleLength(MI);
576 case ARM::MOVi16_ga_pcrel:
577 case ARM::MOVTi16_ga_pcrel:
578 case ARM::t2MOVi16_ga_pcrel:
579 case ARM::t2MOVTi16_ga_pcrel:
582 case ARM::t2MOVi32imm:
584 case ARM::CONSTPOOL_ENTRY:
585 // If this machine instr is a constant pool entry, its size is recorded as
587 return MI->getOperand(2).getImm();
588 case ARM::Int_eh_sjlj_longjmp:
590 case ARM::tInt_eh_sjlj_longjmp:
592 case ARM::Int_eh_sjlj_setjmp:
593 case ARM::Int_eh_sjlj_setjmp_nofp:
595 case ARM::tInt_eh_sjlj_setjmp:
596 case ARM::t2Int_eh_sjlj_setjmp:
597 case ARM::t2Int_eh_sjlj_setjmp_nofp:
605 case ARM::t2TBH_JT: {
606 // These are jumptable branches, i.e. a branch followed by an inlined
607 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
608 // entry is one byte; TBH two byte each.
609 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
610 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
611 unsigned NumOps = MCID.getNumOperands();
612 MachineOperand JTOP =
613 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
614 unsigned JTI = JTOP.getIndex();
615 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
617 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
618 assert(JTI < JT.size());
619 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
620 // 4 aligned. The assembler / linker may add 2 byte padding just before
621 // the JT entries. The size does not include this padding; the
622 // constant islands pass does separate bookkeeping for it.
623 // FIXME: If we know the size of the function is less than (1 << 16) *2
624 // bytes, we can use 16-bit entries instead. Then there won't be an
626 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
627 unsigned NumEntries = getNumJTEntries(JT, JTI);
628 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
629 // Make sure the instruction that follows TBB is 2-byte aligned.
630 // FIXME: Constant island pass should insert an "ALIGN" instruction
633 return NumEntries * EntrySize + InstSize;
636 // Otherwise, pseudo-instruction sizes are zero.
639 return 0; // Not reached
642 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
644 MachineBasicBlock::const_instr_iterator I = MI;
645 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
646 while (++I != E && I->isInsideBundle()) {
647 assert(!I->isBundle() && "No nested bundle!");
648 Size += GetInstSizeInBytes(&*I);
653 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
654 MachineBasicBlock::iterator I, DebugLoc DL,
655 unsigned DestReg, unsigned SrcReg,
656 bool KillSrc) const {
657 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
658 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
660 if (GPRDest && GPRSrc) {
661 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
662 .addReg(SrcReg, getKillRegState(KillSrc))));
666 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
667 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
670 if (SPRDest && SPRSrc)
672 else if (GPRDest && SPRSrc)
674 else if (SPRDest && GPRSrc)
676 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
678 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
682 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
683 MIB.addReg(SrcReg, getKillRegState(KillSrc));
684 if (Opc == ARM::VORRq)
685 MIB.addReg(SrcReg, getKillRegState(KillSrc));
690 // Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
691 if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
692 ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
693 const TargetRegisterInfo *TRI = &getRegisterInfo();
694 assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
695 unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
696 ARM::qsub_1 : ARM::qsub_3;
697 for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
698 unsigned Dst = TRI->getSubReg(DestReg, i);
699 unsigned Src = TRI->getSubReg(SrcReg, i);
700 MachineInstrBuilder Mov =
701 AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VORRq))
702 .addReg(Dst, RegState::Define)
703 .addReg(Src, getKillRegState(KillSrc))
704 .addReg(Src, getKillRegState(KillSrc)));
705 if (i == EndSubReg) {
706 Mov->addRegisterDefined(DestReg, TRI);
708 Mov->addRegisterKilled(SrcReg, TRI);
713 llvm_unreachable("Impossible reg-to-reg copy");
717 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
718 unsigned Reg, unsigned SubIdx, unsigned State,
719 const TargetRegisterInfo *TRI) {
721 return MIB.addReg(Reg, State);
723 if (TargetRegisterInfo::isPhysicalRegister(Reg))
724 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
725 return MIB.addReg(Reg, State, SubIdx);
728 void ARMBaseInstrInfo::
729 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
730 unsigned SrcReg, bool isKill, int FI,
731 const TargetRegisterClass *RC,
732 const TargetRegisterInfo *TRI) const {
734 if (I != MBB.end()) DL = I->getDebugLoc();
735 MachineFunction &MF = *MBB.getParent();
736 MachineFrameInfo &MFI = *MF.getFrameInfo();
737 unsigned Align = MFI.getObjectAlignment(FI);
739 MachineMemOperand *MMO =
740 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
741 MachineMemOperand::MOStore,
742 MFI.getObjectSize(FI),
745 switch (RC->getSize()) {
747 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
748 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
749 .addReg(SrcReg, getKillRegState(isKill))
750 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
751 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
752 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
753 .addReg(SrcReg, getKillRegState(isKill))
754 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
756 llvm_unreachable("Unknown reg class!");
759 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
760 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
761 .addReg(SrcReg, getKillRegState(isKill))
762 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
764 llvm_unreachable("Unknown reg class!");
767 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
768 // Use aligned spills if the stack can be realigned.
769 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
770 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64Pseudo))
771 .addFrameIndex(FI).addImm(16)
772 .addReg(SrcReg, getKillRegState(isKill))
773 .addMemOperand(MMO));
775 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
776 .addReg(SrcReg, getKillRegState(isKill))
778 .addMemOperand(MMO));
781 llvm_unreachable("Unknown reg class!");
784 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
785 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
786 // FIXME: It's possible to only store part of the QQ register if the
787 // spilled def has a sub-register index.
788 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
789 .addFrameIndex(FI).addImm(16)
790 .addReg(SrcReg, getKillRegState(isKill))
791 .addMemOperand(MMO));
793 MachineInstrBuilder MIB =
794 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
797 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
798 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
799 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
800 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
803 llvm_unreachable("Unknown reg class!");
806 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
807 MachineInstrBuilder MIB =
808 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
811 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
812 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
813 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
814 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
815 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
816 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
817 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
818 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
820 llvm_unreachable("Unknown reg class!");
823 llvm_unreachable("Unknown reg class!");
828 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
829 int &FrameIndex) const {
830 switch (MI->getOpcode()) {
833 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
834 if (MI->getOperand(1).isFI() &&
835 MI->getOperand(2).isReg() &&
836 MI->getOperand(3).isImm() &&
837 MI->getOperand(2).getReg() == 0 &&
838 MI->getOperand(3).getImm() == 0) {
839 FrameIndex = MI->getOperand(1).getIndex();
840 return MI->getOperand(0).getReg();
848 if (MI->getOperand(1).isFI() &&
849 MI->getOperand(2).isImm() &&
850 MI->getOperand(2).getImm() == 0) {
851 FrameIndex = MI->getOperand(1).getIndex();
852 return MI->getOperand(0).getReg();
855 case ARM::VST1q64Pseudo:
856 if (MI->getOperand(0).isFI() &&
857 MI->getOperand(2).getSubReg() == 0) {
858 FrameIndex = MI->getOperand(0).getIndex();
859 return MI->getOperand(2).getReg();
863 if (MI->getOperand(1).isFI() &&
864 MI->getOperand(0).getSubReg() == 0) {
865 FrameIndex = MI->getOperand(1).getIndex();
866 return MI->getOperand(0).getReg();
874 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
875 int &FrameIndex) const {
876 const MachineMemOperand *Dummy;
877 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
880 void ARMBaseInstrInfo::
881 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
882 unsigned DestReg, int FI,
883 const TargetRegisterClass *RC,
884 const TargetRegisterInfo *TRI) const {
886 if (I != MBB.end()) DL = I->getDebugLoc();
887 MachineFunction &MF = *MBB.getParent();
888 MachineFrameInfo &MFI = *MF.getFrameInfo();
889 unsigned Align = MFI.getObjectAlignment(FI);
890 MachineMemOperand *MMO =
891 MF.getMachineMemOperand(
892 MachinePointerInfo::getFixedStack(FI),
893 MachineMemOperand::MOLoad,
894 MFI.getObjectSize(FI),
897 switch (RC->getSize()) {
899 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
900 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
901 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
903 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
904 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
905 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
907 llvm_unreachable("Unknown reg class!");
910 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
911 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
912 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
914 llvm_unreachable("Unknown reg class!");
917 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
918 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
919 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64Pseudo), DestReg)
920 .addFrameIndex(FI).addImm(16)
921 .addMemOperand(MMO));
923 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
925 .addMemOperand(MMO));
928 llvm_unreachable("Unknown reg class!");
931 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
932 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
933 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
934 .addFrameIndex(FI).addImm(16)
935 .addMemOperand(MMO));
937 MachineInstrBuilder MIB =
938 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
941 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
942 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
943 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
944 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
945 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
948 llvm_unreachable("Unknown reg class!");
951 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
952 MachineInstrBuilder MIB =
953 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
956 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
957 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
958 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
959 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
960 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
961 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
962 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
963 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
964 MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
966 llvm_unreachable("Unknown reg class!");
969 llvm_unreachable("Unknown regclass!");
974 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
975 int &FrameIndex) const {
976 switch (MI->getOpcode()) {
979 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
980 if (MI->getOperand(1).isFI() &&
981 MI->getOperand(2).isReg() &&
982 MI->getOperand(3).isImm() &&
983 MI->getOperand(2).getReg() == 0 &&
984 MI->getOperand(3).getImm() == 0) {
985 FrameIndex = MI->getOperand(1).getIndex();
986 return MI->getOperand(0).getReg();
994 if (MI->getOperand(1).isFI() &&
995 MI->getOperand(2).isImm() &&
996 MI->getOperand(2).getImm() == 0) {
997 FrameIndex = MI->getOperand(1).getIndex();
998 return MI->getOperand(0).getReg();
1001 case ARM::VLD1q64Pseudo:
1002 if (MI->getOperand(1).isFI() &&
1003 MI->getOperand(0).getSubReg() == 0) {
1004 FrameIndex = MI->getOperand(1).getIndex();
1005 return MI->getOperand(0).getReg();
1009 if (MI->getOperand(1).isFI() &&
1010 MI->getOperand(0).getSubReg() == 0) {
1011 FrameIndex = MI->getOperand(1).getIndex();
1012 return MI->getOperand(0).getReg();
1020 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1021 int &FrameIndex) const {
1022 const MachineMemOperand *Dummy;
1023 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1026 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1027 // This hook gets to expand COPY instructions before they become
1028 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1029 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1030 // changed into a VORR that can go down the NEON pipeline.
1031 if (!WidenVMOVS || !MI->isCopy())
1034 // Look for a copy between even S-registers. That is where we keep floats
1035 // when using NEON v2f32 instructions for f32 arithmetic.
1036 unsigned DstRegS = MI->getOperand(0).getReg();
1037 unsigned SrcRegS = MI->getOperand(1).getReg();
1038 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1041 const TargetRegisterInfo *TRI = &getRegisterInfo();
1042 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1044 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1046 if (!DstRegD || !SrcRegD)
1049 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1050 // legal if the COPY already defines the full DstRegD, and it isn't a
1051 // sub-register insertion.
1052 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1055 // A dead copy shouldn't show up here, but reject it just in case.
1056 if (MI->getOperand(0).isDead())
1059 // All clear, widen the COPY.
1060 DEBUG(dbgs() << "widening: " << *MI);
1062 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1063 // or some other super-register.
1064 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1065 if (ImpDefIdx != -1)
1066 MI->RemoveOperand(ImpDefIdx);
1068 // Change the opcode and operands.
1069 MI->setDesc(get(ARM::VMOVD));
1070 MI->getOperand(0).setReg(DstRegD);
1071 MI->getOperand(1).setReg(SrcRegD);
1072 AddDefaultPred(MachineInstrBuilder(MI));
1074 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1075 // register scavenger and machine verifier, so we need to indicate that we
1076 // are reading an undefined value from SrcRegD, but a proper value from
1078 MI->getOperand(1).setIsUndef();
1079 MachineInstrBuilder(MI).addReg(SrcRegS, RegState::Implicit);
1081 // SrcRegD may actually contain an unrelated value in the ssub_1
1082 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1083 if (MI->getOperand(1).isKill()) {
1084 MI->getOperand(1).setIsKill(false);
1085 MI->addRegisterKilled(SrcRegS, TRI, true);
1088 DEBUG(dbgs() << "replaced by: " << *MI);
1093 ARMBaseInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1094 int FrameIx, uint64_t Offset,
1095 const MDNode *MDPtr,
1096 DebugLoc DL) const {
1097 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::DBG_VALUE))
1098 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
1102 /// Create a copy of a const pool value. Update CPI to the new index and return
1104 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1105 MachineConstantPool *MCP = MF.getConstantPool();
1106 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1108 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1109 assert(MCPE.isMachineConstantPoolEntry() &&
1110 "Expecting a machine constantpool entry!");
1111 ARMConstantPoolValue *ACPV =
1112 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1114 unsigned PCLabelId = AFI->createPICLabelUId();
1115 ARMConstantPoolValue *NewCPV = 0;
1116 // FIXME: The below assumes PIC relocation model and that the function
1117 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1118 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1119 // instructions, so that's probably OK, but is PIC always correct when
1121 if (ACPV->isGlobalValue())
1122 NewCPV = ARMConstantPoolConstant::
1123 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1125 else if (ACPV->isExtSymbol())
1126 NewCPV = ARMConstantPoolSymbol::
1127 Create(MF.getFunction()->getContext(),
1128 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1129 else if (ACPV->isBlockAddress())
1130 NewCPV = ARMConstantPoolConstant::
1131 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1132 ARMCP::CPBlockAddress, 4);
1133 else if (ACPV->isLSDA())
1134 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1136 else if (ACPV->isMachineBasicBlock())
1137 NewCPV = ARMConstantPoolMBB::
1138 Create(MF.getFunction()->getContext(),
1139 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1141 llvm_unreachable("Unexpected ARM constantpool value type!!");
1142 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1146 void ARMBaseInstrInfo::
1147 reMaterialize(MachineBasicBlock &MBB,
1148 MachineBasicBlock::iterator I,
1149 unsigned DestReg, unsigned SubIdx,
1150 const MachineInstr *Orig,
1151 const TargetRegisterInfo &TRI) const {
1152 unsigned Opcode = Orig->getOpcode();
1155 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1156 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1160 case ARM::tLDRpci_pic:
1161 case ARM::t2LDRpci_pic: {
1162 MachineFunction &MF = *MBB.getParent();
1163 unsigned CPI = Orig->getOperand(1).getIndex();
1164 unsigned PCLabelId = duplicateCPV(MF, CPI);
1165 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1167 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1168 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1175 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1176 MachineInstr *MI = TargetInstrInfoImpl::duplicate(Orig, MF);
1177 switch(Orig->getOpcode()) {
1178 case ARM::tLDRpci_pic:
1179 case ARM::t2LDRpci_pic: {
1180 unsigned CPI = Orig->getOperand(1).getIndex();
1181 unsigned PCLabelId = duplicateCPV(MF, CPI);
1182 Orig->getOperand(1).setIndex(CPI);
1183 Orig->getOperand(2).setImm(PCLabelId);
1190 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1191 const MachineInstr *MI1,
1192 const MachineRegisterInfo *MRI) const {
1193 int Opcode = MI0->getOpcode();
1194 if (Opcode == ARM::t2LDRpci ||
1195 Opcode == ARM::t2LDRpci_pic ||
1196 Opcode == ARM::tLDRpci ||
1197 Opcode == ARM::tLDRpci_pic ||
1198 Opcode == ARM::MOV_ga_dyn ||
1199 Opcode == ARM::MOV_ga_pcrel ||
1200 Opcode == ARM::MOV_ga_pcrel_ldr ||
1201 Opcode == ARM::t2MOV_ga_dyn ||
1202 Opcode == ARM::t2MOV_ga_pcrel) {
1203 if (MI1->getOpcode() != Opcode)
1205 if (MI0->getNumOperands() != MI1->getNumOperands())
1208 const MachineOperand &MO0 = MI0->getOperand(1);
1209 const MachineOperand &MO1 = MI1->getOperand(1);
1210 if (MO0.getOffset() != MO1.getOffset())
1213 if (Opcode == ARM::MOV_ga_dyn ||
1214 Opcode == ARM::MOV_ga_pcrel ||
1215 Opcode == ARM::MOV_ga_pcrel_ldr ||
1216 Opcode == ARM::t2MOV_ga_dyn ||
1217 Opcode == ARM::t2MOV_ga_pcrel)
1218 // Ignore the PC labels.
1219 return MO0.getGlobal() == MO1.getGlobal();
1221 const MachineFunction *MF = MI0->getParent()->getParent();
1222 const MachineConstantPool *MCP = MF->getConstantPool();
1223 int CPI0 = MO0.getIndex();
1224 int CPI1 = MO1.getIndex();
1225 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1226 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1227 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1228 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1229 if (isARMCP0 && isARMCP1) {
1230 ARMConstantPoolValue *ACPV0 =
1231 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1232 ARMConstantPoolValue *ACPV1 =
1233 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1234 return ACPV0->hasSameValue(ACPV1);
1235 } else if (!isARMCP0 && !isARMCP1) {
1236 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1239 } else if (Opcode == ARM::PICLDR) {
1240 if (MI1->getOpcode() != Opcode)
1242 if (MI0->getNumOperands() != MI1->getNumOperands())
1245 unsigned Addr0 = MI0->getOperand(1).getReg();
1246 unsigned Addr1 = MI1->getOperand(1).getReg();
1247 if (Addr0 != Addr1) {
1249 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1250 !TargetRegisterInfo::isVirtualRegister(Addr1))
1253 // This assumes SSA form.
1254 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1255 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1256 // Check if the loaded value, e.g. a constantpool of a global address, are
1258 if (!produceSameValue(Def0, Def1, MRI))
1262 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1263 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1264 const MachineOperand &MO0 = MI0->getOperand(i);
1265 const MachineOperand &MO1 = MI1->getOperand(i);
1266 if (!MO0.isIdenticalTo(MO1))
1272 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1275 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1276 /// determine if two loads are loading from the same base address. It should
1277 /// only return true if the base pointers are the same and the only differences
1278 /// between the two addresses is the offset. It also returns the offsets by
1280 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1282 int64_t &Offset2) const {
1283 // Don't worry about Thumb: just ARM and Thumb2.
1284 if (Subtarget.isThumb1Only()) return false;
1286 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1289 switch (Load1->getMachineOpcode()) {
1302 case ARM::t2LDRSHi8:
1304 case ARM::t2LDRSHi12:
1308 switch (Load2->getMachineOpcode()) {
1321 case ARM::t2LDRSHi8:
1323 case ARM::t2LDRSHi12:
1327 // Check if base addresses and chain operands match.
1328 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1329 Load1->getOperand(4) != Load2->getOperand(4))
1332 // Index should be Reg0.
1333 if (Load1->getOperand(3) != Load2->getOperand(3))
1336 // Determine the offsets.
1337 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1338 isa<ConstantSDNode>(Load2->getOperand(1))) {
1339 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1340 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1347 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1348 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1349 /// be scheduled togther. On some targets if two loads are loading from
1350 /// addresses in the same cache line, it's better if they are scheduled
1351 /// together. This function takes two integers that represent the load offsets
1352 /// from the common base address. It returns true if it decides it's desirable
1353 /// to schedule the two loads together. "NumLoads" is the number of loads that
1354 /// have already been scheduled after Load1.
1355 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1356 int64_t Offset1, int64_t Offset2,
1357 unsigned NumLoads) const {
1358 // Don't worry about Thumb: just ARM and Thumb2.
1359 if (Subtarget.isThumb1Only()) return false;
1361 assert(Offset2 > Offset1);
1363 if ((Offset2 - Offset1) / 8 > 64)
1366 if (Load1->getMachineOpcode() != Load2->getMachineOpcode())
1367 return false; // FIXME: overly conservative?
1369 // Four loads in a row should be sufficient.
1376 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1377 const MachineBasicBlock *MBB,
1378 const MachineFunction &MF) const {
1379 // Debug info is never a scheduling boundary. It's necessary to be explicit
1380 // due to the special treatment of IT instructions below, otherwise a
1381 // dbg_value followed by an IT will result in the IT instruction being
1382 // considered a scheduling hazard, which is wrong. It should be the actual
1383 // instruction preceding the dbg_value instruction(s), just like it is
1384 // when debug info is not present.
1385 if (MI->isDebugValue())
1388 // Terminators and labels can't be scheduled around.
1389 if (MI->isTerminator() || MI->isLabel())
1392 // Treat the start of the IT block as a scheduling boundary, but schedule
1393 // t2IT along with all instructions following it.
1394 // FIXME: This is a big hammer. But the alternative is to add all potential
1395 // true and anti dependencies to IT block instructions as implicit operands
1396 // to the t2IT instruction. The added compile time and complexity does not
1398 MachineBasicBlock::const_iterator I = MI;
1399 // Make sure to skip any dbg_value instructions
1400 while (++I != MBB->end() && I->isDebugValue())
1402 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1405 // Don't attempt to schedule around any instruction that defines
1406 // a stack-oriented pointer, as it's unlikely to be profitable. This
1407 // saves compile time, because it doesn't require every single
1408 // stack slot reference to depend on the instruction that does the
1410 if (MI->definesRegister(ARM::SP))
1416 bool ARMBaseInstrInfo::
1417 isProfitableToIfCvt(MachineBasicBlock &MBB,
1418 unsigned NumCycles, unsigned ExtraPredCycles,
1419 const BranchProbability &Probability) const {
1423 // Attempt to estimate the relative costs of predication versus branching.
1424 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1425 UnpredCost /= Probability.getDenominator();
1426 UnpredCost += 1; // The branch itself
1427 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1429 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1432 bool ARMBaseInstrInfo::
1433 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1434 unsigned TCycles, unsigned TExtra,
1435 MachineBasicBlock &FMBB,
1436 unsigned FCycles, unsigned FExtra,
1437 const BranchProbability &Probability) const {
1438 if (!TCycles || !FCycles)
1441 // Attempt to estimate the relative costs of predication versus branching.
1442 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1443 TUnpredCost /= Probability.getDenominator();
1445 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1446 unsigned FUnpredCost = Comp * FCycles;
1447 FUnpredCost /= Probability.getDenominator();
1449 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1450 UnpredCost += 1; // The branch itself
1451 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1453 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1456 /// getInstrPredicate - If instruction is predicated, returns its predicate
1457 /// condition, otherwise returns AL. It also returns the condition code
1458 /// register by reference.
1460 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1461 int PIdx = MI->findFirstPredOperandIdx();
1467 PredReg = MI->getOperand(PIdx+1).getReg();
1468 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1472 int llvm::getMatchingCondBranchOpcode(int Opc) {
1475 else if (Opc == ARM::tB)
1477 else if (Opc == ARM::t2B)
1480 llvm_unreachable("Unknown unconditional branch opcode!");
1485 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1486 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1489 /// This will go away once we can teach tblgen how to set the optional CPSR def
1491 struct AddSubFlagsOpcodePair {
1493 unsigned MachineOpc;
1496 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1497 {ARM::ADDSri, ARM::ADDri},
1498 {ARM::ADDSrr, ARM::ADDrr},
1499 {ARM::ADDSrsi, ARM::ADDrsi},
1500 {ARM::ADDSrsr, ARM::ADDrsr},
1502 {ARM::SUBSri, ARM::SUBri},
1503 {ARM::SUBSrr, ARM::SUBrr},
1504 {ARM::SUBSrsi, ARM::SUBrsi},
1505 {ARM::SUBSrsr, ARM::SUBrsr},
1507 {ARM::RSBSri, ARM::RSBri},
1508 {ARM::RSBSrsi, ARM::RSBrsi},
1509 {ARM::RSBSrsr, ARM::RSBrsr},
1511 {ARM::t2ADDSri, ARM::t2ADDri},
1512 {ARM::t2ADDSrr, ARM::t2ADDrr},
1513 {ARM::t2ADDSrs, ARM::t2ADDrs},
1515 {ARM::t2SUBSri, ARM::t2SUBri},
1516 {ARM::t2SUBSrr, ARM::t2SUBrr},
1517 {ARM::t2SUBSrs, ARM::t2SUBrs},
1519 {ARM::t2RSBSri, ARM::t2RSBri},
1520 {ARM::t2RSBSrs, ARM::t2RSBrs},
1523 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1524 static const int NPairs =
1525 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
1526 for (AddSubFlagsOpcodePair *OpcPair = &AddSubFlagsOpcodeMap[0],
1527 *End = &AddSubFlagsOpcodeMap[NPairs]; OpcPair != End; ++OpcPair) {
1528 if (OldOpc == OpcPair->PseudoOpc) {
1529 return OpcPair->MachineOpc;
1535 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1536 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1537 unsigned DestReg, unsigned BaseReg, int NumBytes,
1538 ARMCC::CondCodes Pred, unsigned PredReg,
1539 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1540 bool isSub = NumBytes < 0;
1541 if (isSub) NumBytes = -NumBytes;
1544 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1545 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1546 assert(ThisVal && "Didn't extract field correctly");
1548 // We will handle these bits from offset, clear them.
1549 NumBytes &= ~ThisVal;
1551 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1553 // Build the new ADD / SUB.
1554 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1555 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1556 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1557 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1558 .setMIFlags(MIFlags);
1563 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1564 unsigned FrameReg, int &Offset,
1565 const ARMBaseInstrInfo &TII) {
1566 unsigned Opcode = MI.getOpcode();
1567 const MCInstrDesc &Desc = MI.getDesc();
1568 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1571 // Memory operands in inline assembly always use AddrMode2.
1572 if (Opcode == ARM::INLINEASM)
1573 AddrMode = ARMII::AddrMode2;
1575 if (Opcode == ARM::ADDri) {
1576 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1578 // Turn it into a move.
1579 MI.setDesc(TII.get(ARM::MOVr));
1580 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1581 MI.RemoveOperand(FrameRegIdx+1);
1584 } else if (Offset < 0) {
1587 MI.setDesc(TII.get(ARM::SUBri));
1590 // Common case: small offset, fits into instruction.
1591 if (ARM_AM::getSOImmVal(Offset) != -1) {
1592 // Replace the FrameIndex with sp / fp
1593 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1594 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1599 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1601 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1602 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1604 // We will handle these bits from offset, clear them.
1605 Offset &= ~ThisImmVal;
1607 // Get the properly encoded SOImmVal field.
1608 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1609 "Bit extraction didn't work?");
1610 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1612 unsigned ImmIdx = 0;
1614 unsigned NumBits = 0;
1617 case ARMII::AddrMode_i12: {
1618 ImmIdx = FrameRegIdx + 1;
1619 InstrOffs = MI.getOperand(ImmIdx).getImm();
1623 case ARMII::AddrMode2: {
1624 ImmIdx = FrameRegIdx+2;
1625 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1626 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1631 case ARMII::AddrMode3: {
1632 ImmIdx = FrameRegIdx+2;
1633 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1634 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1639 case ARMII::AddrMode4:
1640 case ARMII::AddrMode6:
1641 // Can't fold any offset even if it's zero.
1643 case ARMII::AddrMode5: {
1644 ImmIdx = FrameRegIdx+1;
1645 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1646 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1653 llvm_unreachable("Unsupported addressing mode!");
1657 Offset += InstrOffs * Scale;
1658 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1664 // Attempt to fold address comp. if opcode has offset bits
1666 // Common case: small offset, fits into instruction.
1667 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1668 int ImmedOffset = Offset / Scale;
1669 unsigned Mask = (1 << NumBits) - 1;
1670 if ((unsigned)Offset <= Mask * Scale) {
1671 // Replace the FrameIndex with sp
1672 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1673 // FIXME: When addrmode2 goes away, this will simplify (like the
1674 // T2 version), as the LDR.i12 versions don't need the encoding
1675 // tricks for the offset value.
1677 if (AddrMode == ARMII::AddrMode_i12)
1678 ImmedOffset = -ImmedOffset;
1680 ImmedOffset |= 1 << NumBits;
1682 ImmOp.ChangeToImmediate(ImmedOffset);
1687 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1688 ImmedOffset = ImmedOffset & Mask;
1690 if (AddrMode == ARMII::AddrMode_i12)
1691 ImmedOffset = -ImmedOffset;
1693 ImmedOffset |= 1 << NumBits;
1695 ImmOp.ChangeToImmediate(ImmedOffset);
1696 Offset &= ~(Mask*Scale);
1700 Offset = (isSub) ? -Offset : Offset;
1704 bool ARMBaseInstrInfo::
1705 AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpMask,
1706 int &CmpValue) const {
1707 switch (MI->getOpcode()) {
1711 SrcReg = MI->getOperand(0).getReg();
1713 CmpValue = MI->getOperand(1).getImm();
1717 SrcReg = MI->getOperand(0).getReg();
1718 CmpMask = MI->getOperand(1).getImm();
1726 /// isSuitableForMask - Identify a suitable 'and' instruction that
1727 /// operates on the given source register and applies the same mask
1728 /// as a 'tst' instruction. Provide a limited look-through for copies.
1729 /// When successful, MI will hold the found instruction.
1730 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
1731 int CmpMask, bool CommonUse) {
1732 switch (MI->getOpcode()) {
1735 if (CmpMask != MI->getOperand(2).getImm())
1737 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
1741 // Walk down one instruction which is potentially an 'and'.
1742 const MachineInstr &Copy = *MI;
1743 MachineBasicBlock::iterator AND(
1744 llvm::next(MachineBasicBlock::iterator(MI)));
1745 if (AND == MI->getParent()->end()) return false;
1747 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
1755 /// OptimizeCompareInstr - Convert the instruction supplying the argument to the
1756 /// comparison into one that sets the zero bit in the flags register.
1757 bool ARMBaseInstrInfo::
1758 OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
1759 int CmpValue, const MachineRegisterInfo *MRI) const {
1763 MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg);
1764 if (llvm::next(DI) != MRI->def_end())
1765 // Only support one definition.
1768 MachineInstr *MI = &*DI;
1770 // Masked compares sometimes use the same register as the corresponding 'and'.
1771 if (CmpMask != ~0) {
1772 if (!isSuitableForMask(MI, SrcReg, CmpMask, false)) {
1774 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
1775 UE = MRI->use_end(); UI != UE; ++UI) {
1776 if (UI->getParent() != CmpInstr->getParent()) continue;
1777 MachineInstr *PotentialAND = &*UI;
1778 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true))
1783 if (!MI) return false;
1787 // Conservatively refuse to convert an instruction which isn't in the same BB
1788 // as the comparison.
1789 if (MI->getParent() != CmpInstr->getParent())
1792 // Check that CPSR isn't set between the comparison instruction and the one we
1794 MachineBasicBlock::iterator I = CmpInstr,E = MI, B = MI->getParent()->begin();
1796 // Early exit if CmpInstr is at the beginning of the BB.
1797 if (I == B) return false;
1800 for (; I != E; --I) {
1801 const MachineInstr &Instr = *I;
1803 for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
1804 const MachineOperand &MO = Instr.getOperand(IO);
1805 if (!MO.isReg()) continue;
1807 // This instruction modifies or uses CPSR after the one we want to
1808 // change. We can't do this transformation.
1809 if (MO.getReg() == ARM::CPSR)
1814 // The 'and' is below the comparison instruction.
1818 // Set the "zero" bit in CPSR.
1819 switch (MI->getOpcode()) {
1853 case ARM::t2EORri: {
1854 // Scan forward for the use of CPSR, if it's a conditional code requires
1855 // checking of V bit, then this is not safe to do. If we can't find the
1856 // CPSR use (i.e. used in another block), then it's not safe to perform
1857 // the optimization.
1858 bool isSafe = false;
1860 E = MI->getParent()->end();
1861 while (!isSafe && ++I != E) {
1862 const MachineInstr &Instr = *I;
1863 for (unsigned IO = 0, EO = Instr.getNumOperands();
1864 !isSafe && IO != EO; ++IO) {
1865 const MachineOperand &MO = Instr.getOperand(IO);
1866 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
1872 // Condition code is after the operand before CPSR.
1873 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
1892 // Toggle the optional operand to CPSR.
1893 MI->getOperand(5).setReg(ARM::CPSR);
1894 MI->getOperand(5).setIsDef(true);
1895 CmpInstr->eraseFromParent();
1903 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
1904 MachineInstr *DefMI, unsigned Reg,
1905 MachineRegisterInfo *MRI) const {
1906 // Fold large immediates into add, sub, or, xor.
1907 unsigned DefOpc = DefMI->getOpcode();
1908 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
1910 if (!DefMI->getOperand(1).isImm())
1911 // Could be t2MOVi32imm <ga:xx>
1914 if (!MRI->hasOneNonDBGUse(Reg))
1917 unsigned UseOpc = UseMI->getOpcode();
1918 unsigned NewUseOpc = 0;
1919 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
1920 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
1921 bool Commute = false;
1923 default: return false;
1931 case ARM::t2EORrr: {
1932 Commute = UseMI->getOperand(2).getReg() != Reg;
1939 NewUseOpc = ARM::SUBri;
1945 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
1947 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
1948 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
1951 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
1952 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
1953 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
1957 case ARM::t2SUBrr: {
1961 NewUseOpc = ARM::t2SUBri;
1966 case ARM::t2EORrr: {
1967 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
1969 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
1970 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
1973 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
1974 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
1975 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
1983 unsigned OpIdx = Commute ? 2 : 1;
1984 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1985 bool isKill = UseMI->getOperand(OpIdx).isKill();
1986 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
1987 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1988 UseMI, UseMI->getDebugLoc(),
1989 get(NewUseOpc), NewReg)
1990 .addReg(Reg1, getKillRegState(isKill))
1991 .addImm(SOImmValV1)));
1992 UseMI->setDesc(get(NewUseOpc));
1993 UseMI->getOperand(1).setReg(NewReg);
1994 UseMI->getOperand(1).setIsKill();
1995 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
1996 DefMI->eraseFromParent();
2001 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2002 const MachineInstr *MI) const {
2003 if (!ItinData || ItinData->isEmpty())
2006 const MCInstrDesc &Desc = MI->getDesc();
2007 unsigned Class = Desc.getSchedClass();
2008 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2012 unsigned Opc = MI->getOpcode();
2015 llvm_unreachable("Unexpected multi-uops instruction!");
2021 // The number of uOps for load / store multiple are determined by the number
2024 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2025 // same cycle. The scheduling for the first load / store must be done
2026 // separately by assuming the the address is not 64-bit aligned.
2028 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2029 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2030 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2032 case ARM::VLDMDIA_UPD:
2033 case ARM::VLDMDDB_UPD:
2035 case ARM::VLDMSIA_UPD:
2036 case ARM::VLDMSDB_UPD:
2038 case ARM::VSTMDIA_UPD:
2039 case ARM::VSTMDDB_UPD:
2041 case ARM::VSTMSIA_UPD:
2042 case ARM::VSTMSDB_UPD: {
2043 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2044 return (NumRegs / 2) + (NumRegs % 2) + 1;
2047 case ARM::LDMIA_RET:
2052 case ARM::LDMIA_UPD:
2053 case ARM::LDMDA_UPD:
2054 case ARM::LDMDB_UPD:
2055 case ARM::LDMIB_UPD:
2060 case ARM::STMIA_UPD:
2061 case ARM::STMDA_UPD:
2062 case ARM::STMDB_UPD:
2063 case ARM::STMIB_UPD:
2065 case ARM::tLDMIA_UPD:
2066 case ARM::tSTMIA_UPD:
2070 case ARM::t2LDMIA_RET:
2073 case ARM::t2LDMIA_UPD:
2074 case ARM::t2LDMDB_UPD:
2077 case ARM::t2STMIA_UPD:
2078 case ARM::t2STMDB_UPD: {
2079 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2080 if (Subtarget.isCortexA8()) {
2083 // 4 registers would be issued: 2, 2.
2084 // 5 registers would be issued: 2, 2, 1.
2085 UOps = (NumRegs / 2);
2089 } else if (Subtarget.isCortexA9()) {
2090 UOps = (NumRegs / 2);
2091 // If there are odd number of registers or if it's not 64-bit aligned,
2092 // then it takes an extra AGU (Address Generation Unit) cycle.
2093 if ((NumRegs % 2) ||
2094 !MI->hasOneMemOperand() ||
2095 (*MI->memoperands_begin())->getAlignment() < 8)
2099 // Assume the worst.
2107 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2108 const MCInstrDesc &DefMCID,
2110 unsigned DefIdx, unsigned DefAlign) const {
2111 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2113 // Def is the address writeback.
2114 return ItinData->getOperandCycle(DefClass, DefIdx);
2117 if (Subtarget.isCortexA8()) {
2118 // (regno / 2) + (regno % 2) + 1
2119 DefCycle = RegNo / 2 + 1;
2122 } else if (Subtarget.isCortexA9()) {
2124 bool isSLoad = false;
2126 switch (DefMCID.getOpcode()) {
2129 case ARM::VLDMSIA_UPD:
2130 case ARM::VLDMSDB_UPD:
2135 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2136 // then it takes an extra cycle.
2137 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2140 // Assume the worst.
2141 DefCycle = RegNo + 2;
2148 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2149 const MCInstrDesc &DefMCID,
2151 unsigned DefIdx, unsigned DefAlign) const {
2152 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2154 // Def is the address writeback.
2155 return ItinData->getOperandCycle(DefClass, DefIdx);
2158 if (Subtarget.isCortexA8()) {
2159 // 4 registers would be issued: 1, 2, 1.
2160 // 5 registers would be issued: 1, 2, 2.
2161 DefCycle = RegNo / 2;
2164 // Result latency is issue cycle + 2: E2.
2166 } else if (Subtarget.isCortexA9()) {
2167 DefCycle = (RegNo / 2);
2168 // If there are odd number of registers or if it's not 64-bit aligned,
2169 // then it takes an extra AGU (Address Generation Unit) cycle.
2170 if ((RegNo % 2) || DefAlign < 8)
2172 // Result latency is AGU cycles + 2.
2175 // Assume the worst.
2176 DefCycle = RegNo + 2;
2183 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2184 const MCInstrDesc &UseMCID,
2186 unsigned UseIdx, unsigned UseAlign) const {
2187 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2189 return ItinData->getOperandCycle(UseClass, UseIdx);
2192 if (Subtarget.isCortexA8()) {
2193 // (regno / 2) + (regno % 2) + 1
2194 UseCycle = RegNo / 2 + 1;
2197 } else if (Subtarget.isCortexA9()) {
2199 bool isSStore = false;
2201 switch (UseMCID.getOpcode()) {
2204 case ARM::VSTMSIA_UPD:
2205 case ARM::VSTMSDB_UPD:
2210 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2211 // then it takes an extra cycle.
2212 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2215 // Assume the worst.
2216 UseCycle = RegNo + 2;
2223 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2224 const MCInstrDesc &UseMCID,
2226 unsigned UseIdx, unsigned UseAlign) const {
2227 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2229 return ItinData->getOperandCycle(UseClass, UseIdx);
2232 if (Subtarget.isCortexA8()) {
2233 UseCycle = RegNo / 2;
2238 } else if (Subtarget.isCortexA9()) {
2239 UseCycle = (RegNo / 2);
2240 // If there are odd number of registers or if it's not 64-bit aligned,
2241 // then it takes an extra AGU (Address Generation Unit) cycle.
2242 if ((RegNo % 2) || UseAlign < 8)
2245 // Assume the worst.
2252 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2253 const MCInstrDesc &DefMCID,
2254 unsigned DefIdx, unsigned DefAlign,
2255 const MCInstrDesc &UseMCID,
2256 unsigned UseIdx, unsigned UseAlign) const {
2257 unsigned DefClass = DefMCID.getSchedClass();
2258 unsigned UseClass = UseMCID.getSchedClass();
2260 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2261 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2263 // This may be a def / use of a variable_ops instruction, the operand
2264 // latency might be determinable dynamically. Let the target try to
2267 bool LdmBypass = false;
2268 switch (DefMCID.getOpcode()) {
2270 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2274 case ARM::VLDMDIA_UPD:
2275 case ARM::VLDMDDB_UPD:
2277 case ARM::VLDMSIA_UPD:
2278 case ARM::VLDMSDB_UPD:
2279 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2282 case ARM::LDMIA_RET:
2287 case ARM::LDMIA_UPD:
2288 case ARM::LDMDA_UPD:
2289 case ARM::LDMDB_UPD:
2290 case ARM::LDMIB_UPD:
2292 case ARM::tLDMIA_UPD:
2294 case ARM::t2LDMIA_RET:
2297 case ARM::t2LDMIA_UPD:
2298 case ARM::t2LDMDB_UPD:
2300 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2305 // We can't seem to determine the result latency of the def, assume it's 2.
2309 switch (UseMCID.getOpcode()) {
2311 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2315 case ARM::VSTMDIA_UPD:
2316 case ARM::VSTMDDB_UPD:
2318 case ARM::VSTMSIA_UPD:
2319 case ARM::VSTMSDB_UPD:
2320 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2327 case ARM::STMIA_UPD:
2328 case ARM::STMDA_UPD:
2329 case ARM::STMDB_UPD:
2330 case ARM::STMIB_UPD:
2331 case ARM::tSTMIA_UPD:
2336 case ARM::t2STMIA_UPD:
2337 case ARM::t2STMDB_UPD:
2338 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
2343 // Assume it's read in the first stage.
2346 UseCycle = DefCycle - UseCycle + 1;
2349 // It's a variable_ops instruction so we can't use DefIdx here. Just use
2350 // first def operand.
2351 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
2354 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
2355 UseClass, UseIdx)) {
2363 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2364 const MachineInstr *MI, unsigned Reg,
2365 unsigned &DefIdx, unsigned &Dist) {
2368 MachineBasicBlock::const_iterator I = MI; ++I;
2369 MachineBasicBlock::const_instr_iterator II =
2370 llvm::prior(I.getInstrIterator());
2371 assert(II->isInsideBundle() && "Empty bundle?");
2374 while (II->isInsideBundle()) {
2375 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2382 assert(Idx != -1 && "Cannot find bundled definition!");
2387 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2388 const MachineInstr *MI, unsigned Reg,
2389 unsigned &UseIdx, unsigned &Dist) {
2392 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2393 assert(II->isInsideBundle() && "Empty bundle?");
2394 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2396 // FIXME: This doesn't properly handle multiple uses.
2398 while (II != E && II->isInsideBundle()) {
2399 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2402 if (II->getOpcode() != ARM::t2IT)
2417 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2418 const MachineInstr *DefMI, unsigned DefIdx,
2419 const MachineInstr *UseMI, unsigned UseIdx) const {
2420 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2421 DefMI->isRegSequence() || DefMI->isImplicitDef())
2424 if (!ItinData || ItinData->isEmpty())
2425 return DefMI->mayLoad() ? 3 : 1;
2427 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2428 const MCInstrDesc *UseMCID = &UseMI->getDesc();
2429 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
2430 unsigned Reg = DefMO.getReg();
2431 if (Reg == ARM::CPSR) {
2432 if (DefMI->getOpcode() == ARM::FMSTAT) {
2433 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
2434 return Subtarget.isCortexA9() ? 1 : 20;
2437 // CPSR set and branch can be paired in the same cycle.
2438 if (UseMI->isBranch())
2441 // Otherwise it takes the instruction latency (generally one).
2442 int Latency = getInstrLatency(ItinData, DefMI);
2444 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
2445 // its uses. Instructions which are otherwise scheduled between them may
2446 // incur a code size penalty (not able to use the CPSR setting 16-bit
2448 if (Latency > 0 && Subtarget.isThumb2()) {
2449 const MachineFunction *MF = DefMI->getParent()->getParent();
2450 if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2456 unsigned DefAlign = DefMI->hasOneMemOperand()
2457 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
2458 unsigned UseAlign = UseMI->hasOneMemOperand()
2459 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2461 unsigned DefAdj = 0;
2462 if (DefMI->isBundle()) {
2463 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
2464 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2465 DefMI->isRegSequence() || DefMI->isImplicitDef())
2467 DefMCID = &DefMI->getDesc();
2469 unsigned UseAdj = 0;
2470 if (UseMI->isBundle()) {
2472 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
2473 Reg, NewUseIdx, UseAdj);
2477 UseMCID = &UseMI->getDesc();
2481 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2482 *UseMCID, UseIdx, UseAlign);
2483 int Adj = DefAdj + UseAdj;
2485 Latency -= (int)(DefAdj + UseAdj);
2491 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2492 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2493 // variants are one cycle cheaper.
2494 switch (DefMCID->getOpcode()) {
2498 unsigned ShOpVal = DefMI->getOperand(3).getImm();
2499 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2501 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2508 case ARM::t2LDRSHs: {
2509 // Thumb2 mode: lsl only.
2510 unsigned ShAmt = DefMI->getOperand(3).getImm();
2511 if (ShAmt == 0 || ShAmt == 2)
2518 if (DefAlign < 8 && Subtarget.isCortexA9())
2519 switch (DefMCID->getOpcode()) {
2525 case ARM::VLD1q8wb_fixed:
2526 case ARM::VLD1q16wb_fixed:
2527 case ARM::VLD1q32wb_fixed:
2528 case ARM::VLD1q64wb_fixed:
2529 case ARM::VLD1q8wb_register:
2530 case ARM::VLD1q16wb_register:
2531 case ARM::VLD1q32wb_register:
2532 case ARM::VLD1q64wb_register:
2539 case ARM::VLD2d8wb_fixed:
2540 case ARM::VLD2d16wb_fixed:
2541 case ARM::VLD2d32wb_fixed:
2542 case ARM::VLD2q8wb_fixed:
2543 case ARM::VLD2q16wb_fixed:
2544 case ARM::VLD2q32wb_fixed:
2545 case ARM::VLD2d8wb_register:
2546 case ARM::VLD2d16wb_register:
2547 case ARM::VLD2d32wb_register:
2548 case ARM::VLD2q8wb_register:
2549 case ARM::VLD2q16wb_register:
2550 case ARM::VLD2q32wb_register:
2555 case ARM::VLD3d8_UPD:
2556 case ARM::VLD3d16_UPD:
2557 case ARM::VLD3d32_UPD:
2558 case ARM::VLD1d64Twb_fixed:
2559 case ARM::VLD1d64Twb_register:
2560 case ARM::VLD3q8_UPD:
2561 case ARM::VLD3q16_UPD:
2562 case ARM::VLD3q32_UPD:
2567 case ARM::VLD4d8_UPD:
2568 case ARM::VLD4d16_UPD:
2569 case ARM::VLD4d32_UPD:
2570 case ARM::VLD1d64Qwb_fixed:
2571 case ARM::VLD1d64Qwb_register:
2572 case ARM::VLD4q8_UPD:
2573 case ARM::VLD4q16_UPD:
2574 case ARM::VLD4q32_UPD:
2575 case ARM::VLD1DUPq8:
2576 case ARM::VLD1DUPq16:
2577 case ARM::VLD1DUPq32:
2578 case ARM::VLD1DUPq8wb_fixed:
2579 case ARM::VLD1DUPq16wb_fixed:
2580 case ARM::VLD1DUPq32wb_fixed:
2581 case ARM::VLD1DUPq8wb_register:
2582 case ARM::VLD1DUPq16wb_register:
2583 case ARM::VLD1DUPq32wb_register:
2584 case ARM::VLD2DUPd8:
2585 case ARM::VLD2DUPd16:
2586 case ARM::VLD2DUPd32:
2587 case ARM::VLD2DUPd8wb_fixed:
2588 case ARM::VLD2DUPd16wb_fixed:
2589 case ARM::VLD2DUPd32wb_fixed:
2590 case ARM::VLD2DUPd8wb_register:
2591 case ARM::VLD2DUPd16wb_register:
2592 case ARM::VLD2DUPd32wb_register:
2593 case ARM::VLD4DUPd8:
2594 case ARM::VLD4DUPd16:
2595 case ARM::VLD4DUPd32:
2596 case ARM::VLD4DUPd8_UPD:
2597 case ARM::VLD4DUPd16_UPD:
2598 case ARM::VLD4DUPd32_UPD:
2600 case ARM::VLD1LNd16:
2601 case ARM::VLD1LNd32:
2602 case ARM::VLD1LNd8_UPD:
2603 case ARM::VLD1LNd16_UPD:
2604 case ARM::VLD1LNd32_UPD:
2606 case ARM::VLD2LNd16:
2607 case ARM::VLD2LNd32:
2608 case ARM::VLD2LNq16:
2609 case ARM::VLD2LNq32:
2610 case ARM::VLD2LNd8_UPD:
2611 case ARM::VLD2LNd16_UPD:
2612 case ARM::VLD2LNd32_UPD:
2613 case ARM::VLD2LNq16_UPD:
2614 case ARM::VLD2LNq32_UPD:
2616 case ARM::VLD4LNd16:
2617 case ARM::VLD4LNd32:
2618 case ARM::VLD4LNq16:
2619 case ARM::VLD4LNq32:
2620 case ARM::VLD4LNd8_UPD:
2621 case ARM::VLD4LNd16_UPD:
2622 case ARM::VLD4LNd32_UPD:
2623 case ARM::VLD4LNq16_UPD:
2624 case ARM::VLD4LNq32_UPD:
2625 // If the address is not 64-bit aligned, the latencies of these
2626 // instructions increases by one.
2635 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2636 SDNode *DefNode, unsigned DefIdx,
2637 SDNode *UseNode, unsigned UseIdx) const {
2638 if (!DefNode->isMachineOpcode())
2641 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
2643 if (isZeroCost(DefMCID.Opcode))
2646 if (!ItinData || ItinData->isEmpty())
2647 return DefMCID.mayLoad() ? 3 : 1;
2649 if (!UseNode->isMachineOpcode()) {
2650 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2651 if (Subtarget.isCortexA9())
2652 return Latency <= 2 ? 1 : Latency - 1;
2654 return Latency <= 3 ? 1 : Latency - 2;
2657 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
2658 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
2659 unsigned DefAlign = !DefMN->memoperands_empty()
2660 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
2661 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
2662 unsigned UseAlign = !UseMN->memoperands_empty()
2663 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
2664 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2665 UseMCID, UseIdx, UseAlign);
2668 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
2669 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
2670 // variants are one cycle cheaper.
2671 switch (DefMCID.getOpcode()) {
2676 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2677 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2679 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
2686 case ARM::t2LDRSHs: {
2687 // Thumb2 mode: lsl only.
2689 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
2690 if (ShAmt == 0 || ShAmt == 2)
2697 if (DefAlign < 8 && Subtarget.isCortexA9())
2698 switch (DefMCID.getOpcode()) {
2700 case ARM::VLD1q8Pseudo:
2701 case ARM::VLD1q16Pseudo:
2702 case ARM::VLD1q32Pseudo:
2703 case ARM::VLD1q64Pseudo:
2704 case ARM::VLD1q8PseudoWB_register:
2705 case ARM::VLD1q16PseudoWB_register:
2706 case ARM::VLD1q32PseudoWB_register:
2707 case ARM::VLD1q64PseudoWB_register:
2708 case ARM::VLD1q8PseudoWB_fixed:
2709 case ARM::VLD1q16PseudoWB_fixed:
2710 case ARM::VLD1q32PseudoWB_fixed:
2711 case ARM::VLD1q64PseudoWB_fixed:
2712 case ARM::VLD2d8Pseudo:
2713 case ARM::VLD2d16Pseudo:
2714 case ARM::VLD2d32Pseudo:
2715 case ARM::VLD2q8Pseudo:
2716 case ARM::VLD2q16Pseudo:
2717 case ARM::VLD2q32Pseudo:
2718 case ARM::VLD2d8PseudoWB_fixed:
2719 case ARM::VLD2d16PseudoWB_fixed:
2720 case ARM::VLD2d32PseudoWB_fixed:
2721 case ARM::VLD2q8PseudoWB_fixed:
2722 case ARM::VLD2q16PseudoWB_fixed:
2723 case ARM::VLD2q32PseudoWB_fixed:
2724 case ARM::VLD2d8PseudoWB_register:
2725 case ARM::VLD2d16PseudoWB_register:
2726 case ARM::VLD2d32PseudoWB_register:
2727 case ARM::VLD2q8PseudoWB_register:
2728 case ARM::VLD2q16PseudoWB_register:
2729 case ARM::VLD2q32PseudoWB_register:
2730 case ARM::VLD3d8Pseudo:
2731 case ARM::VLD3d16Pseudo:
2732 case ARM::VLD3d32Pseudo:
2733 case ARM::VLD1d64TPseudo:
2734 case ARM::VLD3d8Pseudo_UPD:
2735 case ARM::VLD3d16Pseudo_UPD:
2736 case ARM::VLD3d32Pseudo_UPD:
2737 case ARM::VLD3q8Pseudo_UPD:
2738 case ARM::VLD3q16Pseudo_UPD:
2739 case ARM::VLD3q32Pseudo_UPD:
2740 case ARM::VLD3q8oddPseudo:
2741 case ARM::VLD3q16oddPseudo:
2742 case ARM::VLD3q32oddPseudo:
2743 case ARM::VLD3q8oddPseudo_UPD:
2744 case ARM::VLD3q16oddPseudo_UPD:
2745 case ARM::VLD3q32oddPseudo_UPD:
2746 case ARM::VLD4d8Pseudo:
2747 case ARM::VLD4d16Pseudo:
2748 case ARM::VLD4d32Pseudo:
2749 case ARM::VLD1d64QPseudo:
2750 case ARM::VLD4d8Pseudo_UPD:
2751 case ARM::VLD4d16Pseudo_UPD:
2752 case ARM::VLD4d32Pseudo_UPD:
2753 case ARM::VLD4q8Pseudo_UPD:
2754 case ARM::VLD4q16Pseudo_UPD:
2755 case ARM::VLD4q32Pseudo_UPD:
2756 case ARM::VLD4q8oddPseudo:
2757 case ARM::VLD4q16oddPseudo:
2758 case ARM::VLD4q32oddPseudo:
2759 case ARM::VLD4q8oddPseudo_UPD:
2760 case ARM::VLD4q16oddPseudo_UPD:
2761 case ARM::VLD4q32oddPseudo_UPD:
2762 case ARM::VLD1DUPq8Pseudo:
2763 case ARM::VLD1DUPq16Pseudo:
2764 case ARM::VLD1DUPq32Pseudo:
2765 case ARM::VLD1DUPq8PseudoWB_fixed:
2766 case ARM::VLD1DUPq16PseudoWB_fixed:
2767 case ARM::VLD1DUPq32PseudoWB_fixed:
2768 case ARM::VLD1DUPq8PseudoWB_register:
2769 case ARM::VLD1DUPq16PseudoWB_register:
2770 case ARM::VLD1DUPq32PseudoWB_register:
2771 case ARM::VLD2DUPd8Pseudo:
2772 case ARM::VLD2DUPd16Pseudo:
2773 case ARM::VLD2DUPd32Pseudo:
2774 case ARM::VLD2DUPd8PseudoWB_fixed:
2775 case ARM::VLD2DUPd16PseudoWB_fixed:
2776 case ARM::VLD2DUPd32PseudoWB_fixed:
2777 case ARM::VLD2DUPd8PseudoWB_register:
2778 case ARM::VLD2DUPd16PseudoWB_register:
2779 case ARM::VLD2DUPd32PseudoWB_register:
2780 case ARM::VLD4DUPd8Pseudo:
2781 case ARM::VLD4DUPd16Pseudo:
2782 case ARM::VLD4DUPd32Pseudo:
2783 case ARM::VLD4DUPd8Pseudo_UPD:
2784 case ARM::VLD4DUPd16Pseudo_UPD:
2785 case ARM::VLD4DUPd32Pseudo_UPD:
2786 case ARM::VLD1LNq8Pseudo:
2787 case ARM::VLD1LNq16Pseudo:
2788 case ARM::VLD1LNq32Pseudo:
2789 case ARM::VLD1LNq8Pseudo_UPD:
2790 case ARM::VLD1LNq16Pseudo_UPD:
2791 case ARM::VLD1LNq32Pseudo_UPD:
2792 case ARM::VLD2LNd8Pseudo:
2793 case ARM::VLD2LNd16Pseudo:
2794 case ARM::VLD2LNd32Pseudo:
2795 case ARM::VLD2LNq16Pseudo:
2796 case ARM::VLD2LNq32Pseudo:
2797 case ARM::VLD2LNd8Pseudo_UPD:
2798 case ARM::VLD2LNd16Pseudo_UPD:
2799 case ARM::VLD2LNd32Pseudo_UPD:
2800 case ARM::VLD2LNq16Pseudo_UPD:
2801 case ARM::VLD2LNq32Pseudo_UPD:
2802 case ARM::VLD4LNd8Pseudo:
2803 case ARM::VLD4LNd16Pseudo:
2804 case ARM::VLD4LNd32Pseudo:
2805 case ARM::VLD4LNq16Pseudo:
2806 case ARM::VLD4LNq32Pseudo:
2807 case ARM::VLD4LNd8Pseudo_UPD:
2808 case ARM::VLD4LNd16Pseudo_UPD:
2809 case ARM::VLD4LNd32Pseudo_UPD:
2810 case ARM::VLD4LNq16Pseudo_UPD:
2811 case ARM::VLD4LNq32Pseudo_UPD:
2812 // If the address is not 64-bit aligned, the latencies of these
2813 // instructions increases by one.
2822 ARMBaseInstrInfo::getOutputLatency(const InstrItineraryData *ItinData,
2823 const MachineInstr *DefMI, unsigned DefIdx,
2824 const MachineInstr *DepMI) const {
2825 unsigned Reg = DefMI->getOperand(DefIdx).getReg();
2826 if (DepMI->readsRegister(Reg, &getRegisterInfo()) || !isPredicated(DepMI))
2829 // If the second MI is predicated, then there is an implicit use dependency.
2830 return getOperandLatency(ItinData, DefMI, DefIdx, DepMI,
2831 DepMI->getNumOperands());
2834 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2835 const MachineInstr *MI,
2836 unsigned *PredCost) const {
2837 if (MI->isCopyLike() || MI->isInsertSubreg() ||
2838 MI->isRegSequence() || MI->isImplicitDef())
2841 if (!ItinData || ItinData->isEmpty())
2844 if (MI->isBundle()) {
2846 MachineBasicBlock::const_instr_iterator I = MI;
2847 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2848 while (++I != E && I->isInsideBundle()) {
2849 if (I->getOpcode() != ARM::t2IT)
2850 Latency += getInstrLatency(ItinData, I, PredCost);
2855 const MCInstrDesc &MCID = MI->getDesc();
2856 unsigned Class = MCID.getSchedClass();
2857 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
2858 if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR))
2859 // When predicated, CPSR is an additional source operand for CPSR updating
2860 // instructions, this apparently increases their latencies.
2863 return ItinData->getStageLatency(Class);
2864 return getNumMicroOps(ItinData, MI);
2867 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2868 SDNode *Node) const {
2869 if (!Node->isMachineOpcode())
2872 if (!ItinData || ItinData->isEmpty())
2875 unsigned Opcode = Node->getMachineOpcode();
2878 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2885 bool ARMBaseInstrInfo::
2886 hasHighOperandLatency(const InstrItineraryData *ItinData,
2887 const MachineRegisterInfo *MRI,
2888 const MachineInstr *DefMI, unsigned DefIdx,
2889 const MachineInstr *UseMI, unsigned UseIdx) const {
2890 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2891 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
2892 if (Subtarget.isCortexA8() &&
2893 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
2894 // CortexA8 VFP instructions are not pipelined.
2897 // Hoist VFP / NEON instructions with 4 or higher latency.
2898 int Latency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
2901 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
2902 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
2905 bool ARMBaseInstrInfo::
2906 hasLowDefLatency(const InstrItineraryData *ItinData,
2907 const MachineInstr *DefMI, unsigned DefIdx) const {
2908 if (!ItinData || ItinData->isEmpty())
2911 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
2912 if (DDomain == ARMII::DomainGeneral) {
2913 unsigned DefClass = DefMI->getDesc().getSchedClass();
2914 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2915 return (DefCycle != -1 && DefCycle <= 2);
2920 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
2921 StringRef &ErrInfo) const {
2922 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
2923 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
2930 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
2931 unsigned &AddSubOpc,
2932 bool &NegAcc, bool &HasLane) const {
2933 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
2934 if (I == MLxEntryMap.end())
2937 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
2938 MulOpc = Entry.MulOpc;
2939 AddSubOpc = Entry.AddSubOpc;
2940 NegAcc = Entry.NegAcc;
2941 HasLane = Entry.HasLane;
2945 //===----------------------------------------------------------------------===//
2946 // Execution domains.
2947 //===----------------------------------------------------------------------===//
2949 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
2950 // and some can go down both. The vmov instructions go down the VFP pipeline,
2951 // but they can be changed to vorr equivalents that are executed by the NEON
2954 // We use the following execution domain numbering:
2962 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
2964 std::pair<uint16_t, uint16_t>
2965 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
2966 // VMOVD is a VFP instruction, but can be changed to NEON if it isn't
2968 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
2969 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
2971 // No other instructions can be swizzled, so just determine their domain.
2972 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
2974 if (Domain & ARMII::DomainNEON)
2975 return std::make_pair(ExeNEON, 0);
2977 // Certain instructions can go either way on Cortex-A8.
2978 // Treat them as NEON instructions.
2979 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
2980 return std::make_pair(ExeNEON, 0);
2982 if (Domain & ARMII::DomainVFP)
2983 return std::make_pair(ExeVFP, 0);
2985 return std::make_pair(ExeGeneric, 0);
2989 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
2990 // We only know how to change VMOVD into VORR.
2991 assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD");
2992 if (Domain != ExeNEON)
2995 // Zap the predicate operands.
2996 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
2997 MI->RemoveOperand(3);
2998 MI->RemoveOperand(2);
3000 // Change to a VORRd which requires two identical use operands.
3001 MI->setDesc(get(ARM::VORRd));
3003 // Add the extra source operand and new predicates.
3004 // This will go before any implicit ops.
3005 AddDefaultPred(MachineInstrBuilder(MI).addOperand(MI->getOperand(1)));