1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Support/BranchProbability.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
40 #define GET_INSTRINFO_CTOR
41 #include "ARMGenInstrInfo.inc"
46 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
47 cl::desc("Enable ARM 2-addr to 3-addr conv"));
50 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
51 cl::desc("Widen ARM vmovs to vmovd when possible"));
53 static cl::opt<unsigned>
54 SwiftPartialUpdateClearance("swift-partial-update-clearance",
55 cl::Hidden, cl::init(12),
56 cl::desc("Clearance before partial register updates"));
58 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
60 uint16_t MLxOpc; // MLA / MLS opcode
61 uint16_t MulOpc; // Expanded multiplication opcode
62 uint16_t AddSubOpc; // Expanded add / sub opcode
63 bool NegAcc; // True if the acc is negated before the add / sub.
64 bool HasLane; // True if instruction has an extra "lane" operand.
67 static const ARM_MLxEntry ARM_MLxTable[] = {
68 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
70 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
71 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
72 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
73 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
74 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
75 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
76 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
77 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
80 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
81 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
82 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
83 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
84 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
85 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
86 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
87 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
90 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
91 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
93 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
94 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
95 assert(false && "Duplicated entries?");
96 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
97 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
101 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
102 // currently defaults to no prepass hazard recognizer.
103 ScheduleHazardRecognizer *ARMBaseInstrInfo::
104 CreateTargetHazardRecognizer(const TargetMachine *TM,
105 const ScheduleDAG *DAG) const {
106 if (usePreRAHazardRecognizer()) {
107 const InstrItineraryData *II = TM->getInstrItineraryData();
108 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
110 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
113 ScheduleHazardRecognizer *ARMBaseInstrInfo::
114 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
115 const ScheduleDAG *DAG) const {
116 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
117 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
118 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
122 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
123 MachineBasicBlock::iterator &MBBI,
124 LiveVariables *LV) const {
125 // FIXME: Thumb2 support.
130 MachineInstr *MI = MBBI;
131 MachineFunction &MF = *MI->getParent()->getParent();
132 uint64_t TSFlags = MI->getDesc().TSFlags;
134 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
135 default: return NULL;
136 case ARMII::IndexModePre:
139 case ARMII::IndexModePost:
143 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
145 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
149 MachineInstr *UpdateMI = NULL;
150 MachineInstr *MemMI = NULL;
151 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
152 const MCInstrDesc &MCID = MI->getDesc();
153 unsigned NumOps = MCID.getNumOperands();
154 bool isLoad = !MI->mayStore();
155 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
156 const MachineOperand &Base = MI->getOperand(2);
157 const MachineOperand &Offset = MI->getOperand(NumOps-3);
158 unsigned WBReg = WB.getReg();
159 unsigned BaseReg = Base.getReg();
160 unsigned OffReg = Offset.getReg();
161 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
162 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
164 default: llvm_unreachable("Unknown indexed op!");
165 case ARMII::AddrMode2: {
166 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
167 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
169 if (ARM_AM::getSOImmVal(Amt) == -1)
170 // Can't encode it in a so_imm operand. This transformation will
171 // add more than 1 instruction. Abandon!
173 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
174 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
175 .addReg(BaseReg).addImm(Amt)
176 .addImm(Pred).addReg(0).addReg(0);
177 } else if (Amt != 0) {
178 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
179 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
180 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
181 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
183 .addImm(Pred).addReg(0).addReg(0);
185 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
186 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
187 .addReg(BaseReg).addReg(OffReg)
188 .addImm(Pred).addReg(0).addReg(0);
191 case ARMII::AddrMode3 : {
192 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
193 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
195 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
196 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
197 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
198 .addReg(BaseReg).addImm(Amt)
199 .addImm(Pred).addReg(0).addReg(0);
201 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
202 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
203 .addReg(BaseReg).addReg(OffReg)
204 .addImm(Pred).addReg(0).addReg(0);
209 std::vector<MachineInstr*> NewMIs;
212 MemMI = BuildMI(MF, MI->getDebugLoc(),
213 get(MemOpc), MI->getOperand(0).getReg())
214 .addReg(WBReg).addImm(0).addImm(Pred);
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc)).addReg(MI->getOperand(1).getReg())
218 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
219 NewMIs.push_back(MemMI);
220 NewMIs.push_back(UpdateMI);
223 MemMI = BuildMI(MF, MI->getDebugLoc(),
224 get(MemOpc), MI->getOperand(0).getReg())
225 .addReg(BaseReg).addImm(0).addImm(Pred);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc)).addReg(MI->getOperand(1).getReg())
229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
231 UpdateMI->getOperand(0).setIsDead();
232 NewMIs.push_back(UpdateMI);
233 NewMIs.push_back(MemMI);
236 // Transfer LiveVariables states, kill / dead info.
238 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
239 MachineOperand &MO = MI->getOperand(i);
240 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
241 unsigned Reg = MO.getReg();
243 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
245 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
247 LV->addVirtualRegisterDead(Reg, NewMI);
249 if (MO.isUse() && MO.isKill()) {
250 for (unsigned j = 0; j < 2; ++j) {
251 // Look at the two new MI's in reverse order.
252 MachineInstr *NewMI = NewMIs[j];
253 if (!NewMI->readsRegister(Reg))
255 LV->addVirtualRegisterKilled(Reg, NewMI);
256 if (VI.removeKill(MI))
257 VI.Kills.push_back(NewMI);
265 MFI->insert(MBBI, NewMIs[1]);
266 MFI->insert(MBBI, NewMIs[0]);
272 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
273 MachineBasicBlock *&FBB,
274 SmallVectorImpl<MachineOperand> &Cond,
275 bool AllowModify) const {
279 MachineBasicBlock::iterator I = MBB.end();
280 if (I == MBB.begin())
281 return false; // Empty blocks are easy.
284 // Walk backwards from the end of the basic block until the branch is
285 // analyzed or we give up.
286 while (isPredicated(I) || I->isTerminator()) {
288 // Flag to be raised on unanalyzeable instructions. This is useful in cases
289 // where we want to clean up on the end of the basic block before we bail
291 bool CantAnalyze = false;
293 // Skip over DEBUG values and predicated nonterminators.
294 while (I->isDebugValue() || !I->isTerminator()) {
295 if (I == MBB.begin())
300 if (isIndirectBranchOpcode(I->getOpcode()) ||
301 isJumpTableBranchOpcode(I->getOpcode())) {
302 // Indirect branches and jump tables can't be analyzed, but we still want
303 // to clean up any instructions at the tail of the basic block.
305 } else if (isUncondBranchOpcode(I->getOpcode())) {
306 TBB = I->getOperand(0).getMBB();
307 } else if (isCondBranchOpcode(I->getOpcode())) {
308 // Bail out if we encounter multiple conditional branches.
312 assert(!FBB && "FBB should have been null.");
314 TBB = I->getOperand(0).getMBB();
315 Cond.push_back(I->getOperand(1));
316 Cond.push_back(I->getOperand(2));
317 } else if (I->isReturn()) {
318 // Returns can't be analyzed, but we should run cleanup.
319 CantAnalyze = !isPredicated(I);
321 // We encountered other unrecognized terminator. Bail out immediately.
325 // Cleanup code - to be run for unpredicated unconditional branches and
327 if (!isPredicated(I) &&
328 (isUncondBranchOpcode(I->getOpcode()) ||
329 isIndirectBranchOpcode(I->getOpcode()) ||
330 isJumpTableBranchOpcode(I->getOpcode()) ||
332 // Forget any previous condition branch information - it no longer applies.
336 // If we can modify the function, delete everything below this
337 // unconditional branch.
339 MachineBasicBlock::iterator DI = llvm::next(I);
340 while (DI != MBB.end()) {
341 MachineInstr *InstToDelete = DI;
343 InstToDelete->eraseFromParent();
351 if (I == MBB.begin())
357 // We made it past the terminators without bailing out - we must have
358 // analyzed this branch successfully.
363 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
364 MachineBasicBlock::iterator I = MBB.end();
365 if (I == MBB.begin()) return 0;
367 while (I->isDebugValue()) {
368 if (I == MBB.begin())
372 if (!isUncondBranchOpcode(I->getOpcode()) &&
373 !isCondBranchOpcode(I->getOpcode()))
376 // Remove the branch.
377 I->eraseFromParent();
381 if (I == MBB.begin()) return 1;
383 if (!isCondBranchOpcode(I->getOpcode()))
386 // Remove the branch.
387 I->eraseFromParent();
392 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
393 MachineBasicBlock *FBB,
394 const SmallVectorImpl<MachineOperand> &Cond,
396 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
397 int BOpc = !AFI->isThumbFunction()
398 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
399 int BccOpc = !AFI->isThumbFunction()
400 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
401 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
403 // Shouldn't be a fall through.
404 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
405 assert((Cond.size() == 2 || Cond.size() == 0) &&
406 "ARM branch conditions have two components!");
409 if (Cond.empty()) { // Unconditional branch?
411 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
413 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
415 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
416 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
420 // Two-way conditional branch.
421 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
422 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
424 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
426 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
430 bool ARMBaseInstrInfo::
431 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
432 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
433 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
437 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
438 if (MI->isBundle()) {
439 MachineBasicBlock::const_instr_iterator I = MI;
440 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
441 while (++I != E && I->isInsideBundle()) {
442 int PIdx = I->findFirstPredOperandIdx();
443 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
449 int PIdx = MI->findFirstPredOperandIdx();
450 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
453 bool ARMBaseInstrInfo::
454 PredicateInstruction(MachineInstr *MI,
455 const SmallVectorImpl<MachineOperand> &Pred) const {
456 unsigned Opc = MI->getOpcode();
457 if (isUncondBranchOpcode(Opc)) {
458 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
459 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
460 .addImm(Pred[0].getImm())
461 .addReg(Pred[1].getReg());
465 int PIdx = MI->findFirstPredOperandIdx();
467 MachineOperand &PMO = MI->getOperand(PIdx);
468 PMO.setImm(Pred[0].getImm());
469 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
475 bool ARMBaseInstrInfo::
476 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
477 const SmallVectorImpl<MachineOperand> &Pred2) const {
478 if (Pred1.size() > 2 || Pred2.size() > 2)
481 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
482 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
492 return CC2 == ARMCC::HI;
494 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
496 return CC2 == ARMCC::GT;
498 return CC2 == ARMCC::LT;
502 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
503 std::vector<MachineOperand> &Pred) const {
505 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
506 const MachineOperand &MO = MI->getOperand(i);
507 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
508 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
517 /// isPredicable - Return true if the specified instruction can be predicated.
518 /// By default, this returns true for every instruction with a
519 /// PredicateOperand.
520 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
521 if (!MI->isPredicable())
524 ARMFunctionInfo *AFI =
525 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
527 if (AFI->isThumb2Function()) {
528 if (getSubtarget().hasV8Ops())
529 return isV8EligibleForIT(MI);
530 } else { // non-Thumb
531 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
538 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
539 LLVM_ATTRIBUTE_NOINLINE
540 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
542 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
544 assert(JTI < JT.size());
545 return JT[JTI].MBBs.size();
548 /// GetInstSize - Return the size of the specified MachineInstr.
550 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
551 const MachineBasicBlock &MBB = *MI->getParent();
552 const MachineFunction *MF = MBB.getParent();
553 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
555 const MCInstrDesc &MCID = MI->getDesc();
557 return MCID.getSize();
559 // If this machine instr is an inline asm, measure it.
560 if (MI->getOpcode() == ARM::INLINEASM)
561 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
564 unsigned Opc = MI->getOpcode();
566 case TargetOpcode::IMPLICIT_DEF:
567 case TargetOpcode::KILL:
568 case TargetOpcode::PROLOG_LABEL:
569 case TargetOpcode::EH_LABEL:
570 case TargetOpcode::DBG_VALUE:
572 case TargetOpcode::BUNDLE:
573 return getInstBundleLength(MI);
574 case ARM::MOVi16_ga_pcrel:
575 case ARM::MOVTi16_ga_pcrel:
576 case ARM::t2MOVi16_ga_pcrel:
577 case ARM::t2MOVTi16_ga_pcrel:
580 case ARM::t2MOVi32imm:
582 case ARM::CONSTPOOL_ENTRY:
583 // If this machine instr is a constant pool entry, its size is recorded as
585 return MI->getOperand(2).getImm();
586 case ARM::Int_eh_sjlj_longjmp:
588 case ARM::tInt_eh_sjlj_longjmp:
590 case ARM::Int_eh_sjlj_setjmp:
591 case ARM::Int_eh_sjlj_setjmp_nofp:
593 case ARM::tInt_eh_sjlj_setjmp:
594 case ARM::t2Int_eh_sjlj_setjmp:
595 case ARM::t2Int_eh_sjlj_setjmp_nofp:
603 case ARM::t2TBH_JT: {
604 // These are jumptable branches, i.e. a branch followed by an inlined
605 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
606 // entry is one byte; TBH two byte each.
607 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
608 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
609 unsigned NumOps = MCID.getNumOperands();
610 MachineOperand JTOP =
611 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
612 unsigned JTI = JTOP.getIndex();
613 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
615 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
616 assert(JTI < JT.size());
617 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
618 // 4 aligned. The assembler / linker may add 2 byte padding just before
619 // the JT entries. The size does not include this padding; the
620 // constant islands pass does separate bookkeeping for it.
621 // FIXME: If we know the size of the function is less than (1 << 16) *2
622 // bytes, we can use 16-bit entries instead. Then there won't be an
624 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
625 unsigned NumEntries = getNumJTEntries(JT, JTI);
626 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
627 // Make sure the instruction that follows TBB is 2-byte aligned.
628 // FIXME: Constant island pass should insert an "ALIGN" instruction
631 return NumEntries * EntrySize + InstSize;
634 // Otherwise, pseudo-instruction sizes are zero.
639 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
641 MachineBasicBlock::const_instr_iterator I = MI;
642 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
643 while (++I != E && I->isInsideBundle()) {
644 assert(!I->isBundle() && "No nested bundle!");
645 Size += GetInstSizeInBytes(&*I);
650 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator I, DebugLoc DL,
652 unsigned DestReg, unsigned SrcReg,
653 bool KillSrc) const {
654 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
655 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
657 if (GPRDest && GPRSrc) {
658 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
659 .addReg(SrcReg, getKillRegState(KillSrc))));
663 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
664 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
667 if (SPRDest && SPRSrc)
669 else if (GPRDest && SPRSrc)
671 else if (SPRDest && GPRSrc)
673 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
675 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
679 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
680 MIB.addReg(SrcReg, getKillRegState(KillSrc));
681 if (Opc == ARM::VORRq)
682 MIB.addReg(SrcReg, getKillRegState(KillSrc));
687 // Handle register classes that require multiple instructions.
688 unsigned BeginIdx = 0;
689 unsigned SubRegs = 0;
692 // Use VORRq when possible.
693 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
694 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 2;
695 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
696 Opc = ARM::VORRq, BeginIdx = ARM::qsub_0, SubRegs = 4;
697 // Fall back to VMOVD.
698 else if (ARM::DPairRegClass.contains(DestReg, SrcReg))
699 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2;
700 else if (ARM::DTripleRegClass.contains(DestReg, SrcReg))
701 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3;
702 else if (ARM::DQuadRegClass.contains(DestReg, SrcReg))
703 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4;
704 else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg))
705 Opc = ARM::MOVr, BeginIdx = ARM::gsub_0, SubRegs = 2;
707 else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg))
708 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 2, Spacing = 2;
709 else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg))
710 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 3, Spacing = 2;
711 else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
712 Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
714 assert(Opc && "Impossible reg-to-reg copy");
716 const TargetRegisterInfo *TRI = &getRegisterInfo();
717 MachineInstrBuilder Mov;
719 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
720 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
721 BeginIdx = BeginIdx + ((SubRegs-1)*Spacing);
725 SmallSet<unsigned, 4> DstRegs;
727 for (unsigned i = 0; i != SubRegs; ++i) {
728 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
729 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
730 assert(Dst && Src && "Bad sub-register");
732 assert(!DstRegs.count(Src) && "destructive vector copy");
735 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
737 // VORR takes two source operands.
738 if (Opc == ARM::VORRq)
740 Mov = AddDefaultPred(Mov);
742 if (Opc == ARM::MOVr)
743 Mov = AddDefaultCC(Mov);
745 // Add implicit super-register defs and kills to the last instruction.
746 Mov->addRegisterDefined(DestReg, TRI);
748 Mov->addRegisterKilled(SrcReg, TRI);
751 const MachineInstrBuilder &
752 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
753 unsigned SubIdx, unsigned State,
754 const TargetRegisterInfo *TRI) const {
756 return MIB.addReg(Reg, State);
758 if (TargetRegisterInfo::isPhysicalRegister(Reg))
759 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
760 return MIB.addReg(Reg, State, SubIdx);
763 void ARMBaseInstrInfo::
764 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
765 unsigned SrcReg, bool isKill, int FI,
766 const TargetRegisterClass *RC,
767 const TargetRegisterInfo *TRI) const {
769 if (I != MBB.end()) DL = I->getDebugLoc();
770 MachineFunction &MF = *MBB.getParent();
771 MachineFrameInfo &MFI = *MF.getFrameInfo();
772 unsigned Align = MFI.getObjectAlignment(FI);
774 MachineMemOperand *MMO =
775 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
776 MachineMemOperand::MOStore,
777 MFI.getObjectSize(FI),
780 switch (RC->getSize()) {
782 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
783 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
784 .addReg(SrcReg, getKillRegState(isKill))
785 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
786 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
787 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
788 .addReg(SrcReg, getKillRegState(isKill))
789 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
791 llvm_unreachable("Unknown reg class!");
794 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
795 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
796 .addReg(SrcReg, getKillRegState(isKill))
797 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
798 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
799 if (Subtarget.hasV5TEOps()) {
800 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
801 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
802 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
803 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
807 // Fallback to STM instruction, which has existed since the dawn of
809 MachineInstrBuilder MIB =
810 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
811 .addFrameIndex(FI).addMemOperand(MMO));
812 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
813 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
816 llvm_unreachable("Unknown reg class!");
819 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
820 // Use aligned spills if the stack can be realigned.
821 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
822 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
823 .addFrameIndex(FI).addImm(16)
824 .addReg(SrcReg, getKillRegState(isKill))
825 .addMemOperand(MMO));
827 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
828 .addReg(SrcReg, getKillRegState(isKill))
830 .addMemOperand(MMO));
833 llvm_unreachable("Unknown reg class!");
836 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
837 // Use aligned spills if the stack can be realigned.
838 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
839 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
840 .addFrameIndex(FI).addImm(16)
841 .addReg(SrcReg, getKillRegState(isKill))
842 .addMemOperand(MMO));
844 MachineInstrBuilder MIB =
845 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
848 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
849 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
850 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
853 llvm_unreachable("Unknown reg class!");
856 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
857 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
858 // FIXME: It's possible to only store part of the QQ register if the
859 // spilled def has a sub-register index.
860 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
861 .addFrameIndex(FI).addImm(16)
862 .addReg(SrcReg, getKillRegState(isKill))
863 .addMemOperand(MMO));
865 MachineInstrBuilder MIB =
866 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
869 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
870 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
871 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
872 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
875 llvm_unreachable("Unknown reg class!");
878 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
879 MachineInstrBuilder MIB =
880 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
883 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
884 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
885 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
886 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
887 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
888 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
889 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
890 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
892 llvm_unreachable("Unknown reg class!");
895 llvm_unreachable("Unknown reg class!");
900 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
901 int &FrameIndex) const {
902 switch (MI->getOpcode()) {
905 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
906 if (MI->getOperand(1).isFI() &&
907 MI->getOperand(2).isReg() &&
908 MI->getOperand(3).isImm() &&
909 MI->getOperand(2).getReg() == 0 &&
910 MI->getOperand(3).getImm() == 0) {
911 FrameIndex = MI->getOperand(1).getIndex();
912 return MI->getOperand(0).getReg();
920 if (MI->getOperand(1).isFI() &&
921 MI->getOperand(2).isImm() &&
922 MI->getOperand(2).getImm() == 0) {
923 FrameIndex = MI->getOperand(1).getIndex();
924 return MI->getOperand(0).getReg();
928 case ARM::VST1d64TPseudo:
929 case ARM::VST1d64QPseudo:
930 if (MI->getOperand(0).isFI() &&
931 MI->getOperand(2).getSubReg() == 0) {
932 FrameIndex = MI->getOperand(0).getIndex();
933 return MI->getOperand(2).getReg();
937 if (MI->getOperand(1).isFI() &&
938 MI->getOperand(0).getSubReg() == 0) {
939 FrameIndex = MI->getOperand(1).getIndex();
940 return MI->getOperand(0).getReg();
948 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
949 int &FrameIndex) const {
950 const MachineMemOperand *Dummy;
951 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
954 void ARMBaseInstrInfo::
955 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
956 unsigned DestReg, int FI,
957 const TargetRegisterClass *RC,
958 const TargetRegisterInfo *TRI) const {
960 if (I != MBB.end()) DL = I->getDebugLoc();
961 MachineFunction &MF = *MBB.getParent();
962 MachineFrameInfo &MFI = *MF.getFrameInfo();
963 unsigned Align = MFI.getObjectAlignment(FI);
964 MachineMemOperand *MMO =
965 MF.getMachineMemOperand(
966 MachinePointerInfo::getFixedStack(FI),
967 MachineMemOperand::MOLoad,
968 MFI.getObjectSize(FI),
971 switch (RC->getSize()) {
973 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
974 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
975 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
977 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
978 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
979 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
981 llvm_unreachable("Unknown reg class!");
984 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
985 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
986 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
987 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
988 MachineInstrBuilder MIB;
990 if (Subtarget.hasV5TEOps()) {
991 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
992 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
993 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
994 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
998 // Fallback to LDM instruction, which has existed since the dawn of
1000 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1001 .addFrameIndex(FI).addMemOperand(MMO));
1002 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1003 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1006 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1007 MIB.addReg(DestReg, RegState::ImplicitDefine);
1009 llvm_unreachable("Unknown reg class!");
1012 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1013 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1014 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1015 .addFrameIndex(FI).addImm(16)
1016 .addMemOperand(MMO));
1018 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1020 .addMemOperand(MMO));
1023 llvm_unreachable("Unknown reg class!");
1026 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1027 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1028 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1029 .addFrameIndex(FI).addImm(16)
1030 .addMemOperand(MMO));
1032 MachineInstrBuilder MIB =
1033 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1035 .addMemOperand(MMO));
1036 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1037 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1038 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1039 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1040 MIB.addReg(DestReg, RegState::ImplicitDefine);
1043 llvm_unreachable("Unknown reg class!");
1046 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1047 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1048 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1049 .addFrameIndex(FI).addImm(16)
1050 .addMemOperand(MMO));
1052 MachineInstrBuilder MIB =
1053 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1055 .addMemOperand(MMO);
1056 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1057 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1058 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1059 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1060 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1061 MIB.addReg(DestReg, RegState::ImplicitDefine);
1064 llvm_unreachable("Unknown reg class!");
1067 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1068 MachineInstrBuilder MIB =
1069 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1071 .addMemOperand(MMO);
1072 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1073 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1074 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1075 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1076 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1077 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1078 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1079 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1080 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1081 MIB.addReg(DestReg, RegState::ImplicitDefine);
1083 llvm_unreachable("Unknown reg class!");
1086 llvm_unreachable("Unknown regclass!");
1091 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1092 int &FrameIndex) const {
1093 switch (MI->getOpcode()) {
1096 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1097 if (MI->getOperand(1).isFI() &&
1098 MI->getOperand(2).isReg() &&
1099 MI->getOperand(3).isImm() &&
1100 MI->getOperand(2).getReg() == 0 &&
1101 MI->getOperand(3).getImm() == 0) {
1102 FrameIndex = MI->getOperand(1).getIndex();
1103 return MI->getOperand(0).getReg();
1111 if (MI->getOperand(1).isFI() &&
1112 MI->getOperand(2).isImm() &&
1113 MI->getOperand(2).getImm() == 0) {
1114 FrameIndex = MI->getOperand(1).getIndex();
1115 return MI->getOperand(0).getReg();
1119 case ARM::VLD1d64TPseudo:
1120 case ARM::VLD1d64QPseudo:
1121 if (MI->getOperand(1).isFI() &&
1122 MI->getOperand(0).getSubReg() == 0) {
1123 FrameIndex = MI->getOperand(1).getIndex();
1124 return MI->getOperand(0).getReg();
1128 if (MI->getOperand(1).isFI() &&
1129 MI->getOperand(0).getSubReg() == 0) {
1130 FrameIndex = MI->getOperand(1).getIndex();
1131 return MI->getOperand(0).getReg();
1139 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1140 int &FrameIndex) const {
1141 const MachineMemOperand *Dummy;
1142 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1145 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const{
1146 // This hook gets to expand COPY instructions before they become
1147 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1148 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1149 // changed into a VORR that can go down the NEON pipeline.
1150 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1153 // Look for a copy between even S-registers. That is where we keep floats
1154 // when using NEON v2f32 instructions for f32 arithmetic.
1155 unsigned DstRegS = MI->getOperand(0).getReg();
1156 unsigned SrcRegS = MI->getOperand(1).getReg();
1157 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1160 const TargetRegisterInfo *TRI = &getRegisterInfo();
1161 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1163 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1165 if (!DstRegD || !SrcRegD)
1168 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1169 // legal if the COPY already defines the full DstRegD, and it isn't a
1170 // sub-register insertion.
1171 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1174 // A dead copy shouldn't show up here, but reject it just in case.
1175 if (MI->getOperand(0).isDead())
1178 // All clear, widen the COPY.
1179 DEBUG(dbgs() << "widening: " << *MI);
1180 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1182 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1183 // or some other super-register.
1184 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1185 if (ImpDefIdx != -1)
1186 MI->RemoveOperand(ImpDefIdx);
1188 // Change the opcode and operands.
1189 MI->setDesc(get(ARM::VMOVD));
1190 MI->getOperand(0).setReg(DstRegD);
1191 MI->getOperand(1).setReg(SrcRegD);
1192 AddDefaultPred(MIB);
1194 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1195 // register scavenger and machine verifier, so we need to indicate that we
1196 // are reading an undefined value from SrcRegD, but a proper value from
1198 MI->getOperand(1).setIsUndef();
1199 MIB.addReg(SrcRegS, RegState::Implicit);
1201 // SrcRegD may actually contain an unrelated value in the ssub_1
1202 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1203 if (MI->getOperand(1).isKill()) {
1204 MI->getOperand(1).setIsKill(false);
1205 MI->addRegisterKilled(SrcRegS, TRI, true);
1208 DEBUG(dbgs() << "replaced by: " << *MI);
1212 /// Create a copy of a const pool value. Update CPI to the new index and return
1214 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1215 MachineConstantPool *MCP = MF.getConstantPool();
1216 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1218 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1219 assert(MCPE.isMachineConstantPoolEntry() &&
1220 "Expecting a machine constantpool entry!");
1221 ARMConstantPoolValue *ACPV =
1222 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1224 unsigned PCLabelId = AFI->createPICLabelUId();
1225 ARMConstantPoolValue *NewCPV = 0;
1226 // FIXME: The below assumes PIC relocation model and that the function
1227 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1228 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1229 // instructions, so that's probably OK, but is PIC always correct when
1231 if (ACPV->isGlobalValue())
1232 NewCPV = ARMConstantPoolConstant::
1233 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1235 else if (ACPV->isExtSymbol())
1236 NewCPV = ARMConstantPoolSymbol::
1237 Create(MF.getFunction()->getContext(),
1238 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1239 else if (ACPV->isBlockAddress())
1240 NewCPV = ARMConstantPoolConstant::
1241 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1242 ARMCP::CPBlockAddress, 4);
1243 else if (ACPV->isLSDA())
1244 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1246 else if (ACPV->isMachineBasicBlock())
1247 NewCPV = ARMConstantPoolMBB::
1248 Create(MF.getFunction()->getContext(),
1249 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1251 llvm_unreachable("Unexpected ARM constantpool value type!!");
1252 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1256 void ARMBaseInstrInfo::
1257 reMaterialize(MachineBasicBlock &MBB,
1258 MachineBasicBlock::iterator I,
1259 unsigned DestReg, unsigned SubIdx,
1260 const MachineInstr *Orig,
1261 const TargetRegisterInfo &TRI) const {
1262 unsigned Opcode = Orig->getOpcode();
1265 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1266 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1270 case ARM::tLDRpci_pic:
1271 case ARM::t2LDRpci_pic: {
1272 MachineFunction &MF = *MBB.getParent();
1273 unsigned CPI = Orig->getOperand(1).getIndex();
1274 unsigned PCLabelId = duplicateCPV(MF, CPI);
1275 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1277 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1278 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1285 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1286 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1287 switch(Orig->getOpcode()) {
1288 case ARM::tLDRpci_pic:
1289 case ARM::t2LDRpci_pic: {
1290 unsigned CPI = Orig->getOperand(1).getIndex();
1291 unsigned PCLabelId = duplicateCPV(MF, CPI);
1292 Orig->getOperand(1).setIndex(CPI);
1293 Orig->getOperand(2).setImm(PCLabelId);
1300 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1301 const MachineInstr *MI1,
1302 const MachineRegisterInfo *MRI) const {
1303 int Opcode = MI0->getOpcode();
1304 if (Opcode == ARM::t2LDRpci ||
1305 Opcode == ARM::t2LDRpci_pic ||
1306 Opcode == ARM::tLDRpci ||
1307 Opcode == ARM::tLDRpci_pic ||
1308 Opcode == ARM::MOV_ga_dyn ||
1309 Opcode == ARM::MOV_ga_pcrel ||
1310 Opcode == ARM::MOV_ga_pcrel_ldr ||
1311 Opcode == ARM::t2MOV_ga_dyn ||
1312 Opcode == ARM::t2MOV_ga_pcrel) {
1313 if (MI1->getOpcode() != Opcode)
1315 if (MI0->getNumOperands() != MI1->getNumOperands())
1318 const MachineOperand &MO0 = MI0->getOperand(1);
1319 const MachineOperand &MO1 = MI1->getOperand(1);
1320 if (MO0.getOffset() != MO1.getOffset())
1323 if (Opcode == ARM::MOV_ga_dyn ||
1324 Opcode == ARM::MOV_ga_pcrel ||
1325 Opcode == ARM::MOV_ga_pcrel_ldr ||
1326 Opcode == ARM::t2MOV_ga_dyn ||
1327 Opcode == ARM::t2MOV_ga_pcrel)
1328 // Ignore the PC labels.
1329 return MO0.getGlobal() == MO1.getGlobal();
1331 const MachineFunction *MF = MI0->getParent()->getParent();
1332 const MachineConstantPool *MCP = MF->getConstantPool();
1333 int CPI0 = MO0.getIndex();
1334 int CPI1 = MO1.getIndex();
1335 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1336 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1337 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1338 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1339 if (isARMCP0 && isARMCP1) {
1340 ARMConstantPoolValue *ACPV0 =
1341 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1342 ARMConstantPoolValue *ACPV1 =
1343 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1344 return ACPV0->hasSameValue(ACPV1);
1345 } else if (!isARMCP0 && !isARMCP1) {
1346 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1349 } else if (Opcode == ARM::PICLDR) {
1350 if (MI1->getOpcode() != Opcode)
1352 if (MI0->getNumOperands() != MI1->getNumOperands())
1355 unsigned Addr0 = MI0->getOperand(1).getReg();
1356 unsigned Addr1 = MI1->getOperand(1).getReg();
1357 if (Addr0 != Addr1) {
1359 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1360 !TargetRegisterInfo::isVirtualRegister(Addr1))
1363 // This assumes SSA form.
1364 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1365 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1366 // Check if the loaded value, e.g. a constantpool of a global address, are
1368 if (!produceSameValue(Def0, Def1, MRI))
1372 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1373 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1374 const MachineOperand &MO0 = MI0->getOperand(i);
1375 const MachineOperand &MO1 = MI1->getOperand(i);
1376 if (!MO0.isIdenticalTo(MO1))
1382 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1385 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1386 /// determine if two loads are loading from the same base address. It should
1387 /// only return true if the base pointers are the same and the only differences
1388 /// between the two addresses is the offset. It also returns the offsets by
1391 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1392 /// is permanently disabled.
1393 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1395 int64_t &Offset2) const {
1396 // Don't worry about Thumb: just ARM and Thumb2.
1397 if (Subtarget.isThumb1Only()) return false;
1399 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1402 switch (Load1->getMachineOpcode()) {
1416 case ARM::t2LDRSHi8:
1418 case ARM::t2LDRBi12:
1419 case ARM::t2LDRSHi12:
1423 switch (Load2->getMachineOpcode()) {
1436 case ARM::t2LDRSHi8:
1438 case ARM::t2LDRBi12:
1439 case ARM::t2LDRSHi12:
1443 // Check if base addresses and chain operands match.
1444 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1445 Load1->getOperand(4) != Load2->getOperand(4))
1448 // Index should be Reg0.
1449 if (Load1->getOperand(3) != Load2->getOperand(3))
1452 // Determine the offsets.
1453 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1454 isa<ConstantSDNode>(Load2->getOperand(1))) {
1455 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1456 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1463 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1464 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1465 /// be scheduled togther. On some targets if two loads are loading from
1466 /// addresses in the same cache line, it's better if they are scheduled
1467 /// together. This function takes two integers that represent the load offsets
1468 /// from the common base address. It returns true if it decides it's desirable
1469 /// to schedule the two loads together. "NumLoads" is the number of loads that
1470 /// have already been scheduled after Load1.
1472 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1473 /// is permanently disabled.
1474 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1475 int64_t Offset1, int64_t Offset2,
1476 unsigned NumLoads) const {
1477 // Don't worry about Thumb: just ARM and Thumb2.
1478 if (Subtarget.isThumb1Only()) return false;
1480 assert(Offset2 > Offset1);
1482 if ((Offset2 - Offset1) / 8 > 64)
1485 // Check if the machine opcodes are different. If they are different
1486 // then we consider them to not be of the same base address,
1487 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1488 // In this case, they are considered to be the same because they are different
1489 // encoding forms of the same basic instruction.
1490 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1491 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1492 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1493 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1494 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1495 return false; // FIXME: overly conservative?
1497 // Four loads in a row should be sufficient.
1504 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1505 const MachineBasicBlock *MBB,
1506 const MachineFunction &MF) const {
1507 // Debug info is never a scheduling boundary. It's necessary to be explicit
1508 // due to the special treatment of IT instructions below, otherwise a
1509 // dbg_value followed by an IT will result in the IT instruction being
1510 // considered a scheduling hazard, which is wrong. It should be the actual
1511 // instruction preceding the dbg_value instruction(s), just like it is
1512 // when debug info is not present.
1513 if (MI->isDebugValue())
1516 // Terminators and labels can't be scheduled around.
1517 if (MI->isTerminator() || MI->isLabel())
1520 // Treat the start of the IT block as a scheduling boundary, but schedule
1521 // t2IT along with all instructions following it.
1522 // FIXME: This is a big hammer. But the alternative is to add all potential
1523 // true and anti dependencies to IT block instructions as implicit operands
1524 // to the t2IT instruction. The added compile time and complexity does not
1526 MachineBasicBlock::const_iterator I = MI;
1527 // Make sure to skip any dbg_value instructions
1528 while (++I != MBB->end() && I->isDebugValue())
1530 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1533 // Don't attempt to schedule around any instruction that defines
1534 // a stack-oriented pointer, as it's unlikely to be profitable. This
1535 // saves compile time, because it doesn't require every single
1536 // stack slot reference to depend on the instruction that does the
1538 // Calls don't actually change the stack pointer, even if they have imp-defs.
1539 // No ARM calling conventions change the stack pointer. (X86 calling
1540 // conventions sometimes do).
1541 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1547 bool ARMBaseInstrInfo::
1548 isProfitableToIfCvt(MachineBasicBlock &MBB,
1549 unsigned NumCycles, unsigned ExtraPredCycles,
1550 const BranchProbability &Probability) const {
1554 // Attempt to estimate the relative costs of predication versus branching.
1555 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1556 UnpredCost /= Probability.getDenominator();
1557 UnpredCost += 1; // The branch itself
1558 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1560 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1563 bool ARMBaseInstrInfo::
1564 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1565 unsigned TCycles, unsigned TExtra,
1566 MachineBasicBlock &FMBB,
1567 unsigned FCycles, unsigned FExtra,
1568 const BranchProbability &Probability) const {
1569 if (!TCycles || !FCycles)
1572 // Attempt to estimate the relative costs of predication versus branching.
1573 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1574 TUnpredCost /= Probability.getDenominator();
1576 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1577 unsigned FUnpredCost = Comp * FCycles;
1578 FUnpredCost /= Probability.getDenominator();
1580 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1581 UnpredCost += 1; // The branch itself
1582 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1584 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1588 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1589 MachineBasicBlock &FMBB) const {
1590 // Reduce false anti-dependencies to let Swift's out-of-order execution
1591 // engine do its thing.
1592 return Subtarget.isSwift();
1595 /// getInstrPredicate - If instruction is predicated, returns its predicate
1596 /// condition, otherwise returns AL. It also returns the condition code
1597 /// register by reference.
1599 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1600 int PIdx = MI->findFirstPredOperandIdx();
1606 PredReg = MI->getOperand(PIdx+1).getReg();
1607 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1611 int llvm::getMatchingCondBranchOpcode(int Opc) {
1616 if (Opc == ARM::t2B)
1619 llvm_unreachable("Unknown unconditional branch opcode!");
1622 /// commuteInstruction - Handle commutable instructions.
1624 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1625 switch (MI->getOpcode()) {
1627 case ARM::t2MOVCCr: {
1628 // MOVCC can be commuted by inverting the condition.
1629 unsigned PredReg = 0;
1630 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1631 // MOVCC AL can't be inverted. Shouldn't happen.
1632 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1634 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1637 // After swapping the MOVCC operands, also invert the condition.
1638 MI->getOperand(MI->findFirstPredOperandIdx())
1639 .setImm(ARMCC::getOppositeCondition(CC));
1643 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1646 /// Identify instructions that can be folded into a MOVCC instruction, and
1647 /// return the defining instruction.
1648 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1649 const MachineRegisterInfo &MRI,
1650 const TargetInstrInfo *TII) {
1651 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1653 if (!MRI.hasOneNonDBGUse(Reg))
1655 MachineInstr *MI = MRI.getVRegDef(Reg);
1658 // MI is folded into the MOVCC by predicating it.
1659 if (!MI->isPredicable())
1661 // Check if MI has any non-dead defs or physreg uses. This also detects
1662 // predicated instructions which will be reading CPSR.
1663 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1664 const MachineOperand &MO = MI->getOperand(i);
1665 // Reject frame index operands, PEI can't handle the predicated pseudos.
1666 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1670 // MI can't have any tied operands, that would conflict with predication.
1673 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1675 if (MO.isDef() && !MO.isDead())
1678 bool DontMoveAcrossStores = true;
1679 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ 0, DontMoveAcrossStores))
1684 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1685 SmallVectorImpl<MachineOperand> &Cond,
1686 unsigned &TrueOp, unsigned &FalseOp,
1687 bool &Optimizable) const {
1688 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1689 "Unknown select instruction");
1694 // 3: Condition code.
1698 Cond.push_back(MI->getOperand(3));
1699 Cond.push_back(MI->getOperand(4));
1700 // We can always fold a def.
1705 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1706 bool PreferFalse) const {
1707 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1708 "Unknown select instruction");
1709 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1710 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1711 bool Invert = !DefMI;
1713 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1717 // Find new register class to use.
1718 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1719 unsigned DestReg = MI->getOperand(0).getReg();
1720 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1721 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1724 // Create a new predicated version of DefMI.
1725 // Rfalse is the first use.
1726 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1727 DefMI->getDesc(), DestReg);
1729 // Copy all the DefMI operands, excluding its (null) predicate.
1730 const MCInstrDesc &DefDesc = DefMI->getDesc();
1731 for (unsigned i = 1, e = DefDesc.getNumOperands();
1732 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1733 NewMI.addOperand(DefMI->getOperand(i));
1735 unsigned CondCode = MI->getOperand(3).getImm();
1737 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1739 NewMI.addImm(CondCode);
1740 NewMI.addOperand(MI->getOperand(4));
1742 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1743 if (NewMI->hasOptionalDef())
1744 AddDefaultCC(NewMI);
1746 // The output register value when the predicate is false is an implicit
1747 // register operand tied to the first def.
1748 // The tie makes the register allocator ensure the FalseReg is allocated the
1749 // same register as operand 0.
1750 FalseReg.setImplicit();
1751 NewMI.addOperand(FalseReg);
1752 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1754 // The caller will erase MI, but not DefMI.
1755 DefMI->eraseFromParent();
1759 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1760 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1763 /// This will go away once we can teach tblgen how to set the optional CPSR def
1765 struct AddSubFlagsOpcodePair {
1767 uint16_t MachineOpc;
1770 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1771 {ARM::ADDSri, ARM::ADDri},
1772 {ARM::ADDSrr, ARM::ADDrr},
1773 {ARM::ADDSrsi, ARM::ADDrsi},
1774 {ARM::ADDSrsr, ARM::ADDrsr},
1776 {ARM::SUBSri, ARM::SUBri},
1777 {ARM::SUBSrr, ARM::SUBrr},
1778 {ARM::SUBSrsi, ARM::SUBrsi},
1779 {ARM::SUBSrsr, ARM::SUBrsr},
1781 {ARM::RSBSri, ARM::RSBri},
1782 {ARM::RSBSrsi, ARM::RSBrsi},
1783 {ARM::RSBSrsr, ARM::RSBrsr},
1785 {ARM::t2ADDSri, ARM::t2ADDri},
1786 {ARM::t2ADDSrr, ARM::t2ADDrr},
1787 {ARM::t2ADDSrs, ARM::t2ADDrs},
1789 {ARM::t2SUBSri, ARM::t2SUBri},
1790 {ARM::t2SUBSrr, ARM::t2SUBrr},
1791 {ARM::t2SUBSrs, ARM::t2SUBrs},
1793 {ARM::t2RSBSri, ARM::t2RSBri},
1794 {ARM::t2RSBSrs, ARM::t2RSBrs},
1797 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1798 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1799 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1800 return AddSubFlagsOpcodeMap[i].MachineOpc;
1804 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1805 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1806 unsigned DestReg, unsigned BaseReg, int NumBytes,
1807 ARMCC::CondCodes Pred, unsigned PredReg,
1808 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1809 bool isSub = NumBytes < 0;
1810 if (isSub) NumBytes = -NumBytes;
1813 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1814 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1815 assert(ThisVal && "Didn't extract field correctly");
1817 // We will handle these bits from offset, clear them.
1818 NumBytes &= ~ThisVal;
1820 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1822 // Build the new ADD / SUB.
1823 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1824 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1825 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1826 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1827 .setMIFlags(MIFlags);
1832 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1833 unsigned FrameReg, int &Offset,
1834 const ARMBaseInstrInfo &TII) {
1835 unsigned Opcode = MI.getOpcode();
1836 const MCInstrDesc &Desc = MI.getDesc();
1837 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1840 // Memory operands in inline assembly always use AddrMode2.
1841 if (Opcode == ARM::INLINEASM)
1842 AddrMode = ARMII::AddrMode2;
1844 if (Opcode == ARM::ADDri) {
1845 Offset += MI.getOperand(FrameRegIdx+1).getImm();
1847 // Turn it into a move.
1848 MI.setDesc(TII.get(ARM::MOVr));
1849 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1850 MI.RemoveOperand(FrameRegIdx+1);
1853 } else if (Offset < 0) {
1856 MI.setDesc(TII.get(ARM::SUBri));
1859 // Common case: small offset, fits into instruction.
1860 if (ARM_AM::getSOImmVal(Offset) != -1) {
1861 // Replace the FrameIndex with sp / fp
1862 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1863 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
1868 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
1870 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1871 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1873 // We will handle these bits from offset, clear them.
1874 Offset &= ~ThisImmVal;
1876 // Get the properly encoded SOImmVal field.
1877 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
1878 "Bit extraction didn't work?");
1879 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
1881 unsigned ImmIdx = 0;
1883 unsigned NumBits = 0;
1886 case ARMII::AddrMode_i12: {
1887 ImmIdx = FrameRegIdx + 1;
1888 InstrOffs = MI.getOperand(ImmIdx).getImm();
1892 case ARMII::AddrMode2: {
1893 ImmIdx = FrameRegIdx+2;
1894 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1895 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1900 case ARMII::AddrMode3: {
1901 ImmIdx = FrameRegIdx+2;
1902 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1903 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1908 case ARMII::AddrMode4:
1909 case ARMII::AddrMode6:
1910 // Can't fold any offset even if it's zero.
1912 case ARMII::AddrMode5: {
1913 ImmIdx = FrameRegIdx+1;
1914 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1915 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1922 llvm_unreachable("Unsupported addressing mode!");
1925 Offset += InstrOffs * Scale;
1926 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1932 // Attempt to fold address comp. if opcode has offset bits
1934 // Common case: small offset, fits into instruction.
1935 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1936 int ImmedOffset = Offset / Scale;
1937 unsigned Mask = (1 << NumBits) - 1;
1938 if ((unsigned)Offset <= Mask * Scale) {
1939 // Replace the FrameIndex with sp
1940 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1941 // FIXME: When addrmode2 goes away, this will simplify (like the
1942 // T2 version), as the LDR.i12 versions don't need the encoding
1943 // tricks for the offset value.
1945 if (AddrMode == ARMII::AddrMode_i12)
1946 ImmedOffset = -ImmedOffset;
1948 ImmedOffset |= 1 << NumBits;
1950 ImmOp.ChangeToImmediate(ImmedOffset);
1955 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1956 ImmedOffset = ImmedOffset & Mask;
1958 if (AddrMode == ARMII::AddrMode_i12)
1959 ImmedOffset = -ImmedOffset;
1961 ImmedOffset |= 1 << NumBits;
1963 ImmOp.ChangeToImmediate(ImmedOffset);
1964 Offset &= ~(Mask*Scale);
1968 Offset = (isSub) ? -Offset : Offset;
1972 /// analyzeCompare - For a comparison instruction, return the source registers
1973 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1974 /// compares against in CmpValue. Return true if the comparison instruction
1975 /// can be analyzed.
1976 bool ARMBaseInstrInfo::
1977 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
1978 int &CmpMask, int &CmpValue) const {
1979 switch (MI->getOpcode()) {
1983 SrcReg = MI->getOperand(0).getReg();
1986 CmpValue = MI->getOperand(1).getImm();
1990 SrcReg = MI->getOperand(0).getReg();
1991 SrcReg2 = MI->getOperand(1).getReg();
1997 SrcReg = MI->getOperand(0).getReg();
1999 CmpMask = MI->getOperand(1).getImm();
2007 /// isSuitableForMask - Identify a suitable 'and' instruction that
2008 /// operates on the given source register and applies the same mask
2009 /// as a 'tst' instruction. Provide a limited look-through for copies.
2010 /// When successful, MI will hold the found instruction.
2011 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2012 int CmpMask, bool CommonUse) {
2013 switch (MI->getOpcode()) {
2016 if (CmpMask != MI->getOperand(2).getImm())
2018 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2022 // Walk down one instruction which is potentially an 'and'.
2023 const MachineInstr &Copy = *MI;
2024 MachineBasicBlock::iterator AND(
2025 llvm::next(MachineBasicBlock::iterator(MI)));
2026 if (AND == MI->getParent()->end()) return false;
2028 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2036 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2037 /// the condition code if we modify the instructions such that flags are
2039 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2041 default: return ARMCC::AL;
2042 case ARMCC::EQ: return ARMCC::EQ;
2043 case ARMCC::NE: return ARMCC::NE;
2044 case ARMCC::HS: return ARMCC::LS;
2045 case ARMCC::LO: return ARMCC::HI;
2046 case ARMCC::HI: return ARMCC::LO;
2047 case ARMCC::LS: return ARMCC::HS;
2048 case ARMCC::GE: return ARMCC::LE;
2049 case ARMCC::LT: return ARMCC::GT;
2050 case ARMCC::GT: return ARMCC::LT;
2051 case ARMCC::LE: return ARMCC::GE;
2055 /// isRedundantFlagInstr - check whether the first instruction, whose only
2056 /// purpose is to update flags, can be made redundant.
2057 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2058 /// CMPri can be made redundant by SUBri if the operands are the same.
2059 /// This function can be extended later on.
2060 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2061 unsigned SrcReg2, int ImmValue,
2063 if ((CmpI->getOpcode() == ARM::CMPrr ||
2064 CmpI->getOpcode() == ARM::t2CMPrr) &&
2065 (OI->getOpcode() == ARM::SUBrr ||
2066 OI->getOpcode() == ARM::t2SUBrr) &&
2067 ((OI->getOperand(1).getReg() == SrcReg &&
2068 OI->getOperand(2).getReg() == SrcReg2) ||
2069 (OI->getOperand(1).getReg() == SrcReg2 &&
2070 OI->getOperand(2).getReg() == SrcReg)))
2073 if ((CmpI->getOpcode() == ARM::CMPri ||
2074 CmpI->getOpcode() == ARM::t2CMPri) &&
2075 (OI->getOpcode() == ARM::SUBri ||
2076 OI->getOpcode() == ARM::t2SUBri) &&
2077 OI->getOperand(1).getReg() == SrcReg &&
2078 OI->getOperand(2).getImm() == ImmValue)
2083 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2084 /// comparison into one that sets the zero bit in the flags register;
2085 /// Remove a redundant Compare instruction if an earlier instruction can set the
2086 /// flags in the same way as Compare.
2087 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2088 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2089 /// condition code of instructions which use the flags.
2090 bool ARMBaseInstrInfo::
2091 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2092 int CmpMask, int CmpValue,
2093 const MachineRegisterInfo *MRI) const {
2094 // Get the unique definition of SrcReg.
2095 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2096 if (!MI) return false;
2098 // Masked compares sometimes use the same register as the corresponding 'and'.
2099 if (CmpMask != ~0) {
2100 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2102 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg),
2103 UE = MRI->use_end(); UI != UE; ++UI) {
2104 if (UI->getParent() != CmpInstr->getParent()) continue;
2105 MachineInstr *PotentialAND = &*UI;
2106 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2107 isPredicated(PotentialAND))
2112 if (!MI) return false;
2116 // Get ready to iterate backward from CmpInstr.
2117 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2118 B = CmpInstr->getParent()->begin();
2120 // Early exit if CmpInstr is at the beginning of the BB.
2121 if (I == B) return false;
2123 // There are two possible candidates which can be changed to set CPSR:
2124 // One is MI, the other is a SUB instruction.
2125 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2126 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2127 MachineInstr *Sub = NULL;
2129 // MI is not a candidate for CMPrr.
2131 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2132 // Conservatively refuse to convert an instruction which isn't in the same
2133 // BB as the comparison.
2134 // For CMPri, we need to check Sub, thus we can't return here.
2135 if (CmpInstr->getOpcode() == ARM::CMPri ||
2136 CmpInstr->getOpcode() == ARM::t2CMPri)
2142 // Check that CPSR isn't set between the comparison instruction and the one we
2143 // want to change. At the same time, search for Sub.
2144 const TargetRegisterInfo *TRI = &getRegisterInfo();
2146 for (; I != E; --I) {
2147 const MachineInstr &Instr = *I;
2149 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2150 Instr.readsRegister(ARM::CPSR, TRI))
2151 // This instruction modifies or uses CPSR after the one we want to
2152 // change. We can't do this transformation.
2155 // Check whether CmpInstr can be made redundant by the current instruction.
2156 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2162 // The 'and' is below the comparison instruction.
2166 // Return false if no candidates exist.
2170 // The single candidate is called MI.
2173 // We can't use a predicated instruction - it doesn't always write the flags.
2174 if (isPredicated(MI))
2177 switch (MI->getOpcode()) {
2211 case ARM::t2EORri: {
2212 // Scan forward for the use of CPSR
2213 // When checking against MI: if it's a conditional code requires
2214 // checking of V bit, then this is not safe to do.
2215 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2216 // If we are done with the basic block, we need to check whether CPSR is
2218 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2220 bool isSafe = false;
2222 E = CmpInstr->getParent()->end();
2223 while (!isSafe && ++I != E) {
2224 const MachineInstr &Instr = *I;
2225 for (unsigned IO = 0, EO = Instr.getNumOperands();
2226 !isSafe && IO != EO; ++IO) {
2227 const MachineOperand &MO = Instr.getOperand(IO);
2228 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2232 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2238 // Condition code is after the operand before CPSR.
2239 ARMCC::CondCodes CC = (ARMCC::CondCodes)Instr.getOperand(IO-1).getImm();
2241 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2242 if (NewCC == ARMCC::AL)
2244 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2245 // on CMP needs to be updated to be based on SUB.
2246 // Push the condition code operands to OperandsToUpdate.
2247 // If it is safe to remove CmpInstr, the condition code of these
2248 // operands will be modified.
2249 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2250 Sub->getOperand(2).getReg() == SrcReg)
2251 OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(IO-1)),
2257 // CPSR can be used multiple times, we should continue.
2270 // If CPSR is not killed nor re-defined, we should check whether it is
2271 // live-out. If it is live-out, do not optimize.
2273 MachineBasicBlock *MBB = CmpInstr->getParent();
2274 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2275 SE = MBB->succ_end(); SI != SE; ++SI)
2276 if ((*SI)->isLiveIn(ARM::CPSR))
2280 // Toggle the optional operand to CPSR.
2281 MI->getOperand(5).setReg(ARM::CPSR);
2282 MI->getOperand(5).setIsDef(true);
2283 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2284 CmpInstr->eraseFromParent();
2286 // Modify the condition code of operands in OperandsToUpdate.
2287 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2288 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2289 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2290 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2298 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2299 MachineInstr *DefMI, unsigned Reg,
2300 MachineRegisterInfo *MRI) const {
2301 // Fold large immediates into add, sub, or, xor.
2302 unsigned DefOpc = DefMI->getOpcode();
2303 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2305 if (!DefMI->getOperand(1).isImm())
2306 // Could be t2MOVi32imm <ga:xx>
2309 if (!MRI->hasOneNonDBGUse(Reg))
2312 const MCInstrDesc &DefMCID = DefMI->getDesc();
2313 if (DefMCID.hasOptionalDef()) {
2314 unsigned NumOps = DefMCID.getNumOperands();
2315 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2316 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2317 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2322 const MCInstrDesc &UseMCID = UseMI->getDesc();
2323 if (UseMCID.hasOptionalDef()) {
2324 unsigned NumOps = UseMCID.getNumOperands();
2325 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2326 // If the instruction sets the flag, do not attempt this optimization
2327 // since it may change the semantics of the code.
2331 unsigned UseOpc = UseMI->getOpcode();
2332 unsigned NewUseOpc = 0;
2333 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2334 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2335 bool Commute = false;
2337 default: return false;
2345 case ARM::t2EORrr: {
2346 Commute = UseMI->getOperand(2).getReg() != Reg;
2353 NewUseOpc = ARM::SUBri;
2359 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2361 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2362 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2365 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2366 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2367 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2371 case ARM::t2SUBrr: {
2375 NewUseOpc = ARM::t2SUBri;
2380 case ARM::t2EORrr: {
2381 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2383 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2384 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2387 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2388 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2389 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2397 unsigned OpIdx = Commute ? 2 : 1;
2398 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2399 bool isKill = UseMI->getOperand(OpIdx).isKill();
2400 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2401 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2402 UseMI, UseMI->getDebugLoc(),
2403 get(NewUseOpc), NewReg)
2404 .addReg(Reg1, getKillRegState(isKill))
2405 .addImm(SOImmValV1)));
2406 UseMI->setDesc(get(NewUseOpc));
2407 UseMI->getOperand(1).setReg(NewReg);
2408 UseMI->getOperand(1).setIsKill();
2409 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2410 DefMI->eraseFromParent();
2414 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2415 const MachineInstr *MI) {
2416 switch (MI->getOpcode()) {
2418 const MCInstrDesc &Desc = MI->getDesc();
2419 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2420 assert(UOps >= 0 && "bad # UOps");
2428 unsigned ShOpVal = MI->getOperand(3).getImm();
2429 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2430 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2433 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2434 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2441 if (!MI->getOperand(2).getReg())
2444 unsigned ShOpVal = MI->getOperand(3).getImm();
2445 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2446 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2449 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2450 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2457 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2459 case ARM::LDRSB_POST:
2460 case ARM::LDRSH_POST: {
2461 unsigned Rt = MI->getOperand(0).getReg();
2462 unsigned Rm = MI->getOperand(3).getReg();
2463 return (Rt == Rm) ? 4 : 3;
2466 case ARM::LDR_PRE_REG:
2467 case ARM::LDRB_PRE_REG: {
2468 unsigned Rt = MI->getOperand(0).getReg();
2469 unsigned Rm = MI->getOperand(3).getReg();
2472 unsigned ShOpVal = MI->getOperand(4).getImm();
2473 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2474 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2477 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2478 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2483 case ARM::STR_PRE_REG:
2484 case ARM::STRB_PRE_REG: {
2485 unsigned ShOpVal = MI->getOperand(4).getImm();
2486 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2487 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2490 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2491 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2497 case ARM::STRH_PRE: {
2498 unsigned Rt = MI->getOperand(0).getReg();
2499 unsigned Rm = MI->getOperand(3).getReg();
2504 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2508 case ARM::LDR_POST_REG:
2509 case ARM::LDRB_POST_REG:
2510 case ARM::LDRH_POST: {
2511 unsigned Rt = MI->getOperand(0).getReg();
2512 unsigned Rm = MI->getOperand(3).getReg();
2513 return (Rt == Rm) ? 3 : 2;
2516 case ARM::LDR_PRE_IMM:
2517 case ARM::LDRB_PRE_IMM:
2518 case ARM::LDR_POST_IMM:
2519 case ARM::LDRB_POST_IMM:
2520 case ARM::STRB_POST_IMM:
2521 case ARM::STRB_POST_REG:
2522 case ARM::STRB_PRE_IMM:
2523 case ARM::STRH_POST:
2524 case ARM::STR_POST_IMM:
2525 case ARM::STR_POST_REG:
2526 case ARM::STR_PRE_IMM:
2529 case ARM::LDRSB_PRE:
2530 case ARM::LDRSH_PRE: {
2531 unsigned Rm = MI->getOperand(3).getReg();
2534 unsigned Rt = MI->getOperand(0).getReg();
2537 unsigned ShOpVal = MI->getOperand(4).getImm();
2538 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2539 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2542 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2543 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2549 unsigned Rt = MI->getOperand(0).getReg();
2550 unsigned Rn = MI->getOperand(2).getReg();
2551 unsigned Rm = MI->getOperand(3).getReg();
2553 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2554 return (Rt == Rn) ? 3 : 2;
2558 unsigned Rm = MI->getOperand(3).getReg();
2560 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2564 case ARM::LDRD_POST:
2565 case ARM::t2LDRD_POST:
2568 case ARM::STRD_POST:
2569 case ARM::t2STRD_POST:
2572 case ARM::LDRD_PRE: {
2573 unsigned Rt = MI->getOperand(0).getReg();
2574 unsigned Rn = MI->getOperand(3).getReg();
2575 unsigned Rm = MI->getOperand(4).getReg();
2577 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2578 return (Rt == Rn) ? 4 : 3;
2581 case ARM::t2LDRD_PRE: {
2582 unsigned Rt = MI->getOperand(0).getReg();
2583 unsigned Rn = MI->getOperand(3).getReg();
2584 return (Rt == Rn) ? 4 : 3;
2587 case ARM::STRD_PRE: {
2588 unsigned Rm = MI->getOperand(4).getReg();
2590 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2594 case ARM::t2STRD_PRE:
2597 case ARM::t2LDR_POST:
2598 case ARM::t2LDRB_POST:
2599 case ARM::t2LDRB_PRE:
2600 case ARM::t2LDRSBi12:
2601 case ARM::t2LDRSBi8:
2602 case ARM::t2LDRSBpci:
2604 case ARM::t2LDRH_POST:
2605 case ARM::t2LDRH_PRE:
2607 case ARM::t2LDRSB_POST:
2608 case ARM::t2LDRSB_PRE:
2609 case ARM::t2LDRSH_POST:
2610 case ARM::t2LDRSH_PRE:
2611 case ARM::t2LDRSHi12:
2612 case ARM::t2LDRSHi8:
2613 case ARM::t2LDRSHpci:
2617 case ARM::t2LDRDi8: {
2618 unsigned Rt = MI->getOperand(0).getReg();
2619 unsigned Rn = MI->getOperand(2).getReg();
2620 return (Rt == Rn) ? 3 : 2;
2623 case ARM::t2STRB_POST:
2624 case ARM::t2STRB_PRE:
2627 case ARM::t2STRH_POST:
2628 case ARM::t2STRH_PRE:
2630 case ARM::t2STR_POST:
2631 case ARM::t2STR_PRE:
2637 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2638 // can't be easily determined return 0 (missing MachineMemOperand).
2640 // FIXME: The current MachineInstr design does not support relying on machine
2641 // mem operands to determine the width of a memory access. Instead, we expect
2642 // the target to provide this information based on the instruction opcode and
2643 // operands. However, using MachineMemOperand is a the best solution now for
2646 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2647 // operands. This is much more dangerous than using the MachineMemOperand
2648 // sizes because CodeGen passes can insert/remove optional machine operands. In
2649 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2650 // postRA passes as well.
2652 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2653 // machine model that calls this should handle the unknown (zero size) case.
2655 // Long term, we should require a target hook that verifies MachineMemOperand
2656 // sizes during MC lowering. That target hook should be local to MC lowering
2657 // because we can't ensure that it is aware of other MI forms. Doing this will
2658 // ensure that MachineMemOperands are correctly propagated through all passes.
2659 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2661 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2662 E = MI->memoperands_end(); I != E; ++I) {
2663 Size += (*I)->getSize();
2669 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2670 const MachineInstr *MI) const {
2671 if (!ItinData || ItinData->isEmpty())
2674 const MCInstrDesc &Desc = MI->getDesc();
2675 unsigned Class = Desc.getSchedClass();
2676 int ItinUOps = ItinData->getNumMicroOps(Class);
2677 if (ItinUOps >= 0) {
2678 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2679 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2684 unsigned Opc = MI->getOpcode();
2687 llvm_unreachable("Unexpected multi-uops instruction!");
2692 // The number of uOps for load / store multiple are determined by the number
2695 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2696 // same cycle. The scheduling for the first load / store must be done
2697 // separately by assuming the address is not 64-bit aligned.
2699 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2700 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2701 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2703 case ARM::VLDMDIA_UPD:
2704 case ARM::VLDMDDB_UPD:
2706 case ARM::VLDMSIA_UPD:
2707 case ARM::VLDMSDB_UPD:
2709 case ARM::VSTMDIA_UPD:
2710 case ARM::VSTMDDB_UPD:
2712 case ARM::VSTMSIA_UPD:
2713 case ARM::VSTMSDB_UPD: {
2714 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2715 return (NumRegs / 2) + (NumRegs % 2) + 1;
2718 case ARM::LDMIA_RET:
2723 case ARM::LDMIA_UPD:
2724 case ARM::LDMDA_UPD:
2725 case ARM::LDMDB_UPD:
2726 case ARM::LDMIB_UPD:
2731 case ARM::STMIA_UPD:
2732 case ARM::STMDA_UPD:
2733 case ARM::STMDB_UPD:
2734 case ARM::STMIB_UPD:
2736 case ARM::tLDMIA_UPD:
2737 case ARM::tSTMIA_UPD:
2741 case ARM::t2LDMIA_RET:
2744 case ARM::t2LDMIA_UPD:
2745 case ARM::t2LDMDB_UPD:
2748 case ARM::t2STMIA_UPD:
2749 case ARM::t2STMDB_UPD: {
2750 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2751 if (Subtarget.isSwift()) {
2752 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2755 case ARM::VLDMDIA_UPD:
2756 case ARM::VLDMDDB_UPD:
2757 case ARM::VLDMSIA_UPD:
2758 case ARM::VLDMSDB_UPD:
2759 case ARM::VSTMDIA_UPD:
2760 case ARM::VSTMDDB_UPD:
2761 case ARM::VSTMSIA_UPD:
2762 case ARM::VSTMSDB_UPD:
2763 case ARM::LDMIA_UPD:
2764 case ARM::LDMDA_UPD:
2765 case ARM::LDMDB_UPD:
2766 case ARM::LDMIB_UPD:
2767 case ARM::STMIA_UPD:
2768 case ARM::STMDA_UPD:
2769 case ARM::STMDB_UPD:
2770 case ARM::STMIB_UPD:
2771 case ARM::tLDMIA_UPD:
2772 case ARM::tSTMIA_UPD:
2773 case ARM::t2LDMIA_UPD:
2774 case ARM::t2LDMDB_UPD:
2775 case ARM::t2STMIA_UPD:
2776 case ARM::t2STMDB_UPD:
2777 ++UOps; // One for base register writeback.
2779 case ARM::LDMIA_RET:
2781 case ARM::t2LDMIA_RET:
2782 UOps += 2; // One for base reg wb, one for write to pc.
2786 } else if (Subtarget.isCortexA8()) {
2789 // 4 registers would be issued: 2, 2.
2790 // 5 registers would be issued: 2, 2, 1.
2791 int A8UOps = (NumRegs / 2);
2795 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2796 int A9UOps = (NumRegs / 2);
2797 // If there are odd number of registers or if it's not 64-bit aligned,
2798 // then it takes an extra AGU (Address Generation Unit) cycle.
2799 if ((NumRegs % 2) ||
2800 !MI->hasOneMemOperand() ||
2801 (*MI->memoperands_begin())->getAlignment() < 8)
2805 // Assume the worst.
2813 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
2814 const MCInstrDesc &DefMCID,
2816 unsigned DefIdx, unsigned DefAlign) const {
2817 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2819 // Def is the address writeback.
2820 return ItinData->getOperandCycle(DefClass, DefIdx);
2823 if (Subtarget.isCortexA8()) {
2824 // (regno / 2) + (regno % 2) + 1
2825 DefCycle = RegNo / 2 + 1;
2828 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2830 bool isSLoad = false;
2832 switch (DefMCID.getOpcode()) {
2835 case ARM::VLDMSIA_UPD:
2836 case ARM::VLDMSDB_UPD:
2841 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2842 // then it takes an extra cycle.
2843 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
2846 // Assume the worst.
2847 DefCycle = RegNo + 2;
2854 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
2855 const MCInstrDesc &DefMCID,
2857 unsigned DefIdx, unsigned DefAlign) const {
2858 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
2860 // Def is the address writeback.
2861 return ItinData->getOperandCycle(DefClass, DefIdx);
2864 if (Subtarget.isCortexA8()) {
2865 // 4 registers would be issued: 1, 2, 1.
2866 // 5 registers would be issued: 1, 2, 2.
2867 DefCycle = RegNo / 2;
2870 // Result latency is issue cycle + 2: E2.
2872 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2873 DefCycle = (RegNo / 2);
2874 // If there are odd number of registers or if it's not 64-bit aligned,
2875 // then it takes an extra AGU (Address Generation Unit) cycle.
2876 if ((RegNo % 2) || DefAlign < 8)
2878 // Result latency is AGU cycles + 2.
2881 // Assume the worst.
2882 DefCycle = RegNo + 2;
2889 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
2890 const MCInstrDesc &UseMCID,
2892 unsigned UseIdx, unsigned UseAlign) const {
2893 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2895 return ItinData->getOperandCycle(UseClass, UseIdx);
2898 if (Subtarget.isCortexA8()) {
2899 // (regno / 2) + (regno % 2) + 1
2900 UseCycle = RegNo / 2 + 1;
2903 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2905 bool isSStore = false;
2907 switch (UseMCID.getOpcode()) {
2910 case ARM::VSTMSIA_UPD:
2911 case ARM::VSTMSDB_UPD:
2916 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
2917 // then it takes an extra cycle.
2918 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
2921 // Assume the worst.
2922 UseCycle = RegNo + 2;
2929 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
2930 const MCInstrDesc &UseMCID,
2932 unsigned UseIdx, unsigned UseAlign) const {
2933 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2935 return ItinData->getOperandCycle(UseClass, UseIdx);
2938 if (Subtarget.isCortexA8()) {
2939 UseCycle = RegNo / 2;
2944 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
2945 UseCycle = (RegNo / 2);
2946 // If there are odd number of registers or if it's not 64-bit aligned,
2947 // then it takes an extra AGU (Address Generation Unit) cycle.
2948 if ((RegNo % 2) || UseAlign < 8)
2951 // Assume the worst.
2958 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
2959 const MCInstrDesc &DefMCID,
2960 unsigned DefIdx, unsigned DefAlign,
2961 const MCInstrDesc &UseMCID,
2962 unsigned UseIdx, unsigned UseAlign) const {
2963 unsigned DefClass = DefMCID.getSchedClass();
2964 unsigned UseClass = UseMCID.getSchedClass();
2966 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2967 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2969 // This may be a def / use of a variable_ops instruction, the operand
2970 // latency might be determinable dynamically. Let the target try to
2973 bool LdmBypass = false;
2974 switch (DefMCID.getOpcode()) {
2976 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
2980 case ARM::VLDMDIA_UPD:
2981 case ARM::VLDMDDB_UPD:
2983 case ARM::VLDMSIA_UPD:
2984 case ARM::VLDMSDB_UPD:
2985 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
2988 case ARM::LDMIA_RET:
2993 case ARM::LDMIA_UPD:
2994 case ARM::LDMDA_UPD:
2995 case ARM::LDMDB_UPD:
2996 case ARM::LDMIB_UPD:
2998 case ARM::tLDMIA_UPD:
3000 case ARM::t2LDMIA_RET:
3003 case ARM::t2LDMIA_UPD:
3004 case ARM::t2LDMDB_UPD:
3006 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3011 // We can't seem to determine the result latency of the def, assume it's 2.
3015 switch (UseMCID.getOpcode()) {
3017 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3021 case ARM::VSTMDIA_UPD:
3022 case ARM::VSTMDDB_UPD:
3024 case ARM::VSTMSIA_UPD:
3025 case ARM::VSTMSDB_UPD:
3026 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3033 case ARM::STMIA_UPD:
3034 case ARM::STMDA_UPD:
3035 case ARM::STMDB_UPD:
3036 case ARM::STMIB_UPD:
3037 case ARM::tSTMIA_UPD:
3042 case ARM::t2STMIA_UPD:
3043 case ARM::t2STMDB_UPD:
3044 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3049 // Assume it's read in the first stage.
3052 UseCycle = DefCycle - UseCycle + 1;
3055 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3056 // first def operand.
3057 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3060 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3061 UseClass, UseIdx)) {
3069 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3070 const MachineInstr *MI, unsigned Reg,
3071 unsigned &DefIdx, unsigned &Dist) {
3074 MachineBasicBlock::const_iterator I = MI; ++I;
3075 MachineBasicBlock::const_instr_iterator II =
3076 llvm::prior(I.getInstrIterator());
3077 assert(II->isInsideBundle() && "Empty bundle?");
3080 while (II->isInsideBundle()) {
3081 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3088 assert(Idx != -1 && "Cannot find bundled definition!");
3093 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3094 const MachineInstr *MI, unsigned Reg,
3095 unsigned &UseIdx, unsigned &Dist) {
3098 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3099 assert(II->isInsideBundle() && "Empty bundle?");
3100 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3102 // FIXME: This doesn't properly handle multiple uses.
3104 while (II != E && II->isInsideBundle()) {
3105 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3108 if (II->getOpcode() != ARM::t2IT)
3122 /// Return the number of cycles to add to (or subtract from) the static
3123 /// itinerary based on the def opcode and alignment. The caller will ensure that
3124 /// adjusted latency is at least one cycle.
3125 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3126 const MachineInstr *DefMI,
3127 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3129 if (Subtarget.isCortexA8() || Subtarget.isLikeA9()) {
3130 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3131 // variants are one cycle cheaper.
3132 switch (DefMCID->getOpcode()) {
3136 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3137 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3139 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3146 case ARM::t2LDRSHs: {
3147 // Thumb2 mode: lsl only.
3148 unsigned ShAmt = DefMI->getOperand(3).getImm();
3149 if (ShAmt == 0 || ShAmt == 2)
3154 } else if (Subtarget.isSwift()) {
3155 // FIXME: Properly handle all of the latency adjustments for address
3157 switch (DefMCID->getOpcode()) {
3161 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3162 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3163 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3166 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3167 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3170 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3177 case ARM::t2LDRSHs: {
3178 // Thumb2 mode: lsl only.
3179 unsigned ShAmt = DefMI->getOperand(3).getImm();
3180 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3187 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3188 switch (DefMCID->getOpcode()) {
3194 case ARM::VLD1q8wb_fixed:
3195 case ARM::VLD1q16wb_fixed:
3196 case ARM::VLD1q32wb_fixed:
3197 case ARM::VLD1q64wb_fixed:
3198 case ARM::VLD1q8wb_register:
3199 case ARM::VLD1q16wb_register:
3200 case ARM::VLD1q32wb_register:
3201 case ARM::VLD1q64wb_register:
3208 case ARM::VLD2d8wb_fixed:
3209 case ARM::VLD2d16wb_fixed:
3210 case ARM::VLD2d32wb_fixed:
3211 case ARM::VLD2q8wb_fixed:
3212 case ARM::VLD2q16wb_fixed:
3213 case ARM::VLD2q32wb_fixed:
3214 case ARM::VLD2d8wb_register:
3215 case ARM::VLD2d16wb_register:
3216 case ARM::VLD2d32wb_register:
3217 case ARM::VLD2q8wb_register:
3218 case ARM::VLD2q16wb_register:
3219 case ARM::VLD2q32wb_register:
3224 case ARM::VLD3d8_UPD:
3225 case ARM::VLD3d16_UPD:
3226 case ARM::VLD3d32_UPD:
3227 case ARM::VLD1d64Twb_fixed:
3228 case ARM::VLD1d64Twb_register:
3229 case ARM::VLD3q8_UPD:
3230 case ARM::VLD3q16_UPD:
3231 case ARM::VLD3q32_UPD:
3236 case ARM::VLD4d8_UPD:
3237 case ARM::VLD4d16_UPD:
3238 case ARM::VLD4d32_UPD:
3239 case ARM::VLD1d64Qwb_fixed:
3240 case ARM::VLD1d64Qwb_register:
3241 case ARM::VLD4q8_UPD:
3242 case ARM::VLD4q16_UPD:
3243 case ARM::VLD4q32_UPD:
3244 case ARM::VLD1DUPq8:
3245 case ARM::VLD1DUPq16:
3246 case ARM::VLD1DUPq32:
3247 case ARM::VLD1DUPq8wb_fixed:
3248 case ARM::VLD1DUPq16wb_fixed:
3249 case ARM::VLD1DUPq32wb_fixed:
3250 case ARM::VLD1DUPq8wb_register:
3251 case ARM::VLD1DUPq16wb_register:
3252 case ARM::VLD1DUPq32wb_register:
3253 case ARM::VLD2DUPd8:
3254 case ARM::VLD2DUPd16:
3255 case ARM::VLD2DUPd32:
3256 case ARM::VLD2DUPd8wb_fixed:
3257 case ARM::VLD2DUPd16wb_fixed:
3258 case ARM::VLD2DUPd32wb_fixed:
3259 case ARM::VLD2DUPd8wb_register:
3260 case ARM::VLD2DUPd16wb_register:
3261 case ARM::VLD2DUPd32wb_register:
3262 case ARM::VLD4DUPd8:
3263 case ARM::VLD4DUPd16:
3264 case ARM::VLD4DUPd32:
3265 case ARM::VLD4DUPd8_UPD:
3266 case ARM::VLD4DUPd16_UPD:
3267 case ARM::VLD4DUPd32_UPD:
3269 case ARM::VLD1LNd16:
3270 case ARM::VLD1LNd32:
3271 case ARM::VLD1LNd8_UPD:
3272 case ARM::VLD1LNd16_UPD:
3273 case ARM::VLD1LNd32_UPD:
3275 case ARM::VLD2LNd16:
3276 case ARM::VLD2LNd32:
3277 case ARM::VLD2LNq16:
3278 case ARM::VLD2LNq32:
3279 case ARM::VLD2LNd8_UPD:
3280 case ARM::VLD2LNd16_UPD:
3281 case ARM::VLD2LNd32_UPD:
3282 case ARM::VLD2LNq16_UPD:
3283 case ARM::VLD2LNq32_UPD:
3285 case ARM::VLD4LNd16:
3286 case ARM::VLD4LNd32:
3287 case ARM::VLD4LNq16:
3288 case ARM::VLD4LNq32:
3289 case ARM::VLD4LNd8_UPD:
3290 case ARM::VLD4LNd16_UPD:
3291 case ARM::VLD4LNd32_UPD:
3292 case ARM::VLD4LNq16_UPD:
3293 case ARM::VLD4LNq32_UPD:
3294 // If the address is not 64-bit aligned, the latencies of these
3295 // instructions increases by one.
3306 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3307 const MachineInstr *DefMI, unsigned DefIdx,
3308 const MachineInstr *UseMI,
3309 unsigned UseIdx) const {
3310 // No operand latency. The caller may fall back to getInstrLatency.
3311 if (!ItinData || ItinData->isEmpty())
3314 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3315 unsigned Reg = DefMO.getReg();
3316 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3317 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3319 unsigned DefAdj = 0;
3320 if (DefMI->isBundle()) {
3321 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3322 DefMCID = &DefMI->getDesc();
3324 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3325 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3329 unsigned UseAdj = 0;
3330 if (UseMI->isBundle()) {
3332 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3333 Reg, NewUseIdx, UseAdj);
3339 UseMCID = &UseMI->getDesc();
3342 if (Reg == ARM::CPSR) {
3343 if (DefMI->getOpcode() == ARM::FMSTAT) {
3344 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3345 return Subtarget.isLikeA9() ? 1 : 20;
3348 // CPSR set and branch can be paired in the same cycle.
3349 if (UseMI->isBranch())
3352 // Otherwise it takes the instruction latency (generally one).
3353 unsigned Latency = getInstrLatency(ItinData, DefMI);
3355 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3356 // its uses. Instructions which are otherwise scheduled between them may
3357 // incur a code size penalty (not able to use the CPSR setting 16-bit
3359 if (Latency > 0 && Subtarget.isThumb2()) {
3360 const MachineFunction *MF = DefMI->getParent()->getParent();
3361 if (MF->getFunction()->getAttributes().
3362 hasAttribute(AttributeSet::FunctionIndex,
3363 Attribute::OptimizeForSize))
3369 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3372 unsigned DefAlign = DefMI->hasOneMemOperand()
3373 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3374 unsigned UseAlign = UseMI->hasOneMemOperand()
3375 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3377 // Get the itinerary's latency if possible, and handle variable_ops.
3378 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3379 *UseMCID, UseIdx, UseAlign);
3380 // Unable to find operand latency. The caller may resort to getInstrLatency.
3384 // Adjust for IT block position.
3385 int Adj = DefAdj + UseAdj;
3387 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3388 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3389 if (Adj >= 0 || (int)Latency > -Adj) {
3390 return Latency + Adj;
3392 // Return the itinerary latency, which may be zero but not less than zero.
3397 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3398 SDNode *DefNode, unsigned DefIdx,
3399 SDNode *UseNode, unsigned UseIdx) const {
3400 if (!DefNode->isMachineOpcode())
3403 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3405 if (isZeroCost(DefMCID.Opcode))
3408 if (!ItinData || ItinData->isEmpty())
3409 return DefMCID.mayLoad() ? 3 : 1;
3411 if (!UseNode->isMachineOpcode()) {
3412 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3413 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3414 return Latency <= 2 ? 1 : Latency - 1;
3416 return Latency <= 3 ? 1 : Latency - 2;
3419 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3420 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3421 unsigned DefAlign = !DefMN->memoperands_empty()
3422 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3423 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3424 unsigned UseAlign = !UseMN->memoperands_empty()
3425 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3426 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3427 UseMCID, UseIdx, UseAlign);
3430 (Subtarget.isCortexA8() || Subtarget.isLikeA9())) {
3431 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3432 // variants are one cycle cheaper.
3433 switch (DefMCID.getOpcode()) {
3438 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3439 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3441 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3448 case ARM::t2LDRSHs: {
3449 // Thumb2 mode: lsl only.
3451 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3452 if (ShAmt == 0 || ShAmt == 2)
3457 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3458 // FIXME: Properly handle all of the latency adjustments for address
3460 switch (DefMCID.getOpcode()) {
3465 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3466 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3468 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3469 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3471 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3478 case ARM::t2LDRSHs: {
3479 // Thumb2 mode: lsl 0-3 only.
3486 if (DefAlign < 8 && Subtarget.isLikeA9())
3487 switch (DefMCID.getOpcode()) {
3493 case ARM::VLD1q8wb_register:
3494 case ARM::VLD1q16wb_register:
3495 case ARM::VLD1q32wb_register:
3496 case ARM::VLD1q64wb_register:
3497 case ARM::VLD1q8wb_fixed:
3498 case ARM::VLD1q16wb_fixed:
3499 case ARM::VLD1q32wb_fixed:
3500 case ARM::VLD1q64wb_fixed:
3504 case ARM::VLD2q8Pseudo:
3505 case ARM::VLD2q16Pseudo:
3506 case ARM::VLD2q32Pseudo:
3507 case ARM::VLD2d8wb_fixed:
3508 case ARM::VLD2d16wb_fixed:
3509 case ARM::VLD2d32wb_fixed:
3510 case ARM::VLD2q8PseudoWB_fixed:
3511 case ARM::VLD2q16PseudoWB_fixed:
3512 case ARM::VLD2q32PseudoWB_fixed:
3513 case ARM::VLD2d8wb_register:
3514 case ARM::VLD2d16wb_register:
3515 case ARM::VLD2d32wb_register:
3516 case ARM::VLD2q8PseudoWB_register:
3517 case ARM::VLD2q16PseudoWB_register:
3518 case ARM::VLD2q32PseudoWB_register:
3519 case ARM::VLD3d8Pseudo:
3520 case ARM::VLD3d16Pseudo:
3521 case ARM::VLD3d32Pseudo:
3522 case ARM::VLD1d64TPseudo:
3523 case ARM::VLD3d8Pseudo_UPD:
3524 case ARM::VLD3d16Pseudo_UPD:
3525 case ARM::VLD3d32Pseudo_UPD:
3526 case ARM::VLD3q8Pseudo_UPD:
3527 case ARM::VLD3q16Pseudo_UPD:
3528 case ARM::VLD3q32Pseudo_UPD:
3529 case ARM::VLD3q8oddPseudo:
3530 case ARM::VLD3q16oddPseudo:
3531 case ARM::VLD3q32oddPseudo:
3532 case ARM::VLD3q8oddPseudo_UPD:
3533 case ARM::VLD3q16oddPseudo_UPD:
3534 case ARM::VLD3q32oddPseudo_UPD:
3535 case ARM::VLD4d8Pseudo:
3536 case ARM::VLD4d16Pseudo:
3537 case ARM::VLD4d32Pseudo:
3538 case ARM::VLD1d64QPseudo:
3539 case ARM::VLD4d8Pseudo_UPD:
3540 case ARM::VLD4d16Pseudo_UPD:
3541 case ARM::VLD4d32Pseudo_UPD:
3542 case ARM::VLD4q8Pseudo_UPD:
3543 case ARM::VLD4q16Pseudo_UPD:
3544 case ARM::VLD4q32Pseudo_UPD:
3545 case ARM::VLD4q8oddPseudo:
3546 case ARM::VLD4q16oddPseudo:
3547 case ARM::VLD4q32oddPseudo:
3548 case ARM::VLD4q8oddPseudo_UPD:
3549 case ARM::VLD4q16oddPseudo_UPD:
3550 case ARM::VLD4q32oddPseudo_UPD:
3551 case ARM::VLD1DUPq8:
3552 case ARM::VLD1DUPq16:
3553 case ARM::VLD1DUPq32:
3554 case ARM::VLD1DUPq8wb_fixed:
3555 case ARM::VLD1DUPq16wb_fixed:
3556 case ARM::VLD1DUPq32wb_fixed:
3557 case ARM::VLD1DUPq8wb_register:
3558 case ARM::VLD1DUPq16wb_register:
3559 case ARM::VLD1DUPq32wb_register:
3560 case ARM::VLD2DUPd8:
3561 case ARM::VLD2DUPd16:
3562 case ARM::VLD2DUPd32:
3563 case ARM::VLD2DUPd8wb_fixed:
3564 case ARM::VLD2DUPd16wb_fixed:
3565 case ARM::VLD2DUPd32wb_fixed:
3566 case ARM::VLD2DUPd8wb_register:
3567 case ARM::VLD2DUPd16wb_register:
3568 case ARM::VLD2DUPd32wb_register:
3569 case ARM::VLD4DUPd8Pseudo:
3570 case ARM::VLD4DUPd16Pseudo:
3571 case ARM::VLD4DUPd32Pseudo:
3572 case ARM::VLD4DUPd8Pseudo_UPD:
3573 case ARM::VLD4DUPd16Pseudo_UPD:
3574 case ARM::VLD4DUPd32Pseudo_UPD:
3575 case ARM::VLD1LNq8Pseudo:
3576 case ARM::VLD1LNq16Pseudo:
3577 case ARM::VLD1LNq32Pseudo:
3578 case ARM::VLD1LNq8Pseudo_UPD:
3579 case ARM::VLD1LNq16Pseudo_UPD:
3580 case ARM::VLD1LNq32Pseudo_UPD:
3581 case ARM::VLD2LNd8Pseudo:
3582 case ARM::VLD2LNd16Pseudo:
3583 case ARM::VLD2LNd32Pseudo:
3584 case ARM::VLD2LNq16Pseudo:
3585 case ARM::VLD2LNq32Pseudo:
3586 case ARM::VLD2LNd8Pseudo_UPD:
3587 case ARM::VLD2LNd16Pseudo_UPD:
3588 case ARM::VLD2LNd32Pseudo_UPD:
3589 case ARM::VLD2LNq16Pseudo_UPD:
3590 case ARM::VLD2LNq32Pseudo_UPD:
3591 case ARM::VLD4LNd8Pseudo:
3592 case ARM::VLD4LNd16Pseudo:
3593 case ARM::VLD4LNd32Pseudo:
3594 case ARM::VLD4LNq16Pseudo:
3595 case ARM::VLD4LNq32Pseudo:
3596 case ARM::VLD4LNd8Pseudo_UPD:
3597 case ARM::VLD4LNd16Pseudo_UPD:
3598 case ARM::VLD4LNd32Pseudo_UPD:
3599 case ARM::VLD4LNq16Pseudo_UPD:
3600 case ARM::VLD4LNq32Pseudo_UPD:
3601 // If the address is not 64-bit aligned, the latencies of these
3602 // instructions increases by one.
3610 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3611 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3612 MI->isRegSequence() || MI->isImplicitDef())
3618 const MCInstrDesc &MCID = MI->getDesc();
3620 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3621 // When predicated, CPSR is an additional source operand for CPSR updating
3622 // instructions, this apparently increases their latencies.
3628 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3629 const MachineInstr *MI,
3630 unsigned *PredCost) const {
3631 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3632 MI->isRegSequence() || MI->isImplicitDef())
3635 // An instruction scheduler typically runs on unbundled instructions, however
3636 // other passes may query the latency of a bundled instruction.
3637 if (MI->isBundle()) {
3638 unsigned Latency = 0;
3639 MachineBasicBlock::const_instr_iterator I = MI;
3640 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3641 while (++I != E && I->isInsideBundle()) {
3642 if (I->getOpcode() != ARM::t2IT)
3643 Latency += getInstrLatency(ItinData, I, PredCost);
3648 const MCInstrDesc &MCID = MI->getDesc();
3649 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3650 // When predicated, CPSR is an additional source operand for CPSR updating
3651 // instructions, this apparently increases their latencies.
3654 // Be sure to call getStageLatency for an empty itinerary in case it has a
3655 // valid MinLatency property.
3657 return MI->mayLoad() ? 3 : 1;
3659 unsigned Class = MCID.getSchedClass();
3661 // For instructions with variable uops, use uops as latency.
3662 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3663 return getNumMicroOps(ItinData, MI);
3665 // For the common case, fall back on the itinerary's latency.
3666 unsigned Latency = ItinData->getStageLatency(Class);
3668 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3669 unsigned DefAlign = MI->hasOneMemOperand()
3670 ? (*MI->memoperands_begin())->getAlignment() : 0;
3671 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3672 if (Adj >= 0 || (int)Latency > -Adj) {
3673 return Latency + Adj;
3678 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3679 SDNode *Node) const {
3680 if (!Node->isMachineOpcode())
3683 if (!ItinData || ItinData->isEmpty())
3686 unsigned Opcode = Node->getMachineOpcode();
3689 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3696 bool ARMBaseInstrInfo::
3697 hasHighOperandLatency(const InstrItineraryData *ItinData,
3698 const MachineRegisterInfo *MRI,
3699 const MachineInstr *DefMI, unsigned DefIdx,
3700 const MachineInstr *UseMI, unsigned UseIdx) const {
3701 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3702 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3703 if (Subtarget.isCortexA8() &&
3704 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3705 // CortexA8 VFP instructions are not pipelined.
3708 // Hoist VFP / NEON instructions with 4 or higher latency.
3709 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3711 Latency = getInstrLatency(ItinData, DefMI);
3714 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3715 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3718 bool ARMBaseInstrInfo::
3719 hasLowDefLatency(const InstrItineraryData *ItinData,
3720 const MachineInstr *DefMI, unsigned DefIdx) const {
3721 if (!ItinData || ItinData->isEmpty())
3724 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3725 if (DDomain == ARMII::DomainGeneral) {
3726 unsigned DefClass = DefMI->getDesc().getSchedClass();
3727 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3728 return (DefCycle != -1 && DefCycle <= 2);
3733 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3734 StringRef &ErrInfo) const {
3735 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3736 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3743 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
3744 unsigned &AddSubOpc,
3745 bool &NegAcc, bool &HasLane) const {
3746 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
3747 if (I == MLxEntryMap.end())
3750 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
3751 MulOpc = Entry.MulOpc;
3752 AddSubOpc = Entry.AddSubOpc;
3753 NegAcc = Entry.NegAcc;
3754 HasLane = Entry.HasLane;
3758 //===----------------------------------------------------------------------===//
3759 // Execution domains.
3760 //===----------------------------------------------------------------------===//
3762 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
3763 // and some can go down both. The vmov instructions go down the VFP pipeline,
3764 // but they can be changed to vorr equivalents that are executed by the NEON
3767 // We use the following execution domain numbering:
3775 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
3777 std::pair<uint16_t, uint16_t>
3778 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3779 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
3780 // if they are not predicated.
3781 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
3782 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3784 // CortexA9 is particularly picky about mixing the two and wants these
3786 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
3787 (MI->getOpcode() == ARM::VMOVRS ||
3788 MI->getOpcode() == ARM::VMOVSR ||
3789 MI->getOpcode() == ARM::VMOVS))
3790 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
3792 // No other instructions can be swizzled, so just determine their domain.
3793 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
3795 if (Domain & ARMII::DomainNEON)
3796 return std::make_pair(ExeNEON, 0);
3798 // Certain instructions can go either way on Cortex-A8.
3799 // Treat them as NEON instructions.
3800 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
3801 return std::make_pair(ExeNEON, 0);
3803 if (Domain & ARMII::DomainVFP)
3804 return std::make_pair(ExeVFP, 0);
3806 return std::make_pair(ExeGeneric, 0);
3809 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
3810 unsigned SReg, unsigned &Lane) {
3811 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
3814 if (DReg != ARM::NoRegister)
3818 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
3820 assert(DReg && "S-register with no D super-register?");
3824 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
3825 /// set ImplicitSReg to a register number that must be marked as implicit-use or
3826 /// zero if no register needs to be defined as implicit-use.
3828 /// If the function cannot determine if an SPR should be marked implicit use or
3829 /// not, it returns false.
3831 /// This function handles cases where an instruction is being modified from taking
3832 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
3833 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
3834 /// lane of the DPR).
3836 /// If the other SPR is defined, an implicit-use of it should be added. Else,
3837 /// (including the case where the DPR itself is defined), it should not.
3839 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
3841 unsigned DReg, unsigned Lane,
3842 unsigned &ImplicitSReg) {
3843 // If the DPR is defined or used already, the other SPR lane will be chained
3844 // correctly, so there is nothing to be done.
3845 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
3850 // Otherwise we need to go searching to see if the SPR is set explicitly.
3851 ImplicitSReg = TRI->getSubReg(DReg,
3852 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
3853 MachineBasicBlock::LivenessQueryResult LQR =
3854 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
3856 if (LQR == MachineBasicBlock::LQR_Live)
3858 else if (LQR == MachineBasicBlock::LQR_Unknown)
3861 // If the register is known not to be live, there is no need to add an
3868 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3869 unsigned DstReg, SrcReg, DReg;
3871 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3872 const TargetRegisterInfo *TRI = &getRegisterInfo();
3873 switch (MI->getOpcode()) {
3875 llvm_unreachable("cannot handle opcode!");
3878 if (Domain != ExeNEON)
3881 // Zap the predicate operands.
3882 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
3884 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
3885 DstReg = MI->getOperand(0).getReg();
3886 SrcReg = MI->getOperand(1).getReg();
3888 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3889 MI->RemoveOperand(i-1);
3891 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
3892 MI->setDesc(get(ARM::VORRd));
3893 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3898 if (Domain != ExeNEON)
3900 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
3902 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
3903 DstReg = MI->getOperand(0).getReg();
3904 SrcReg = MI->getOperand(1).getReg();
3906 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3907 MI->RemoveOperand(i-1);
3909 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
3911 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
3912 // Note that DSrc has been widened and the other lane may be undef, which
3913 // contaminates the entire register.
3914 MI->setDesc(get(ARM::VGETLNi32));
3915 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3916 .addReg(DReg, RegState::Undef)
3919 // The old source should be an implicit use, otherwise we might think it
3920 // was dead before here.
3921 MIB.addReg(SrcReg, RegState::Implicit);
3924 if (Domain != ExeNEON)
3926 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
3928 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
3929 DstReg = MI->getOperand(0).getReg();
3930 SrcReg = MI->getOperand(1).getReg();
3932 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
3934 unsigned ImplicitSReg;
3935 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
3938 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3939 MI->RemoveOperand(i-1);
3941 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
3942 // Again DDst may be undefined at the beginning of this instruction.
3943 MI->setDesc(get(ARM::VSETLNi32));
3944 MIB.addReg(DReg, RegState::Define)
3945 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
3948 AddDefaultPred(MIB);
3950 // The narrower destination must be marked as set to keep previous chains
3952 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3953 if (ImplicitSReg != 0)
3954 MIB.addReg(ImplicitSReg, RegState::Implicit);
3958 if (Domain != ExeNEON)
3961 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
3962 DstReg = MI->getOperand(0).getReg();
3963 SrcReg = MI->getOperand(1).getReg();
3965 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
3966 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
3967 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
3969 unsigned ImplicitSReg;
3970 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
3973 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
3974 MI->RemoveOperand(i-1);
3977 // Destination can be:
3978 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
3979 MI->setDesc(get(ARM::VDUPLN32d));
3980 MIB.addReg(DDst, RegState::Define)
3981 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
3983 AddDefaultPred(MIB);
3985 // Neither the source or the destination are naturally represented any
3986 // more, so add them in manually.
3987 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
3988 MIB.addReg(SrcReg, RegState::Implicit);
3989 if (ImplicitSReg != 0)
3990 MIB.addReg(ImplicitSReg, RegState::Implicit);
3994 // In general there's no single instruction that can perform an S <-> S
3995 // move in NEON space, but a pair of VEXT instructions *can* do the
3996 // job. It turns out that the VEXTs needed will only use DSrc once, with
3997 // the position based purely on the combination of lane-0 and lane-1
3998 // involved. For example
3999 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4000 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4001 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4002 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4004 // Pattern of the MachineInstrs is:
4005 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4006 MachineInstrBuilder NewMIB;
4007 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4008 get(ARM::VEXTd32), DDst);
4010 // On the first instruction, both DSrc and DDst may be <undef> if present.
4011 // Specifically when the original instruction didn't have them as an
4013 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4014 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4015 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4017 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4018 CurUndef = !MI->readsRegister(CurReg, TRI);
4019 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4022 AddDefaultPred(NewMIB);
4024 if (SrcLane == DstLane)
4025 NewMIB.addReg(SrcReg, RegState::Implicit);
4027 MI->setDesc(get(ARM::VEXTd32));
4028 MIB.addReg(DDst, RegState::Define);
4030 // On the second instruction, DDst has definitely been defined above, so
4031 // it is not <undef>. DSrc, if present, can be <undef> as above.
4032 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4033 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4034 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4036 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4037 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4038 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4041 AddDefaultPred(MIB);
4043 if (SrcLane != DstLane)
4044 MIB.addReg(SrcReg, RegState::Implicit);
4046 // As before, the original destination is no longer represented, add it
4048 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4049 if (ImplicitSReg != 0)
4050 MIB.addReg(ImplicitSReg, RegState::Implicit);
4057 //===----------------------------------------------------------------------===//
4058 // Partial register updates
4059 //===----------------------------------------------------------------------===//
4061 // Swift renames NEON registers with 64-bit granularity. That means any
4062 // instruction writing an S-reg implicitly reads the containing D-reg. The
4063 // problem is mostly avoided by translating f32 operations to v2f32 operations
4064 // on D-registers, but f32 loads are still a problem.
4066 // These instructions can load an f32 into a NEON register:
4068 // VLDRS - Only writes S, partial D update.
4069 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4070 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4072 // FCONSTD can be used as a dependency-breaking instruction.
4073 unsigned ARMBaseInstrInfo::
4074 getPartialRegUpdateClearance(const MachineInstr *MI,
4076 const TargetRegisterInfo *TRI) const {
4077 if (!SwiftPartialUpdateClearance ||
4078 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4081 assert(TRI && "Need TRI instance");
4083 const MachineOperand &MO = MI->getOperand(OpNum);
4086 unsigned Reg = MO.getReg();
4089 switch(MI->getOpcode()) {
4090 // Normal instructions writing only an S-register.
4095 case ARM::VMOVv4i16:
4096 case ARM::VMOVv2i32:
4097 case ARM::VMOVv2f32:
4098 case ARM::VMOVv1i64:
4099 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4102 // Explicitly reads the dependency.
4103 case ARM::VLD1LNd32:
4110 // If this instruction actually reads a value from Reg, there is no unwanted
4112 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4115 // We must be able to clobber the whole D-reg.
4116 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4117 // Virtual register must be a foo:ssub_0<def,undef> operand.
4118 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4120 } else if (ARM::SPRRegClass.contains(Reg)) {
4121 // Physical register: MI must define the full D-reg.
4122 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4124 if (!DReg || !MI->definesRegister(DReg, TRI))
4128 // MI has an unwanted D-register dependency.
4129 // Avoid defs in the previous N instructrions.
4130 return SwiftPartialUpdateClearance;
4133 // Break a partial register dependency after getPartialRegUpdateClearance
4134 // returned non-zero.
4135 void ARMBaseInstrInfo::
4136 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4138 const TargetRegisterInfo *TRI) const {
4139 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4140 assert(TRI && "Need TRI instance");
4142 const MachineOperand &MO = MI->getOperand(OpNum);
4143 unsigned Reg = MO.getReg();
4144 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4145 "Can't break virtual register dependencies.");
4146 unsigned DReg = Reg;
4148 // If MI defines an S-reg, find the corresponding D super-register.
4149 if (ARM::SPRRegClass.contains(Reg)) {
4150 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4151 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4154 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4155 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4157 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4158 // the full D-register by loading the same value to both lanes. The
4159 // instruction is micro-coded with 2 uops, so don't do this until we can
4160 // properly schedule micro-coded instructions. The dispatcher stalls cause
4161 // too big regressions.
4163 // Insert the dependency-breaking FCONSTD before MI.
4164 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4165 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4166 get(ARM::FCONSTD), DReg).addImm(96));
4167 MI->addRegisterKilled(DReg, TRI, true);
4170 bool ARMBaseInstrInfo::hasNOP() const {
4171 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4174 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4175 if (MI->getNumOperands() < 4)
4177 unsigned ShOpVal = MI->getOperand(3).getImm();
4178 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4179 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4180 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4181 ((ShImm == 1 || ShImm == 2) &&
4182 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))