1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GlobalValue.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/Support/BranchProbability.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
43 #define DEBUG_TYPE "arm-instrinfo"
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "ARMGenInstrInfo.inc"
49 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
50 cl::desc("Enable ARM 2-addr to 3-addr conv"));
53 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
54 cl::desc("Widen ARM vmovs to vmovd when possible"));
56 static cl::opt<unsigned>
57 SwiftPartialUpdateClearance("swift-partial-update-clearance",
58 cl::Hidden, cl::init(12),
59 cl::desc("Clearance before partial register updates"));
61 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
63 uint16_t MLxOpc; // MLA / MLS opcode
64 uint16_t MulOpc; // Expanded multiplication opcode
65 uint16_t AddSubOpc; // Expanded add / sub opcode
66 bool NegAcc; // True if the acc is negated before the add / sub.
67 bool HasLane; // True if instruction has an extra "lane" operand.
70 static const ARM_MLxEntry ARM_MLxTable[] = {
71 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
73 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
74 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
75 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
76 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
77 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
78 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
79 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
80 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
83 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
84 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
85 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
86 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
87 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
88 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
89 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
90 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
93 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
94 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
96 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
97 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
98 assert(false && "Duplicated entries?");
99 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
100 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
104 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
105 // currently defaults to no prepass hazard recognizer.
106 ScheduleHazardRecognizer *
107 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
108 const ScheduleDAG *DAG) const {
109 if (usePreRAHazardRecognizer()) {
110 const InstrItineraryData *II =
111 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
112 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
114 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
117 ScheduleHazardRecognizer *ARMBaseInstrInfo::
118 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
119 const ScheduleDAG *DAG) const {
120 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
121 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
122 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
126 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
127 MachineBasicBlock::iterator &MBBI,
128 LiveVariables *LV) const {
129 // FIXME: Thumb2 support.
134 MachineInstr *MI = MBBI;
135 MachineFunction &MF = *MI->getParent()->getParent();
136 uint64_t TSFlags = MI->getDesc().TSFlags;
138 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
139 default: return nullptr;
140 case ARMII::IndexModePre:
143 case ARMII::IndexModePost:
147 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
149 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
153 MachineInstr *UpdateMI = nullptr;
154 MachineInstr *MemMI = nullptr;
155 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
156 const MCInstrDesc &MCID = MI->getDesc();
157 unsigned NumOps = MCID.getNumOperands();
158 bool isLoad = !MI->mayStore();
159 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
160 const MachineOperand &Base = MI->getOperand(2);
161 const MachineOperand &Offset = MI->getOperand(NumOps-3);
162 unsigned WBReg = WB.getReg();
163 unsigned BaseReg = Base.getReg();
164 unsigned OffReg = Offset.getReg();
165 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
166 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
168 default: llvm_unreachable("Unknown indexed op!");
169 case ARMII::AddrMode2: {
170 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
171 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
173 if (ARM_AM::getSOImmVal(Amt) == -1)
174 // Can't encode it in a so_imm operand. This transformation will
175 // add more than 1 instruction. Abandon!
177 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
178 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
179 .addReg(BaseReg).addImm(Amt)
180 .addImm(Pred).addReg(0).addReg(0);
181 } else if (Amt != 0) {
182 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
183 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
184 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
185 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
186 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
187 .addImm(Pred).addReg(0).addReg(0);
189 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
190 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
191 .addReg(BaseReg).addReg(OffReg)
192 .addImm(Pred).addReg(0).addReg(0);
195 case ARMII::AddrMode3 : {
196 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
197 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
199 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
200 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
201 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
202 .addReg(BaseReg).addImm(Amt)
203 .addImm(Pred).addReg(0).addReg(0);
205 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
206 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
207 .addReg(BaseReg).addReg(OffReg)
208 .addImm(Pred).addReg(0).addReg(0);
213 std::vector<MachineInstr*> NewMIs;
216 MemMI = BuildMI(MF, MI->getDebugLoc(),
217 get(MemOpc), MI->getOperand(0).getReg())
218 .addReg(WBReg).addImm(0).addImm(Pred);
220 MemMI = BuildMI(MF, MI->getDebugLoc(),
221 get(MemOpc)).addReg(MI->getOperand(1).getReg())
222 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
223 NewMIs.push_back(MemMI);
224 NewMIs.push_back(UpdateMI);
227 MemMI = BuildMI(MF, MI->getDebugLoc(),
228 get(MemOpc), MI->getOperand(0).getReg())
229 .addReg(BaseReg).addImm(0).addImm(Pred);
231 MemMI = BuildMI(MF, MI->getDebugLoc(),
232 get(MemOpc)).addReg(MI->getOperand(1).getReg())
233 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
235 UpdateMI->getOperand(0).setIsDead();
236 NewMIs.push_back(UpdateMI);
237 NewMIs.push_back(MemMI);
240 // Transfer LiveVariables states, kill / dead info.
242 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243 MachineOperand &MO = MI->getOperand(i);
244 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
245 unsigned Reg = MO.getReg();
247 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
249 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
251 LV->addVirtualRegisterDead(Reg, NewMI);
253 if (MO.isUse() && MO.isKill()) {
254 for (unsigned j = 0; j < 2; ++j) {
255 // Look at the two new MI's in reverse order.
256 MachineInstr *NewMI = NewMIs[j];
257 if (!NewMI->readsRegister(Reg))
259 LV->addVirtualRegisterKilled(Reg, NewMI);
260 if (VI.removeKill(MI))
261 VI.Kills.push_back(NewMI);
269 MFI->insert(MBBI, NewMIs[1]);
270 MFI->insert(MBBI, NewMIs[0]);
276 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
277 MachineBasicBlock *&FBB,
278 SmallVectorImpl<MachineOperand> &Cond,
279 bool AllowModify) const {
283 MachineBasicBlock::iterator I = MBB.end();
284 if (I == MBB.begin())
285 return false; // Empty blocks are easy.
288 // Walk backwards from the end of the basic block until the branch is
289 // analyzed or we give up.
290 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
292 // Flag to be raised on unanalyzeable instructions. This is useful in cases
293 // where we want to clean up on the end of the basic block before we bail
295 bool CantAnalyze = false;
297 // Skip over DEBUG values and predicated nonterminators.
298 while (I->isDebugValue() || !I->isTerminator()) {
299 if (I == MBB.begin())
304 if (isIndirectBranchOpcode(I->getOpcode()) ||
305 isJumpTableBranchOpcode(I->getOpcode())) {
306 // Indirect branches and jump tables can't be analyzed, but we still want
307 // to clean up any instructions at the tail of the basic block.
309 } else if (isUncondBranchOpcode(I->getOpcode())) {
310 TBB = I->getOperand(0).getMBB();
311 } else if (isCondBranchOpcode(I->getOpcode())) {
312 // Bail out if we encounter multiple conditional branches.
316 assert(!FBB && "FBB should have been null.");
318 TBB = I->getOperand(0).getMBB();
319 Cond.push_back(I->getOperand(1));
320 Cond.push_back(I->getOperand(2));
321 } else if (I->isReturn()) {
322 // Returns can't be analyzed, but we should run cleanup.
323 CantAnalyze = !isPredicated(I);
325 // We encountered other unrecognized terminator. Bail out immediately.
329 // Cleanup code - to be run for unpredicated unconditional branches and
331 if (!isPredicated(I) &&
332 (isUncondBranchOpcode(I->getOpcode()) ||
333 isIndirectBranchOpcode(I->getOpcode()) ||
334 isJumpTableBranchOpcode(I->getOpcode()) ||
336 // Forget any previous condition branch information - it no longer applies.
340 // If we can modify the function, delete everything below this
341 // unconditional branch.
343 MachineBasicBlock::iterator DI = std::next(I);
344 while (DI != MBB.end()) {
345 MachineInstr *InstToDelete = DI;
347 InstToDelete->eraseFromParent();
355 if (I == MBB.begin())
361 // We made it past the terminators without bailing out - we must have
362 // analyzed this branch successfully.
367 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
368 MachineBasicBlock::iterator I = MBB.end();
369 if (I == MBB.begin()) return 0;
371 while (I->isDebugValue()) {
372 if (I == MBB.begin())
376 if (!isUncondBranchOpcode(I->getOpcode()) &&
377 !isCondBranchOpcode(I->getOpcode()))
380 // Remove the branch.
381 I->eraseFromParent();
385 if (I == MBB.begin()) return 1;
387 if (!isCondBranchOpcode(I->getOpcode()))
390 // Remove the branch.
391 I->eraseFromParent();
396 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
397 MachineBasicBlock *FBB,
398 const SmallVectorImpl<MachineOperand> &Cond,
400 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
401 int BOpc = !AFI->isThumbFunction()
402 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
403 int BccOpc = !AFI->isThumbFunction()
404 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
405 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
407 // Shouldn't be a fall through.
408 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
409 assert((Cond.size() == 2 || Cond.size() == 0) &&
410 "ARM branch conditions have two components!");
413 if (Cond.empty()) { // Unconditional branch?
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
424 // Two-way conditional branch.
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
434 bool ARMBaseInstrInfo::
435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI;
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
457 bool ARMBaseInstrInfo::
458 PredicateInstruction(MachineInstr *MI,
459 const SmallVectorImpl<MachineOperand> &Pred) const {
460 unsigned Opc = MI->getOpcode();
461 if (isUncondBranchOpcode(Opc)) {
462 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
463 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
464 .addImm(Pred[0].getImm())
465 .addReg(Pred[1].getReg());
469 int PIdx = MI->findFirstPredOperandIdx();
471 MachineOperand &PMO = MI->getOperand(PIdx);
472 PMO.setImm(Pred[0].getImm());
473 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
479 bool ARMBaseInstrInfo::
480 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
481 const SmallVectorImpl<MachineOperand> &Pred2) const {
482 if (Pred1.size() > 2 || Pred2.size() > 2)
485 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
486 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
496 return CC2 == ARMCC::HI;
498 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
500 return CC2 == ARMCC::GT;
502 return CC2 == ARMCC::LT;
506 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
507 std::vector<MachineOperand> &Pred) const {
509 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
510 const MachineOperand &MO = MI->getOperand(i);
511 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
512 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
521 static bool isCPSRDefined(const MachineInstr *MI) {
522 for (const auto &MO : MI->operands())
523 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef())
528 static bool isEligibleForITBlock(const MachineInstr *MI) {
529 switch (MI->getOpcode()) {
530 default: return true;
531 case ARM::tADC: // ADC (register) T1
532 case ARM::tADDi3: // ADD (immediate) T1
533 case ARM::tADDi8: // ADD (immediate) T2
534 case ARM::tADDrr: // ADD (register) T1
535 case ARM::tAND: // AND (register) T1
536 case ARM::tASRri: // ASR (immediate) T1
537 case ARM::tASRrr: // ASR (register) T1
538 case ARM::tBIC: // BIC (register) T1
539 case ARM::tEOR: // EOR (register) T1
540 case ARM::tLSLri: // LSL (immediate) T1
541 case ARM::tLSLrr: // LSL (register) T1
542 case ARM::tLSRri: // LSR (immediate) T1
543 case ARM::tLSRrr: // LSR (register) T1
544 case ARM::tMUL: // MUL T1
545 case ARM::tMVN: // MVN (register) T1
546 case ARM::tORR: // ORR (register) T1
547 case ARM::tROR: // ROR (register) T1
548 case ARM::tRSB: // RSB (immediate) T1
549 case ARM::tSBC: // SBC (register) T1
550 case ARM::tSUBi3: // SUB (immediate) T1
551 case ARM::tSUBi8: // SUB (immediate) T2
552 case ARM::tSUBrr: // SUB (register) T1
553 return !isCPSRDefined(MI);
557 /// isPredicable - Return true if the specified instruction can be predicated.
558 /// By default, this returns true for every instruction with a
559 /// PredicateOperand.
560 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
561 if (!MI->isPredicable())
564 if (!isEligibleForITBlock(MI))
567 ARMFunctionInfo *AFI =
568 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
570 if (AFI->isThumb2Function()) {
571 if (getSubtarget().restrictIT())
572 return isV8EligibleForIT(MI);
573 } else { // non-Thumb
574 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
582 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
583 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
584 const MachineOperand &MO = MI->getOperand(i);
585 if (!MO.isReg() || MO.isUndef() || MO.isUse())
587 if (MO.getReg() != ARM::CPSR)
592 // all definitions of CPSR are dead
597 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing.
598 LLVM_ATTRIBUTE_NOINLINE
599 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
601 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
603 assert(JTI < JT.size());
604 return JT[JTI].MBBs.size();
607 /// GetInstSize - Return the size of the specified MachineInstr.
609 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
610 const MachineBasicBlock &MBB = *MI->getParent();
611 const MachineFunction *MF = MBB.getParent();
612 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
614 const MCInstrDesc &MCID = MI->getDesc();
616 return MCID.getSize();
618 // If this machine instr is an inline asm, measure it.
619 if (MI->getOpcode() == ARM::INLINEASM)
620 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
621 unsigned Opc = MI->getOpcode();
624 // pseudo-instruction sizes are zero.
626 case TargetOpcode::BUNDLE:
627 return getInstBundleLength(MI);
628 case ARM::MOVi16_ga_pcrel:
629 case ARM::MOVTi16_ga_pcrel:
630 case ARM::t2MOVi16_ga_pcrel:
631 case ARM::t2MOVTi16_ga_pcrel:
634 case ARM::t2MOVi32imm:
636 case ARM::CONSTPOOL_ENTRY:
637 // If this machine instr is a constant pool entry, its size is recorded as
639 return MI->getOperand(2).getImm();
640 case ARM::Int_eh_sjlj_longjmp:
642 case ARM::tInt_eh_sjlj_longjmp:
644 case ARM::Int_eh_sjlj_setjmp:
645 case ARM::Int_eh_sjlj_setjmp_nofp:
647 case ARM::tInt_eh_sjlj_setjmp:
648 case ARM::t2Int_eh_sjlj_setjmp:
649 case ARM::t2Int_eh_sjlj_setjmp_nofp:
657 case ARM::t2TBH_JT: {
658 // These are jumptable branches, i.e. a branch followed by an inlined
659 // jumptable. The size is 4 + 4 * number of entries. For TBB, each
660 // entry is one byte; TBH two byte each.
661 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
662 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
663 unsigned NumOps = MCID.getNumOperands();
664 MachineOperand JTOP =
665 MI->getOperand(NumOps - (MI->isPredicable() ? 3 : 2));
666 unsigned JTI = JTOP.getIndex();
667 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
668 assert(MJTI != nullptr);
669 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
670 assert(JTI < JT.size());
671 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
672 // 4 aligned. The assembler / linker may add 2 byte padding just before
673 // the JT entries. The size does not include this padding; the
674 // constant islands pass does separate bookkeeping for it.
675 // FIXME: If we know the size of the function is less than (1 << 16) *2
676 // bytes, we can use 16-bit entries instead. Then there won't be an
678 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
679 unsigned NumEntries = getNumJTEntries(JT, JTI);
680 if (Opc == ARM::t2TBB_JT && (NumEntries & 1))
681 // Make sure the instruction that follows TBB is 2-byte aligned.
682 // FIXME: Constant island pass should insert an "ALIGN" instruction
685 return NumEntries * EntrySize + InstSize;
690 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
692 MachineBasicBlock::const_instr_iterator I = MI;
693 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
694 while (++I != E && I->isInsideBundle()) {
695 assert(!I->isBundle() && "No nested bundle!");
696 Size += GetInstSizeInBytes(&*I);
701 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
702 MachineBasicBlock::iterator I, DebugLoc DL,
703 unsigned DestReg, unsigned SrcReg,
704 bool KillSrc) const {
705 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
706 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
708 if (GPRDest && GPRSrc) {
709 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
710 .addReg(SrcReg, getKillRegState(KillSrc))));
714 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
715 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
718 if (SPRDest && SPRSrc)
720 else if (GPRDest && SPRSrc)
722 else if (SPRDest && GPRSrc)
724 else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
726 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
730 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
731 MIB.addReg(SrcReg, getKillRegState(KillSrc));
732 if (Opc == ARM::VORRq)
733 MIB.addReg(SrcReg, getKillRegState(KillSrc));
738 // Handle register classes that require multiple instructions.
739 unsigned BeginIdx = 0;
740 unsigned SubRegs = 0;
743 // Use VORRq when possible.
744 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
746 BeginIdx = ARM::qsub_0;
748 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
750 BeginIdx = ARM::qsub_0;
752 // Fall back to VMOVD.
753 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
755 BeginIdx = ARM::dsub_0;
757 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
759 BeginIdx = ARM::dsub_0;
761 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
763 BeginIdx = ARM::dsub_0;
765 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
766 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
767 BeginIdx = ARM::gsub_0;
769 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
771 BeginIdx = ARM::dsub_0;
774 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
776 BeginIdx = ARM::dsub_0;
779 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
781 BeginIdx = ARM::dsub_0;
786 assert(Opc && "Impossible reg-to-reg copy");
788 const TargetRegisterInfo *TRI = &getRegisterInfo();
789 MachineInstrBuilder Mov;
791 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
792 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
793 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
797 SmallSet<unsigned, 4> DstRegs;
799 for (unsigned i = 0; i != SubRegs; ++i) {
800 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
801 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
802 assert(Dst && Src && "Bad sub-register");
804 assert(!DstRegs.count(Src) && "destructive vector copy");
807 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
808 // VORR takes two source operands.
809 if (Opc == ARM::VORRq)
811 Mov = AddDefaultPred(Mov);
813 if (Opc == ARM::MOVr)
814 Mov = AddDefaultCC(Mov);
816 // Add implicit super-register defs and kills to the last instruction.
817 Mov->addRegisterDefined(DestReg, TRI);
819 Mov->addRegisterKilled(SrcReg, TRI);
822 const MachineInstrBuilder &
823 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
824 unsigned SubIdx, unsigned State,
825 const TargetRegisterInfo *TRI) const {
827 return MIB.addReg(Reg, State);
829 if (TargetRegisterInfo::isPhysicalRegister(Reg))
830 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
831 return MIB.addReg(Reg, State, SubIdx);
834 void ARMBaseInstrInfo::
835 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
836 unsigned SrcReg, bool isKill, int FI,
837 const TargetRegisterClass *RC,
838 const TargetRegisterInfo *TRI) const {
840 if (I != MBB.end()) DL = I->getDebugLoc();
841 MachineFunction &MF = *MBB.getParent();
842 MachineFrameInfo &MFI = *MF.getFrameInfo();
843 unsigned Align = MFI.getObjectAlignment(FI);
845 MachineMemOperand *MMO =
846 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
847 MachineMemOperand::MOStore,
848 MFI.getObjectSize(FI),
851 switch (RC->getSize()) {
853 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
854 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
855 .addReg(SrcReg, getKillRegState(isKill))
856 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
857 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
858 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
859 .addReg(SrcReg, getKillRegState(isKill))
860 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
862 llvm_unreachable("Unknown reg class!");
865 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
866 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
867 .addReg(SrcReg, getKillRegState(isKill))
868 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
869 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
870 if (Subtarget.hasV5TEOps()) {
871 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
872 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
873 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
874 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
878 // Fallback to STM instruction, which has existed since the dawn of
880 MachineInstrBuilder MIB =
881 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
882 .addFrameIndex(FI).addMemOperand(MMO));
883 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
884 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
887 llvm_unreachable("Unknown reg class!");
890 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
891 // Use aligned spills if the stack can be realigned.
892 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
893 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
894 .addFrameIndex(FI).addImm(16)
895 .addReg(SrcReg, getKillRegState(isKill))
896 .addMemOperand(MMO));
898 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
899 .addReg(SrcReg, getKillRegState(isKill))
901 .addMemOperand(MMO));
904 llvm_unreachable("Unknown reg class!");
907 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
908 // Use aligned spills if the stack can be realigned.
909 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
910 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
911 .addFrameIndex(FI).addImm(16)
912 .addReg(SrcReg, getKillRegState(isKill))
913 .addMemOperand(MMO));
915 MachineInstrBuilder MIB =
916 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
919 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
920 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
921 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
924 llvm_unreachable("Unknown reg class!");
927 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
928 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
929 // FIXME: It's possible to only store part of the QQ register if the
930 // spilled def has a sub-register index.
931 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
932 .addFrameIndex(FI).addImm(16)
933 .addReg(SrcReg, getKillRegState(isKill))
934 .addMemOperand(MMO));
936 MachineInstrBuilder MIB =
937 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
940 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
941 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
942 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
943 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
946 llvm_unreachable("Unknown reg class!");
949 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
950 MachineInstrBuilder MIB =
951 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
954 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
955 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
956 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
957 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
958 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
959 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
960 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
961 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
963 llvm_unreachable("Unknown reg class!");
966 llvm_unreachable("Unknown reg class!");
971 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
972 int &FrameIndex) const {
973 switch (MI->getOpcode()) {
976 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
977 if (MI->getOperand(1).isFI() &&
978 MI->getOperand(2).isReg() &&
979 MI->getOperand(3).isImm() &&
980 MI->getOperand(2).getReg() == 0 &&
981 MI->getOperand(3).getImm() == 0) {
982 FrameIndex = MI->getOperand(1).getIndex();
983 return MI->getOperand(0).getReg();
991 if (MI->getOperand(1).isFI() &&
992 MI->getOperand(2).isImm() &&
993 MI->getOperand(2).getImm() == 0) {
994 FrameIndex = MI->getOperand(1).getIndex();
995 return MI->getOperand(0).getReg();
999 case ARM::VST1d64TPseudo:
1000 case ARM::VST1d64QPseudo:
1001 if (MI->getOperand(0).isFI() &&
1002 MI->getOperand(2).getSubReg() == 0) {
1003 FrameIndex = MI->getOperand(0).getIndex();
1004 return MI->getOperand(2).getReg();
1008 if (MI->getOperand(1).isFI() &&
1009 MI->getOperand(0).getSubReg() == 0) {
1010 FrameIndex = MI->getOperand(1).getIndex();
1011 return MI->getOperand(0).getReg();
1019 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1020 int &FrameIndex) const {
1021 const MachineMemOperand *Dummy;
1022 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1025 void ARMBaseInstrInfo::
1026 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1027 unsigned DestReg, int FI,
1028 const TargetRegisterClass *RC,
1029 const TargetRegisterInfo *TRI) const {
1031 if (I != MBB.end()) DL = I->getDebugLoc();
1032 MachineFunction &MF = *MBB.getParent();
1033 MachineFrameInfo &MFI = *MF.getFrameInfo();
1034 unsigned Align = MFI.getObjectAlignment(FI);
1035 MachineMemOperand *MMO =
1036 MF.getMachineMemOperand(
1037 MachinePointerInfo::getFixedStack(FI),
1038 MachineMemOperand::MOLoad,
1039 MFI.getObjectSize(FI),
1042 switch (RC->getSize()) {
1044 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1045 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1046 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1048 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1049 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1050 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1052 llvm_unreachable("Unknown reg class!");
1055 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1056 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1057 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1058 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1059 MachineInstrBuilder MIB;
1061 if (Subtarget.hasV5TEOps()) {
1062 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1063 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1064 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1065 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1067 AddDefaultPred(MIB);
1069 // Fallback to LDM instruction, which has existed since the dawn of
1071 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1072 .addFrameIndex(FI).addMemOperand(MMO));
1073 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1074 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1077 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1078 MIB.addReg(DestReg, RegState::ImplicitDefine);
1080 llvm_unreachable("Unknown reg class!");
1083 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1084 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1085 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1086 .addFrameIndex(FI).addImm(16)
1087 .addMemOperand(MMO));
1089 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1091 .addMemOperand(MMO));
1094 llvm_unreachable("Unknown reg class!");
1097 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1098 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1099 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1100 .addFrameIndex(FI).addImm(16)
1101 .addMemOperand(MMO));
1103 MachineInstrBuilder MIB =
1104 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1106 .addMemOperand(MMO));
1107 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1108 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1109 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1110 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1111 MIB.addReg(DestReg, RegState::ImplicitDefine);
1114 llvm_unreachable("Unknown reg class!");
1117 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1118 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1119 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1120 .addFrameIndex(FI).addImm(16)
1121 .addMemOperand(MMO));
1123 MachineInstrBuilder MIB =
1124 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1126 .addMemOperand(MMO);
1127 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1128 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1129 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1130 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1131 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1132 MIB.addReg(DestReg, RegState::ImplicitDefine);
1135 llvm_unreachable("Unknown reg class!");
1138 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1139 MachineInstrBuilder MIB =
1140 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1142 .addMemOperand(MMO);
1143 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1144 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1145 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1146 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1147 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1148 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1149 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1150 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1151 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1152 MIB.addReg(DestReg, RegState::ImplicitDefine);
1154 llvm_unreachable("Unknown reg class!");
1157 llvm_unreachable("Unknown regclass!");
1162 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1163 int &FrameIndex) const {
1164 switch (MI->getOpcode()) {
1167 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1168 if (MI->getOperand(1).isFI() &&
1169 MI->getOperand(2).isReg() &&
1170 MI->getOperand(3).isImm() &&
1171 MI->getOperand(2).getReg() == 0 &&
1172 MI->getOperand(3).getImm() == 0) {
1173 FrameIndex = MI->getOperand(1).getIndex();
1174 return MI->getOperand(0).getReg();
1182 if (MI->getOperand(1).isFI() &&
1183 MI->getOperand(2).isImm() &&
1184 MI->getOperand(2).getImm() == 0) {
1185 FrameIndex = MI->getOperand(1).getIndex();
1186 return MI->getOperand(0).getReg();
1190 case ARM::VLD1d64TPseudo:
1191 case ARM::VLD1d64QPseudo:
1192 if (MI->getOperand(1).isFI() &&
1193 MI->getOperand(0).getSubReg() == 0) {
1194 FrameIndex = MI->getOperand(1).getIndex();
1195 return MI->getOperand(0).getReg();
1199 if (MI->getOperand(1).isFI() &&
1200 MI->getOperand(0).getSubReg() == 0) {
1201 FrameIndex = MI->getOperand(1).getIndex();
1202 return MI->getOperand(0).getReg();
1210 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1211 int &FrameIndex) const {
1212 const MachineMemOperand *Dummy;
1213 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1217 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1218 MachineFunction &MF = *MI->getParent()->getParent();
1219 Reloc::Model RM = MF.getTarget().getRelocationModel();
1221 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1222 assert(getSubtarget().getTargetTriple().getObjectFormat() ==
1224 "LOAD_STACK_GUARD currently supported only for MachO.");
1225 expandLoadStackGuard(MI, RM);
1226 MI->getParent()->erase(MI);
1230 // This hook gets to expand COPY instructions before they become
1231 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1232 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1233 // changed into a VORR that can go down the NEON pipeline.
1234 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15())
1237 // Look for a copy between even S-registers. That is where we keep floats
1238 // when using NEON v2f32 instructions for f32 arithmetic.
1239 unsigned DstRegS = MI->getOperand(0).getReg();
1240 unsigned SrcRegS = MI->getOperand(1).getReg();
1241 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1244 const TargetRegisterInfo *TRI = &getRegisterInfo();
1245 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1247 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1249 if (!DstRegD || !SrcRegD)
1252 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1253 // legal if the COPY already defines the full DstRegD, and it isn't a
1254 // sub-register insertion.
1255 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1258 // A dead copy shouldn't show up here, but reject it just in case.
1259 if (MI->getOperand(0).isDead())
1262 // All clear, widen the COPY.
1263 DEBUG(dbgs() << "widening: " << *MI);
1264 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1266 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1267 // or some other super-register.
1268 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1269 if (ImpDefIdx != -1)
1270 MI->RemoveOperand(ImpDefIdx);
1272 // Change the opcode and operands.
1273 MI->setDesc(get(ARM::VMOVD));
1274 MI->getOperand(0).setReg(DstRegD);
1275 MI->getOperand(1).setReg(SrcRegD);
1276 AddDefaultPred(MIB);
1278 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1279 // register scavenger and machine verifier, so we need to indicate that we
1280 // are reading an undefined value from SrcRegD, but a proper value from
1282 MI->getOperand(1).setIsUndef();
1283 MIB.addReg(SrcRegS, RegState::Implicit);
1285 // SrcRegD may actually contain an unrelated value in the ssub_1
1286 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1287 if (MI->getOperand(1).isKill()) {
1288 MI->getOperand(1).setIsKill(false);
1289 MI->addRegisterKilled(SrcRegS, TRI, true);
1292 DEBUG(dbgs() << "replaced by: " << *MI);
1296 /// Create a copy of a const pool value. Update CPI to the new index and return
1298 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1299 MachineConstantPool *MCP = MF.getConstantPool();
1300 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1302 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1303 assert(MCPE.isMachineConstantPoolEntry() &&
1304 "Expecting a machine constantpool entry!");
1305 ARMConstantPoolValue *ACPV =
1306 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1308 unsigned PCLabelId = AFI->createPICLabelUId();
1309 ARMConstantPoolValue *NewCPV = nullptr;
1311 // FIXME: The below assumes PIC relocation model and that the function
1312 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1313 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1314 // instructions, so that's probably OK, but is PIC always correct when
1316 if (ACPV->isGlobalValue())
1317 NewCPV = ARMConstantPoolConstant::
1318 Create(cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId,
1320 else if (ACPV->isExtSymbol())
1321 NewCPV = ARMConstantPoolSymbol::
1322 Create(MF.getFunction()->getContext(),
1323 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1324 else if (ACPV->isBlockAddress())
1325 NewCPV = ARMConstantPoolConstant::
1326 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1327 ARMCP::CPBlockAddress, 4);
1328 else if (ACPV->isLSDA())
1329 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1331 else if (ACPV->isMachineBasicBlock())
1332 NewCPV = ARMConstantPoolMBB::
1333 Create(MF.getFunction()->getContext(),
1334 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1336 llvm_unreachable("Unexpected ARM constantpool value type!!");
1337 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1341 void ARMBaseInstrInfo::
1342 reMaterialize(MachineBasicBlock &MBB,
1343 MachineBasicBlock::iterator I,
1344 unsigned DestReg, unsigned SubIdx,
1345 const MachineInstr *Orig,
1346 const TargetRegisterInfo &TRI) const {
1347 unsigned Opcode = Orig->getOpcode();
1350 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1351 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1355 case ARM::tLDRpci_pic:
1356 case ARM::t2LDRpci_pic: {
1357 MachineFunction &MF = *MBB.getParent();
1358 unsigned CPI = Orig->getOperand(1).getIndex();
1359 unsigned PCLabelId = duplicateCPV(MF, CPI);
1360 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1362 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1363 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1370 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1371 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1372 switch(Orig->getOpcode()) {
1373 case ARM::tLDRpci_pic:
1374 case ARM::t2LDRpci_pic: {
1375 unsigned CPI = Orig->getOperand(1).getIndex();
1376 unsigned PCLabelId = duplicateCPV(MF, CPI);
1377 Orig->getOperand(1).setIndex(CPI);
1378 Orig->getOperand(2).setImm(PCLabelId);
1385 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1386 const MachineInstr *MI1,
1387 const MachineRegisterInfo *MRI) const {
1388 int Opcode = MI0->getOpcode();
1389 if (Opcode == ARM::t2LDRpci ||
1390 Opcode == ARM::t2LDRpci_pic ||
1391 Opcode == ARM::tLDRpci ||
1392 Opcode == ARM::tLDRpci_pic ||
1393 Opcode == ARM::LDRLIT_ga_pcrel ||
1394 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1395 Opcode == ARM::tLDRLIT_ga_pcrel ||
1396 Opcode == ARM::MOV_ga_pcrel ||
1397 Opcode == ARM::MOV_ga_pcrel_ldr ||
1398 Opcode == ARM::t2MOV_ga_pcrel) {
1399 if (MI1->getOpcode() != Opcode)
1401 if (MI0->getNumOperands() != MI1->getNumOperands())
1404 const MachineOperand &MO0 = MI0->getOperand(1);
1405 const MachineOperand &MO1 = MI1->getOperand(1);
1406 if (MO0.getOffset() != MO1.getOffset())
1409 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1410 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1411 Opcode == ARM::tLDRLIT_ga_pcrel ||
1412 Opcode == ARM::MOV_ga_pcrel ||
1413 Opcode == ARM::MOV_ga_pcrel_ldr ||
1414 Opcode == ARM::t2MOV_ga_pcrel)
1415 // Ignore the PC labels.
1416 return MO0.getGlobal() == MO1.getGlobal();
1418 const MachineFunction *MF = MI0->getParent()->getParent();
1419 const MachineConstantPool *MCP = MF->getConstantPool();
1420 int CPI0 = MO0.getIndex();
1421 int CPI1 = MO1.getIndex();
1422 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1423 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1424 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1425 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1426 if (isARMCP0 && isARMCP1) {
1427 ARMConstantPoolValue *ACPV0 =
1428 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1429 ARMConstantPoolValue *ACPV1 =
1430 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1431 return ACPV0->hasSameValue(ACPV1);
1432 } else if (!isARMCP0 && !isARMCP1) {
1433 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1436 } else if (Opcode == ARM::PICLDR) {
1437 if (MI1->getOpcode() != Opcode)
1439 if (MI0->getNumOperands() != MI1->getNumOperands())
1442 unsigned Addr0 = MI0->getOperand(1).getReg();
1443 unsigned Addr1 = MI1->getOperand(1).getReg();
1444 if (Addr0 != Addr1) {
1446 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1447 !TargetRegisterInfo::isVirtualRegister(Addr1))
1450 // This assumes SSA form.
1451 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1452 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1453 // Check if the loaded value, e.g. a constantpool of a global address, are
1455 if (!produceSameValue(Def0, Def1, MRI))
1459 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1460 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1461 const MachineOperand &MO0 = MI0->getOperand(i);
1462 const MachineOperand &MO1 = MI1->getOperand(i);
1463 if (!MO0.isIdenticalTo(MO1))
1469 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1472 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1473 /// determine if two loads are loading from the same base address. It should
1474 /// only return true if the base pointers are the same and the only differences
1475 /// between the two addresses is the offset. It also returns the offsets by
1478 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1479 /// is permanently disabled.
1480 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1482 int64_t &Offset2) const {
1483 // Don't worry about Thumb: just ARM and Thumb2.
1484 if (Subtarget.isThumb1Only()) return false;
1486 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1489 switch (Load1->getMachineOpcode()) {
1503 case ARM::t2LDRSHi8:
1505 case ARM::t2LDRBi12:
1506 case ARM::t2LDRSHi12:
1510 switch (Load2->getMachineOpcode()) {
1523 case ARM::t2LDRSHi8:
1525 case ARM::t2LDRBi12:
1526 case ARM::t2LDRSHi12:
1530 // Check if base addresses and chain operands match.
1531 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1532 Load1->getOperand(4) != Load2->getOperand(4))
1535 // Index should be Reg0.
1536 if (Load1->getOperand(3) != Load2->getOperand(3))
1539 // Determine the offsets.
1540 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1541 isa<ConstantSDNode>(Load2->getOperand(1))) {
1542 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1543 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1550 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1551 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1552 /// be scheduled togther. On some targets if two loads are loading from
1553 /// addresses in the same cache line, it's better if they are scheduled
1554 /// together. This function takes two integers that represent the load offsets
1555 /// from the common base address. It returns true if it decides it's desirable
1556 /// to schedule the two loads together. "NumLoads" is the number of loads that
1557 /// have already been scheduled after Load1.
1559 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1560 /// is permanently disabled.
1561 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1562 int64_t Offset1, int64_t Offset2,
1563 unsigned NumLoads) const {
1564 // Don't worry about Thumb: just ARM and Thumb2.
1565 if (Subtarget.isThumb1Only()) return false;
1567 assert(Offset2 > Offset1);
1569 if ((Offset2 - Offset1) / 8 > 64)
1572 // Check if the machine opcodes are different. If they are different
1573 // then we consider them to not be of the same base address,
1574 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1575 // In this case, they are considered to be the same because they are different
1576 // encoding forms of the same basic instruction.
1577 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1578 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1579 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1580 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1581 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1582 return false; // FIXME: overly conservative?
1584 // Four loads in a row should be sufficient.
1591 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1592 const MachineBasicBlock *MBB,
1593 const MachineFunction &MF) const {
1594 // Debug info is never a scheduling boundary. It's necessary to be explicit
1595 // due to the special treatment of IT instructions below, otherwise a
1596 // dbg_value followed by an IT will result in the IT instruction being
1597 // considered a scheduling hazard, which is wrong. It should be the actual
1598 // instruction preceding the dbg_value instruction(s), just like it is
1599 // when debug info is not present.
1600 if (MI->isDebugValue())
1603 // Terminators and labels can't be scheduled around.
1604 if (MI->isTerminator() || MI->isPosition())
1607 // Treat the start of the IT block as a scheduling boundary, but schedule
1608 // t2IT along with all instructions following it.
1609 // FIXME: This is a big hammer. But the alternative is to add all potential
1610 // true and anti dependencies to IT block instructions as implicit operands
1611 // to the t2IT instruction. The added compile time and complexity does not
1613 MachineBasicBlock::const_iterator I = MI;
1614 // Make sure to skip any dbg_value instructions
1615 while (++I != MBB->end() && I->isDebugValue())
1617 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1620 // Don't attempt to schedule around any instruction that defines
1621 // a stack-oriented pointer, as it's unlikely to be profitable. This
1622 // saves compile time, because it doesn't require every single
1623 // stack slot reference to depend on the instruction that does the
1625 // Calls don't actually change the stack pointer, even if they have imp-defs.
1626 // No ARM calling conventions change the stack pointer. (X86 calling
1627 // conventions sometimes do).
1628 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1634 bool ARMBaseInstrInfo::
1635 isProfitableToIfCvt(MachineBasicBlock &MBB,
1636 unsigned NumCycles, unsigned ExtraPredCycles,
1637 const BranchProbability &Probability) const {
1641 // Attempt to estimate the relative costs of predication versus branching.
1642 unsigned UnpredCost = Probability.getNumerator() * NumCycles;
1643 UnpredCost /= Probability.getDenominator();
1644 UnpredCost += 1; // The branch itself
1645 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1647 return (NumCycles + ExtraPredCycles) <= UnpredCost;
1650 bool ARMBaseInstrInfo::
1651 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1652 unsigned TCycles, unsigned TExtra,
1653 MachineBasicBlock &FMBB,
1654 unsigned FCycles, unsigned FExtra,
1655 const BranchProbability &Probability) const {
1656 if (!TCycles || !FCycles)
1659 // Attempt to estimate the relative costs of predication versus branching.
1660 unsigned TUnpredCost = Probability.getNumerator() * TCycles;
1661 TUnpredCost /= Probability.getDenominator();
1663 uint32_t Comp = Probability.getDenominator() - Probability.getNumerator();
1664 unsigned FUnpredCost = Comp * FCycles;
1665 FUnpredCost /= Probability.getDenominator();
1667 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1668 UnpredCost += 1; // The branch itself
1669 UnpredCost += Subtarget.getMispredictionPenalty() / 10;
1671 return (TCycles + FCycles + TExtra + FExtra) <= UnpredCost;
1675 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1676 MachineBasicBlock &FMBB) const {
1677 // Reduce false anti-dependencies to let Swift's out-of-order execution
1678 // engine do its thing.
1679 return Subtarget.isSwift();
1682 /// getInstrPredicate - If instruction is predicated, returns its predicate
1683 /// condition, otherwise returns AL. It also returns the condition code
1684 /// register by reference.
1686 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1687 int PIdx = MI->findFirstPredOperandIdx();
1693 PredReg = MI->getOperand(PIdx+1).getReg();
1694 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1698 int llvm::getMatchingCondBranchOpcode(int Opc) {
1703 if (Opc == ARM::t2B)
1706 llvm_unreachable("Unknown unconditional branch opcode!");
1709 /// commuteInstruction - Handle commutable instructions.
1711 ARMBaseInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1712 switch (MI->getOpcode()) {
1714 case ARM::t2MOVCCr: {
1715 // MOVCC can be commuted by inverting the condition.
1716 unsigned PredReg = 0;
1717 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1718 // MOVCC AL can't be inverted. Shouldn't happen.
1719 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1721 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
1724 // After swapping the MOVCC operands, also invert the condition.
1725 MI->getOperand(MI->findFirstPredOperandIdx())
1726 .setImm(ARMCC::getOppositeCondition(CC));
1730 return TargetInstrInfo::commuteInstruction(MI, NewMI);
1733 /// Identify instructions that can be folded into a MOVCC instruction, and
1734 /// return the defining instruction.
1735 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1736 const MachineRegisterInfo &MRI,
1737 const TargetInstrInfo *TII) {
1738 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1740 if (!MRI.hasOneNonDBGUse(Reg))
1742 MachineInstr *MI = MRI.getVRegDef(Reg);
1745 // MI is folded into the MOVCC by predicating it.
1746 if (!MI->isPredicable())
1748 // Check if MI has any non-dead defs or physreg uses. This also detects
1749 // predicated instructions which will be reading CPSR.
1750 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1751 const MachineOperand &MO = MI->getOperand(i);
1752 // Reject frame index operands, PEI can't handle the predicated pseudos.
1753 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1757 // MI can't have any tied operands, that would conflict with predication.
1760 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1762 if (MO.isDef() && !MO.isDead())
1765 bool DontMoveAcrossStores = true;
1766 if (!MI->isSafeToMove(TII, /* AliasAnalysis = */ nullptr,
1767 DontMoveAcrossStores))
1772 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1773 SmallVectorImpl<MachineOperand> &Cond,
1774 unsigned &TrueOp, unsigned &FalseOp,
1775 bool &Optimizable) const {
1776 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1777 "Unknown select instruction");
1782 // 3: Condition code.
1786 Cond.push_back(MI->getOperand(3));
1787 Cond.push_back(MI->getOperand(4));
1788 // We can always fold a def.
1793 MachineInstr *ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1794 bool PreferFalse) const {
1795 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1796 "Unknown select instruction");
1797 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1798 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1799 bool Invert = !DefMI;
1801 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1805 // Find new register class to use.
1806 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1807 unsigned DestReg = MI->getOperand(0).getReg();
1808 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1809 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1812 // Create a new predicated version of DefMI.
1813 // Rfalse is the first use.
1814 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1815 DefMI->getDesc(), DestReg);
1817 // Copy all the DefMI operands, excluding its (null) predicate.
1818 const MCInstrDesc &DefDesc = DefMI->getDesc();
1819 for (unsigned i = 1, e = DefDesc.getNumOperands();
1820 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1821 NewMI.addOperand(DefMI->getOperand(i));
1823 unsigned CondCode = MI->getOperand(3).getImm();
1825 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1827 NewMI.addImm(CondCode);
1828 NewMI.addOperand(MI->getOperand(4));
1830 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1831 if (NewMI->hasOptionalDef())
1832 AddDefaultCC(NewMI);
1834 // The output register value when the predicate is false is an implicit
1835 // register operand tied to the first def.
1836 // The tie makes the register allocator ensure the FalseReg is allocated the
1837 // same register as operand 0.
1838 FalseReg.setImplicit();
1839 NewMI.addOperand(FalseReg);
1840 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1842 // The caller will erase MI, but not DefMI.
1843 DefMI->eraseFromParent();
1847 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1848 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1851 /// This will go away once we can teach tblgen how to set the optional CPSR def
1853 struct AddSubFlagsOpcodePair {
1855 uint16_t MachineOpc;
1858 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1859 {ARM::ADDSri, ARM::ADDri},
1860 {ARM::ADDSrr, ARM::ADDrr},
1861 {ARM::ADDSrsi, ARM::ADDrsi},
1862 {ARM::ADDSrsr, ARM::ADDrsr},
1864 {ARM::SUBSri, ARM::SUBri},
1865 {ARM::SUBSrr, ARM::SUBrr},
1866 {ARM::SUBSrsi, ARM::SUBrsi},
1867 {ARM::SUBSrsr, ARM::SUBrsr},
1869 {ARM::RSBSri, ARM::RSBri},
1870 {ARM::RSBSrsi, ARM::RSBrsi},
1871 {ARM::RSBSrsr, ARM::RSBrsr},
1873 {ARM::t2ADDSri, ARM::t2ADDri},
1874 {ARM::t2ADDSrr, ARM::t2ADDrr},
1875 {ARM::t2ADDSrs, ARM::t2ADDrs},
1877 {ARM::t2SUBSri, ARM::t2SUBri},
1878 {ARM::t2SUBSrr, ARM::t2SUBrr},
1879 {ARM::t2SUBSrs, ARM::t2SUBrs},
1881 {ARM::t2RSBSri, ARM::t2RSBri},
1882 {ARM::t2RSBSrs, ARM::t2RSBrs},
1885 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1886 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1887 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1888 return AddSubFlagsOpcodeMap[i].MachineOpc;
1892 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1893 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1894 unsigned DestReg, unsigned BaseReg, int NumBytes,
1895 ARMCC::CondCodes Pred, unsigned PredReg,
1896 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
1897 if (NumBytes == 0 && DestReg != BaseReg) {
1898 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
1899 .addReg(BaseReg, RegState::Kill)
1900 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1901 .setMIFlags(MIFlags);
1905 bool isSub = NumBytes < 0;
1906 if (isSub) NumBytes = -NumBytes;
1909 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
1910 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
1911 assert(ThisVal && "Didn't extract field correctly");
1913 // We will handle these bits from offset, clear them.
1914 NumBytes &= ~ThisVal;
1916 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
1918 // Build the new ADD / SUB.
1919 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
1920 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
1921 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
1922 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
1923 .setMIFlags(MIFlags);
1928 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
1930 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
1931 Subreg.isValid(); ++Subreg)
1932 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
1933 MachineBasicBlock::LQR_Dead)
1937 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
1938 MachineFunction &MF, MachineInstr *MI,
1939 unsigned NumBytes) {
1940 // This optimisation potentially adds lots of load and store
1941 // micro-operations, it's only really a great benefit to code-size.
1942 if (!MF.getFunction()->getAttributes().hasAttribute(
1943 AttributeSet::FunctionIndex, Attribute::MinSize))
1946 // If only one register is pushed/popped, LLVM can use an LDR/STR
1947 // instead. We can't modify those so make sure we're dealing with an
1948 // instruction we understand.
1949 bool IsPop = isPopOpcode(MI->getOpcode());
1950 bool IsPush = isPushOpcode(MI->getOpcode());
1951 if (!IsPush && !IsPop)
1954 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
1955 MI->getOpcode() == ARM::VLDMDIA_UPD;
1956 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
1957 MI->getOpcode() == ARM::tPOP ||
1958 MI->getOpcode() == ARM::tPOP_RET;
1960 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
1961 MI->getOperand(1).getReg() == ARM::SP)) &&
1962 "trying to fold sp update into non-sp-updating push/pop");
1964 // The VFP push & pop act on D-registers, so we can only fold an adjustment
1965 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
1966 // if this is violated.
1967 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
1970 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
1971 // pred) so the list starts at 4. Thumb1 starts after the predicate.
1972 int RegListIdx = IsT1PushPop ? 2 : 4;
1974 // Calculate the space we'll need in terms of registers.
1975 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
1976 unsigned RD0Reg, RegsNeeded;
1979 RegsNeeded = NumBytes / 8;
1982 RegsNeeded = NumBytes / 4;
1985 // We're going to have to strip all list operands off before
1986 // re-adding them since the order matters, so save the existing ones
1988 SmallVector<MachineOperand, 4> RegList;
1989 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
1990 RegList.push_back(MI->getOperand(i));
1992 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
1993 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
1995 // Now try to find enough space in the reglist to allocate NumBytes.
1996 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
1999 // Pushing any register is completely harmless, mark the
2000 // register involved as undef since we don't care about it in
2002 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2003 false, false, true));
2008 // However, we can only pop an extra register if it's not live. For
2009 // registers live within the function we might clobber a return value
2010 // register; the other way a register can be live here is if it's
2012 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2013 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2014 // can replace isAnySubRegLive().
2015 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2016 isAnySubRegLive(CurReg, TRI, MI)) {
2017 // VFP pops don't allow holes in the register list, so any skip is fatal
2018 // for our transformation. GPR pops do, so we should just keep looking.
2025 // Mark the unimportant registers as <def,dead> in the POP.
2026 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2034 // Finally we know we can profitably perform the optimisation so go
2035 // ahead: strip all existing registers off and add them back again
2036 // in the right order.
2037 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2038 MI->RemoveOperand(i);
2040 // Add the complete list back in.
2041 MachineInstrBuilder MIB(MF, &*MI);
2042 for (int i = RegList.size() - 1; i >= 0; --i)
2043 MIB.addOperand(RegList[i]);
2048 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2049 unsigned FrameReg, int &Offset,
2050 const ARMBaseInstrInfo &TII) {
2051 unsigned Opcode = MI.getOpcode();
2052 const MCInstrDesc &Desc = MI.getDesc();
2053 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2056 // Memory operands in inline assembly always use AddrMode2.
2057 if (Opcode == ARM::INLINEASM)
2058 AddrMode = ARMII::AddrMode2;
2060 if (Opcode == ARM::ADDri) {
2061 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2063 // Turn it into a move.
2064 MI.setDesc(TII.get(ARM::MOVr));
2065 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2066 MI.RemoveOperand(FrameRegIdx+1);
2069 } else if (Offset < 0) {
2072 MI.setDesc(TII.get(ARM::SUBri));
2075 // Common case: small offset, fits into instruction.
2076 if (ARM_AM::getSOImmVal(Offset) != -1) {
2077 // Replace the FrameIndex with sp / fp
2078 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2079 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2084 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2086 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2087 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2089 // We will handle these bits from offset, clear them.
2090 Offset &= ~ThisImmVal;
2092 // Get the properly encoded SOImmVal field.
2093 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2094 "Bit extraction didn't work?");
2095 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2097 unsigned ImmIdx = 0;
2099 unsigned NumBits = 0;
2102 case ARMII::AddrMode_i12: {
2103 ImmIdx = FrameRegIdx + 1;
2104 InstrOffs = MI.getOperand(ImmIdx).getImm();
2108 case ARMII::AddrMode2: {
2109 ImmIdx = FrameRegIdx+2;
2110 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2111 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2116 case ARMII::AddrMode3: {
2117 ImmIdx = FrameRegIdx+2;
2118 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2119 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2124 case ARMII::AddrMode4:
2125 case ARMII::AddrMode6:
2126 // Can't fold any offset even if it's zero.
2128 case ARMII::AddrMode5: {
2129 ImmIdx = FrameRegIdx+1;
2130 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2131 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2138 llvm_unreachable("Unsupported addressing mode!");
2141 Offset += InstrOffs * Scale;
2142 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2148 // Attempt to fold address comp. if opcode has offset bits
2150 // Common case: small offset, fits into instruction.
2151 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2152 int ImmedOffset = Offset / Scale;
2153 unsigned Mask = (1 << NumBits) - 1;
2154 if ((unsigned)Offset <= Mask * Scale) {
2155 // Replace the FrameIndex with sp
2156 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2157 // FIXME: When addrmode2 goes away, this will simplify (like the
2158 // T2 version), as the LDR.i12 versions don't need the encoding
2159 // tricks for the offset value.
2161 if (AddrMode == ARMII::AddrMode_i12)
2162 ImmedOffset = -ImmedOffset;
2164 ImmedOffset |= 1 << NumBits;
2166 ImmOp.ChangeToImmediate(ImmedOffset);
2171 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2172 ImmedOffset = ImmedOffset & Mask;
2174 if (AddrMode == ARMII::AddrMode_i12)
2175 ImmedOffset = -ImmedOffset;
2177 ImmedOffset |= 1 << NumBits;
2179 ImmOp.ChangeToImmediate(ImmedOffset);
2180 Offset &= ~(Mask*Scale);
2184 Offset = (isSub) ? -Offset : Offset;
2188 /// analyzeCompare - For a comparison instruction, return the source registers
2189 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2190 /// compares against in CmpValue. Return true if the comparison instruction
2191 /// can be analyzed.
2192 bool ARMBaseInstrInfo::
2193 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2194 int &CmpMask, int &CmpValue) const {
2195 switch (MI->getOpcode()) {
2199 SrcReg = MI->getOperand(0).getReg();
2202 CmpValue = MI->getOperand(1).getImm();
2206 SrcReg = MI->getOperand(0).getReg();
2207 SrcReg2 = MI->getOperand(1).getReg();
2213 SrcReg = MI->getOperand(0).getReg();
2215 CmpMask = MI->getOperand(1).getImm();
2223 /// isSuitableForMask - Identify a suitable 'and' instruction that
2224 /// operates on the given source register and applies the same mask
2225 /// as a 'tst' instruction. Provide a limited look-through for copies.
2226 /// When successful, MI will hold the found instruction.
2227 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2228 int CmpMask, bool CommonUse) {
2229 switch (MI->getOpcode()) {
2232 if (CmpMask != MI->getOperand(2).getImm())
2234 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2238 // Walk down one instruction which is potentially an 'and'.
2239 const MachineInstr &Copy = *MI;
2240 MachineBasicBlock::iterator AND(
2241 std::next(MachineBasicBlock::iterator(MI)));
2242 if (AND == MI->getParent()->end()) return false;
2244 return isSuitableForMask(MI, Copy.getOperand(0).getReg(),
2252 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2253 /// the condition code if we modify the instructions such that flags are
2255 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2257 default: return ARMCC::AL;
2258 case ARMCC::EQ: return ARMCC::EQ;
2259 case ARMCC::NE: return ARMCC::NE;
2260 case ARMCC::HS: return ARMCC::LS;
2261 case ARMCC::LO: return ARMCC::HI;
2262 case ARMCC::HI: return ARMCC::LO;
2263 case ARMCC::LS: return ARMCC::HS;
2264 case ARMCC::GE: return ARMCC::LE;
2265 case ARMCC::LT: return ARMCC::GT;
2266 case ARMCC::GT: return ARMCC::LT;
2267 case ARMCC::LE: return ARMCC::GE;
2271 /// isRedundantFlagInstr - check whether the first instruction, whose only
2272 /// purpose is to update flags, can be made redundant.
2273 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2274 /// CMPri can be made redundant by SUBri if the operands are the same.
2275 /// This function can be extended later on.
2276 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2277 unsigned SrcReg2, int ImmValue,
2279 if ((CmpI->getOpcode() == ARM::CMPrr ||
2280 CmpI->getOpcode() == ARM::t2CMPrr) &&
2281 (OI->getOpcode() == ARM::SUBrr ||
2282 OI->getOpcode() == ARM::t2SUBrr) &&
2283 ((OI->getOperand(1).getReg() == SrcReg &&
2284 OI->getOperand(2).getReg() == SrcReg2) ||
2285 (OI->getOperand(1).getReg() == SrcReg2 &&
2286 OI->getOperand(2).getReg() == SrcReg)))
2289 if ((CmpI->getOpcode() == ARM::CMPri ||
2290 CmpI->getOpcode() == ARM::t2CMPri) &&
2291 (OI->getOpcode() == ARM::SUBri ||
2292 OI->getOpcode() == ARM::t2SUBri) &&
2293 OI->getOperand(1).getReg() == SrcReg &&
2294 OI->getOperand(2).getImm() == ImmValue)
2299 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2300 /// comparison into one that sets the zero bit in the flags register;
2301 /// Remove a redundant Compare instruction if an earlier instruction can set the
2302 /// flags in the same way as Compare.
2303 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2304 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2305 /// condition code of instructions which use the flags.
2306 bool ARMBaseInstrInfo::
2307 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2308 int CmpMask, int CmpValue,
2309 const MachineRegisterInfo *MRI) const {
2310 // Get the unique definition of SrcReg.
2311 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2312 if (!MI) return false;
2314 // Masked compares sometimes use the same register as the corresponding 'and'.
2315 if (CmpMask != ~0) {
2316 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2318 for (MachineRegisterInfo::use_instr_iterator
2319 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2321 if (UI->getParent() != CmpInstr->getParent()) continue;
2322 MachineInstr *PotentialAND = &*UI;
2323 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2324 isPredicated(PotentialAND))
2329 if (!MI) return false;
2333 // Get ready to iterate backward from CmpInstr.
2334 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2335 B = CmpInstr->getParent()->begin();
2337 // Early exit if CmpInstr is at the beginning of the BB.
2338 if (I == B) return false;
2340 // There are two possible candidates which can be changed to set CPSR:
2341 // One is MI, the other is a SUB instruction.
2342 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2343 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2344 MachineInstr *Sub = nullptr;
2346 // MI is not a candidate for CMPrr.
2348 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2349 // Conservatively refuse to convert an instruction which isn't in the same
2350 // BB as the comparison.
2351 // For CMPri, we need to check Sub, thus we can't return here.
2352 if (CmpInstr->getOpcode() == ARM::CMPri ||
2353 CmpInstr->getOpcode() == ARM::t2CMPri)
2359 // Check that CPSR isn't set between the comparison instruction and the one we
2360 // want to change. At the same time, search for Sub.
2361 const TargetRegisterInfo *TRI = &getRegisterInfo();
2363 for (; I != E; --I) {
2364 const MachineInstr &Instr = *I;
2366 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2367 Instr.readsRegister(ARM::CPSR, TRI))
2368 // This instruction modifies or uses CPSR after the one we want to
2369 // change. We can't do this transformation.
2372 // Check whether CmpInstr can be made redundant by the current instruction.
2373 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2379 // The 'and' is below the comparison instruction.
2383 // Return false if no candidates exist.
2387 // The single candidate is called MI.
2390 // We can't use a predicated instruction - it doesn't always write the flags.
2391 if (isPredicated(MI))
2394 switch (MI->getOpcode()) {
2428 case ARM::t2EORri: {
2429 // Scan forward for the use of CPSR
2430 // When checking against MI: if it's a conditional code requires
2431 // checking of V bit, then this is not safe to do.
2432 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2433 // If we are done with the basic block, we need to check whether CPSR is
2435 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2437 bool isSafe = false;
2439 E = CmpInstr->getParent()->end();
2440 while (!isSafe && ++I != E) {
2441 const MachineInstr &Instr = *I;
2442 for (unsigned IO = 0, EO = Instr.getNumOperands();
2443 !isSafe && IO != EO; ++IO) {
2444 const MachineOperand &MO = Instr.getOperand(IO);
2445 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2449 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2455 // Condition code is after the operand before CPSR except for VSELs.
2456 ARMCC::CondCodes CC;
2457 bool IsInstrVSel = true;
2458 switch (Instr.getOpcode()) {
2460 IsInstrVSel = false;
2461 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2482 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2483 if (NewCC == ARMCC::AL)
2485 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2486 // on CMP needs to be updated to be based on SUB.
2487 // Push the condition code operands to OperandsToUpdate.
2488 // If it is safe to remove CmpInstr, the condition code of these
2489 // operands will be modified.
2490 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2491 Sub->getOperand(2).getReg() == SrcReg) {
2492 // VSel doesn't support condition code update.
2495 OperandsToUpdate.push_back(
2496 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2501 // CPSR can be used multiple times, we should continue.
2514 // If CPSR is not killed nor re-defined, we should check whether it is
2515 // live-out. If it is live-out, do not optimize.
2517 MachineBasicBlock *MBB = CmpInstr->getParent();
2518 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2519 SE = MBB->succ_end(); SI != SE; ++SI)
2520 if ((*SI)->isLiveIn(ARM::CPSR))
2524 // Toggle the optional operand to CPSR.
2525 MI->getOperand(5).setReg(ARM::CPSR);
2526 MI->getOperand(5).setIsDef(true);
2527 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2528 CmpInstr->eraseFromParent();
2530 // Modify the condition code of operands in OperandsToUpdate.
2531 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2532 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2533 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2534 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2542 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2543 MachineInstr *DefMI, unsigned Reg,
2544 MachineRegisterInfo *MRI) const {
2545 // Fold large immediates into add, sub, or, xor.
2546 unsigned DefOpc = DefMI->getOpcode();
2547 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2549 if (!DefMI->getOperand(1).isImm())
2550 // Could be t2MOVi32imm <ga:xx>
2553 if (!MRI->hasOneNonDBGUse(Reg))
2556 const MCInstrDesc &DefMCID = DefMI->getDesc();
2557 if (DefMCID.hasOptionalDef()) {
2558 unsigned NumOps = DefMCID.getNumOperands();
2559 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2560 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2561 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2566 const MCInstrDesc &UseMCID = UseMI->getDesc();
2567 if (UseMCID.hasOptionalDef()) {
2568 unsigned NumOps = UseMCID.getNumOperands();
2569 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2570 // If the instruction sets the flag, do not attempt this optimization
2571 // since it may change the semantics of the code.
2575 unsigned UseOpc = UseMI->getOpcode();
2576 unsigned NewUseOpc = 0;
2577 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2578 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2579 bool Commute = false;
2581 default: return false;
2589 case ARM::t2EORrr: {
2590 Commute = UseMI->getOperand(2).getReg() != Reg;
2597 NewUseOpc = ARM::SUBri;
2603 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2605 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2606 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2609 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2610 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2611 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2615 case ARM::t2SUBrr: {
2619 NewUseOpc = ARM::t2SUBri;
2624 case ARM::t2EORrr: {
2625 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2627 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2628 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2631 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2632 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2633 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2641 unsigned OpIdx = Commute ? 2 : 1;
2642 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2643 bool isKill = UseMI->getOperand(OpIdx).isKill();
2644 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2645 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2646 UseMI, UseMI->getDebugLoc(),
2647 get(NewUseOpc), NewReg)
2648 .addReg(Reg1, getKillRegState(isKill))
2649 .addImm(SOImmValV1)));
2650 UseMI->setDesc(get(NewUseOpc));
2651 UseMI->getOperand(1).setReg(NewReg);
2652 UseMI->getOperand(1).setIsKill();
2653 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2654 DefMI->eraseFromParent();
2658 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2659 const MachineInstr *MI) {
2660 switch (MI->getOpcode()) {
2662 const MCInstrDesc &Desc = MI->getDesc();
2663 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2664 assert(UOps >= 0 && "bad # UOps");
2672 unsigned ShOpVal = MI->getOperand(3).getImm();
2673 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2674 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2677 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2678 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2685 if (!MI->getOperand(2).getReg())
2688 unsigned ShOpVal = MI->getOperand(3).getImm();
2689 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2690 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2693 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2694 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2701 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2703 case ARM::LDRSB_POST:
2704 case ARM::LDRSH_POST: {
2705 unsigned Rt = MI->getOperand(0).getReg();
2706 unsigned Rm = MI->getOperand(3).getReg();
2707 return (Rt == Rm) ? 4 : 3;
2710 case ARM::LDR_PRE_REG:
2711 case ARM::LDRB_PRE_REG: {
2712 unsigned Rt = MI->getOperand(0).getReg();
2713 unsigned Rm = MI->getOperand(3).getReg();
2716 unsigned ShOpVal = MI->getOperand(4).getImm();
2717 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2718 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2721 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2722 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2727 case ARM::STR_PRE_REG:
2728 case ARM::STRB_PRE_REG: {
2729 unsigned ShOpVal = MI->getOperand(4).getImm();
2730 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2731 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2734 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2735 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2741 case ARM::STRH_PRE: {
2742 unsigned Rt = MI->getOperand(0).getReg();
2743 unsigned Rm = MI->getOperand(3).getReg();
2748 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2752 case ARM::LDR_POST_REG:
2753 case ARM::LDRB_POST_REG:
2754 case ARM::LDRH_POST: {
2755 unsigned Rt = MI->getOperand(0).getReg();
2756 unsigned Rm = MI->getOperand(3).getReg();
2757 return (Rt == Rm) ? 3 : 2;
2760 case ARM::LDR_PRE_IMM:
2761 case ARM::LDRB_PRE_IMM:
2762 case ARM::LDR_POST_IMM:
2763 case ARM::LDRB_POST_IMM:
2764 case ARM::STRB_POST_IMM:
2765 case ARM::STRB_POST_REG:
2766 case ARM::STRB_PRE_IMM:
2767 case ARM::STRH_POST:
2768 case ARM::STR_POST_IMM:
2769 case ARM::STR_POST_REG:
2770 case ARM::STR_PRE_IMM:
2773 case ARM::LDRSB_PRE:
2774 case ARM::LDRSH_PRE: {
2775 unsigned Rm = MI->getOperand(3).getReg();
2778 unsigned Rt = MI->getOperand(0).getReg();
2781 unsigned ShOpVal = MI->getOperand(4).getImm();
2782 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2783 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2786 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2787 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2793 unsigned Rt = MI->getOperand(0).getReg();
2794 unsigned Rn = MI->getOperand(2).getReg();
2795 unsigned Rm = MI->getOperand(3).getReg();
2797 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2798 return (Rt == Rn) ? 3 : 2;
2802 unsigned Rm = MI->getOperand(3).getReg();
2804 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2808 case ARM::LDRD_POST:
2809 case ARM::t2LDRD_POST:
2812 case ARM::STRD_POST:
2813 case ARM::t2STRD_POST:
2816 case ARM::LDRD_PRE: {
2817 unsigned Rt = MI->getOperand(0).getReg();
2818 unsigned Rn = MI->getOperand(3).getReg();
2819 unsigned Rm = MI->getOperand(4).getReg();
2821 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2822 return (Rt == Rn) ? 4 : 3;
2825 case ARM::t2LDRD_PRE: {
2826 unsigned Rt = MI->getOperand(0).getReg();
2827 unsigned Rn = MI->getOperand(3).getReg();
2828 return (Rt == Rn) ? 4 : 3;
2831 case ARM::STRD_PRE: {
2832 unsigned Rm = MI->getOperand(4).getReg();
2834 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2838 case ARM::t2STRD_PRE:
2841 case ARM::t2LDR_POST:
2842 case ARM::t2LDRB_POST:
2843 case ARM::t2LDRB_PRE:
2844 case ARM::t2LDRSBi12:
2845 case ARM::t2LDRSBi8:
2846 case ARM::t2LDRSBpci:
2848 case ARM::t2LDRH_POST:
2849 case ARM::t2LDRH_PRE:
2851 case ARM::t2LDRSB_POST:
2852 case ARM::t2LDRSB_PRE:
2853 case ARM::t2LDRSH_POST:
2854 case ARM::t2LDRSH_PRE:
2855 case ARM::t2LDRSHi12:
2856 case ARM::t2LDRSHi8:
2857 case ARM::t2LDRSHpci:
2861 case ARM::t2LDRDi8: {
2862 unsigned Rt = MI->getOperand(0).getReg();
2863 unsigned Rn = MI->getOperand(2).getReg();
2864 return (Rt == Rn) ? 3 : 2;
2867 case ARM::t2STRB_POST:
2868 case ARM::t2STRB_PRE:
2871 case ARM::t2STRH_POST:
2872 case ARM::t2STRH_PRE:
2874 case ARM::t2STR_POST:
2875 case ARM::t2STR_PRE:
2881 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2882 // can't be easily determined return 0 (missing MachineMemOperand).
2884 // FIXME: The current MachineInstr design does not support relying on machine
2885 // mem operands to determine the width of a memory access. Instead, we expect
2886 // the target to provide this information based on the instruction opcode and
2887 // operands. However, using MachineMemOperand is a the best solution now for
2890 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2891 // operands. This is much more dangerous than using the MachineMemOperand
2892 // sizes because CodeGen passes can insert/remove optional machine operands. In
2893 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2894 // postRA passes as well.
2896 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2897 // machine model that calls this should handle the unknown (zero size) case.
2899 // Long term, we should require a target hook that verifies MachineMemOperand
2900 // sizes during MC lowering. That target hook should be local to MC lowering
2901 // because we can't ensure that it is aware of other MI forms. Doing this will
2902 // ensure that MachineMemOperands are correctly propagated through all passes.
2903 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2905 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
2906 E = MI->memoperands_end(); I != E; ++I) {
2907 Size += (*I)->getSize();
2913 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
2914 const MachineInstr *MI) const {
2915 if (!ItinData || ItinData->isEmpty())
2918 const MCInstrDesc &Desc = MI->getDesc();
2919 unsigned Class = Desc.getSchedClass();
2920 int ItinUOps = ItinData->getNumMicroOps(Class);
2921 if (ItinUOps >= 0) {
2922 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
2923 return getNumMicroOpsSwiftLdSt(ItinData, MI);
2928 unsigned Opc = MI->getOpcode();
2931 llvm_unreachable("Unexpected multi-uops instruction!");
2936 // The number of uOps for load / store multiple are determined by the number
2939 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
2940 // same cycle. The scheduling for the first load / store must be done
2941 // separately by assuming the address is not 64-bit aligned.
2943 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
2944 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
2945 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
2947 case ARM::VLDMDIA_UPD:
2948 case ARM::VLDMDDB_UPD:
2950 case ARM::VLDMSIA_UPD:
2951 case ARM::VLDMSDB_UPD:
2953 case ARM::VSTMDIA_UPD:
2954 case ARM::VSTMDDB_UPD:
2956 case ARM::VSTMSIA_UPD:
2957 case ARM::VSTMSDB_UPD: {
2958 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
2959 return (NumRegs / 2) + (NumRegs % 2) + 1;
2962 case ARM::LDMIA_RET:
2967 case ARM::LDMIA_UPD:
2968 case ARM::LDMDA_UPD:
2969 case ARM::LDMDB_UPD:
2970 case ARM::LDMIB_UPD:
2975 case ARM::STMIA_UPD:
2976 case ARM::STMDA_UPD:
2977 case ARM::STMDB_UPD:
2978 case ARM::STMIB_UPD:
2980 case ARM::tLDMIA_UPD:
2981 case ARM::tSTMIA_UPD:
2985 case ARM::t2LDMIA_RET:
2988 case ARM::t2LDMIA_UPD:
2989 case ARM::t2LDMDB_UPD:
2992 case ARM::t2STMIA_UPD:
2993 case ARM::t2STMDB_UPD: {
2994 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
2995 if (Subtarget.isSwift()) {
2996 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
2999 case ARM::VLDMDIA_UPD:
3000 case ARM::VLDMDDB_UPD:
3001 case ARM::VLDMSIA_UPD:
3002 case ARM::VLDMSDB_UPD:
3003 case ARM::VSTMDIA_UPD:
3004 case ARM::VSTMDDB_UPD:
3005 case ARM::VSTMSIA_UPD:
3006 case ARM::VSTMSDB_UPD:
3007 case ARM::LDMIA_UPD:
3008 case ARM::LDMDA_UPD:
3009 case ARM::LDMDB_UPD:
3010 case ARM::LDMIB_UPD:
3011 case ARM::STMIA_UPD:
3012 case ARM::STMDA_UPD:
3013 case ARM::STMDB_UPD:
3014 case ARM::STMIB_UPD:
3015 case ARM::tLDMIA_UPD:
3016 case ARM::tSTMIA_UPD:
3017 case ARM::t2LDMIA_UPD:
3018 case ARM::t2LDMDB_UPD:
3019 case ARM::t2STMIA_UPD:
3020 case ARM::t2STMDB_UPD:
3021 ++UOps; // One for base register writeback.
3023 case ARM::LDMIA_RET:
3025 case ARM::t2LDMIA_RET:
3026 UOps += 2; // One for base reg wb, one for write to pc.
3030 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3033 // 4 registers would be issued: 2, 2.
3034 // 5 registers would be issued: 2, 2, 1.
3035 int A8UOps = (NumRegs / 2);
3039 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3040 int A9UOps = (NumRegs / 2);
3041 // If there are odd number of registers or if it's not 64-bit aligned,
3042 // then it takes an extra AGU (Address Generation Unit) cycle.
3043 if ((NumRegs % 2) ||
3044 !MI->hasOneMemOperand() ||
3045 (*MI->memoperands_begin())->getAlignment() < 8)
3049 // Assume the worst.
3057 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3058 const MCInstrDesc &DefMCID,
3060 unsigned DefIdx, unsigned DefAlign) const {
3061 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3063 // Def is the address writeback.
3064 return ItinData->getOperandCycle(DefClass, DefIdx);
3067 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3068 // (regno / 2) + (regno % 2) + 1
3069 DefCycle = RegNo / 2 + 1;
3072 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3074 bool isSLoad = false;
3076 switch (DefMCID.getOpcode()) {
3079 case ARM::VLDMSIA_UPD:
3080 case ARM::VLDMSDB_UPD:
3085 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3086 // then it takes an extra cycle.
3087 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3090 // Assume the worst.
3091 DefCycle = RegNo + 2;
3098 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3099 const MCInstrDesc &DefMCID,
3101 unsigned DefIdx, unsigned DefAlign) const {
3102 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3104 // Def is the address writeback.
3105 return ItinData->getOperandCycle(DefClass, DefIdx);
3108 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3109 // 4 registers would be issued: 1, 2, 1.
3110 // 5 registers would be issued: 1, 2, 2.
3111 DefCycle = RegNo / 2;
3114 // Result latency is issue cycle + 2: E2.
3116 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3117 DefCycle = (RegNo / 2);
3118 // If there are odd number of registers or if it's not 64-bit aligned,
3119 // then it takes an extra AGU (Address Generation Unit) cycle.
3120 if ((RegNo % 2) || DefAlign < 8)
3122 // Result latency is AGU cycles + 2.
3125 // Assume the worst.
3126 DefCycle = RegNo + 2;
3133 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3134 const MCInstrDesc &UseMCID,
3136 unsigned UseIdx, unsigned UseAlign) const {
3137 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3139 return ItinData->getOperandCycle(UseClass, UseIdx);
3142 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3143 // (regno / 2) + (regno % 2) + 1
3144 UseCycle = RegNo / 2 + 1;
3147 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3149 bool isSStore = false;
3151 switch (UseMCID.getOpcode()) {
3154 case ARM::VSTMSIA_UPD:
3155 case ARM::VSTMSDB_UPD:
3160 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3161 // then it takes an extra cycle.
3162 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3165 // Assume the worst.
3166 UseCycle = RegNo + 2;
3173 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3174 const MCInstrDesc &UseMCID,
3176 unsigned UseIdx, unsigned UseAlign) const {
3177 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3179 return ItinData->getOperandCycle(UseClass, UseIdx);
3182 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3183 UseCycle = RegNo / 2;
3188 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3189 UseCycle = (RegNo / 2);
3190 // If there are odd number of registers or if it's not 64-bit aligned,
3191 // then it takes an extra AGU (Address Generation Unit) cycle.
3192 if ((RegNo % 2) || UseAlign < 8)
3195 // Assume the worst.
3202 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3203 const MCInstrDesc &DefMCID,
3204 unsigned DefIdx, unsigned DefAlign,
3205 const MCInstrDesc &UseMCID,
3206 unsigned UseIdx, unsigned UseAlign) const {
3207 unsigned DefClass = DefMCID.getSchedClass();
3208 unsigned UseClass = UseMCID.getSchedClass();
3210 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3211 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3213 // This may be a def / use of a variable_ops instruction, the operand
3214 // latency might be determinable dynamically. Let the target try to
3217 bool LdmBypass = false;
3218 switch (DefMCID.getOpcode()) {
3220 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3224 case ARM::VLDMDIA_UPD:
3225 case ARM::VLDMDDB_UPD:
3227 case ARM::VLDMSIA_UPD:
3228 case ARM::VLDMSDB_UPD:
3229 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3232 case ARM::LDMIA_RET:
3237 case ARM::LDMIA_UPD:
3238 case ARM::LDMDA_UPD:
3239 case ARM::LDMDB_UPD:
3240 case ARM::LDMIB_UPD:
3242 case ARM::tLDMIA_UPD:
3244 case ARM::t2LDMIA_RET:
3247 case ARM::t2LDMIA_UPD:
3248 case ARM::t2LDMDB_UPD:
3250 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3255 // We can't seem to determine the result latency of the def, assume it's 2.
3259 switch (UseMCID.getOpcode()) {
3261 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3265 case ARM::VSTMDIA_UPD:
3266 case ARM::VSTMDDB_UPD:
3268 case ARM::VSTMSIA_UPD:
3269 case ARM::VSTMSDB_UPD:
3270 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3277 case ARM::STMIA_UPD:
3278 case ARM::STMDA_UPD:
3279 case ARM::STMDB_UPD:
3280 case ARM::STMIB_UPD:
3281 case ARM::tSTMIA_UPD:
3286 case ARM::t2STMIA_UPD:
3287 case ARM::t2STMDB_UPD:
3288 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3293 // Assume it's read in the first stage.
3296 UseCycle = DefCycle - UseCycle + 1;
3299 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3300 // first def operand.
3301 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3304 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3305 UseClass, UseIdx)) {
3313 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3314 const MachineInstr *MI, unsigned Reg,
3315 unsigned &DefIdx, unsigned &Dist) {
3318 MachineBasicBlock::const_iterator I = MI; ++I;
3319 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3320 assert(II->isInsideBundle() && "Empty bundle?");
3323 while (II->isInsideBundle()) {
3324 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3331 assert(Idx != -1 && "Cannot find bundled definition!");
3336 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3337 const MachineInstr *MI, unsigned Reg,
3338 unsigned &UseIdx, unsigned &Dist) {
3341 MachineBasicBlock::const_instr_iterator II = MI; ++II;
3342 assert(II->isInsideBundle() && "Empty bundle?");
3343 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3345 // FIXME: This doesn't properly handle multiple uses.
3347 while (II != E && II->isInsideBundle()) {
3348 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3351 if (II->getOpcode() != ARM::t2IT)
3365 /// Return the number of cycles to add to (or subtract from) the static
3366 /// itinerary based on the def opcode and alignment. The caller will ensure that
3367 /// adjusted latency is at least one cycle.
3368 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3369 const MachineInstr *DefMI,
3370 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3372 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3373 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3374 // variants are one cycle cheaper.
3375 switch (DefMCID->getOpcode()) {
3379 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3380 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3382 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3389 case ARM::t2LDRSHs: {
3390 // Thumb2 mode: lsl only.
3391 unsigned ShAmt = DefMI->getOperand(3).getImm();
3392 if (ShAmt == 0 || ShAmt == 2)
3397 } else if (Subtarget.isSwift()) {
3398 // FIXME: Properly handle all of the latency adjustments for address
3400 switch (DefMCID->getOpcode()) {
3404 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3405 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3406 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3409 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3410 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3413 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3420 case ARM::t2LDRSHs: {
3421 // Thumb2 mode: lsl only.
3422 unsigned ShAmt = DefMI->getOperand(3).getImm();
3423 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3430 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3431 switch (DefMCID->getOpcode()) {
3437 case ARM::VLD1q8wb_fixed:
3438 case ARM::VLD1q16wb_fixed:
3439 case ARM::VLD1q32wb_fixed:
3440 case ARM::VLD1q64wb_fixed:
3441 case ARM::VLD1q8wb_register:
3442 case ARM::VLD1q16wb_register:
3443 case ARM::VLD1q32wb_register:
3444 case ARM::VLD1q64wb_register:
3451 case ARM::VLD2d8wb_fixed:
3452 case ARM::VLD2d16wb_fixed:
3453 case ARM::VLD2d32wb_fixed:
3454 case ARM::VLD2q8wb_fixed:
3455 case ARM::VLD2q16wb_fixed:
3456 case ARM::VLD2q32wb_fixed:
3457 case ARM::VLD2d8wb_register:
3458 case ARM::VLD2d16wb_register:
3459 case ARM::VLD2d32wb_register:
3460 case ARM::VLD2q8wb_register:
3461 case ARM::VLD2q16wb_register:
3462 case ARM::VLD2q32wb_register:
3467 case ARM::VLD3d8_UPD:
3468 case ARM::VLD3d16_UPD:
3469 case ARM::VLD3d32_UPD:
3470 case ARM::VLD1d64Twb_fixed:
3471 case ARM::VLD1d64Twb_register:
3472 case ARM::VLD3q8_UPD:
3473 case ARM::VLD3q16_UPD:
3474 case ARM::VLD3q32_UPD:
3479 case ARM::VLD4d8_UPD:
3480 case ARM::VLD4d16_UPD:
3481 case ARM::VLD4d32_UPD:
3482 case ARM::VLD1d64Qwb_fixed:
3483 case ARM::VLD1d64Qwb_register:
3484 case ARM::VLD4q8_UPD:
3485 case ARM::VLD4q16_UPD:
3486 case ARM::VLD4q32_UPD:
3487 case ARM::VLD1DUPq8:
3488 case ARM::VLD1DUPq16:
3489 case ARM::VLD1DUPq32:
3490 case ARM::VLD1DUPq8wb_fixed:
3491 case ARM::VLD1DUPq16wb_fixed:
3492 case ARM::VLD1DUPq32wb_fixed:
3493 case ARM::VLD1DUPq8wb_register:
3494 case ARM::VLD1DUPq16wb_register:
3495 case ARM::VLD1DUPq32wb_register:
3496 case ARM::VLD2DUPd8:
3497 case ARM::VLD2DUPd16:
3498 case ARM::VLD2DUPd32:
3499 case ARM::VLD2DUPd8wb_fixed:
3500 case ARM::VLD2DUPd16wb_fixed:
3501 case ARM::VLD2DUPd32wb_fixed:
3502 case ARM::VLD2DUPd8wb_register:
3503 case ARM::VLD2DUPd16wb_register:
3504 case ARM::VLD2DUPd32wb_register:
3505 case ARM::VLD4DUPd8:
3506 case ARM::VLD4DUPd16:
3507 case ARM::VLD4DUPd32:
3508 case ARM::VLD4DUPd8_UPD:
3509 case ARM::VLD4DUPd16_UPD:
3510 case ARM::VLD4DUPd32_UPD:
3512 case ARM::VLD1LNd16:
3513 case ARM::VLD1LNd32:
3514 case ARM::VLD1LNd8_UPD:
3515 case ARM::VLD1LNd16_UPD:
3516 case ARM::VLD1LNd32_UPD:
3518 case ARM::VLD2LNd16:
3519 case ARM::VLD2LNd32:
3520 case ARM::VLD2LNq16:
3521 case ARM::VLD2LNq32:
3522 case ARM::VLD2LNd8_UPD:
3523 case ARM::VLD2LNd16_UPD:
3524 case ARM::VLD2LNd32_UPD:
3525 case ARM::VLD2LNq16_UPD:
3526 case ARM::VLD2LNq32_UPD:
3528 case ARM::VLD4LNd16:
3529 case ARM::VLD4LNd32:
3530 case ARM::VLD4LNq16:
3531 case ARM::VLD4LNq32:
3532 case ARM::VLD4LNd8_UPD:
3533 case ARM::VLD4LNd16_UPD:
3534 case ARM::VLD4LNd32_UPD:
3535 case ARM::VLD4LNq16_UPD:
3536 case ARM::VLD4LNq32_UPD:
3537 // If the address is not 64-bit aligned, the latencies of these
3538 // instructions increases by one.
3549 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3550 const MachineInstr *DefMI, unsigned DefIdx,
3551 const MachineInstr *UseMI,
3552 unsigned UseIdx) const {
3553 // No operand latency. The caller may fall back to getInstrLatency.
3554 if (!ItinData || ItinData->isEmpty())
3557 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3558 unsigned Reg = DefMO.getReg();
3559 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3560 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3562 unsigned DefAdj = 0;
3563 if (DefMI->isBundle()) {
3564 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3565 DefMCID = &DefMI->getDesc();
3567 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3568 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3572 unsigned UseAdj = 0;
3573 if (UseMI->isBundle()) {
3575 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3576 Reg, NewUseIdx, UseAdj);
3582 UseMCID = &UseMI->getDesc();
3585 if (Reg == ARM::CPSR) {
3586 if (DefMI->getOpcode() == ARM::FMSTAT) {
3587 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3588 return Subtarget.isLikeA9() ? 1 : 20;
3591 // CPSR set and branch can be paired in the same cycle.
3592 if (UseMI->isBranch())
3595 // Otherwise it takes the instruction latency (generally one).
3596 unsigned Latency = getInstrLatency(ItinData, DefMI);
3598 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3599 // its uses. Instructions which are otherwise scheduled between them may
3600 // incur a code size penalty (not able to use the CPSR setting 16-bit
3602 if (Latency > 0 && Subtarget.isThumb2()) {
3603 const MachineFunction *MF = DefMI->getParent()->getParent();
3604 if (MF->getFunction()->getAttributes().
3605 hasAttribute(AttributeSet::FunctionIndex,
3606 Attribute::OptimizeForSize))
3612 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3615 unsigned DefAlign = DefMI->hasOneMemOperand()
3616 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3617 unsigned UseAlign = UseMI->hasOneMemOperand()
3618 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3620 // Get the itinerary's latency if possible, and handle variable_ops.
3621 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3622 *UseMCID, UseIdx, UseAlign);
3623 // Unable to find operand latency. The caller may resort to getInstrLatency.
3627 // Adjust for IT block position.
3628 int Adj = DefAdj + UseAdj;
3630 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3631 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3632 if (Adj >= 0 || (int)Latency > -Adj) {
3633 return Latency + Adj;
3635 // Return the itinerary latency, which may be zero but not less than zero.
3640 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3641 SDNode *DefNode, unsigned DefIdx,
3642 SDNode *UseNode, unsigned UseIdx) const {
3643 if (!DefNode->isMachineOpcode())
3646 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3648 if (isZeroCost(DefMCID.Opcode))
3651 if (!ItinData || ItinData->isEmpty())
3652 return DefMCID.mayLoad() ? 3 : 1;
3654 if (!UseNode->isMachineOpcode()) {
3655 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3656 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3657 return Latency <= 2 ? 1 : Latency - 1;
3659 return Latency <= 3 ? 1 : Latency - 2;
3662 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3663 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3664 unsigned DefAlign = !DefMN->memoperands_empty()
3665 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3666 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3667 unsigned UseAlign = !UseMN->memoperands_empty()
3668 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3669 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3670 UseMCID, UseIdx, UseAlign);
3673 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3674 Subtarget.isCortexA7())) {
3675 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3676 // variants are one cycle cheaper.
3677 switch (DefMCID.getOpcode()) {
3682 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3683 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3685 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3692 case ARM::t2LDRSHs: {
3693 // Thumb2 mode: lsl only.
3695 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3696 if (ShAmt == 0 || ShAmt == 2)
3701 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3702 // FIXME: Properly handle all of the latency adjustments for address
3704 switch (DefMCID.getOpcode()) {
3709 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3710 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3712 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3713 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3715 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3722 case ARM::t2LDRSHs: {
3723 // Thumb2 mode: lsl 0-3 only.
3730 if (DefAlign < 8 && Subtarget.isLikeA9())
3731 switch (DefMCID.getOpcode()) {
3737 case ARM::VLD1q8wb_register:
3738 case ARM::VLD1q16wb_register:
3739 case ARM::VLD1q32wb_register:
3740 case ARM::VLD1q64wb_register:
3741 case ARM::VLD1q8wb_fixed:
3742 case ARM::VLD1q16wb_fixed:
3743 case ARM::VLD1q32wb_fixed:
3744 case ARM::VLD1q64wb_fixed:
3748 case ARM::VLD2q8Pseudo:
3749 case ARM::VLD2q16Pseudo:
3750 case ARM::VLD2q32Pseudo:
3751 case ARM::VLD2d8wb_fixed:
3752 case ARM::VLD2d16wb_fixed:
3753 case ARM::VLD2d32wb_fixed:
3754 case ARM::VLD2q8PseudoWB_fixed:
3755 case ARM::VLD2q16PseudoWB_fixed:
3756 case ARM::VLD2q32PseudoWB_fixed:
3757 case ARM::VLD2d8wb_register:
3758 case ARM::VLD2d16wb_register:
3759 case ARM::VLD2d32wb_register:
3760 case ARM::VLD2q8PseudoWB_register:
3761 case ARM::VLD2q16PseudoWB_register:
3762 case ARM::VLD2q32PseudoWB_register:
3763 case ARM::VLD3d8Pseudo:
3764 case ARM::VLD3d16Pseudo:
3765 case ARM::VLD3d32Pseudo:
3766 case ARM::VLD1d64TPseudo:
3767 case ARM::VLD1d64TPseudoWB_fixed:
3768 case ARM::VLD3d8Pseudo_UPD:
3769 case ARM::VLD3d16Pseudo_UPD:
3770 case ARM::VLD3d32Pseudo_UPD:
3771 case ARM::VLD3q8Pseudo_UPD:
3772 case ARM::VLD3q16Pseudo_UPD:
3773 case ARM::VLD3q32Pseudo_UPD:
3774 case ARM::VLD3q8oddPseudo:
3775 case ARM::VLD3q16oddPseudo:
3776 case ARM::VLD3q32oddPseudo:
3777 case ARM::VLD3q8oddPseudo_UPD:
3778 case ARM::VLD3q16oddPseudo_UPD:
3779 case ARM::VLD3q32oddPseudo_UPD:
3780 case ARM::VLD4d8Pseudo:
3781 case ARM::VLD4d16Pseudo:
3782 case ARM::VLD4d32Pseudo:
3783 case ARM::VLD1d64QPseudo:
3784 case ARM::VLD1d64QPseudoWB_fixed:
3785 case ARM::VLD4d8Pseudo_UPD:
3786 case ARM::VLD4d16Pseudo_UPD:
3787 case ARM::VLD4d32Pseudo_UPD:
3788 case ARM::VLD4q8Pseudo_UPD:
3789 case ARM::VLD4q16Pseudo_UPD:
3790 case ARM::VLD4q32Pseudo_UPD:
3791 case ARM::VLD4q8oddPseudo:
3792 case ARM::VLD4q16oddPseudo:
3793 case ARM::VLD4q32oddPseudo:
3794 case ARM::VLD4q8oddPseudo_UPD:
3795 case ARM::VLD4q16oddPseudo_UPD:
3796 case ARM::VLD4q32oddPseudo_UPD:
3797 case ARM::VLD1DUPq8:
3798 case ARM::VLD1DUPq16:
3799 case ARM::VLD1DUPq32:
3800 case ARM::VLD1DUPq8wb_fixed:
3801 case ARM::VLD1DUPq16wb_fixed:
3802 case ARM::VLD1DUPq32wb_fixed:
3803 case ARM::VLD1DUPq8wb_register:
3804 case ARM::VLD1DUPq16wb_register:
3805 case ARM::VLD1DUPq32wb_register:
3806 case ARM::VLD2DUPd8:
3807 case ARM::VLD2DUPd16:
3808 case ARM::VLD2DUPd32:
3809 case ARM::VLD2DUPd8wb_fixed:
3810 case ARM::VLD2DUPd16wb_fixed:
3811 case ARM::VLD2DUPd32wb_fixed:
3812 case ARM::VLD2DUPd8wb_register:
3813 case ARM::VLD2DUPd16wb_register:
3814 case ARM::VLD2DUPd32wb_register:
3815 case ARM::VLD4DUPd8Pseudo:
3816 case ARM::VLD4DUPd16Pseudo:
3817 case ARM::VLD4DUPd32Pseudo:
3818 case ARM::VLD4DUPd8Pseudo_UPD:
3819 case ARM::VLD4DUPd16Pseudo_UPD:
3820 case ARM::VLD4DUPd32Pseudo_UPD:
3821 case ARM::VLD1LNq8Pseudo:
3822 case ARM::VLD1LNq16Pseudo:
3823 case ARM::VLD1LNq32Pseudo:
3824 case ARM::VLD1LNq8Pseudo_UPD:
3825 case ARM::VLD1LNq16Pseudo_UPD:
3826 case ARM::VLD1LNq32Pseudo_UPD:
3827 case ARM::VLD2LNd8Pseudo:
3828 case ARM::VLD2LNd16Pseudo:
3829 case ARM::VLD2LNd32Pseudo:
3830 case ARM::VLD2LNq16Pseudo:
3831 case ARM::VLD2LNq32Pseudo:
3832 case ARM::VLD2LNd8Pseudo_UPD:
3833 case ARM::VLD2LNd16Pseudo_UPD:
3834 case ARM::VLD2LNd32Pseudo_UPD:
3835 case ARM::VLD2LNq16Pseudo_UPD:
3836 case ARM::VLD2LNq32Pseudo_UPD:
3837 case ARM::VLD4LNd8Pseudo:
3838 case ARM::VLD4LNd16Pseudo:
3839 case ARM::VLD4LNd32Pseudo:
3840 case ARM::VLD4LNq16Pseudo:
3841 case ARM::VLD4LNq32Pseudo:
3842 case ARM::VLD4LNd8Pseudo_UPD:
3843 case ARM::VLD4LNd16Pseudo_UPD:
3844 case ARM::VLD4LNd32Pseudo_UPD:
3845 case ARM::VLD4LNq16Pseudo_UPD:
3846 case ARM::VLD4LNq32Pseudo_UPD:
3847 // If the address is not 64-bit aligned, the latencies of these
3848 // instructions increases by one.
3856 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3857 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3858 MI->isRegSequence() || MI->isImplicitDef())
3864 const MCInstrDesc &MCID = MI->getDesc();
3866 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3867 // When predicated, CPSR is an additional source operand for CPSR updating
3868 // instructions, this apparently increases their latencies.
3874 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3875 const MachineInstr *MI,
3876 unsigned *PredCost) const {
3877 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3878 MI->isRegSequence() || MI->isImplicitDef())
3881 // An instruction scheduler typically runs on unbundled instructions, however
3882 // other passes may query the latency of a bundled instruction.
3883 if (MI->isBundle()) {
3884 unsigned Latency = 0;
3885 MachineBasicBlock::const_instr_iterator I = MI;
3886 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3887 while (++I != E && I->isInsideBundle()) {
3888 if (I->getOpcode() != ARM::t2IT)
3889 Latency += getInstrLatency(ItinData, I, PredCost);
3894 const MCInstrDesc &MCID = MI->getDesc();
3895 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3896 // When predicated, CPSR is an additional source operand for CPSR updating
3897 // instructions, this apparently increases their latencies.
3900 // Be sure to call getStageLatency for an empty itinerary in case it has a
3901 // valid MinLatency property.
3903 return MI->mayLoad() ? 3 : 1;
3905 unsigned Class = MCID.getSchedClass();
3907 // For instructions with variable uops, use uops as latency.
3908 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
3909 return getNumMicroOps(ItinData, MI);
3911 // For the common case, fall back on the itinerary's latency.
3912 unsigned Latency = ItinData->getStageLatency(Class);
3914 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3915 unsigned DefAlign = MI->hasOneMemOperand()
3916 ? (*MI->memoperands_begin())->getAlignment() : 0;
3917 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
3918 if (Adj >= 0 || (int)Latency > -Adj) {
3919 return Latency + Adj;
3924 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3925 SDNode *Node) const {
3926 if (!Node->isMachineOpcode())
3929 if (!ItinData || ItinData->isEmpty())
3932 unsigned Opcode = Node->getMachineOpcode();
3935 return ItinData->getStageLatency(get(Opcode).getSchedClass());
3942 bool ARMBaseInstrInfo::
3943 hasHighOperandLatency(const InstrItineraryData *ItinData,
3944 const MachineRegisterInfo *MRI,
3945 const MachineInstr *DefMI, unsigned DefIdx,
3946 const MachineInstr *UseMI, unsigned UseIdx) const {
3947 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3948 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
3949 if (Subtarget.isCortexA8() &&
3950 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
3951 // CortexA8 VFP instructions are not pipelined.
3954 // Hoist VFP / NEON instructions with 4 or higher latency.
3955 int Latency = computeOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
3957 Latency = getInstrLatency(ItinData, DefMI);
3960 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
3961 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
3964 bool ARMBaseInstrInfo::
3965 hasLowDefLatency(const InstrItineraryData *ItinData,
3966 const MachineInstr *DefMI, unsigned DefIdx) const {
3967 if (!ItinData || ItinData->isEmpty())
3970 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
3971 if (DDomain == ARMII::DomainGeneral) {
3972 unsigned DefClass = DefMI->getDesc().getSchedClass();
3973 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3974 return (DefCycle != -1 && DefCycle <= 2);
3979 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
3980 StringRef &ErrInfo) const {
3981 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
3982 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
3988 // LoadStackGuard has so far only been implemented for MachO. Different code
3989 // sequence is needed for other targets.
3990 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
3991 unsigned LoadImmOpc,
3993 Reloc::Model RM) const {
3994 MachineBasicBlock &MBB = *MI->getParent();
3995 DebugLoc DL = MI->getDebugLoc();
3996 unsigned Reg = MI->getOperand(0).getReg();
3997 const GlobalValue *GV =
3998 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
3999 MachineInstrBuilder MIB;
4001 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4002 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4004 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4005 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4006 MIB.addReg(Reg, RegState::Kill).addImm(0);
4007 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4008 MachineMemOperand *MMO = MBB.getParent()->
4009 getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 4, 4);
4010 MIB.addMemOperand(MMO);
4011 AddDefaultPred(MIB);
4014 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4015 MIB.addReg(Reg, RegState::Kill).addImm(0);
4016 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4017 AddDefaultPred(MIB);
4021 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4022 unsigned &AddSubOpc,
4023 bool &NegAcc, bool &HasLane) const {
4024 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4025 if (I == MLxEntryMap.end())
4028 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4029 MulOpc = Entry.MulOpc;
4030 AddSubOpc = Entry.AddSubOpc;
4031 NegAcc = Entry.NegAcc;
4032 HasLane = Entry.HasLane;
4036 //===----------------------------------------------------------------------===//
4037 // Execution domains.
4038 //===----------------------------------------------------------------------===//
4040 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4041 // and some can go down both. The vmov instructions go down the VFP pipeline,
4042 // but they can be changed to vorr equivalents that are executed by the NEON
4045 // We use the following execution domain numbering:
4053 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4055 std::pair<uint16_t, uint16_t>
4056 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4057 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4058 // if they are not predicated.
4059 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4060 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
4062 // CortexA9 is particularly picky about mixing the two and wants these
4064 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4065 (MI->getOpcode() == ARM::VMOVRS ||
4066 MI->getOpcode() == ARM::VMOVSR ||
4067 MI->getOpcode() == ARM::VMOVS))
4068 return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON));
4070 // No other instructions can be swizzled, so just determine their domain.
4071 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4073 if (Domain & ARMII::DomainNEON)
4074 return std::make_pair(ExeNEON, 0);
4076 // Certain instructions can go either way on Cortex-A8.
4077 // Treat them as NEON instructions.
4078 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4079 return std::make_pair(ExeNEON, 0);
4081 if (Domain & ARMII::DomainVFP)
4082 return std::make_pair(ExeVFP, 0);
4084 return std::make_pair(ExeGeneric, 0);
4087 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4088 unsigned SReg, unsigned &Lane) {
4089 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4092 if (DReg != ARM::NoRegister)
4096 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4098 assert(DReg && "S-register with no D super-register?");
4102 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4103 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4104 /// zero if no register needs to be defined as implicit-use.
4106 /// If the function cannot determine if an SPR should be marked implicit use or
4107 /// not, it returns false.
4109 /// This function handles cases where an instruction is being modified from taking
4110 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4111 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4112 /// lane of the DPR).
4114 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4115 /// (including the case where the DPR itself is defined), it should not.
4117 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4119 unsigned DReg, unsigned Lane,
4120 unsigned &ImplicitSReg) {
4121 // If the DPR is defined or used already, the other SPR lane will be chained
4122 // correctly, so there is nothing to be done.
4123 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4128 // Otherwise we need to go searching to see if the SPR is set explicitly.
4129 ImplicitSReg = TRI->getSubReg(DReg,
4130 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4131 MachineBasicBlock::LivenessQueryResult LQR =
4132 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4134 if (LQR == MachineBasicBlock::LQR_Live)
4136 else if (LQR == MachineBasicBlock::LQR_Unknown)
4139 // If the register is known not to be live, there is no need to add an
4146 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4147 unsigned DstReg, SrcReg, DReg;
4149 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4150 const TargetRegisterInfo *TRI = &getRegisterInfo();
4151 switch (MI->getOpcode()) {
4153 llvm_unreachable("cannot handle opcode!");
4156 if (Domain != ExeNEON)
4159 // Zap the predicate operands.
4160 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4162 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4163 DstReg = MI->getOperand(0).getReg();
4164 SrcReg = MI->getOperand(1).getReg();
4166 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4167 MI->RemoveOperand(i-1);
4169 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4170 MI->setDesc(get(ARM::VORRd));
4171 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4176 if (Domain != ExeNEON)
4178 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4180 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4181 DstReg = MI->getOperand(0).getReg();
4182 SrcReg = MI->getOperand(1).getReg();
4184 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4185 MI->RemoveOperand(i-1);
4187 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4189 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4190 // Note that DSrc has been widened and the other lane may be undef, which
4191 // contaminates the entire register.
4192 MI->setDesc(get(ARM::VGETLNi32));
4193 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4194 .addReg(DReg, RegState::Undef)
4197 // The old source should be an implicit use, otherwise we might think it
4198 // was dead before here.
4199 MIB.addReg(SrcReg, RegState::Implicit);
4202 if (Domain != ExeNEON)
4204 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4206 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4207 DstReg = MI->getOperand(0).getReg();
4208 SrcReg = MI->getOperand(1).getReg();
4210 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4212 unsigned ImplicitSReg;
4213 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4216 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4217 MI->RemoveOperand(i-1);
4219 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4220 // Again DDst may be undefined at the beginning of this instruction.
4221 MI->setDesc(get(ARM::VSETLNi32));
4222 MIB.addReg(DReg, RegState::Define)
4223 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4226 AddDefaultPred(MIB);
4228 // The narrower destination must be marked as set to keep previous chains
4230 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4231 if (ImplicitSReg != 0)
4232 MIB.addReg(ImplicitSReg, RegState::Implicit);
4236 if (Domain != ExeNEON)
4239 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4240 DstReg = MI->getOperand(0).getReg();
4241 SrcReg = MI->getOperand(1).getReg();
4243 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4244 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4245 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4247 unsigned ImplicitSReg;
4248 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4251 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4252 MI->RemoveOperand(i-1);
4255 // Destination can be:
4256 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4257 MI->setDesc(get(ARM::VDUPLN32d));
4258 MIB.addReg(DDst, RegState::Define)
4259 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4261 AddDefaultPred(MIB);
4263 // Neither the source or the destination are naturally represented any
4264 // more, so add them in manually.
4265 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4266 MIB.addReg(SrcReg, RegState::Implicit);
4267 if (ImplicitSReg != 0)
4268 MIB.addReg(ImplicitSReg, RegState::Implicit);
4272 // In general there's no single instruction that can perform an S <-> S
4273 // move in NEON space, but a pair of VEXT instructions *can* do the
4274 // job. It turns out that the VEXTs needed will only use DSrc once, with
4275 // the position based purely on the combination of lane-0 and lane-1
4276 // involved. For example
4277 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4278 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4279 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4280 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4282 // Pattern of the MachineInstrs is:
4283 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4284 MachineInstrBuilder NewMIB;
4285 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4286 get(ARM::VEXTd32), DDst);
4288 // On the first instruction, both DSrc and DDst may be <undef> if present.
4289 // Specifically when the original instruction didn't have them as an
4291 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4292 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4293 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4295 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4296 CurUndef = !MI->readsRegister(CurReg, TRI);
4297 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4300 AddDefaultPred(NewMIB);
4302 if (SrcLane == DstLane)
4303 NewMIB.addReg(SrcReg, RegState::Implicit);
4305 MI->setDesc(get(ARM::VEXTd32));
4306 MIB.addReg(DDst, RegState::Define);
4308 // On the second instruction, DDst has definitely been defined above, so
4309 // it is not <undef>. DSrc, if present, can be <undef> as above.
4310 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4311 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4312 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4314 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4315 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4316 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4319 AddDefaultPred(MIB);
4321 if (SrcLane != DstLane)
4322 MIB.addReg(SrcReg, RegState::Implicit);
4324 // As before, the original destination is no longer represented, add it
4326 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4327 if (ImplicitSReg != 0)
4328 MIB.addReg(ImplicitSReg, RegState::Implicit);
4335 //===----------------------------------------------------------------------===//
4336 // Partial register updates
4337 //===----------------------------------------------------------------------===//
4339 // Swift renames NEON registers with 64-bit granularity. That means any
4340 // instruction writing an S-reg implicitly reads the containing D-reg. The
4341 // problem is mostly avoided by translating f32 operations to v2f32 operations
4342 // on D-registers, but f32 loads are still a problem.
4344 // These instructions can load an f32 into a NEON register:
4346 // VLDRS - Only writes S, partial D update.
4347 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4348 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4350 // FCONSTD can be used as a dependency-breaking instruction.
4351 unsigned ARMBaseInstrInfo::
4352 getPartialRegUpdateClearance(const MachineInstr *MI,
4354 const TargetRegisterInfo *TRI) const {
4355 if (!SwiftPartialUpdateClearance ||
4356 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4359 assert(TRI && "Need TRI instance");
4361 const MachineOperand &MO = MI->getOperand(OpNum);
4364 unsigned Reg = MO.getReg();
4367 switch(MI->getOpcode()) {
4368 // Normal instructions writing only an S-register.
4373 case ARM::VMOVv4i16:
4374 case ARM::VMOVv2i32:
4375 case ARM::VMOVv2f32:
4376 case ARM::VMOVv1i64:
4377 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4380 // Explicitly reads the dependency.
4381 case ARM::VLD1LNd32:
4388 // If this instruction actually reads a value from Reg, there is no unwanted
4390 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4393 // We must be able to clobber the whole D-reg.
4394 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4395 // Virtual register must be a foo:ssub_0<def,undef> operand.
4396 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4398 } else if (ARM::SPRRegClass.contains(Reg)) {
4399 // Physical register: MI must define the full D-reg.
4400 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4402 if (!DReg || !MI->definesRegister(DReg, TRI))
4406 // MI has an unwanted D-register dependency.
4407 // Avoid defs in the previous N instructrions.
4408 return SwiftPartialUpdateClearance;
4411 // Break a partial register dependency after getPartialRegUpdateClearance
4412 // returned non-zero.
4413 void ARMBaseInstrInfo::
4414 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4416 const TargetRegisterInfo *TRI) const {
4417 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4418 assert(TRI && "Need TRI instance");
4420 const MachineOperand &MO = MI->getOperand(OpNum);
4421 unsigned Reg = MO.getReg();
4422 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4423 "Can't break virtual register dependencies.");
4424 unsigned DReg = Reg;
4426 // If MI defines an S-reg, find the corresponding D super-register.
4427 if (ARM::SPRRegClass.contains(Reg)) {
4428 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4429 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4432 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4433 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4435 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4436 // the full D-register by loading the same value to both lanes. The
4437 // instruction is micro-coded with 2 uops, so don't do this until we can
4438 // properly schedule micro-coded instructions. The dispatcher stalls cause
4439 // too big regressions.
4441 // Insert the dependency-breaking FCONSTD before MI.
4442 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4443 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4444 get(ARM::FCONSTD), DReg).addImm(96));
4445 MI->addRegisterKilled(DReg, TRI, true);
4448 void ARMBaseInstrInfo::getUnconditionalBranch(
4449 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
4450 if (Subtarget.isThumb())
4451 Branch.setOpcode(ARM::tB);
4452 else if (Subtarget.isThumb2())
4453 Branch.setOpcode(ARM::t2B);
4455 Branch.setOpcode(ARM::Bcc);
4457 Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
4458 Branch.addOperand(MCOperand::CreateImm(ARMCC::AL));
4459 Branch.addOperand(MCOperand::CreateReg(0));
4462 void ARMBaseInstrInfo::getTrap(MCInst &MI) const {
4463 if (Subtarget.isThumb())
4464 MI.setOpcode(ARM::tTRAP);
4465 else if (Subtarget.useNaClTrap())
4466 MI.setOpcode(ARM::TRAPNaCl);
4468 MI.setOpcode(ARM::TRAP);
4471 bool ARMBaseInstrInfo::hasNOP() const {
4472 return (Subtarget.getFeatureBits() & ARM::HasV6T2Ops) != 0;
4475 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4476 if (MI->getNumOperands() < 4)
4478 unsigned ShOpVal = MI->getOperand(3).getImm();
4479 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4480 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4481 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4482 ((ShImm == 1 || ShImm == 2) &&
4483 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))